2 * Driver for NEC VR4100 series General-purpose I/O Unit.
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <source@mvista.com>
6 * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
24 #include <linux/gpio.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/spinlock.h>
33 #include <linux/types.h>
35 #include <asm/vr41xx/giu.h>
36 #include <asm/vr41xx/irq.h>
37 #include <asm/vr41xx/vr41xx.h>
39 MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
40 MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
41 MODULE_LICENSE("GPL");
43 #define GIUIOSELL 0x00
44 #define GIUIOSELH 0x02
47 #define GIUINTSTATL 0x08
48 #define GIUINTSTATH 0x0a
49 #define GIUINTENL 0x0c
50 #define GIUINTENH 0x0e
51 #define GIUINTTYPL 0x10
52 #define GIUINTTYPH 0x12
53 #define GIUINTALSELL 0x14
54 #define GIUINTALSELH 0x16
55 #define GIUINTHTSELL 0x18
56 #define GIUINTHTSELH 0x1a
57 #define GIUPODATL 0x1c
58 #define GIUPODATEN 0x1c
59 #define GIUPODATH 0x1e
63 #define GIUFEDGEINHL 0x20
64 #define GIUFEDGEINHH 0x22
65 #define GIUREDGEINHL 0x24
66 #define GIUREDGEINHH 0x26
68 #define GIUUSEUPDN 0x1e0
69 #define GIUTERMUPDN 0x1e2
71 #define GPIO_HAS_PULLUPDOWN_IO 0x0001
72 #define GPIO_HAS_OUTPUT_ENABLE 0x0002
73 #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
80 static DEFINE_SPINLOCK(giu_lock);
81 static unsigned long giu_flags;
83 static void __iomem *giu_base;
84 static struct gpio_chip vr41xx_gpio_chip;
86 #define giu_read(offset) readw(giu_base + (offset))
87 #define giu_write(offset, value) writew((value), giu_base + (offset))
89 #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
90 #define GIUINT_HIGH_OFFSET 16
91 #define GIUINT_HIGH_MAX 32
93 static inline u16 giu_set(u16 offset, u16 set)
97 data = giu_read(offset);
99 giu_write(offset, data);
104 static inline u16 giu_clear(u16 offset, u16 clear)
108 data = giu_read(offset);
110 giu_write(offset, data);
115 static void ack_giuint_low(struct irq_data *d)
117 giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq));
120 static void mask_giuint_low(struct irq_data *d)
122 giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
125 static void mask_ack_giuint_low(struct irq_data *d)
129 pin = GPIO_PIN_OF_IRQ(d->irq);
130 giu_clear(GIUINTENL, 1 << pin);
131 giu_write(GIUINTSTATL, 1 << pin);
134 static void unmask_giuint_low(struct irq_data *d)
136 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
139 static unsigned int startup_giuint(struct irq_data *data)
143 ret = gpiochip_lock_as_irq(&vr41xx_gpio_chip, irqd_to_hwirq(data));
145 dev_err(vr41xx_gpio_chip.parent,
146 "unable to lock HW IRQ %lu for IRQ\n",
151 /* Satisfy the .enable semantics by unmasking the line */
152 unmask_giuint_low(data);
156 static void shutdown_giuint(struct irq_data *data)
158 mask_giuint_low(data);
159 gpiochip_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
162 static struct irq_chip giuint_low_irq_chip = {
164 .irq_ack = ack_giuint_low,
165 .irq_mask = mask_giuint_low,
166 .irq_mask_ack = mask_ack_giuint_low,
167 .irq_unmask = unmask_giuint_low,
168 .irq_startup = startup_giuint,
169 .irq_shutdown = shutdown_giuint,
172 static void ack_giuint_high(struct irq_data *d)
174 giu_write(GIUINTSTATH,
175 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
178 static void mask_giuint_high(struct irq_data *d)
180 giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
183 static void mask_ack_giuint_high(struct irq_data *d)
187 pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET;
188 giu_clear(GIUINTENH, 1 << pin);
189 giu_write(GIUINTSTATH, 1 << pin);
192 static void unmask_giuint_high(struct irq_data *d)
194 giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
197 static struct irq_chip giuint_high_irq_chip = {
199 .irq_ack = ack_giuint_high,
200 .irq_mask = mask_giuint_high,
201 .irq_mask_ack = mask_ack_giuint_high,
202 .irq_unmask = unmask_giuint_high,
205 static int giu_get_irq(unsigned int irq)
207 u16 pendl, pendh, maskl, maskh;
210 pendl = giu_read(GIUINTSTATL);
211 pendh = giu_read(GIUINTSTATH);
212 maskl = giu_read(GIUINTENL);
213 maskh = giu_read(GIUINTENH);
219 for (i = 0; i < 16; i++) {
220 if (maskl & (1 << i))
224 for (i = 0; i < 16; i++) {
225 if (maskh & (1 << i))
226 return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
230 printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
231 maskl, pendl, maskh, pendh);
236 void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
241 if (pin < GIUINT_HIGH_OFFSET) {
243 if (trigger != IRQ_TRIGGER_LEVEL) {
244 giu_set(GIUINTTYPL, mask);
245 if (signal == IRQ_SIGNAL_HOLD)
246 giu_set(GIUINTHTSELL, mask);
248 giu_clear(GIUINTHTSELL, mask);
249 if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
251 case IRQ_TRIGGER_EDGE_FALLING:
252 giu_set(GIUFEDGEINHL, mask);
253 giu_clear(GIUREDGEINHL, mask);
255 case IRQ_TRIGGER_EDGE_RISING:
256 giu_clear(GIUFEDGEINHL, mask);
257 giu_set(GIUREDGEINHL, mask);
260 giu_set(GIUFEDGEINHL, mask);
261 giu_set(GIUREDGEINHL, mask);
265 irq_set_chip_and_handler(GIU_IRQ(pin),
266 &giuint_low_irq_chip,
269 giu_clear(GIUINTTYPL, mask);
270 giu_clear(GIUINTHTSELL, mask);
271 irq_set_chip_and_handler(GIU_IRQ(pin),
272 &giuint_low_irq_chip,
275 giu_write(GIUINTSTATL, mask);
276 } else if (pin < GIUINT_HIGH_MAX) {
277 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
278 if (trigger != IRQ_TRIGGER_LEVEL) {
279 giu_set(GIUINTTYPH, mask);
280 if (signal == IRQ_SIGNAL_HOLD)
281 giu_set(GIUINTHTSELH, mask);
283 giu_clear(GIUINTHTSELH, mask);
284 if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
286 case IRQ_TRIGGER_EDGE_FALLING:
287 giu_set(GIUFEDGEINHH, mask);
288 giu_clear(GIUREDGEINHH, mask);
290 case IRQ_TRIGGER_EDGE_RISING:
291 giu_clear(GIUFEDGEINHH, mask);
292 giu_set(GIUREDGEINHH, mask);
295 giu_set(GIUFEDGEINHH, mask);
296 giu_set(GIUREDGEINHH, mask);
300 irq_set_chip_and_handler(GIU_IRQ(pin),
301 &giuint_high_irq_chip,
304 giu_clear(GIUINTTYPH, mask);
305 giu_clear(GIUINTHTSELH, mask);
306 irq_set_chip_and_handler(GIU_IRQ(pin),
307 &giuint_high_irq_chip,
310 giu_write(GIUINTSTATH, mask);
313 EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
315 void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
319 if (pin < GIUINT_HIGH_OFFSET) {
321 if (level == IRQ_LEVEL_HIGH)
322 giu_set(GIUINTALSELL, mask);
324 giu_clear(GIUINTALSELL, mask);
325 giu_write(GIUINTSTATL, mask);
326 } else if (pin < GIUINT_HIGH_MAX) {
327 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
328 if (level == IRQ_LEVEL_HIGH)
329 giu_set(GIUINTALSELH, mask);
331 giu_clear(GIUINTALSELH, mask);
332 giu_write(GIUINTSTATH, mask);
335 EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
337 static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir)
339 u16 offset, mask, reg;
342 if (pin >= chip->ngpio)
348 } else if (pin < 32) {
350 mask = 1 << (pin - 16);
352 if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
354 mask = 1 << (pin - 32);
371 spin_lock_irqsave(&giu_lock, flags);
373 reg = giu_read(offset);
374 if (dir == GPIO_OUTPUT)
378 giu_write(offset, reg);
380 spin_unlock_irqrestore(&giu_lock, flags);
385 int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
390 if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
398 spin_lock_irqsave(&giu_lock, flags);
400 if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
401 reg = giu_read(GIUTERMUPDN);
402 if (pull == GPIO_PULL_UP)
406 giu_write(GIUTERMUPDN, reg);
408 reg = giu_read(GIUUSEUPDN);
410 giu_write(GIUUSEUPDN, reg);
412 reg = giu_read(GIUUSEUPDN);
414 giu_write(GIUUSEUPDN, reg);
417 spin_unlock_irqrestore(&giu_lock, flags);
421 EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
423 static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin)
427 if (pin >= chip->ngpio)
431 reg = giu_read(GIUPIODL);
433 } else if (pin < 32) {
434 reg = giu_read(GIUPIODH);
435 mask = 1 << (pin - 16);
436 } else if (pin < 48) {
437 reg = giu_read(GIUPODATL);
438 mask = 1 << (pin - 32);
440 reg = giu_read(GIUPODATH);
441 mask = 1 << (pin - 48);
450 static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin,
453 u16 offset, mask, reg;
456 if (pin >= chip->ngpio)
462 } else if (pin < 32) {
464 mask = 1 << (pin - 16);
465 } else if (pin < 48) {
467 mask = 1 << (pin - 32);
470 mask = 1 << (pin - 48);
473 spin_lock_irqsave(&giu_lock, flags);
475 reg = giu_read(offset);
480 giu_write(offset, reg);
482 spin_unlock_irqrestore(&giu_lock, flags);
486 static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
488 return giu_set_direction(chip, offset, GPIO_INPUT);
491 static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
494 vr41xx_gpio_set(chip, offset, value);
496 return giu_set_direction(chip, offset, GPIO_OUTPUT);
499 static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
501 if (offset >= chip->ngpio)
504 return GIU_IRQ_BASE + offset;
507 static struct gpio_chip vr41xx_gpio_chip = {
509 .owner = THIS_MODULE,
510 .direction_input = vr41xx_gpio_direction_input,
511 .get = vr41xx_gpio_get,
512 .direction_output = vr41xx_gpio_direction_output,
513 .set = vr41xx_gpio_set,
514 .to_irq = vr41xx_gpio_to_irq,
517 static int giu_probe(struct platform_device *pdev)
519 struct resource *res;
520 unsigned int trigger, i, pin;
521 struct irq_chip *chip;
525 case GPIO_50PINS_PULLUPDOWN:
526 giu_flags = GPIO_HAS_PULLUPDOWN_IO;
527 vr41xx_gpio_chip.ngpio = 50;
530 vr41xx_gpio_chip.ngpio = 36;
532 case GPIO_48PINS_EDGE_SELECT:
533 giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
534 vr41xx_gpio_chip.ngpio = 48;
537 dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id);
541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
545 giu_base = ioremap(res->start, resource_size(res));
549 vr41xx_gpio_chip.parent = &pdev->dev;
551 ret = gpiochip_add_data(&vr41xx_gpio_chip, NULL);
557 giu_write(GIUINTENL, 0);
558 giu_write(GIUINTENH, 0);
560 trigger = giu_read(GIUINTTYPH) << 16;
561 trigger |= giu_read(GIUINTTYPL);
562 for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
563 pin = GPIO_PIN_OF_IRQ(i);
564 if (pin < GIUINT_HIGH_OFFSET)
565 chip = &giuint_low_irq_chip;
567 chip = &giuint_high_irq_chip;
569 if (trigger & (1 << pin))
570 irq_set_chip_and_handler(i, chip, handle_edge_irq);
572 irq_set_chip_and_handler(i, chip, handle_level_irq);
576 irq = platform_get_irq(pdev, 0);
577 if (irq < 0 || irq >= nr_irqs)
580 return cascade_irq(irq, giu_get_irq);
583 static int giu_remove(struct platform_device *pdev)
593 static struct platform_driver giu_device_driver = {
595 .remove = giu_remove,
601 module_platform_driver(giu_device_driver);