drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_fb_helper.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "atom.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_i2c.h"
  37
  38 #include <linux/pm_runtime.h>
  39
  40 void amdgpu_connector_hotplug(struct drm_connector *connector)
  41 {
  42         struct drm_device *dev = connector->dev;
  43         struct amdgpu_device *adev = dev->dev_private;
  44         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  45
  46         /* bail if the connector does not have hpd pin, e.g.,
  47          * VGA, TV, etc.
  48          */
  49         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  50                 return;
  51
  52         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  53
  54         /* if the connector is already off, don't turn it back on */
  55         if (connector->dpms != DRM_MODE_DPMS_ON)
  56                 return;
  57
  58         /* just deal with DP (not eDP) here. */
  59         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  60                 struct amdgpu_connector_atom_dig *dig_connector =
  61                         amdgpu_connector->con_priv;
  62
  63                 /* if existing sink type was not DP no need to retrain */
  64                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  65                         return;
  66
  67                 /* first get sink type as it may be reset after (un)plug */
  68                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  69                 /* don't do anything if sink is not display port, i.e.,
  70                  * passive dp->(dvi|hdmi) adaptor
  71                  */
  72                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  73                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  74                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  75                         /* Don't start link training before we have the DPCD */
  76                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  77                                 return;
  78
  79                         /* Turn the connector off and back on immediately, which
  80                          * will trigger link training
  81                          */
  82                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  83                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  84                 }
  85         }
  86 }
  87
  88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  89 {
  90         struct drm_crtc *crtc = encoder->crtc;
  91
  92         if (crtc && crtc->enabled) {
  93                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  94                                          crtc->x, crtc->y, crtc->primary->fb);
  95         }
  96 }
  97
  98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
  99 {
 100         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 101         struct amdgpu_connector_atom_dig *dig_connector;
 102         int bpc = 8;
 103         unsigned mode_clock, max_tmds_clock;
 104
 105         switch (connector->connector_type) {
 106         case DRM_MODE_CONNECTOR_DVII:
 107         case DRM_MODE_CONNECTOR_HDMIB:
 108                 if (amdgpu_connector->use_digital) {
 109                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 110                                 if (connector->display_info.bpc)
 111                                         bpc = connector->display_info.bpc;
 112                         }
 113                 }
 114                 break;
 115         case DRM_MODE_CONNECTOR_DVID:
 116         case DRM_MODE_CONNECTOR_HDMIA:
 117                 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 118                         if (connector->display_info.bpc)
 119                                 bpc = connector->display_info.bpc;
 120                 }
 121                 break;
 122         case DRM_MODE_CONNECTOR_DisplayPort:
 123                 dig_connector = amdgpu_connector->con_priv;
 124                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 125                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 126                     drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 127                         if (connector->display_info.bpc)
 128                                 bpc = connector->display_info.bpc;
 129                 }
 130                 break;
 131         case DRM_MODE_CONNECTOR_eDP:
 132         case DRM_MODE_CONNECTOR_LVDS:
 133                 if (connector->display_info.bpc)
 134                         bpc = connector->display_info.bpc;
 135                 else {
 136                         const struct drm_connector_helper_funcs *connector_funcs =
 137                                 connector->helper_private;
 138                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 139                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 140                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 141
 142                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 143                                 bpc = 6;
 144                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 145                                 bpc = 8;
 146                 }
 147                 break;
 148         }
 149
 150         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 151                 /*
 152                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 153                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 154                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 155                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 156                  */
 157                 if (bpc > 12) {
 158                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 159                                   connector->name, bpc);
 160                         bpc = 12;
 161                 }
 162
 163                 /* Any defined maximum tmds clock limit we must not exceed? */
 164                 if (connector->display_info.max_tmds_clock > 0) {
 165                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 166                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 167
 168                         /* Maximum allowable input clock in kHz */
 169                         max_tmds_clock = connector->display_info.max_tmds_clock;
 170
 171                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 172                                   connector->name, mode_clock, max_tmds_clock);
 173
 174                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 175                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 176                                 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 177                                     (mode_clock * 5/4 <= max_tmds_clock))
 178                                         bpc = 10;
 179                                 else
 180                                         bpc = 8;
 181
 182                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 183                                           connector->name, bpc);
 184                         }
 185
 186                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 187                                 bpc = 8;
 188                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 189                                           connector->name, bpc);
 190                         }
 191                 } else if (bpc > 8) {
 192                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 193                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 194                                   connector->name);
 195                         bpc = 8;
 196                 }
 197         }
 198
 199         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 200                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 201                           connector->name);
 202                 bpc = 8;
 203         }
 204
 205         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 206                   connector->name, connector->display_info.bpc, bpc);
 207
 208         return bpc;
 209 }
 210
 211 static void
 212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 213                                       enum drm_connector_status status)
 214 {
 215         struct drm_encoder *best_encoder = NULL;
 216         struct drm_encoder *encoder = NULL;
 217         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 218         bool connected;
 219         int i;
 220
 221         best_encoder = connector_funcs->best_encoder(connector);
 222
 223         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 224                 if (connector->encoder_ids[i] == 0)
 225                         break;
 226
 227                 encoder = drm_encoder_find(connector->dev,
 228                                         connector->encoder_ids[i]);
 229                 if (!encoder)
 230                         continue;
 231
 232                 if ((encoder == best_encoder) && (status == connector_status_connected))
 233                         connected = true;
 234                 else
 235                         connected = false;
 236
 237                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 238
 239         }
 240 }
 241
 242 static struct drm_encoder *
 243 amdgpu_connector_find_encoder(struct drm_connector *connector,
 244                                int encoder_type)
 245 {
 246         struct drm_encoder *encoder;
 247         int i;
 248
 249         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 250                 if (connector->encoder_ids[i] == 0)
 251                         break;
 252                 encoder = drm_encoder_find(connector->dev,
 253                                         connector->encoder_ids[i]);
 254                 if (!encoder)
 255                         continue;
 256
 257                 if (encoder->encoder_type == encoder_type)
 258                         return encoder;
 259         }
 260         return NULL;
 261 }
 262
 263 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 264 {
 265         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 266         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 267
 268         if (amdgpu_connector->edid) {
 269                 return amdgpu_connector->edid;
 270         } else if (edid_blob) {
 271                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 272                 if (edid)
 273                         amdgpu_connector->edid = edid;
 274         }
 275         return amdgpu_connector->edid;
 276 }
 277
 278 static struct edid *
 279 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 280 {
 281         struct edid *edid;
 282
 283         if (adev->mode_info.bios_hardcoded_edid) {
 284                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 285                 if (edid) {
 286                         memcpy((unsigned char *)edid,
 287                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 288                                adev->mode_info.bios_hardcoded_edid_size);
 289                         return edid;
 290                 }
 291         }
 292         return NULL;
 293 }
 294
 295 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 296 {
 297         struct drm_device *dev = connector->dev;
 298         struct amdgpu_device *adev = dev->dev_private;
 299         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 300
 301         if (amdgpu_connector->edid)
 302                 return;
 303
 304         /* on hw with routers, select right port */
 305         if (amdgpu_connector->router.ddc_valid)
 306                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 307
 308         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 309              ENCODER_OBJECT_ID_NONE) &&
 310             amdgpu_connector->ddc_bus->has_aux) {
 311                 amdgpu_connector->edid = drm_get_edid(connector,
 312                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 313         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 314                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 315                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 316
 317                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 318                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 319                     amdgpu_connector->ddc_bus->has_aux)
 320                         amdgpu_connector->edid = drm_get_edid(connector,
 321                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 322                 else if (amdgpu_connector->ddc_bus)
 323                         amdgpu_connector->edid = drm_get_edid(connector,
 324                                                               &amdgpu_connector->ddc_bus->adapter);
 325         } else if (amdgpu_connector->ddc_bus) {
 326                 amdgpu_connector->edid = drm_get_edid(connector,
 327                                                       &amdgpu_connector->ddc_bus->adapter);
 328         }
 329
 330         if (!amdgpu_connector->edid) {
 331                 /* some laptops provide a hardcoded edid in rom for LCDs */
 332                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 333                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 334                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 335         }
 336 }
 337
 338 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 339 {
 340         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 341
 342         if (amdgpu_connector->edid) {
 343                 kfree(amdgpu_connector->edid);
 344                 amdgpu_connector->edid = NULL;
 345         }
 346 }
 347
 348 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 349 {
 350         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 351         int ret;
 352
 353         if (amdgpu_connector->edid) {
 354                 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
 355                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 356                 drm_edid_to_eld(connector, amdgpu_connector->edid);
 357                 return ret;
 358         }
 359         drm_mode_connector_update_edid_property(connector, NULL);
 360         return 0;
 361 }
 362
 363 static struct drm_encoder *
 364 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 365 {
 366         int enc_id = connector->encoder_ids[0];
 367
 368         /* pick the encoder ids */
 369         if (enc_id)
 370                 return drm_encoder_find(connector->dev, enc_id);
 371         return NULL;
 372 }
 373
 374 static void amdgpu_get_native_mode(struct drm_connector *connector)
 375 {
 376         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 377         struct amdgpu_encoder *amdgpu_encoder;
 378
 379         if (encoder == NULL)
 380                 return;
 381
 382         amdgpu_encoder = to_amdgpu_encoder(encoder);
 383
 384         if (!list_empty(&connector->probed_modes)) {
 385                 struct drm_display_mode *preferred_mode =
 386                         list_first_entry(&connector->probed_modes,
 387                                          struct drm_display_mode, head);
 388
 389                 amdgpu_encoder->native_mode = *preferred_mode;
 390         } else {
 391                 amdgpu_encoder->native_mode.clock = 0;
 392         }
 393 }
 394
 395 static struct drm_display_mode *
 396 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 397 {
 398         struct drm_device *dev = encoder->dev;
 399         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 400         struct drm_display_mode *mode = NULL;
 401         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 402
 403         if (native_mode->hdisplay != 0 &&
 404             native_mode->vdisplay != 0 &&
 405             native_mode->clock != 0) {
 406                 mode = drm_mode_duplicate(dev, native_mode);
 407                 if (!mode)
 408                         return NULL;
 409
 410                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 411                 drm_mode_set_name(mode);
 412
 413                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 414         } else if (native_mode->hdisplay != 0 &&
 415                    native_mode->vdisplay != 0) {
 416                 /* mac laptops without an edid */
 417                 /* Note that this is not necessarily the exact panel mode,
 418                  * but an approximation based on the cvt formula.  For these
 419                  * systems we should ideally read the mode info out of the
 420                  * registers or add a mode table, but this works and is much
 421                  * simpler.
 422                  */
 423                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 424                 if (!mode)
 425                         return NULL;
 426
 427                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 428                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 429         }
 430         return mode;
 431 }
 432
 433 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 434                                                struct drm_connector *connector)
 435 {
 436         struct drm_device *dev = encoder->dev;
 437         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 438         struct drm_display_mode *mode = NULL;
 439         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 440         int i;
 441         static const struct mode_size {
 442                 int w;
 443                 int h;
 444         } common_modes[17] = {
 445                 { 640,  480},
 446                 { 720,  480},
 447                 { 800,  600},
 448                 { 848,  480},
 449                 {1024,  768},
 450                 {1152,  768},
 451                 {1280,  720},
 452                 {1280,  800},
 453                 {1280,  854},
 454                 {1280,  960},
 455                 {1280, 1024},
 456                 {1440,  900},
 457                 {1400, 1050},
 458                 {1680, 1050},
 459                 {1600, 1200},
 460                 {1920, 1080},
 461                 {1920, 1200}
 462         };
 463
 464         for (i = 0; i < 17; i++) {
 465                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 466                         if (common_modes[i].w > 1024 ||
 467                             common_modes[i].h > 768)
 468                                 continue;
 469                 }
 470                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 471                         if (common_modes[i].w > native_mode->hdisplay ||
 472                             common_modes[i].h > native_mode->vdisplay ||
 473                             (common_modes[i].w == native_mode->hdisplay &&
 474                              common_modes[i].h == native_mode->vdisplay))
 475                                 continue;
 476                 }
 477                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 478                         continue;
 479
 480                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 481                 drm_mode_probed_add(connector, mode);
 482         }
 483 }
 484
 485 static int amdgpu_connector_set_property(struct drm_connector *connector,
 486                                           struct drm_property *property,
 487                                           uint64_t val)
 488 {
 489         struct drm_device *dev = connector->dev;
 490         struct amdgpu_device *adev = dev->dev_private;
 491         struct drm_encoder *encoder;
 492         struct amdgpu_encoder *amdgpu_encoder;
 493
 494         if (property == adev->mode_info.coherent_mode_property) {
 495                 struct amdgpu_encoder_atom_dig *dig;
 496                 bool new_coherent_mode;
 497
 498                 /* need to find digital encoder on connector */
 499                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 500                 if (!encoder)
 501                         return 0;
 502
 503                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 504
 505                 if (!amdgpu_encoder->enc_priv)
 506                         return 0;
 507
 508                 dig = amdgpu_encoder->enc_priv;
 509                 new_coherent_mode = val ? true : false;
 510                 if (dig->coherent_mode != new_coherent_mode) {
 511                         dig->coherent_mode = new_coherent_mode;
 512                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 513                 }
 514         }
 515
 516         if (property == adev->mode_info.audio_property) {
 517                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 518                 /* need to find digital encoder on connector */
 519                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 520                 if (!encoder)
 521                         return 0;
 522
 523                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 524
 525                 if (amdgpu_connector->audio != val) {
 526                         amdgpu_connector->audio = val;
 527                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 528                 }
 529         }
 530
 531         if (property == adev->mode_info.dither_property) {
 532                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 533                 /* need to find digital encoder on connector */
 534                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 535                 if (!encoder)
 536                         return 0;
 537
 538                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 539
 540                 if (amdgpu_connector->dither != val) {
 541                         amdgpu_connector->dither = val;
 542                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 543                 }
 544         }
 545
 546         if (property == adev->mode_info.underscan_property) {
 547                 /* need to find digital encoder on connector */
 548                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 549                 if (!encoder)
 550                         return 0;
 551
 552                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 553
 554                 if (amdgpu_encoder->underscan_type != val) {
 555                         amdgpu_encoder->underscan_type = val;
 556                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 557                 }
 558         }
 559
 560         if (property == adev->mode_info.underscan_hborder_property) {
 561                 /* need to find digital encoder on connector */
 562                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 563                 if (!encoder)
 564                         return 0;
 565
 566                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 567
 568                 if (amdgpu_encoder->underscan_hborder != val) {
 569                         amdgpu_encoder->underscan_hborder = val;
 570                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 571                 }
 572         }
 573
 574         if (property == adev->mode_info.underscan_vborder_property) {
 575                 /* need to find digital encoder on connector */
 576                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 577                 if (!encoder)
 578                         return 0;
 579
 580                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 581
 582                 if (amdgpu_encoder->underscan_vborder != val) {
 583                         amdgpu_encoder->underscan_vborder = val;
 584                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 585                 }
 586         }
 587
 588         if (property == adev->mode_info.load_detect_property) {
 589                 struct amdgpu_connector *amdgpu_connector =
 590                         to_amdgpu_connector(connector);
 591
 592                 if (val == 0)
 593                         amdgpu_connector->dac_load_detect = false;
 594                 else
 595                         amdgpu_connector->dac_load_detect = true;
 596         }
 597
 598         if (property == dev->mode_config.scaling_mode_property) {
 599                 enum amdgpu_rmx_type rmx_type;
 600
 601                 if (connector->encoder) {
 602                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 603                 } else {
 604                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 605                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 606                 }
 607
 608                 switch (val) {
 609                 default:
 610                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 611                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 612                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 613                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 614                 }
 615                 if (amdgpu_encoder->rmx_type == rmx_type)
 616                         return 0;
 617
 618                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 619                     (amdgpu_encoder->native_mode.clock == 0))
 620                         return 0;
 621
 622                 amdgpu_encoder->rmx_type = rmx_type;
 623
 624                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 625         }
 626
 627         return 0;
 628 }
 629
 630 static void
 631 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 632                                         struct drm_connector *connector)
 633 {
 634         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 635         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 636         struct drm_display_mode *t, *mode;
 637
 638         /* If the EDID preferred mode doesn't match the native mode, use it */
 639         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 640                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 641                         if (mode->hdisplay != native_mode->hdisplay ||
 642                             mode->vdisplay != native_mode->vdisplay)
 643                                 memcpy(native_mode, mode, sizeof(*mode));
 644                 }
 645         }
 646
 647         /* Try to get native mode details from EDID if necessary */
 648         if (!native_mode->clock) {
 649                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 650                         if (mode->hdisplay == native_mode->hdisplay &&
 651                             mode->vdisplay == native_mode->vdisplay) {
 652                                 *native_mode = *mode;
 653                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 654                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 655                                 break;
 656                         }
 657                 }
 658         }
 659
 660         if (!native_mode->clock) {
 661                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 662                 amdgpu_encoder->rmx_type = RMX_OFF;
 663         }
 664 }
 665
 666 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 667 {
 668         struct drm_encoder *encoder;
 669         int ret = 0;
 670         struct drm_display_mode *mode;
 671
 672         amdgpu_connector_get_edid(connector);
 673         ret = amdgpu_connector_ddc_get_modes(connector);
 674         if (ret > 0) {
 675                 encoder = amdgpu_connector_best_single_encoder(connector);
 676                 if (encoder) {
 677                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 678                         /* add scaled modes */
 679                         amdgpu_connector_add_common_modes(encoder, connector);
 680                 }
 681                 return ret;
 682         }
 683
 684         encoder = amdgpu_connector_best_single_encoder(connector);
 685         if (!encoder)
 686                 return 0;
 687
 688         /* we have no EDID modes */
 689         mode = amdgpu_connector_lcd_native_mode(encoder);
 690         if (mode) {
 691                 ret = 1;
 692                 drm_mode_probed_add(connector, mode);
 693                 /* add the width/height from vbios tables if available */
 694                 connector->display_info.width_mm = mode->width_mm;
 695                 connector->display_info.height_mm = mode->height_mm;
 696                 /* add scaled modes */
 697                 amdgpu_connector_add_common_modes(encoder, connector);
 698         }
 699
 700         return ret;
 701 }
 702
 703 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 704                                              struct drm_display_mode *mode)
 705 {
 706         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 707
 708         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 709                 return MODE_PANEL;
 710
 711         if (encoder) {
 712                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 713                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 714
 715                 /* AVIVO hardware supports downscaling modes larger than the panel
 716                  * to the panel size, but I'm not sure this is desirable.
 717                  */
 718                 if ((mode->hdisplay > native_mode->hdisplay) ||
 719                     (mode->vdisplay > native_mode->vdisplay))
 720                         return MODE_PANEL;
 721
 722                 /* if scaling is disabled, block non-native modes */
 723                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 724                         if ((mode->hdisplay != native_mode->hdisplay) ||
 725                             (mode->vdisplay != native_mode->vdisplay))
 726                                 return MODE_PANEL;
 727                 }
 728         }
 729
 730         return MODE_OK;
 731 }
 732
 733 static enum drm_connector_status
 734 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 735 {
 736         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 737         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 738         enum drm_connector_status ret = connector_status_disconnected;
 739         int r;
 740
 741         if (!drm_kms_helper_is_poll_worker()) {
 742                 r = pm_runtime_get_sync(connector->dev->dev);
 743                 if (r < 0) {
 744                         pm_runtime_put_autosuspend(connector->dev->dev);
 745                         return connector_status_disconnected;
 746                 }
 747         }
 748
 749         if (encoder) {
 750                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 751                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 752
 753                 /* check if panel is valid */
 754                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 755                         ret = connector_status_connected;
 756
 757         }
 758
 759         /* check for edid as well */
 760         amdgpu_connector_get_edid(connector);
 761         if (amdgpu_connector->edid)
 762                 ret = connector_status_connected;
 763         /* check acpi lid status ??? */
 764
 765         amdgpu_connector_update_scratch_regs(connector, ret);
 766
 767         if (!drm_kms_helper_is_poll_worker()) {
 768                 pm_runtime_mark_last_busy(connector->dev->dev);
 769                 pm_runtime_put_autosuspend(connector->dev->dev);
 770         }
 771
 772         return ret;
 773 }
 774
 775 static void amdgpu_connector_unregister(struct drm_connector *connector)
 776 {
 777         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 778
 779         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 780                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 781                 amdgpu_connector->ddc_bus->has_aux = false;
 782         }
 783 }
 784
 785 static void amdgpu_connector_destroy(struct drm_connector *connector)
 786 {
 787         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 788
 789         amdgpu_connector_free_edid(connector);
 790         kfree(amdgpu_connector->con_priv);
 791         drm_connector_unregister(connector);
 792         drm_connector_cleanup(connector);
 793         kfree(connector);
 794 }
 795
 796 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 797                                               struct drm_property *property,
 798                                               uint64_t value)
 799 {
 800         struct drm_device *dev = connector->dev;
 801         struct amdgpu_encoder *amdgpu_encoder;
 802         enum amdgpu_rmx_type rmx_type;
 803
 804         DRM_DEBUG_KMS("\n");
 805         if (property != dev->mode_config.scaling_mode_property)
 806                 return 0;
 807
 808         if (connector->encoder)
 809                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 810         else {
 811                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 812                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 813         }
 814
 815         switch (value) {
 816         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 817         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 818         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 819         default:
 820         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 821         }
 822         if (amdgpu_encoder->rmx_type == rmx_type)
 823                 return 0;
 824
 825         amdgpu_encoder->rmx_type = rmx_type;
 826
 827         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 828         return 0;
 829 }
 830
 831
 832 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 833         .get_modes = amdgpu_connector_lvds_get_modes,
 834         .mode_valid = amdgpu_connector_lvds_mode_valid,
 835         .best_encoder = amdgpu_connector_best_single_encoder,
 836 };
 837
 838 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 839         .dpms = drm_helper_connector_dpms,
 840         .detect = amdgpu_connector_lvds_detect,
 841         .fill_modes = drm_helper_probe_single_connector_modes,
 842         .early_unregister = amdgpu_connector_unregister,
 843         .destroy = amdgpu_connector_destroy,
 844         .set_property = amdgpu_connector_set_lcd_property,
 845 };
 846
 847 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 848 {
 849         int ret;
 850
 851         amdgpu_connector_get_edid(connector);
 852         ret = amdgpu_connector_ddc_get_modes(connector);
 853         amdgpu_get_native_mode(connector);
 854
 855         return ret;
 856 }
 857
 858 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 859                                             struct drm_display_mode *mode)
 860 {
 861         struct drm_device *dev = connector->dev;
 862         struct amdgpu_device *adev = dev->dev_private;
 863
 864         /* XXX check mode bandwidth */
 865
 866         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 867                 return MODE_CLOCK_HIGH;
 868
 869         return MODE_OK;
 870 }
 871
 872 static enum drm_connector_status
 873 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 874 {
 875         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 876         struct drm_encoder *encoder;
 877         const struct drm_encoder_helper_funcs *encoder_funcs;
 878         bool dret = false;
 879         enum drm_connector_status ret = connector_status_disconnected;
 880         int r;
 881
 882         if (!drm_kms_helper_is_poll_worker()) {
 883                 r = pm_runtime_get_sync(connector->dev->dev);
 884                 if (r < 0) {
 885                         pm_runtime_put_autosuspend(connector->dev->dev);
 886                         return connector_status_disconnected;
 887                 }
 888         }
 889
 890         encoder = amdgpu_connector_best_single_encoder(connector);
 891         if (!encoder)
 892                 ret = connector_status_disconnected;
 893
 894         if (amdgpu_connector->ddc_bus)
 895                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
 896         if (dret) {
 897                 amdgpu_connector->detected_by_load = false;
 898                 amdgpu_connector_free_edid(connector);
 899                 amdgpu_connector_get_edid(connector);
 900
 901                 if (!amdgpu_connector->edid) {
 902                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 903                                         connector->name);
 904                         ret = connector_status_connected;
 905                 } else {
 906                         amdgpu_connector->use_digital =
 907                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 908
 909                         /* some oems have boards with separate digital and analog connectors
 910                          * with a shared ddc line (often vga + hdmi)
 911                          */
 912                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 913                                 amdgpu_connector_free_edid(connector);
 914                                 ret = connector_status_disconnected;
 915                         } else {
 916                                 ret = connector_status_connected;
 917                         }
 918                 }
 919         } else {
 920
 921                 /* if we aren't forcing don't do destructive polling */
 922                 if (!force) {
 923                         /* only return the previous status if we last
 924                          * detected a monitor via load.
 925                          */
 926                         if (amdgpu_connector->detected_by_load)
 927                                 ret = connector->status;
 928                         goto out;
 929                 }
 930
 931                 if (amdgpu_connector->dac_load_detect && encoder) {
 932                         encoder_funcs = encoder->helper_private;
 933                         ret = encoder_funcs->detect(encoder, connector);
 934                         if (ret != connector_status_disconnected)
 935                                 amdgpu_connector->detected_by_load = true;
 936                 }
 937         }
 938
 939         amdgpu_connector_update_scratch_regs(connector, ret);
 940
 941 out:
 942         if (!drm_kms_helper_is_poll_worker()) {
 943                 pm_runtime_mark_last_busy(connector->dev->dev);
 944                 pm_runtime_put_autosuspend(connector->dev->dev);
 945         }
 946
 947         return ret;
 948 }
 949
 950 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 951         .get_modes = amdgpu_connector_vga_get_modes,
 952         .mode_valid = amdgpu_connector_vga_mode_valid,
 953         .best_encoder = amdgpu_connector_best_single_encoder,
 954 };
 955
 956 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 957         .dpms = drm_helper_connector_dpms,
 958         .detect = amdgpu_connector_vga_detect,
 959         .fill_modes = drm_helper_probe_single_connector_modes,
 960         .early_unregister = amdgpu_connector_unregister,
 961         .destroy = amdgpu_connector_destroy,
 962         .set_property = amdgpu_connector_set_property,
 963 };
 964
 965 static bool
 966 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 967 {
 968         struct drm_device *dev = connector->dev;
 969         struct amdgpu_device *adev = dev->dev_private;
 970         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 971         enum drm_connector_status status;
 972
 973         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 974                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 975                         status = connector_status_connected;
 976                 else
 977                         status = connector_status_disconnected;
 978                 if (connector->status == status)
 979                         return true;
 980         }
 981
 982         return false;
 983 }
 984
 985 /*
 986  * DVI is complicated
 987  * Do a DDC probe, if DDC probe passes, get the full EDID so
 988  * we can do analog/digital monitor detection at this point.
 989  * If the monitor is an analog monitor or we got no DDC,
 990  * we need to find the DAC encoder object for this connector.
 991  * If we got no DDC, we do load detection on the DAC encoder object.
 992  * If we got analog DDC or load detection passes on the DAC encoder
 993  * we have to check if this analog encoder is shared with anyone else (TV)
 994  * if its shared we have to set the other connector to disconnected.
 995  */
 996 static enum drm_connector_status
 997 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 998 {
 999         struct drm_device *dev = connector->dev;
1000         struct amdgpu_device *adev = dev->dev_private;
1001         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1002         struct drm_encoder *encoder = NULL;
1003         const struct drm_encoder_helper_funcs *encoder_funcs;
1004         int i, r;
1005         enum drm_connector_status ret = connector_status_disconnected;
1006         bool dret = false, broken_edid = false;
1007
1008         if (!drm_kms_helper_is_poll_worker()) {
1009                 r = pm_runtime_get_sync(connector->dev->dev);
1010                 if (r < 0) {
1011                         pm_runtime_put_autosuspend(connector->dev->dev);
1012                         return connector_status_disconnected;
1013                 }
1014         }
1015
1016         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1017                 ret = connector->status;
1018                 goto exit;
1019         }
1020
1021         if (amdgpu_connector->ddc_bus)
1022                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1023         if (dret) {
1024                 amdgpu_connector->detected_by_load = false;
1025                 amdgpu_connector_free_edid(connector);
1026                 amdgpu_connector_get_edid(connector);
1027
1028                 if (!amdgpu_connector->edid) {
1029                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1030                                         connector->name);
1031                         ret = connector_status_connected;
1032                         broken_edid = true; /* defer use_digital to later */
1033                 } else {
1034                         amdgpu_connector->use_digital =
1035                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1036
1037                         /* some oems have boards with separate digital and analog connectors
1038                          * with a shared ddc line (often vga + hdmi)
1039                          */
1040                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1041                                 amdgpu_connector_free_edid(connector);
1042                                 ret = connector_status_disconnected;
1043                         } else {
1044                                 ret = connector_status_connected;
1045                         }
1046
1047                         /* This gets complicated.  We have boards with VGA + HDMI with a
1048                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1049                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1050                          * you don't really know what's connected to which port as both are digital.
1051                          */
1052                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1053                                 struct drm_connector *list_connector;
1054                                 struct amdgpu_connector *list_amdgpu_connector;
1055                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1056                                         if (connector == list_connector)
1057                                                 continue;
1058                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1059                                         if (list_amdgpu_connector->shared_ddc &&
1060                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1061                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1062                                                 /* cases where both connectors are digital */
1063                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1064                                                         /* hpd is our only option in this case */
1065                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1066                                                                 amdgpu_connector_free_edid(connector);
1067                                                                 ret = connector_status_disconnected;
1068                                                         }
1069                                                 }
1070                                         }
1071                                 }
1072                         }
1073                 }
1074         }
1075
1076         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1077                 goto out;
1078
1079         /* DVI-D and HDMI-A are digital only */
1080         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1081             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1082                 goto out;
1083
1084         /* if we aren't forcing don't do destructive polling */
1085         if (!force) {
1086                 /* only return the previous status if we last
1087                  * detected a monitor via load.
1088                  */
1089                 if (amdgpu_connector->detected_by_load)
1090                         ret = connector->status;
1091                 goto out;
1092         }
1093
1094         /* find analog encoder */
1095         if (amdgpu_connector->dac_load_detect) {
1096                 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1097                         if (connector->encoder_ids[i] == 0)
1098                                 break;
1099
1100                         encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1101                         if (!encoder)
1102                                 continue;
1103
1104                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1105                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1106                                 continue;
1107
1108                         encoder_funcs = encoder->helper_private;
1109                         if (encoder_funcs->detect) {
1110                                 if (!broken_edid) {
1111                                         if (ret != connector_status_connected) {
1112                                                 /* deal with analog monitors without DDC */
1113                                                 ret = encoder_funcs->detect(encoder, connector);
1114                                                 if (ret == connector_status_connected) {
1115                                                         amdgpu_connector->use_digital = false;
1116                                                 }
1117                                                 if (ret != connector_status_disconnected)
1118                                                         amdgpu_connector->detected_by_load = true;
1119                                         }
1120                                 } else {
1121                                         enum drm_connector_status lret;
1122                                         /* assume digital unless load detected otherwise */
1123                                         amdgpu_connector->use_digital = true;
1124                                         lret = encoder_funcs->detect(encoder, connector);
1125                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1126                                         if (lret == connector_status_connected)
1127                                                 amdgpu_connector->use_digital = false;
1128                                 }
1129                                 break;
1130                         }
1131                 }
1132         }
1133
1134 out:
1135         /* updated in get modes as well since we need to know if it's analog or digital */
1136         amdgpu_connector_update_scratch_regs(connector, ret);
1137
1138 exit:
1139         if (!drm_kms_helper_is_poll_worker()) {
1140                 pm_runtime_mark_last_busy(connector->dev->dev);
1141                 pm_runtime_put_autosuspend(connector->dev->dev);
1142         }
1143
1144         return ret;
1145 }
1146
1147 /* okay need to be smart in here about which encoder to pick */
1148 static struct drm_encoder *
1149 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1150 {
1151         int enc_id = connector->encoder_ids[0];
1152         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1153         struct drm_encoder *encoder;
1154         int i;
1155         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1156                 if (connector->encoder_ids[i] == 0)
1157                         break;
1158
1159                 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1160                 if (!encoder)
1161                         continue;
1162
1163                 if (amdgpu_connector->use_digital == true) {
1164                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1165                                 return encoder;
1166                 } else {
1167                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1168                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1169                                 return encoder;
1170                 }
1171         }
1172
1173         /* see if we have a default encoder  TODO */
1174
1175         /* then check use digitial */
1176         /* pick the first one */
1177         if (enc_id)
1178                 return drm_encoder_find(connector->dev, enc_id);
1179         return NULL;
1180 }
1181
1182 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1183 {
1184         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1185         if (connector->force == DRM_FORCE_ON)
1186                 amdgpu_connector->use_digital = false;
1187         if (connector->force == DRM_FORCE_ON_DIGITAL)
1188                 amdgpu_connector->use_digital = true;
1189 }
1190
1191 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1192                                             struct drm_display_mode *mode)
1193 {
1194         struct drm_device *dev = connector->dev;
1195         struct amdgpu_device *adev = dev->dev_private;
1196         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1197
1198         /* XXX check mode bandwidth */
1199
1200         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1201                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1202                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1203                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1204                         return MODE_OK;
1205                 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1206                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1207                         if (mode->clock > 340000)
1208                                 return MODE_CLOCK_HIGH;
1209                         else
1210                                 return MODE_OK;
1211                 } else {
1212                         return MODE_CLOCK_HIGH;
1213                 }
1214         }
1215
1216         /* check against the max pixel clock */
1217         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1218                 return MODE_CLOCK_HIGH;
1219
1220         return MODE_OK;
1221 }
1222
1223 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1224         .get_modes = amdgpu_connector_vga_get_modes,
1225         .mode_valid = amdgpu_connector_dvi_mode_valid,
1226         .best_encoder = amdgpu_connector_dvi_encoder,
1227 };
1228
1229 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1230         .dpms = drm_helper_connector_dpms,
1231         .detect = amdgpu_connector_dvi_detect,
1232         .fill_modes = drm_helper_probe_single_connector_modes,
1233         .set_property = amdgpu_connector_set_property,
1234         .early_unregister = amdgpu_connector_unregister,
1235         .destroy = amdgpu_connector_destroy,
1236         .force = amdgpu_connector_dvi_force,
1237 };
1238
1239 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1240 {
1241         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1242         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1243         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1244         int ret;
1245
1246         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1247             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1248                 struct drm_display_mode *mode;
1249
1250                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1251                         if (!amdgpu_dig_connector->edp_on)
1252                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1253                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1254                         amdgpu_connector_get_edid(connector);
1255                         ret = amdgpu_connector_ddc_get_modes(connector);
1256                         if (!amdgpu_dig_connector->edp_on)
1257                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1258                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1259                 } else {
1260                         /* need to setup ddc on the bridge */
1261                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1262                             ENCODER_OBJECT_ID_NONE) {
1263                                 if (encoder)
1264                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1265                         }
1266                         amdgpu_connector_get_edid(connector);
1267                         ret = amdgpu_connector_ddc_get_modes(connector);
1268                 }
1269
1270                 if (ret > 0) {
1271                         if (encoder) {
1272                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1273                                 /* add scaled modes */
1274                                 amdgpu_connector_add_common_modes(encoder, connector);
1275                         }
1276                         return ret;
1277                 }
1278
1279                 if (!encoder)
1280                         return 0;
1281
1282                 /* we have no EDID modes */
1283                 mode = amdgpu_connector_lcd_native_mode(encoder);
1284                 if (mode) {
1285                         ret = 1;
1286                         drm_mode_probed_add(connector, mode);
1287                         /* add the width/height from vbios tables if available */
1288                         connector->display_info.width_mm = mode->width_mm;
1289                         connector->display_info.height_mm = mode->height_mm;
1290                         /* add scaled modes */
1291                         amdgpu_connector_add_common_modes(encoder, connector);
1292                 }
1293         } else {
1294                 /* need to setup ddc on the bridge */
1295                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1296                         ENCODER_OBJECT_ID_NONE) {
1297                         if (encoder)
1298                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1299                 }
1300                 amdgpu_connector_get_edid(connector);
1301                 ret = amdgpu_connector_ddc_get_modes(connector);
1302
1303                 amdgpu_get_native_mode(connector);
1304         }
1305
1306         return ret;
1307 }
1308
1309 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1310 {
1311         struct drm_encoder *encoder;
1312         struct amdgpu_encoder *amdgpu_encoder;
1313         int i;
1314
1315         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1316                 if (connector->encoder_ids[i] == 0)
1317                         break;
1318
1319                 encoder = drm_encoder_find(connector->dev,
1320                                         connector->encoder_ids[i]);
1321                 if (!encoder)
1322                         continue;
1323
1324                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1325
1326                 switch (amdgpu_encoder->encoder_id) {
1327                 case ENCODER_OBJECT_ID_TRAVIS:
1328                 case ENCODER_OBJECT_ID_NUTMEG:
1329                         return amdgpu_encoder->encoder_id;
1330                 default:
1331                         break;
1332                 }
1333         }
1334
1335         return ENCODER_OBJECT_ID_NONE;
1336 }
1337
1338 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1339 {
1340         struct drm_encoder *encoder;
1341         struct amdgpu_encoder *amdgpu_encoder;
1342         int i;
1343         bool found = false;
1344
1345         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1346                 if (connector->encoder_ids[i] == 0)
1347                         break;
1348                 encoder = drm_encoder_find(connector->dev,
1349                                         connector->encoder_ids[i]);
1350                 if (!encoder)
1351                         continue;
1352
1353                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1354                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1355                         found = true;
1356         }
1357
1358         return found;
1359 }
1360
1361 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1362 {
1363         struct drm_device *dev = connector->dev;
1364         struct amdgpu_device *adev = dev->dev_private;
1365
1366         if ((adev->clock.default_dispclk >= 53900) &&
1367             amdgpu_connector_encoder_is_hbr2(connector)) {
1368                 return true;
1369         }
1370
1371         return false;
1372 }
1373
1374 static enum drm_connector_status
1375 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1376 {
1377         struct drm_device *dev = connector->dev;
1378         struct amdgpu_device *adev = dev->dev_private;
1379         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1380         enum drm_connector_status ret = connector_status_disconnected;
1381         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1382         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1383         int r;
1384
1385         if (!drm_kms_helper_is_poll_worker()) {
1386                 r = pm_runtime_get_sync(connector->dev->dev);
1387                 if (r < 0) {
1388                         pm_runtime_put_autosuspend(connector->dev->dev);
1389                         return connector_status_disconnected;
1390                 }
1391         }
1392
1393         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1394                 ret = connector->status;
1395                 goto out;
1396         }
1397
1398         amdgpu_connector_free_edid(connector);
1399
1400         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1401             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1402                 if (encoder) {
1403                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1404                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1405
1406                         /* check if panel is valid */
1407                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1408                                 ret = connector_status_connected;
1409                 }
1410                 /* eDP is always DP */
1411                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1412                 if (!amdgpu_dig_connector->edp_on)
1413                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1414                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1415                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1416                         ret = connector_status_connected;
1417                 if (!amdgpu_dig_connector->edp_on)
1418                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1419                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1420         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1421                    ENCODER_OBJECT_ID_NONE) {
1422                 /* DP bridges are always DP */
1423                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1424                 /* get the DPCD from the bridge */
1425                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1426
1427                 if (encoder) {
1428                         /* setup ddc on the bridge */
1429                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1430                         /* bridge chips are always aux */
1431                         if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1432                                 ret = connector_status_connected;
1433                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1434                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1435                                 ret = encoder_funcs->detect(encoder, connector);
1436                         }
1437                 }
1438         } else {
1439                 amdgpu_dig_connector->dp_sink_type =
1440                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1441                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1442                         ret = connector_status_connected;
1443                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1444                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1445                 } else {
1446                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1447                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1448                                         ret = connector_status_connected;
1449                         } else {
1450                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1451                                 if (amdgpu_ddc_probe(amdgpu_connector, false))
1452                                         ret = connector_status_connected;
1453                         }
1454                 }
1455         }
1456
1457         amdgpu_connector_update_scratch_regs(connector, ret);
1458 out:
1459         if (!drm_kms_helper_is_poll_worker()) {
1460                 pm_runtime_mark_last_busy(connector->dev->dev);
1461                 pm_runtime_put_autosuspend(connector->dev->dev);
1462         }
1463
1464         return ret;
1465 }
1466
1467 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1468                                            struct drm_display_mode *mode)
1469 {
1470         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1471         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1472
1473         /* XXX check mode bandwidth */
1474
1475         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1476             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1477                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1478
1479                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1480                         return MODE_PANEL;
1481
1482                 if (encoder) {
1483                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1484                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1485
1486                         /* AVIVO hardware supports downscaling modes larger than the panel
1487                          * to the panel size, but I'm not sure this is desirable.
1488                          */
1489                         if ((mode->hdisplay > native_mode->hdisplay) ||
1490                             (mode->vdisplay > native_mode->vdisplay))
1491                                 return MODE_PANEL;
1492
1493                         /* if scaling is disabled, block non-native modes */
1494                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1495                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1496                                     (mode->vdisplay != native_mode->vdisplay))
1497                                         return MODE_PANEL;
1498                         }
1499                 }
1500                 return MODE_OK;
1501         } else {
1502                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1503                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1504                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1505                 } else {
1506                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1507                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1508                                 if (mode->clock > 340000)
1509                                         return MODE_CLOCK_HIGH;
1510                         } else {
1511                                 if (mode->clock > 165000)
1512                                         return MODE_CLOCK_HIGH;
1513                         }
1514                 }
1515         }
1516
1517         return MODE_OK;
1518 }
1519
1520 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1521         .get_modes = amdgpu_connector_dp_get_modes,
1522         .mode_valid = amdgpu_connector_dp_mode_valid,
1523         .best_encoder = amdgpu_connector_dvi_encoder,
1524 };
1525
1526 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1527         .dpms = drm_helper_connector_dpms,
1528         .detect = amdgpu_connector_dp_detect,
1529         .fill_modes = drm_helper_probe_single_connector_modes,
1530         .set_property = amdgpu_connector_set_property,
1531         .early_unregister = amdgpu_connector_unregister,
1532         .destroy = amdgpu_connector_destroy,
1533         .force = amdgpu_connector_dvi_force,
1534 };
1535
1536 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1537         .dpms = drm_helper_connector_dpms,
1538         .detect = amdgpu_connector_dp_detect,
1539         .fill_modes = drm_helper_probe_single_connector_modes,
1540         .set_property = amdgpu_connector_set_lcd_property,
1541         .early_unregister = amdgpu_connector_unregister,
1542         .destroy = amdgpu_connector_destroy,
1543         .force = amdgpu_connector_dvi_force,
1544 };
1545
1546 static struct drm_encoder *
1547 amdgpu_connector_virtual_encoder(struct drm_connector *connector)
1548 {
1549         int enc_id = connector->encoder_ids[0];
1550         struct drm_encoder *encoder;
1551         int i;
1552         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1553                 if (connector->encoder_ids[i] == 0)
1554                         break;
1555
1556                 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1557                 if (!encoder)
1558                         continue;
1559
1560                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1561                         return encoder;
1562         }
1563
1564         /* pick the first one */
1565         if (enc_id)
1566                 return drm_encoder_find(connector->dev, enc_id);
1567         return NULL;
1568 }
1569
1570 static int amdgpu_connector_virtual_get_modes(struct drm_connector *connector)
1571 {
1572         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1573
1574         if (encoder) {
1575                 amdgpu_connector_add_common_modes(encoder, connector);
1576         }
1577
1578         return 0;
1579 }
1580
1581 static int amdgpu_connector_virtual_mode_valid(struct drm_connector *connector,
1582                                            struct drm_display_mode *mode)
1583 {
1584         return MODE_OK;
1585 }
1586
1587 static int
1588 amdgpu_connector_virtual_dpms(struct drm_connector *connector, int mode)
1589 {
1590         return 0;
1591 }
1592
1593 static enum drm_connector_status
1594
1595 amdgpu_connector_virtual_detect(struct drm_connector *connector, bool force)
1596 {
1597         return connector_status_connected;
1598 }
1599
1600 static int
1601 amdgpu_connector_virtual_set_property(struct drm_connector *connector,
1602                                   struct drm_property *property,
1603                                   uint64_t val)
1604 {
1605         return 0;
1606 }
1607
1608 static void amdgpu_connector_virtual_force(struct drm_connector *connector)
1609 {
1610         return;
1611 }
1612
1613 static const struct drm_connector_helper_funcs amdgpu_connector_virtual_helper_funcs = {
1614         .get_modes = amdgpu_connector_virtual_get_modes,
1615         .mode_valid = amdgpu_connector_virtual_mode_valid,
1616         .best_encoder = amdgpu_connector_virtual_encoder,
1617 };
1618
1619 static const struct drm_connector_funcs amdgpu_connector_virtual_funcs = {
1620         .dpms = amdgpu_connector_virtual_dpms,
1621         .detect = amdgpu_connector_virtual_detect,
1622         .fill_modes = drm_helper_probe_single_connector_modes,
1623         .set_property = amdgpu_connector_virtual_set_property,
1624         .destroy = amdgpu_connector_destroy,
1625         .force = amdgpu_connector_virtual_force,
1626 };
1627
1628 void
1629 amdgpu_connector_add(struct amdgpu_device *adev,
1630                       uint32_t connector_id,
1631                       uint32_t supported_device,
1632                       int connector_type,
1633                       struct amdgpu_i2c_bus_rec *i2c_bus,
1634                       uint16_t connector_object_id,
1635                       struct amdgpu_hpd *hpd,
1636                       struct amdgpu_router *router)
1637 {
1638         struct drm_device *dev = adev->ddev;
1639         struct drm_connector *connector;
1640         struct amdgpu_connector *amdgpu_connector;
1641         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1642         struct drm_encoder *encoder;
1643         struct amdgpu_encoder *amdgpu_encoder;
1644         uint32_t subpixel_order = SubPixelNone;
1645         bool shared_ddc = false;
1646         bool is_dp_bridge = false;
1647         bool has_aux = false;
1648
1649         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1650                 return;
1651
1652         /* see if we already added it */
1653         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1654                 amdgpu_connector = to_amdgpu_connector(connector);
1655                 if (amdgpu_connector->connector_id == connector_id) {
1656                         amdgpu_connector->devices |= supported_device;
1657                         return;
1658                 }
1659                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1660                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1661                                 amdgpu_connector->shared_ddc = true;
1662                                 shared_ddc = true;
1663                         }
1664                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1665                             (amdgpu_connector->router.router_id == router->router_id)) {
1666                                 amdgpu_connector->shared_ddc = false;
1667                                 shared_ddc = false;
1668                         }
1669                 }
1670         }
1671
1672         /* check if it's a dp bridge */
1673         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1674                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1675                 if (amdgpu_encoder->devices & supported_device) {
1676                         switch (amdgpu_encoder->encoder_id) {
1677                         case ENCODER_OBJECT_ID_TRAVIS:
1678                         case ENCODER_OBJECT_ID_NUTMEG:
1679                                 is_dp_bridge = true;
1680                                 break;
1681                         default:
1682                                 break;
1683                         }
1684                 }
1685         }
1686
1687         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1688         if (!amdgpu_connector)
1689                 return;
1690
1691         connector = &amdgpu_connector->base;
1692
1693         amdgpu_connector->connector_id = connector_id;
1694         amdgpu_connector->devices = supported_device;
1695         amdgpu_connector->shared_ddc = shared_ddc;
1696         amdgpu_connector->connector_object_id = connector_object_id;
1697         amdgpu_connector->hpd = *hpd;
1698
1699         amdgpu_connector->router = *router;
1700         if (router->ddc_valid || router->cd_valid) {
1701                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1702                 if (!amdgpu_connector->router_bus)
1703                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1704         }
1705
1706         if (is_dp_bridge) {
1707                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1708                 if (!amdgpu_dig_connector)
1709                         goto failed;
1710                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1711                 if (i2c_bus->valid) {
1712                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1713                         if (amdgpu_connector->ddc_bus)
1714                                 has_aux = true;
1715                         else
1716                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1717                 }
1718                 switch (connector_type) {
1719                 case DRM_MODE_CONNECTOR_VGA:
1720                 case DRM_MODE_CONNECTOR_DVIA:
1721                 default:
1722                         drm_connector_init(dev, &amdgpu_connector->base,
1723                                            &amdgpu_connector_dp_funcs, connector_type);
1724                         drm_connector_helper_add(&amdgpu_connector->base,
1725                                                  &amdgpu_connector_dp_helper_funcs);
1726                         connector->interlace_allowed = true;
1727                         connector->doublescan_allowed = true;
1728                         amdgpu_connector->dac_load_detect = true;
1729                         drm_object_attach_property(&amdgpu_connector->base.base,
1730                                                       adev->mode_info.load_detect_property,
1731                                                       1);
1732                         drm_object_attach_property(&amdgpu_connector->base.base,
1733                                                    dev->mode_config.scaling_mode_property,
1734                                                    DRM_MODE_SCALE_NONE);
1735                         break;
1736                 case DRM_MODE_CONNECTOR_DVII:
1737                 case DRM_MODE_CONNECTOR_DVID:
1738                 case DRM_MODE_CONNECTOR_HDMIA:
1739                 case DRM_MODE_CONNECTOR_HDMIB:
1740                 case DRM_MODE_CONNECTOR_DisplayPort:
1741                         drm_connector_init(dev, &amdgpu_connector->base,
1742                                            &amdgpu_connector_dp_funcs, connector_type);
1743                         drm_connector_helper_add(&amdgpu_connector->base,
1744                                                  &amdgpu_connector_dp_helper_funcs);
1745                         drm_object_attach_property(&amdgpu_connector->base.base,
1746                                                       adev->mode_info.underscan_property,
1747                                                       UNDERSCAN_OFF);
1748                         drm_object_attach_property(&amdgpu_connector->base.base,
1749                                                       adev->mode_info.underscan_hborder_property,
1750                                                       0);
1751                         drm_object_attach_property(&amdgpu_connector->base.base,
1752                                                       adev->mode_info.underscan_vborder_property,
1753                                                       0);
1754
1755                         drm_object_attach_property(&amdgpu_connector->base.base,
1756                                                    dev->mode_config.scaling_mode_property,
1757                                                    DRM_MODE_SCALE_NONE);
1758
1759                         drm_object_attach_property(&amdgpu_connector->base.base,
1760                                                    adev->mode_info.dither_property,
1761                                                    AMDGPU_FMT_DITHER_DISABLE);
1762
1763                         if (amdgpu_audio != 0) {
1764                                 drm_object_attach_property(&amdgpu_connector->base.base,
1765                                                            adev->mode_info.audio_property,
1766                                                            AMDGPU_AUDIO_AUTO);
1767                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1768                         }
1769
1770                         subpixel_order = SubPixelHorizontalRGB;
1771                         connector->interlace_allowed = true;
1772                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1773                                 connector->doublescan_allowed = true;
1774                         else
1775                                 connector->doublescan_allowed = false;
1776                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1777                                 amdgpu_connector->dac_load_detect = true;
1778                                 drm_object_attach_property(&amdgpu_connector->base.base,
1779                                                               adev->mode_info.load_detect_property,
1780                                                               1);
1781                         }
1782                         break;
1783                 case DRM_MODE_CONNECTOR_LVDS:
1784                 case DRM_MODE_CONNECTOR_eDP:
1785                         drm_connector_init(dev, &amdgpu_connector->base,
1786                                            &amdgpu_connector_edp_funcs, connector_type);
1787                         drm_connector_helper_add(&amdgpu_connector->base,
1788                                                  &amdgpu_connector_dp_helper_funcs);
1789                         drm_object_attach_property(&amdgpu_connector->base.base,
1790                                                       dev->mode_config.scaling_mode_property,
1791                                                       DRM_MODE_SCALE_FULLSCREEN);
1792                         subpixel_order = SubPixelHorizontalRGB;
1793                         connector->interlace_allowed = false;
1794                         connector->doublescan_allowed = false;
1795                         break;
1796                 }
1797         } else {
1798                 switch (connector_type) {
1799                 case DRM_MODE_CONNECTOR_VGA:
1800                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1801                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1802                         if (i2c_bus->valid) {
1803                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1804                                 if (!amdgpu_connector->ddc_bus)
1805                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1806                         }
1807                         amdgpu_connector->dac_load_detect = true;
1808                         drm_object_attach_property(&amdgpu_connector->base.base,
1809                                                       adev->mode_info.load_detect_property,
1810                                                       1);
1811                         drm_object_attach_property(&amdgpu_connector->base.base,
1812                                                    dev->mode_config.scaling_mode_property,
1813                                                    DRM_MODE_SCALE_NONE);
1814                         /* no HPD on analog connectors */
1815                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1816                         connector->interlace_allowed = true;
1817                         connector->doublescan_allowed = true;
1818                         break;
1819                 case DRM_MODE_CONNECTOR_DVIA:
1820                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1821                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1822                         if (i2c_bus->valid) {
1823                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1824                                 if (!amdgpu_connector->ddc_bus)
1825                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1826                         }
1827                         amdgpu_connector->dac_load_detect = true;
1828                         drm_object_attach_property(&amdgpu_connector->base.base,
1829                                                       adev->mode_info.load_detect_property,
1830                                                       1);
1831                         drm_object_attach_property(&amdgpu_connector->base.base,
1832                                                    dev->mode_config.scaling_mode_property,
1833                                                    DRM_MODE_SCALE_NONE);
1834                         /* no HPD on analog connectors */
1835                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1836                         connector->interlace_allowed = true;
1837                         connector->doublescan_allowed = true;
1838                         break;
1839                 case DRM_MODE_CONNECTOR_DVII:
1840                 case DRM_MODE_CONNECTOR_DVID:
1841                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1842                         if (!amdgpu_dig_connector)
1843                                 goto failed;
1844                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1845                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1846                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1847                         if (i2c_bus->valid) {
1848                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1849                                 if (!amdgpu_connector->ddc_bus)
1850                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1851                         }
1852                         subpixel_order = SubPixelHorizontalRGB;
1853                         drm_object_attach_property(&amdgpu_connector->base.base,
1854                                                       adev->mode_info.coherent_mode_property,
1855                                                       1);
1856                         drm_object_attach_property(&amdgpu_connector->base.base,
1857                                                    adev->mode_info.underscan_property,
1858                                                    UNDERSCAN_OFF);
1859                         drm_object_attach_property(&amdgpu_connector->base.base,
1860                                                    adev->mode_info.underscan_hborder_property,
1861                                                    0);
1862                         drm_object_attach_property(&amdgpu_connector->base.base,
1863                                                    adev->mode_info.underscan_vborder_property,
1864                                                    0);
1865                         drm_object_attach_property(&amdgpu_connector->base.base,
1866                                                    dev->mode_config.scaling_mode_property,
1867                                                    DRM_MODE_SCALE_NONE);
1868
1869                         if (amdgpu_audio != 0) {
1870                                 drm_object_attach_property(&amdgpu_connector->base.base,
1871                                                            adev->mode_info.audio_property,
1872                                                            AMDGPU_AUDIO_AUTO);
1873                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1874                         }
1875                         drm_object_attach_property(&amdgpu_connector->base.base,
1876                                                    adev->mode_info.dither_property,
1877                                                    AMDGPU_FMT_DITHER_DISABLE);
1878                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1879                                 amdgpu_connector->dac_load_detect = true;
1880                                 drm_object_attach_property(&amdgpu_connector->base.base,
1881                                                            adev->mode_info.load_detect_property,
1882                                                            1);
1883                         }
1884                         connector->interlace_allowed = true;
1885                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1886                                 connector->doublescan_allowed = true;
1887                         else
1888                                 connector->doublescan_allowed = false;
1889                         break;
1890                 case DRM_MODE_CONNECTOR_HDMIA:
1891                 case DRM_MODE_CONNECTOR_HDMIB:
1892                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1893                         if (!amdgpu_dig_connector)
1894                                 goto failed;
1895                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1896                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1897                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1898                         if (i2c_bus->valid) {
1899                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1900                                 if (!amdgpu_connector->ddc_bus)
1901                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1902                         }
1903                         drm_object_attach_property(&amdgpu_connector->base.base,
1904                                                       adev->mode_info.coherent_mode_property,
1905                                                       1);
1906                         drm_object_attach_property(&amdgpu_connector->base.base,
1907                                                    adev->mode_info.underscan_property,
1908                                                    UNDERSCAN_OFF);
1909                         drm_object_attach_property(&amdgpu_connector->base.base,
1910                                                    adev->mode_info.underscan_hborder_property,
1911                                                    0);
1912                         drm_object_attach_property(&amdgpu_connector->base.base,
1913                                                    adev->mode_info.underscan_vborder_property,
1914                                                    0);
1915                         drm_object_attach_property(&amdgpu_connector->base.base,
1916                                                    dev->mode_config.scaling_mode_property,
1917                                                    DRM_MODE_SCALE_NONE);
1918                         if (amdgpu_audio != 0) {
1919                                 drm_object_attach_property(&amdgpu_connector->base.base,
1920                                                            adev->mode_info.audio_property,
1921                                                            AMDGPU_AUDIO_AUTO);
1922                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1923                         }
1924                         drm_object_attach_property(&amdgpu_connector->base.base,
1925                                                    adev->mode_info.dither_property,
1926                                                    AMDGPU_FMT_DITHER_DISABLE);
1927                         subpixel_order = SubPixelHorizontalRGB;
1928                         connector->interlace_allowed = true;
1929                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1930                                 connector->doublescan_allowed = true;
1931                         else
1932                                 connector->doublescan_allowed = false;
1933                         break;
1934                 case DRM_MODE_CONNECTOR_DisplayPort:
1935                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1936                         if (!amdgpu_dig_connector)
1937                                 goto failed;
1938                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1939                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1940                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1941                         if (i2c_bus->valid) {
1942                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1943                                 if (amdgpu_connector->ddc_bus)
1944                                         has_aux = true;
1945                                 else
1946                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1947                         }
1948                         subpixel_order = SubPixelHorizontalRGB;
1949                         drm_object_attach_property(&amdgpu_connector->base.base,
1950                                                       adev->mode_info.coherent_mode_property,
1951                                                       1);
1952                         drm_object_attach_property(&amdgpu_connector->base.base,
1953                                                    adev->mode_info.underscan_property,
1954                                                    UNDERSCAN_OFF);
1955                         drm_object_attach_property(&amdgpu_connector->base.base,
1956                                                    adev->mode_info.underscan_hborder_property,
1957                                                    0);
1958                         drm_object_attach_property(&amdgpu_connector->base.base,
1959                                                    adev->mode_info.underscan_vborder_property,
1960                                                    0);
1961                         drm_object_attach_property(&amdgpu_connector->base.base,
1962                                                    dev->mode_config.scaling_mode_property,
1963                                                    DRM_MODE_SCALE_NONE);
1964                         if (amdgpu_audio != 0) {
1965                                 drm_object_attach_property(&amdgpu_connector->base.base,
1966                                                            adev->mode_info.audio_property,
1967                                                            AMDGPU_AUDIO_AUTO);
1968                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1969                         }
1970                         drm_object_attach_property(&amdgpu_connector->base.base,
1971                                                    adev->mode_info.dither_property,
1972                                                    AMDGPU_FMT_DITHER_DISABLE);
1973                         connector->interlace_allowed = true;
1974                         /* in theory with a DP to VGA converter... */
1975                         connector->doublescan_allowed = false;
1976                         break;
1977                 case DRM_MODE_CONNECTOR_eDP:
1978                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1979                         if (!amdgpu_dig_connector)
1980                                 goto failed;
1981                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1982                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1983                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1984                         if (i2c_bus->valid) {
1985                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1986                                 if (amdgpu_connector->ddc_bus)
1987                                         has_aux = true;
1988                                 else
1989                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1990                         }
1991                         drm_object_attach_property(&amdgpu_connector->base.base,
1992                                                       dev->mode_config.scaling_mode_property,
1993                                                       DRM_MODE_SCALE_FULLSCREEN);
1994                         subpixel_order = SubPixelHorizontalRGB;
1995                         connector->interlace_allowed = false;
1996                         connector->doublescan_allowed = false;
1997                         break;
1998                 case DRM_MODE_CONNECTOR_LVDS:
1999                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
2000                         if (!amdgpu_dig_connector)
2001                                 goto failed;
2002                         amdgpu_connector->con_priv = amdgpu_dig_connector;
2003                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
2004                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
2005                         if (i2c_bus->valid) {
2006                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
2007                                 if (!amdgpu_connector->ddc_bus)
2008                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2009                         }
2010                         drm_object_attach_property(&amdgpu_connector->base.base,
2011                                                       dev->mode_config.scaling_mode_property,
2012                                                       DRM_MODE_SCALE_FULLSCREEN);
2013                         subpixel_order = SubPixelHorizontalRGB;
2014                         connector->interlace_allowed = false;
2015                         connector->doublescan_allowed = false;
2016                         break;
2017                 case DRM_MODE_CONNECTOR_VIRTUAL:
2018                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
2019                         if (!amdgpu_dig_connector)
2020                                 goto failed;
2021                         amdgpu_connector->con_priv = amdgpu_dig_connector;
2022                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_virtual_funcs, connector_type);
2023                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_virtual_helper_funcs);
2024                         subpixel_order = SubPixelHorizontalRGB;
2025                         connector->interlace_allowed = false;
2026                         connector->doublescan_allowed = false;
2027                         break;
2028                 }
2029         }
2030
2031         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
2032                 if (i2c_bus->valid) {
2033                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2034                                             DRM_CONNECTOR_POLL_DISCONNECT;
2035                 }
2036         } else
2037                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2038
2039         connector->display_info.subpixel_order = subpixel_order;
2040         drm_connector_register(connector);
2041
2042         if (has_aux)
2043                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
2044
2045         return;
2046
2047 failed:
2048         drm_connector_cleanup(connector);
2049         kfree(connector);
2050 }