drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  34                        u32 ip_instance, u32 ring,
  35                        struct amdgpu_ring **out_ring)
  36 {
  37         /* Right now all IPs have only one instance - multiple rings. */
  38         if (ip_instance != 0) {
  39                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  40                 return -EINVAL;
  41         }
  42
  43         switch (ip_type) {
  44         default:
  45                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  46                 return -EINVAL;
  47         case AMDGPU_HW_IP_GFX:
  48                 if (ring < adev->gfx.num_gfx_rings) {
  49                         *out_ring = &adev->gfx.gfx_ring[ring];
  50                 } else {
  51                         DRM_ERROR("only %d gfx rings are supported now\n",
  52                                   adev->gfx.num_gfx_rings);
  53                         return -EINVAL;
  54                 }
  55                 break;
  56         case AMDGPU_HW_IP_COMPUTE:
  57                 if (ring < adev->gfx.num_compute_rings) {
  58                         *out_ring = &adev->gfx.compute_ring[ring];
  59                 } else {
  60                         DRM_ERROR("only %d compute rings are supported now\n",
  61                                   adev->gfx.num_compute_rings);
  62                         return -EINVAL;
  63                 }
  64                 break;
  65         case AMDGPU_HW_IP_DMA:
  66                 if (ring < adev->sdma.num_instances) {
  67                         *out_ring = &adev->sdma.instance[ring].ring;
  68                 } else {
  69                         DRM_ERROR("only %d SDMA rings are supported\n",
  70                                   adev->sdma.num_instances);
  71                         return -EINVAL;
  72                 }
  73                 break;
  74         case AMDGPU_HW_IP_UVD:
  75                 *out_ring = &adev->uvd.ring;
  76                 break;
  77         case AMDGPU_HW_IP_VCE:
  78                 if (ring < 2){
  79                         *out_ring = &adev->vce.ring[ring];
  80                 } else {
  81                         DRM_ERROR("only two VCE rings are supported\n");
  82                         return -EINVAL;
  83                 }
  84                 break;
  85         }
  86
  87         if (!(*out_ring && (*out_ring)->adev)) {
  88                 DRM_ERROR("Ring %d is not initialized on IP %d\n",
  89                           ring, ip_type);
  90                 return -EINVAL;
  91         }
  92
  93         return 0;
  94 }
  95
  96 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  97                                       struct drm_amdgpu_cs_chunk_fence *data,
  98                                       uint32_t *offset)
  99 {
 100         struct drm_gem_object *gobj;
 101         unsigned long size;
 102
 103         gobj = drm_gem_object_lookup(p->filp, data->handle);
 104         if (gobj == NULL)
 105                 return -EINVAL;
 106
 107         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
 108         p->uf_entry.priority = 0;
 109         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
 110         p->uf_entry.tv.shared = true;
 111         p->uf_entry.user_pages = NULL;
 112
 113         size = amdgpu_bo_size(p->uf_entry.robj);
 114         if (size != PAGE_SIZE || (data->offset + 8) > size)
 115                 return -EINVAL;
 116
 117         *offset = data->offset;
 118
 119         drm_gem_object_unreference_unlocked(gobj);
 120
 121         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
 122                 amdgpu_bo_unref(&p->uf_entry.robj);
 123                 return -EINVAL;
 124         }
 125
 126         return 0;
 127 }
 128
 129 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 130 {
 131         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 132         struct amdgpu_vm *vm = &fpriv->vm;
 133         union drm_amdgpu_cs *cs = data;
 134         uint64_t *chunk_array_user;
 135         uint64_t *chunk_array;
 136         unsigned size, num_ibs = 0;
 137         uint32_t uf_offset = 0;
 138         int i;
 139         int ret;
 140
 141         if (cs->in.num_chunks == 0)
 142                 return 0;
 143
 144         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 145         if (!chunk_array)
 146                 return -ENOMEM;
 147
 148         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 149         if (!p->ctx) {
 150                 ret = -EINVAL;
 151                 goto free_chunk;
 152         }
 153
 154         /* get chunks */
 155         chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
 156         if (copy_from_user(chunk_array, chunk_array_user,
 157                            sizeof(uint64_t)*cs->in.num_chunks)) {
 158                 ret = -EFAULT;
 159                 goto put_ctx;
 160         }
 161
 162         p->nchunks = cs->in.num_chunks;
 163         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 164                             GFP_KERNEL);
 165         if (!p->chunks) {
 166                 ret = -ENOMEM;
 167                 goto put_ctx;
 168         }
 169
 170         for (i = 0; i < p->nchunks; i++) {
 171                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 172                 struct drm_amdgpu_cs_chunk user_chunk;
 173                 uint32_t __user *cdata;
 174
 175                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 176                 if (copy_from_user(&user_chunk, chunk_ptr,
 177                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 178                         ret = -EFAULT;
 179                         i--;
 180                         goto free_partial_kdata;
 181                 }
 182                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 183                 p->chunks[i].length_dw = user_chunk.length_dw;
 184
 185                 size = p->chunks[i].length_dw;
 186                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 187
 188                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 189                 if (p->chunks[i].kdata == NULL) {
 190                         ret = -ENOMEM;
 191                         i--;
 192                         goto free_partial_kdata;
 193                 }
 194                 size *= sizeof(uint32_t);
 195                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 196                         ret = -EFAULT;
 197                         goto free_partial_kdata;
 198                 }
 199
 200                 switch (p->chunks[i].chunk_id) {
 201                 case AMDGPU_CHUNK_ID_IB:
 202                         ++num_ibs;
 203                         break;
 204
 205                 case AMDGPU_CHUNK_ID_FENCE:
 206                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 207                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 208                                 ret = -EINVAL;
 209                                 goto free_partial_kdata;
 210                         }
 211
 212                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 213                                                          &uf_offset);
 214                         if (ret)
 215                                 goto free_partial_kdata;
 216
 217                         break;
 218
 219                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 220                         break;
 221
 222                 default:
 223                         ret = -EINVAL;
 224                         goto free_partial_kdata;
 225                 }
 226         }
 227
 228         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 229         if (ret)
 230                 goto free_all_kdata;
 231
 232         if (p->uf_entry.robj)
 233                 p->job->uf_addr = uf_offset;
 234         kfree(chunk_array);
 235         return 0;
 236
 237 free_all_kdata:
 238         i = p->nchunks - 1;
 239 free_partial_kdata:
 240         for (; i >= 0; i--)
 241                 drm_free_large(p->chunks[i].kdata);
 242         kfree(p->chunks);
 243         p->chunks = NULL;
 244         p->nchunks = 0;
 245 put_ctx:
 246         amdgpu_ctx_put(p->ctx);
 247 free_chunk:
 248         kfree(chunk_array);
 249
 250         return ret;
 251 }
 252
 253 /* Convert microseconds to bytes. */
 254 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 255 {
 256         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 257                 return 0;
 258
 259         /* Since accum_us is incremented by a million per second, just
 260          * multiply it by the number of MB/s to get the number of bytes.
 261          */
 262         return us << adev->mm_stats.log2_max_MBps;
 263 }
 264
 265 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 266 {
 267         if (!adev->mm_stats.log2_max_MBps)
 268                 return 0;
 269
 270         return bytes >> adev->mm_stats.log2_max_MBps;
 271 }
 272
 273 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 274  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 275  * which means it can go over the threshold once. If that happens, the driver
 276  * will be in debt and no other buffer migrations can be done until that debt
 277  * is repaid.
 278  *
 279  * This approach allows moving a buffer of any size (it's important to allow
 280  * that).
 281  *
 282  * The currency is simply time in microseconds and it increases as the clock
 283  * ticks. The accumulated microseconds (us) are converted to bytes and
 284  * returned.
 285  */
 286 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 287 {
 288         s64 time_us, increment_us;
 289         u64 max_bytes;
 290         u64 free_vram, total_vram, used_vram;
 291
 292         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 293          * throttling.
 294          *
 295          * It means that in order to get full max MBps, at least 5 IBs per
 296          * second must be submitted and not more than 200ms apart from each
 297          * other.
 298          */
 299         const s64 us_upper_bound = 200000;
 300
 301         if (!adev->mm_stats.log2_max_MBps)
 302                 return 0;
 303
 304         total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
 305         used_vram = atomic64_read(&adev->vram_usage);
 306         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 307
 308         spin_lock(&adev->mm_stats.lock);
 309
 310         /* Increase the amount of accumulated us. */
 311         time_us = ktime_to_us(ktime_get());
 312         increment_us = time_us - adev->mm_stats.last_update_us;
 313         adev->mm_stats.last_update_us = time_us;
 314         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 315                                       us_upper_bound);
 316
 317         /* This prevents the short period of low performance when the VRAM
 318          * usage is low and the driver is in debt or doesn't have enough
 319          * accumulated us to fill VRAM quickly.
 320          *
 321          * The situation can occur in these cases:
 322          * - a lot of VRAM is freed by userspace
 323          * - the presence of a big buffer causes a lot of evictions
 324          *   (solution: split buffers into smaller ones)
 325          *
 326          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 327          * accum_us to a positive number.
 328          */
 329         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 330                 s64 min_us;
 331
 332                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 333                  * VRAM now.
 334                  */
 335                 if (!(adev->flags & AMD_IS_APU))
 336                         min_us = bytes_to_us(adev, free_vram / 4);
 337                 else
 338                         min_us = 0; /* Reset accum_us on APUs. */
 339
 340                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 341         }
 342
 343         /* This returns 0 if the driver is in debt to disallow (optional)
 344          * buffer moves.
 345          */
 346         max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 347
 348         spin_unlock(&adev->mm_stats.lock);
 349         return max_bytes;
 350 }
 351
 352 /* Report how many bytes have really been moved for the last command
 353  * submission. This can result in a debt that can stop buffer migrations
 354  * temporarily.
 355  */
 356 static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev,
 357                                          u64 num_bytes)
 358 {
 359         spin_lock(&adev->mm_stats.lock);
 360         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 361         spin_unlock(&adev->mm_stats.lock);
 362 }
 363
 364 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 365                                  struct amdgpu_bo *bo)
 366 {
 367         u64 initial_bytes_moved;
 368         uint32_t domain;
 369         int r;
 370
 371         if (bo->pin_count)
 372                 return 0;
 373
 374         /* Don't move this buffer if we have depleted our allowance
 375          * to move it. Don't move anything if the threshold is zero.
 376          */
 377         if (p->bytes_moved < p->bytes_moved_threshold)
 378                 domain = bo->prefered_domains;
 379         else
 380                 domain = bo->allowed_domains;
 381
 382 retry:
 383         amdgpu_ttm_placement_from_domain(bo, domain);
 384         initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
 385         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 386         p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
 387                 initial_bytes_moved;
 388
 389         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 390                 domain = bo->allowed_domains;
 391                 goto retry;
 392         }
 393
 394         return r;
 395 }
 396
 397 /* Last resort, try to evict something from the current working set */
 398 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 399                                 struct amdgpu_bo_list_entry *lobj)
 400 {
 401         uint32_t domain = lobj->robj->allowed_domains;
 402         int r;
 403
 404         if (!p->evictable)
 405                 return false;
 406
 407         for (;&p->evictable->tv.head != &p->validated;
 408              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 409
 410                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 411                 struct amdgpu_bo *bo = candidate->robj;
 412                 u64 initial_bytes_moved;
 413                 uint32_t other;
 414
 415                 /* If we reached our current BO we can forget it */
 416                 if (candidate == lobj)
 417                         break;
 418
 419                 /* We can't move pinned BOs here */
 420                 if (bo->pin_count)
 421                         continue;
 422
 423                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 424
 425                 /* Check if this BO is in one of the domains we need space for */
 426                 if (!(other & domain))
 427                         continue;
 428
 429                 /* Check if we can move this BO somewhere else */
 430                 other = bo->allowed_domains & ~domain;
 431                 if (!other)
 432                         continue;
 433
 434                 /* Good we can try to move this BO somewhere else */
 435                 amdgpu_ttm_placement_from_domain(bo, other);
 436                 initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
 437                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 438                 p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
 439                         initial_bytes_moved;
 440
 441                 if (unlikely(r))
 442                         break;
 443
 444                 p->evictable = list_prev_entry(p->evictable, tv.head);
 445                 list_move(&candidate->tv.head, &p->validated);
 446
 447                 return true;
 448         }
 449
 450         return false;
 451 }
 452
 453 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 454                             struct list_head *validated)
 455 {
 456         struct amdgpu_bo_list_entry *lobj;
 457         int r;
 458
 459         list_for_each_entry(lobj, validated, tv.head) {
 460                 struct amdgpu_bo *bo = lobj->robj;
 461                 bool binding_userptr = false;
 462                 struct mm_struct *usermm;
 463
 464                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 465                 if (usermm && usermm != current->mm)
 466                         return -EPERM;
 467
 468                 /* Check if we have user pages and nobody bound the BO already */
 469                 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
 470                         size_t size = sizeof(struct page *);
 471
 472                         size *= bo->tbo.ttm->num_pages;
 473                         memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
 474                         binding_userptr = true;
 475                 }
 476
 477                 if (p->evictable == lobj)
 478                         p->evictable = NULL;
 479
 480                 do {
 481                         r = amdgpu_cs_bo_validate(p, bo);
 482                 } while (r == -ENOMEM && amdgpu_cs_try_evict(p, lobj));
 483                 if (r)
 484                         return r;
 485
 486                 if (bo->shadow) {
 487                         r = amdgpu_cs_bo_validate(p, bo);
 488                         if (r)
 489                                 return r;
 490                 }
 491
 492                 if (binding_userptr) {
 493                         drm_free_large(lobj->user_pages);
 494                         lobj->user_pages = NULL;
 495                 }
 496         }
 497         return 0;
 498 }
 499
 500 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 501                                 union drm_amdgpu_cs *cs)
 502 {
 503         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 504         struct amdgpu_bo_list_entry *e;
 505         struct list_head duplicates;
 506         bool need_mmap_lock = false;
 507         unsigned i, tries = 10;
 508         int r;
 509
 510         INIT_LIST_HEAD(&p->validated);
 511
 512         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 513         if (p->bo_list) {
 514                 need_mmap_lock = p->bo_list->first_userptr !=
 515                         p->bo_list->num_entries;
 516                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 517         }
 518
 519         INIT_LIST_HEAD(&duplicates);
 520         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 521
 522         if (p->uf_entry.robj && !p->uf_entry.robj->parent)
 523                 list_add(&p->uf_entry.tv.head, &p->validated);
 524
 525         if (need_mmap_lock)
 526                 down_read(&current->mm->mmap_sem);
 527
 528         while (1) {
 529                 struct list_head need_pages;
 530                 unsigned i;
 531
 532                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 533                                            &duplicates);
 534                 if (unlikely(r != 0)) {
 535                         if (r != -ERESTARTSYS)
 536                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 537                         goto error_free_pages;
 538                 }
 539
 540                 /* Without a BO list we don't have userptr BOs */
 541                 if (!p->bo_list)
 542                         break;
 543
 544                 INIT_LIST_HEAD(&need_pages);
 545                 for (i = p->bo_list->first_userptr;
 546                      i < p->bo_list->num_entries; ++i) {
 547
 548                         e = &p->bo_list->array[i];
 549
 550                         if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
 551                                  &e->user_invalidated) && e->user_pages) {
 552
 553                                 /* We acquired a page array, but somebody
 554                                  * invalidated it. Free it an try again
 555                                  */
 556                                 release_pages(e->user_pages,
 557                                               e->robj->tbo.ttm->num_pages,
 558                                               false);
 559                                 drm_free_large(e->user_pages);
 560                                 e->user_pages = NULL;
 561                         }
 562
 563                         if (e->robj->tbo.ttm->state != tt_bound &&
 564                             !e->user_pages) {
 565                                 list_del(&e->tv.head);
 566                                 list_add(&e->tv.head, &need_pages);
 567
 568                                 amdgpu_bo_unreserve(e->robj);
 569                         }
 570                 }
 571
 572                 if (list_empty(&need_pages))
 573                         break;
 574
 575                 /* Unreserve everything again. */
 576                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 577
 578                 /* We tried too many times, just abort */
 579                 if (!--tries) {
 580                         r = -EDEADLK;
 581                         DRM_ERROR("deadlock in %s\n", __func__);
 582                         goto error_free_pages;
 583                 }
 584
 585                 /* Fill the page arrays for all useptrs. */
 586                 list_for_each_entry(e, &need_pages, tv.head) {
 587                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 588
 589                         e->user_pages = drm_calloc_large(ttm->num_pages,
 590                                                          sizeof(struct page*));
 591                         if (!e->user_pages) {
 592                                 r = -ENOMEM;
 593                                 DRM_ERROR("calloc failure in %s\n", __func__);
 594                                 goto error_free_pages;
 595                         }
 596
 597                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 598                         if (r) {
 599                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 600                                 drm_free_large(e->user_pages);
 601                                 e->user_pages = NULL;
 602                                 goto error_free_pages;
 603                         }
 604                 }
 605
 606                 /* And try again. */
 607                 list_splice(&need_pages, &p->validated);
 608         }
 609
 610         amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates);
 611
 612         p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
 613         p->bytes_moved = 0;
 614         p->evictable = list_last_entry(&p->validated,
 615                                        struct amdgpu_bo_list_entry,
 616                                        tv.head);
 617
 618         r = amdgpu_cs_list_validate(p, &duplicates);
 619         if (r) {
 620                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 621                 goto error_validate;
 622         }
 623
 624         r = amdgpu_cs_list_validate(p, &p->validated);
 625         if (r) {
 626                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 627                 goto error_validate;
 628         }
 629
 630         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved);
 631
 632         fpriv->vm.last_eviction_counter =
 633                 atomic64_read(&p->adev->num_evictions);
 634
 635         if (p->bo_list) {
 636                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 637                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 638                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 639                 struct amdgpu_vm *vm = &fpriv->vm;
 640                 unsigned i;
 641
 642                 for (i = 0; i < p->bo_list->num_entries; i++) {
 643                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 644
 645                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 646                 }
 647
 648                 if (gds) {
 649                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 650                         p->job->gds_size = amdgpu_bo_size(gds);
 651                 }
 652                 if (gws) {
 653                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 654                         p->job->gws_size = amdgpu_bo_size(gws);
 655                 }
 656                 if (oa) {
 657                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 658                         p->job->oa_size = amdgpu_bo_size(oa);
 659                 }
 660         }
 661
 662         if (!r && p->uf_entry.robj) {
 663                 struct amdgpu_bo *uf = p->uf_entry.robj;
 664
 665                 r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
 666                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 667         }
 668
 669 error_validate:
 670         if (r) {
 671                 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
 672                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 673         }
 674
 675 error_free_pages:
 676
 677         if (need_mmap_lock)
 678                 up_read(&current->mm->mmap_sem);
 679
 680         if (p->bo_list) {
 681                 for (i = p->bo_list->first_userptr;
 682                      i < p->bo_list->num_entries; ++i) {
 683                         e = &p->bo_list->array[i];
 684
 685                         if (!e->user_pages)
 686                                 continue;
 687
 688                         release_pages(e->user_pages,
 689                                       e->robj->tbo.ttm->num_pages,
 690                                       false);
 691                         drm_free_large(e->user_pages);
 692                 }
 693         }
 694
 695         return r;
 696 }
 697
 698 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 699 {
 700         struct amdgpu_bo_list_entry *e;
 701         int r;
 702
 703         list_for_each_entry(e, &p->validated, tv.head) {
 704                 struct reservation_object *resv = e->robj->tbo.resv;
 705                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
 706
 707                 if (r)
 708                         return r;
 709         }
 710         return 0;
 711 }
 712
 713 /**
 714  * cs_parser_fini() - clean parser states
 715  * @parser:     parser structure holding parsing context.
 716  * @error:      error number
 717  *
 718  * If error is set than unvalidate buffer, otherwise just free memory
 719  * used by parsing context.
 720  **/
 721 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 722 {
 723         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 724         unsigned i;
 725
 726         if (!error) {
 727                 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
 728
 729                 ttm_eu_fence_buffer_objects(&parser->ticket,
 730                                             &parser->validated,
 731                                             parser->fence);
 732         } else if (backoff) {
 733                 ttm_eu_backoff_reservation(&parser->ticket,
 734                                            &parser->validated);
 735         }
 736         fence_put(parser->fence);
 737
 738         if (parser->ctx)
 739                 amdgpu_ctx_put(parser->ctx);
 740         if (parser->bo_list)
 741                 amdgpu_bo_list_put(parser->bo_list);
 742
 743         for (i = 0; i < parser->nchunks; i++)
 744                 drm_free_large(parser->chunks[i].kdata);
 745         kfree(parser->chunks);
 746         if (parser->job)
 747                 amdgpu_job_free(parser->job);
 748         amdgpu_bo_unref(&parser->uf_entry.robj);
 749 }
 750
 751 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 752                                    struct amdgpu_vm *vm)
 753 {
 754         struct amdgpu_device *adev = p->adev;
 755         struct amdgpu_bo_va *bo_va;
 756         struct amdgpu_bo *bo;
 757         int i, r;
 758
 759         r = amdgpu_vm_update_page_directory(adev, vm);
 760         if (r)
 761                 return r;
 762
 763         r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
 764         if (r)
 765                 return r;
 766
 767         r = amdgpu_vm_clear_freed(adev, vm);
 768         if (r)
 769                 return r;
 770
 771         if (p->bo_list) {
 772                 for (i = 0; i < p->bo_list->num_entries; i++) {
 773                         struct fence *f;
 774
 775                         /* ignore duplicates */
 776                         bo = p->bo_list->array[i].robj;
 777                         if (!bo)
 778                                 continue;
 779
 780                         bo_va = p->bo_list->array[i].bo_va;
 781                         if (bo_va == NULL)
 782                                 continue;
 783
 784                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 785                         if (r)
 786                                 return r;
 787
 788                         f = bo_va->last_pt_update;
 789                         r = amdgpu_sync_fence(adev, &p->job->sync, f);
 790                         if (r)
 791                                 return r;
 792                 }
 793
 794         }
 795
 796         r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
 797
 798         if (amdgpu_vm_debug && p->bo_list) {
 799                 /* Invalidate all BOs to test for userspace bugs */
 800                 for (i = 0; i < p->bo_list->num_entries; i++) {
 801                         /* ignore duplicates */
 802                         bo = p->bo_list->array[i].robj;
 803                         if (!bo)
 804                                 continue;
 805
 806                         amdgpu_vm_bo_invalidate(adev, bo);
 807                 }
 808         }
 809
 810         return r;
 811 }
 812
 813 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 814                                  struct amdgpu_cs_parser *p)
 815 {
 816         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 817         struct amdgpu_vm *vm = &fpriv->vm;
 818         struct amdgpu_ring *ring = p->job->ring;
 819         int i, r;
 820
 821         /* Only for UVD/VCE VM emulation */
 822         if (ring->funcs->parse_cs) {
 823                 p->job->vm = NULL;
 824                 for (i = 0; i < p->job->num_ibs; i++) {
 825                         r = amdgpu_ring_parse_cs(ring, p, i);
 826                         if (r)
 827                                 return r;
 828                 }
 829         } else {
 830                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
 831
 832                 r = amdgpu_bo_vm_update_pte(p, vm);
 833                 if (r)
 834                         return r;
 835         }
 836
 837         return amdgpu_cs_sync_rings(p);
 838 }
 839
 840 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 841 {
 842         if (r == -EDEADLK) {
 843                 r = amdgpu_gpu_reset(adev);
 844                 if (!r)
 845                         r = -EAGAIN;
 846         }
 847         return r;
 848 }
 849
 850 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 851                              struct amdgpu_cs_parser *parser)
 852 {
 853         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 854         struct amdgpu_vm *vm = &fpriv->vm;
 855         int i, j;
 856         int r;
 857
 858         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 859                 struct amdgpu_cs_chunk *chunk;
 860                 struct amdgpu_ib *ib;
 861                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 862                 struct amdgpu_ring *ring;
 863
 864                 chunk = &parser->chunks[i];
 865                 ib = &parser->job->ibs[j];
 866                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 867
 868                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 869                         continue;
 870
 871                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 872                                        chunk_ib->ip_instance, chunk_ib->ring,
 873                                        &ring);
 874                 if (r)
 875                         return r;
 876
 877                 if (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 878                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 879                         if (!parser->ctx->preamble_presented) {
 880                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 881                                 parser->ctx->preamble_presented = true;
 882                         }
 883                 }
 884
 885                 if (parser->job->ring && parser->job->ring != ring)
 886                         return -EINVAL;
 887
 888                 parser->job->ring = ring;
 889
 890                 if (ring->funcs->parse_cs) {
 891                         struct amdgpu_bo_va_mapping *m;
 892                         struct amdgpu_bo *aobj = NULL;
 893                         uint64_t offset;
 894                         uint8_t *kptr;
 895
 896                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 897                                                    &aobj);
 898                         if (!aobj) {
 899                                 DRM_ERROR("IB va_start is invalid\n");
 900                                 return -EINVAL;
 901                         }
 902
 903                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 904                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 905                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 906                                 return -EINVAL;
 907                         }
 908
 909                         /* the IB should be reserved at this point */
 910                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 911                         if (r) {
 912                                 return r;
 913                         }
 914
 915                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 916                         kptr += chunk_ib->va_start - offset;
 917
 918                         r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
 919                         if (r) {
 920                                 DRM_ERROR("Failed to get ib !\n");
 921                                 return r;
 922                         }
 923
 924                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 925                         amdgpu_bo_kunmap(aobj);
 926                 } else {
 927                         r =  amdgpu_ib_get(adev, vm, 0, ib);
 928                         if (r) {
 929                                 DRM_ERROR("Failed to get ib !\n");
 930                                 return r;
 931                         }
 932
 933                         ib->gpu_addr = chunk_ib->va_start;
 934                 }
 935
 936                 ib->length_dw = chunk_ib->ib_bytes / 4;
 937                 ib->flags = chunk_ib->flags;
 938                 j++;
 939         }
 940
 941         /* UVD & VCE fw doesn't support user fences */
 942         if (parser->job->uf_addr && (
 943             parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
 944             parser->job->ring->type == AMDGPU_RING_TYPE_VCE))
 945                 return -EINVAL;
 946
 947         return 0;
 948 }
 949
 950 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 951                                   struct amdgpu_cs_parser *p)
 952 {
 953         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 954         int i, j, r;
 955
 956         for (i = 0; i < p->nchunks; ++i) {
 957                 struct drm_amdgpu_cs_chunk_dep *deps;
 958                 struct amdgpu_cs_chunk *chunk;
 959                 unsigned num_deps;
 960
 961                 chunk = &p->chunks[i];
 962
 963                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 964                         continue;
 965
 966                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 967                 num_deps = chunk->length_dw * 4 /
 968                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 969
 970                 for (j = 0; j < num_deps; ++j) {
 971                         struct amdgpu_ring *ring;
 972                         struct amdgpu_ctx *ctx;
 973                         struct fence *fence;
 974
 975                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 976                                                deps[j].ip_instance,
 977                                                deps[j].ring, &ring);
 978                         if (r)
 979                                 return r;
 980
 981                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 982                         if (ctx == NULL)
 983                                 return -EINVAL;
 984
 985                         fence = amdgpu_ctx_get_fence(ctx, ring,
 986                                                      deps[j].handle);
 987                         if (IS_ERR(fence)) {
 988                                 r = PTR_ERR(fence);
 989                                 amdgpu_ctx_put(ctx);
 990                                 return r;
 991
 992                         } else if (fence) {
 993                                 r = amdgpu_sync_fence(adev, &p->job->sync,
 994                                                       fence);
 995                                 fence_put(fence);
 996                                 amdgpu_ctx_put(ctx);
 997                                 if (r)
 998                                         return r;
 999                         }
1000                 }
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1007                             union drm_amdgpu_cs *cs)
1008 {
1009         struct amdgpu_ring *ring = p->job->ring;
1010         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1011         struct amdgpu_job *job;
1012         int r;
1013
1014         job = p->job;
1015         p->job = NULL;
1016
1017         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1018         if (r) {
1019                 amdgpu_job_free(job);
1020                 return r;
1021         }
1022
1023         job->owner = p->filp;
1024         job->fence_ctx = entity->fence_context;
1025         p->fence = fence_get(&job->base.s_fence->finished);
1026         cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
1027         job->uf_sequence = cs->out.handle;
1028         amdgpu_job_free_resources(job);
1029
1030         trace_amdgpu_cs_ioctl(job);
1031         amd_sched_entity_push_job(&job->base);
1032
1033         return 0;
1034 }
1035
1036 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1037 {
1038         struct amdgpu_device *adev = dev->dev_private;
1039         union drm_amdgpu_cs *cs = data;
1040         struct amdgpu_cs_parser parser = {};
1041         bool reserved_buffers = false;
1042         int i, r;
1043
1044         if (!adev->accel_working)
1045                 return -EBUSY;
1046
1047         parser.adev = adev;
1048         parser.filp = filp;
1049
1050         r = amdgpu_cs_parser_init(&parser, data);
1051         if (r) {
1052                 DRM_ERROR("Failed to initialize parser !\n");
1053                 amdgpu_cs_parser_fini(&parser, r, false);
1054                 r = amdgpu_cs_handle_lockup(adev, r);
1055                 return r;
1056         }
1057         r = amdgpu_cs_parser_bos(&parser, data);
1058         if (r == -ENOMEM)
1059                 DRM_ERROR("Not enough memory for command submission!\n");
1060         else if (r && r != -ERESTARTSYS)
1061                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1062         else if (!r) {
1063                 reserved_buffers = true;
1064                 r = amdgpu_cs_ib_fill(adev, &parser);
1065         }
1066
1067         if (!r) {
1068                 r = amdgpu_cs_dependencies(adev, &parser);
1069                 if (r)
1070                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1071         }
1072
1073         if (r)
1074                 goto out;
1075
1076         for (i = 0; i < parser.job->num_ibs; i++)
1077                 trace_amdgpu_cs(&parser, i);
1078
1079         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1080         if (r)
1081                 goto out;
1082
1083         r = amdgpu_cs_submit(&parser, cs);
1084
1085 out:
1086         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1087         r = amdgpu_cs_handle_lockup(adev, r);
1088         return r;
1089 }
1090
1091 /**
1092  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1093  *
1094  * @dev: drm device
1095  * @data: data from userspace
1096  * @filp: file private
1097  *
1098  * Wait for the command submission identified by handle to finish.
1099  */
1100 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1101                          struct drm_file *filp)
1102 {
1103         union drm_amdgpu_wait_cs *wait = data;
1104         struct amdgpu_device *adev = dev->dev_private;
1105         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1106         struct amdgpu_ring *ring = NULL;
1107         struct amdgpu_ctx *ctx;
1108         struct fence *fence;
1109         long r;
1110
1111         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
1112                                wait->in.ring, &ring);
1113         if (r)
1114                 return r;
1115
1116         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1117         if (ctx == NULL)
1118                 return -EINVAL;
1119
1120         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1121         if (IS_ERR(fence))
1122                 r = PTR_ERR(fence);
1123         else if (fence) {
1124                 r = fence_wait_timeout(fence, true, timeout);
1125                 fence_put(fence);
1126         } else
1127                 r = 1;
1128
1129         amdgpu_ctx_put(ctx);
1130         if (r < 0)
1131                 return r;
1132
1133         memset(wait, 0, sizeof(*wait));
1134         wait->out.status = (r == 0);
1135
1136         return 0;
1137 }
1138
1139 /**
1140  * amdgpu_cs_find_bo_va - find bo_va for VM address
1141  *
1142  * @parser: command submission parser context
1143  * @addr: VM address
1144  * @bo: resulting BO of the mapping found
1145  *
1146  * Search the buffer objects in the command submission context for a certain
1147  * virtual memory address. Returns allocation structure when found, NULL
1148  * otherwise.
1149  */
1150 struct amdgpu_bo_va_mapping *
1151 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1152                        uint64_t addr, struct amdgpu_bo **bo)
1153 {
1154         struct amdgpu_bo_va_mapping *mapping;
1155         unsigned i;
1156
1157         if (!parser->bo_list)
1158                 return NULL;
1159
1160         addr /= AMDGPU_GPU_PAGE_SIZE;
1161
1162         for (i = 0; i < parser->bo_list->num_entries; i++) {
1163                 struct amdgpu_bo_list_entry *lobj;
1164
1165                 lobj = &parser->bo_list->array[i];
1166                 if (!lobj->bo_va)
1167                         continue;
1168
1169                 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1170                         if (mapping->it.start > addr ||
1171                             addr > mapping->it.last)
1172                                 continue;
1173
1174                         *bo = lobj->bo_va->bo;
1175                         return mapping;
1176                 }
1177
1178                 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1179                         if (mapping->it.start > addr ||
1180                             addr > mapping->it.last)
1181                                 continue;
1182
1183                         *bo = lobj->bo_va->bo;
1184                         return mapping;
1185                 }
1186         }
1187
1188         return NULL;
1189 }
1190
1191 /**
1192  * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1193  *
1194  * @parser: command submission parser context
1195  *
1196  * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1197  */
1198 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
1199 {
1200         unsigned i;
1201         int r;
1202
1203         if (!parser->bo_list)
1204                 return 0;
1205
1206         for (i = 0; i < parser->bo_list->num_entries; i++) {
1207                 struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
1208
1209                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1210                 if (unlikely(r))
1211                         return r;
1212         }
1213
1214         return 0;
1215 }