2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
56 #include "amdgpu_vf_error.h"
58 #include "amdgpu_amdkfd.h"
62 #define AMDGPU_RESUME_MS 2000
64 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
65 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
66 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
68 static const char *amdgpu_asic_name[] = {
92 bool amdgpu_device_is_px(struct drm_device *dev)
94 struct amdgpu_device *adev = dev->dev_private;
96 if (adev->flags & AMD_IS_PX)
102 * MMIO register access helper functions.
104 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
109 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
110 BUG_ON(in_interrupt());
111 return amdgpu_virt_kiq_rreg(adev, reg);
114 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
115 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
119 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
120 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
121 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
122 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
124 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
128 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
131 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
133 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
134 adev->last_mm_index = v;
137 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
138 BUG_ON(in_interrupt());
139 return amdgpu_virt_kiq_wreg(adev, reg, v);
142 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
143 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
147 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
148 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
149 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
150 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
153 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
158 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
160 if ((reg * 4) < adev->rio_mem_size)
161 return ioread32(adev->rio_mem + (reg * 4));
163 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
164 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
168 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
170 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
171 adev->last_mm_index = v;
174 if ((reg * 4) < adev->rio_mem_size)
175 iowrite32(v, adev->rio_mem + (reg * 4));
177 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
178 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
181 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
187 * amdgpu_mm_rdoorbell - read a doorbell dword
189 * @adev: amdgpu_device pointer
190 * @index: doorbell index
192 * Returns the value in the doorbell aperture at the
193 * requested doorbell index (CIK).
195 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
197 if (index < adev->doorbell.num_doorbells) {
198 return readl(adev->doorbell.ptr + index);
200 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
206 * amdgpu_mm_wdoorbell - write a doorbell dword
208 * @adev: amdgpu_device pointer
209 * @index: doorbell index
212 * Writes @v to the doorbell aperture at the
213 * requested doorbell index (CIK).
215 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
217 if (index < adev->doorbell.num_doorbells) {
218 writel(v, adev->doorbell.ptr + index);
220 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
225 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
227 * @adev: amdgpu_device pointer
228 * @index: doorbell index
230 * Returns the value in the doorbell aperture at the
231 * requested doorbell index (VEGA10+).
233 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
235 if (index < adev->doorbell.num_doorbells) {
236 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
238 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
244 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
246 * @adev: amdgpu_device pointer
247 * @index: doorbell index
250 * Writes @v to the doorbell aperture at the
251 * requested doorbell index (VEGA10+).
253 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
255 if (index < adev->doorbell.num_doorbells) {
256 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
258 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
263 * amdgpu_invalid_rreg - dummy reg read function
265 * @adev: amdgpu device pointer
266 * @reg: offset of register
268 * Dummy register read function. Used for register blocks
269 * that certain asics don't have (all asics).
270 * Returns the value in the register.
272 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
274 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
280 * amdgpu_invalid_wreg - dummy reg write function
282 * @adev: amdgpu device pointer
283 * @reg: offset of register
284 * @v: value to write to the register
286 * Dummy register read function. Used for register blocks
287 * that certain asics don't have (all asics).
289 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
291 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
297 * amdgpu_block_invalid_rreg - dummy reg read function
299 * @adev: amdgpu device pointer
300 * @block: offset of instance
301 * @reg: offset of register
303 * Dummy register read function. Used for register blocks
304 * that certain asics don't have (all asics).
305 * Returns the value in the register.
307 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
308 uint32_t block, uint32_t reg)
310 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
317 * amdgpu_block_invalid_wreg - dummy reg write function
319 * @adev: amdgpu device pointer
320 * @block: offset of instance
321 * @reg: offset of register
322 * @v: value to write to the register
324 * Dummy register read function. Used for register blocks
325 * that certain asics don't have (all asics).
327 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
329 uint32_t reg, uint32_t v)
331 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
336 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
338 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
339 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
340 &adev->vram_scratch.robj,
341 &adev->vram_scratch.gpu_addr,
342 (void **)&adev->vram_scratch.ptr);
345 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
347 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
351 * amdgpu_program_register_sequence - program an array of registers.
353 * @adev: amdgpu_device pointer
354 * @registers: pointer to the register array
355 * @array_size: size of the register array
357 * Programs an array or registers with and and or masks.
358 * This is a helper for setting golden registers.
360 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
361 const u32 *registers,
362 const u32 array_size)
364 u32 tmp, reg, and_mask, or_mask;
370 for (i = 0; i < array_size; i +=3) {
371 reg = registers[i + 0];
372 and_mask = registers[i + 1];
373 or_mask = registers[i + 2];
375 if (and_mask == 0xffffffff) {
386 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
388 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
392 * GPU doorbell aperture helpers function.
395 * amdgpu_doorbell_init - Init doorbell driver information.
397 * @adev: amdgpu_device pointer
399 * Init doorbell driver information (CIK)
400 * Returns 0 on success, error on failure.
402 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
404 /* doorbell bar mapping */
405 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
406 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
408 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
409 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
410 if (adev->doorbell.num_doorbells == 0)
413 adev->doorbell.ptr = ioremap(adev->doorbell.base,
414 adev->doorbell.num_doorbells *
416 if (adev->doorbell.ptr == NULL)
423 * amdgpu_doorbell_fini - Tear down doorbell driver information.
425 * @adev: amdgpu_device pointer
427 * Tear down doorbell driver information (CIK)
429 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
431 iounmap(adev->doorbell.ptr);
432 adev->doorbell.ptr = NULL;
436 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
439 * @adev: amdgpu_device pointer
440 * @aperture_base: output returning doorbell aperture base physical address
441 * @aperture_size: output returning doorbell aperture size in bytes
442 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
444 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
445 * takes doorbells required for its own rings and reports the setup to amdkfd.
446 * amdgpu reserved doorbells are at the start of the doorbell aperture.
448 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
449 phys_addr_t *aperture_base,
450 size_t *aperture_size,
451 size_t *start_offset)
454 * The first num_doorbells are used by amdgpu.
455 * amdkfd takes whatever's left in the aperture.
457 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
458 *aperture_base = adev->doorbell.base;
459 *aperture_size = adev->doorbell.size;
460 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
470 * Writeback is the method by which the GPU updates special pages in memory
471 * with the status of certain GPU events (fences, ring pointers,etc.).
475 * amdgpu_wb_fini - Disable Writeback and free memory
477 * @adev: amdgpu_device pointer
479 * Disables Writeback and frees the Writeback memory (all asics).
480 * Used at driver shutdown.
482 static void amdgpu_wb_fini(struct amdgpu_device *adev)
484 if (adev->wb.wb_obj) {
485 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
487 (void **)&adev->wb.wb);
488 adev->wb.wb_obj = NULL;
493 * amdgpu_wb_init- Init Writeback driver info and allocate memory
495 * @adev: amdgpu_device pointer
497 * Initializes writeback and allocates writeback memory (all asics).
498 * Used at driver startup.
499 * Returns 0 on success or an -error on failure.
501 static int amdgpu_wb_init(struct amdgpu_device *adev)
505 if (adev->wb.wb_obj == NULL) {
506 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
507 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
509 &adev->wb.wb_obj, &adev->wb.gpu_addr,
510 (void **)&adev->wb.wb);
512 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
516 adev->wb.num_wb = AMDGPU_MAX_WB;
517 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
519 /* clear wb memory */
520 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
527 * amdgpu_wb_get - Allocate a wb entry
529 * @adev: amdgpu_device pointer
532 * Allocate a wb slot for use by the driver (all asics).
533 * Returns 0 on success or -EINVAL on failure.
535 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
537 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
539 if (offset < adev->wb.num_wb) {
540 __set_bit(offset, adev->wb.used);
541 *wb = offset * 8; /* convert to dw offset */
549 * amdgpu_wb_free - Free a wb entry
551 * @adev: amdgpu_device pointer
554 * Free a wb slot allocated for use by the driver (all asics)
556 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
558 if (wb < adev->wb.num_wb)
559 __clear_bit(wb, adev->wb.used);
563 * amdgpu_vram_location - try to find VRAM location
564 * @adev: amdgpu device structure holding all necessary informations
565 * @mc: memory controller structure holding memory informations
566 * @base: base address at which to put VRAM
568 * Function will try to place VRAM at base address provided
569 * as parameter (which is so far either PCI aperture address or
570 * for IGP TOM base address).
572 * If there is not enough space to fit the unvisible VRAM in the 32bits
573 * address space then we limit the VRAM size to the aperture.
575 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
576 * this shouldn't be a problem as we are using the PCI aperture as a reference.
577 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
580 * Note: we use mc_vram_size as on some board we need to program the mc to
581 * cover the whole aperture even if VRAM size is inferior to aperture size
582 * Novell bug 204882 + along with lots of ubuntu ones
584 * Note: when limiting vram it's safe to overwritte real_vram_size because
585 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
586 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
589 * Note: IGP TOM addr should be the same as the aperture addr, we don't
590 * explicitly check for that though.
592 * FIXME: when reducing VRAM size align new size on power of 2.
594 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
596 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
598 mc->vram_start = base;
599 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
600 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
601 mc->real_vram_size = mc->aper_size;
602 mc->mc_vram_size = mc->aper_size;
604 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
605 if (limit && limit < mc->real_vram_size)
606 mc->real_vram_size = limit;
607 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
608 mc->mc_vram_size >> 20, mc->vram_start,
609 mc->vram_end, mc->real_vram_size >> 20);
613 * amdgpu_gart_location - try to find GTT location
614 * @adev: amdgpu device structure holding all necessary informations
615 * @mc: memory controller structure holding memory informations
617 * Function will place try to place GTT before or after VRAM.
619 * If GTT size is bigger than space left then we ajust GTT size.
620 * Thus function will never fails.
622 * FIXME: when reducing GTT size align new size on power of 2.
624 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
626 u64 size_af, size_bf;
628 size_af = adev->mc.mc_mask - mc->vram_end;
629 size_bf = mc->vram_start;
630 if (size_bf > size_af) {
631 if (mc->gart_size > size_bf) {
632 dev_warn(adev->dev, "limiting GTT\n");
633 mc->gart_size = size_bf;
637 if (mc->gart_size > size_af) {
638 dev_warn(adev->dev, "limiting GTT\n");
639 mc->gart_size = size_af;
641 mc->gart_start = mc->vram_end + 1;
643 mc->gart_end = mc->gart_start + mc->gart_size - 1;
644 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
645 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
649 * GPU helpers function.
652 * amdgpu_need_post - check if the hw need post or not
654 * @adev: amdgpu_device pointer
656 * Check if the asic has been initialized (all asics) at driver startup
657 * or post is needed if hw reset is performed.
658 * Returns true if need or false if not.
660 bool amdgpu_need_post(struct amdgpu_device *adev)
664 if (adev->has_hw_reset) {
665 adev->has_hw_reset = false;
669 /* bios scratch used on CIK+ */
670 if (adev->asic_type >= CHIP_BONAIRE)
671 return amdgpu_atombios_scratch_need_asic_init(adev);
673 /* check MEM_SIZE for older asics */
674 reg = amdgpu_asic_get_config_memsize(adev);
676 if ((reg != 0) && (reg != 0xffffffff))
683 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
685 if (amdgpu_sriov_vf(adev))
688 if (amdgpu_passthrough(adev)) {
689 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
690 * some old smc fw still need driver do vPost otherwise gpu hang, while
691 * those smc fw version above 22.15 doesn't have this flaw, so we force
692 * vpost executed for smc version below 22.15
694 if (adev->asic_type == CHIP_FIJI) {
697 err = reject_firmware(&adev->pm.fw, "/*(DEBLOBBED)*/", adev->dev);
698 /* force vPost if error occured */
702 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
703 if (fw_ver < 0x00160e00)
707 return amdgpu_need_post(adev);
711 * amdgpu_dummy_page_init - init dummy page used by the driver
713 * @adev: amdgpu_device pointer
715 * Allocate the dummy page used by the driver (all asics).
716 * This dummy page is used by the driver as a filler for gart entries
717 * when pages are taken out of the GART
718 * Returns 0 on sucess, -ENOMEM on failure.
720 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
722 if (adev->dummy_page.page)
724 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
725 if (adev->dummy_page.page == NULL)
727 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
728 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
729 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
730 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
731 __free_page(adev->dummy_page.page);
732 adev->dummy_page.page = NULL;
739 * amdgpu_dummy_page_fini - free dummy page used by the driver
741 * @adev: amdgpu_device pointer
743 * Frees the dummy page used by the driver (all asics).
745 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
747 if (adev->dummy_page.page == NULL)
749 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
750 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
751 __free_page(adev->dummy_page.page);
752 adev->dummy_page.page = NULL;
756 /* ATOM accessor methods */
758 * ATOM is an interpreted byte code stored in tables in the vbios. The
759 * driver registers callbacks to access registers and the interpreter
760 * in the driver parses the tables and executes then to program specific
761 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
762 * atombios.h, and atom.c
766 * cail_pll_read - read PLL register
768 * @info: atom card_info pointer
769 * @reg: PLL register offset
771 * Provides a PLL register accessor for the atom interpreter (r4xx+).
772 * Returns the value of the PLL register.
774 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
780 * cail_pll_write - write PLL register
782 * @info: atom card_info pointer
783 * @reg: PLL register offset
784 * @val: value to write to the pll register
786 * Provides a PLL register accessor for the atom interpreter (r4xx+).
788 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
794 * cail_mc_read - read MC (Memory Controller) register
796 * @info: atom card_info pointer
797 * @reg: MC register offset
799 * Provides an MC register accessor for the atom interpreter (r4xx+).
800 * Returns the value of the MC register.
802 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
808 * cail_mc_write - write MC (Memory Controller) register
810 * @info: atom card_info pointer
811 * @reg: MC register offset
812 * @val: value to write to the pll register
814 * Provides a MC register accessor for the atom interpreter (r4xx+).
816 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
822 * cail_reg_write - write MMIO register
824 * @info: atom card_info pointer
825 * @reg: MMIO register offset
826 * @val: value to write to the pll register
828 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
830 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
832 struct amdgpu_device *adev = info->dev->dev_private;
838 * cail_reg_read - read MMIO register
840 * @info: atom card_info pointer
841 * @reg: MMIO register offset
843 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
844 * Returns the value of the MMIO register.
846 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
848 struct amdgpu_device *adev = info->dev->dev_private;
856 * cail_ioreg_write - write IO register
858 * @info: atom card_info pointer
859 * @reg: IO register offset
860 * @val: value to write to the pll register
862 * Provides a IO register accessor for the atom interpreter (r4xx+).
864 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
866 struct amdgpu_device *adev = info->dev->dev_private;
872 * cail_ioreg_read - read IO register
874 * @info: atom card_info pointer
875 * @reg: IO register offset
877 * Provides an IO register accessor for the atom interpreter (r4xx+).
878 * Returns the value of the IO register.
880 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
882 struct amdgpu_device *adev = info->dev->dev_private;
890 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
892 * @adev: amdgpu_device pointer
894 * Frees the driver info and register access callbacks for the ATOM
895 * interpreter (r4xx+).
896 * Called at driver shutdown.
898 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
900 if (adev->mode_info.atom_context) {
901 kfree(adev->mode_info.atom_context->scratch);
902 kfree(adev->mode_info.atom_context->iio);
904 kfree(adev->mode_info.atom_context);
905 adev->mode_info.atom_context = NULL;
906 kfree(adev->mode_info.atom_card_info);
907 adev->mode_info.atom_card_info = NULL;
911 * amdgpu_atombios_init - init the driver info and callbacks for atombios
913 * @adev: amdgpu_device pointer
915 * Initializes the driver info and register access callbacks for the
916 * ATOM interpreter (r4xx+).
917 * Returns 0 on sucess, -ENOMEM on failure.
918 * Called at driver startup.
920 static int amdgpu_atombios_init(struct amdgpu_device *adev)
922 struct card_info *atom_card_info =
923 kzalloc(sizeof(struct card_info), GFP_KERNEL);
928 adev->mode_info.atom_card_info = atom_card_info;
929 atom_card_info->dev = adev->ddev;
930 atom_card_info->reg_read = cail_reg_read;
931 atom_card_info->reg_write = cail_reg_write;
932 /* needed for iio ops */
934 atom_card_info->ioreg_read = cail_ioreg_read;
935 atom_card_info->ioreg_write = cail_ioreg_write;
937 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
938 atom_card_info->ioreg_read = cail_reg_read;
939 atom_card_info->ioreg_write = cail_reg_write;
941 atom_card_info->mc_read = cail_mc_read;
942 atom_card_info->mc_write = cail_mc_write;
943 atom_card_info->pll_read = cail_pll_read;
944 atom_card_info->pll_write = cail_pll_write;
946 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
947 if (!adev->mode_info.atom_context) {
948 amdgpu_atombios_fini(adev);
952 mutex_init(&adev->mode_info.atom_context->mutex);
953 if (adev->is_atom_fw) {
954 amdgpu_atomfirmware_scratch_regs_init(adev);
955 amdgpu_atomfirmware_allocate_fb_scratch(adev);
957 amdgpu_atombios_scratch_regs_init(adev);
958 amdgpu_atombios_allocate_fb_scratch(adev);
963 /* if we get transitioned to only one device, take VGA back */
965 * amdgpu_vga_set_decode - enable/disable vga decode
967 * @cookie: amdgpu_device pointer
968 * @state: enable/disable vga decode
970 * Enable/disable vga decode (all asics).
971 * Returns VGA resource flags.
973 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
975 struct amdgpu_device *adev = cookie;
976 amdgpu_asic_set_vga_state(adev, state);
978 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
979 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
981 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
984 static void amdgpu_check_block_size(struct amdgpu_device *adev)
986 /* defines number of bits in page table versus page directory,
987 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
988 * page table and the remaining bits are in the page directory */
989 if (amdgpu_vm_block_size == -1)
992 if (amdgpu_vm_block_size < 9) {
993 dev_warn(adev->dev, "VM page table size (%d) too small\n",
994 amdgpu_vm_block_size);
998 if (amdgpu_vm_block_size > 24 ||
999 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1000 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1001 amdgpu_vm_block_size);
1008 amdgpu_vm_block_size = -1;
1011 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1013 /* no need to check the default value */
1014 if (amdgpu_vm_size == -1)
1017 if (!is_power_of_2(amdgpu_vm_size)) {
1018 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1023 if (amdgpu_vm_size < 1) {
1024 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1030 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1032 if (amdgpu_vm_size > 1024) {
1033 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1041 amdgpu_vm_size = -1;
1045 * amdgpu_check_arguments - validate module params
1047 * @adev: amdgpu_device pointer
1049 * Validates certain module parameters and updates
1050 * the associated values used by the driver (all asics).
1052 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1054 if (amdgpu_sched_jobs < 4) {
1055 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1057 amdgpu_sched_jobs = 4;
1058 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1059 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1061 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1064 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1065 /* gart size must be greater or equal to 32M */
1066 dev_warn(adev->dev, "gart size (%d) too small\n",
1068 amdgpu_gart_size = -1;
1071 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1072 /* gtt size must be greater or equal to 32M */
1073 dev_warn(adev->dev, "gtt size (%d) too small\n",
1075 amdgpu_gtt_size = -1;
1078 /* valid range is between 4 and 9 inclusive */
1079 if (amdgpu_vm_fragment_size != -1 &&
1080 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1081 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1082 amdgpu_vm_fragment_size = -1;
1085 amdgpu_check_vm_size(adev);
1087 amdgpu_check_block_size(adev);
1089 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1090 !is_power_of_2(amdgpu_vram_page_split))) {
1091 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1092 amdgpu_vram_page_split);
1093 amdgpu_vram_page_split = 1024;
1098 * amdgpu_switcheroo_set_state - set switcheroo state
1100 * @pdev: pci dev pointer
1101 * @state: vga_switcheroo state
1103 * Callback for the switcheroo driver. Suspends or resumes the
1104 * the asics before or after it is powered up using ACPI methods.
1106 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1108 struct drm_device *dev = pci_get_drvdata(pdev);
1110 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1113 if (state == VGA_SWITCHEROO_ON) {
1114 pr_info("amdgpu: switched on\n");
1115 /* don't suspend or resume card normally */
1116 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1118 amdgpu_device_resume(dev, true, true);
1120 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1121 drm_kms_helper_poll_enable(dev);
1123 pr_info("amdgpu: switched off\n");
1124 drm_kms_helper_poll_disable(dev);
1125 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1126 amdgpu_device_suspend(dev, true, true);
1127 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1132 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1134 * @pdev: pci dev pointer
1136 * Callback for the switcheroo driver. Check of the switcheroo
1137 * state can be changed.
1138 * Returns true if the state can be changed, false if not.
1140 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1142 struct drm_device *dev = pci_get_drvdata(pdev);
1145 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1146 * locking inversion with the driver load path. And the access here is
1147 * completely racy anyway. So don't bother with locking for now.
1149 return dev->open_count == 0;
1152 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1153 .set_gpu_state = amdgpu_switcheroo_set_state,
1155 .can_switch = amdgpu_switcheroo_can_switch,
1158 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1159 enum amd_ip_block_type block_type,
1160 enum amd_clockgating_state state)
1164 for (i = 0; i < adev->num_ip_blocks; i++) {
1165 if (!adev->ip_blocks[i].status.valid)
1167 if (adev->ip_blocks[i].version->type != block_type)
1169 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1171 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1172 (void *)adev, state);
1174 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1175 adev->ip_blocks[i].version->funcs->name, r);
1180 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1181 enum amd_ip_block_type block_type,
1182 enum amd_powergating_state state)
1186 for (i = 0; i < adev->num_ip_blocks; i++) {
1187 if (!adev->ip_blocks[i].status.valid)
1189 if (adev->ip_blocks[i].version->type != block_type)
1191 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1193 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1194 (void *)adev, state);
1196 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1197 adev->ip_blocks[i].version->funcs->name, r);
1202 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1206 for (i = 0; i < adev->num_ip_blocks; i++) {
1207 if (!adev->ip_blocks[i].status.valid)
1209 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1210 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1214 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1215 enum amd_ip_block_type block_type)
1219 for (i = 0; i < adev->num_ip_blocks; i++) {
1220 if (!adev->ip_blocks[i].status.valid)
1222 if (adev->ip_blocks[i].version->type == block_type) {
1223 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1233 bool amdgpu_is_idle(struct amdgpu_device *adev,
1234 enum amd_ip_block_type block_type)
1238 for (i = 0; i < adev->num_ip_blocks; i++) {
1239 if (!adev->ip_blocks[i].status.valid)
1241 if (adev->ip_blocks[i].version->type == block_type)
1242 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1248 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1249 enum amd_ip_block_type type)
1253 for (i = 0; i < adev->num_ip_blocks; i++)
1254 if (adev->ip_blocks[i].version->type == type)
1255 return &adev->ip_blocks[i];
1261 * amdgpu_ip_block_version_cmp
1263 * @adev: amdgpu_device pointer
1264 * @type: enum amd_ip_block_type
1265 * @major: major version
1266 * @minor: minor version
1268 * return 0 if equal or greater
1269 * return 1 if smaller or the ip_block doesn't exist
1271 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1272 enum amd_ip_block_type type,
1273 u32 major, u32 minor)
1275 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1277 if (ip_block && ((ip_block->version->major > major) ||
1278 ((ip_block->version->major == major) &&
1279 (ip_block->version->minor >= minor))))
1286 * amdgpu_ip_block_add
1288 * @adev: amdgpu_device pointer
1289 * @ip_block_version: pointer to the IP to add
1291 * Adds the IP block driver information to the collection of IPs
1294 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1295 const struct amdgpu_ip_block_version *ip_block_version)
1297 if (!ip_block_version)
1300 DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
1301 ip_block_version->funcs->name);
1303 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1308 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1310 adev->enable_virtual_display = false;
1312 if (amdgpu_virtual_display) {
1313 struct drm_device *ddev = adev->ddev;
1314 const char *pci_address_name = pci_name(ddev->pdev);
1315 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1317 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1318 pciaddstr_tmp = pciaddstr;
1319 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1320 pciaddname = strsep(&pciaddname_tmp, ",");
1321 if (!strcmp("all", pciaddname)
1322 || !strcmp(pci_address_name, pciaddname)) {
1326 adev->enable_virtual_display = true;
1329 res = kstrtol(pciaddname_tmp, 10,
1337 adev->mode_info.num_crtc = num_crtc;
1339 adev->mode_info.num_crtc = 1;
1345 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1346 amdgpu_virtual_display, pci_address_name,
1347 adev->enable_virtual_display, adev->mode_info.num_crtc);
1353 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1355 const char *chip_name;
1358 const struct gpu_info_firmware_header_v1_0 *hdr;
1360 adev->firmware.gpu_info_fw = NULL;
1362 switch (adev->asic_type) {
1366 case CHIP_POLARIS11:
1367 case CHIP_POLARIS10:
1368 case CHIP_POLARIS12:
1371 #ifdef CONFIG_DRM_AMDGPU_SI
1378 #ifdef CONFIG_DRM_AMDGPU_CIK
1388 chip_name = "vega10";
1391 chip_name = "raven";
1395 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1396 err = reject_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1399 "Failed to load gpu_info firmware \"%s\"\n",
1403 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1406 "Failed to validate gpu_info firmware \"%s\"\n",
1411 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1412 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1414 switch (hdr->version_major) {
1417 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1418 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1419 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1421 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1422 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1423 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1424 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1425 adev->gfx.config.max_texture_channel_caches =
1426 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1427 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1428 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1429 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1430 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1431 adev->gfx.config.double_offchip_lds_buf =
1432 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1433 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1434 adev->gfx.cu_info.max_waves_per_simd =
1435 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1436 adev->gfx.cu_info.max_scratch_slots_per_cu =
1437 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1438 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1443 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1451 static int amdgpu_early_init(struct amdgpu_device *adev)
1455 amdgpu_device_enable_virtual_display(adev);
1457 switch (adev->asic_type) {
1461 case CHIP_POLARIS11:
1462 case CHIP_POLARIS10:
1463 case CHIP_POLARIS12:
1466 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1467 adev->family = AMDGPU_FAMILY_CZ;
1469 adev->family = AMDGPU_FAMILY_VI;
1471 r = vi_set_ip_blocks(adev);
1475 #ifdef CONFIG_DRM_AMDGPU_SI
1481 adev->family = AMDGPU_FAMILY_SI;
1482 r = si_set_ip_blocks(adev);
1487 #ifdef CONFIG_DRM_AMDGPU_CIK
1493 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1494 adev->family = AMDGPU_FAMILY_CI;
1496 adev->family = AMDGPU_FAMILY_KV;
1498 r = cik_set_ip_blocks(adev);
1505 if (adev->asic_type == CHIP_RAVEN)
1506 adev->family = AMDGPU_FAMILY_RV;
1508 adev->family = AMDGPU_FAMILY_AI;
1510 r = soc15_set_ip_blocks(adev);
1515 /* FIXME: not supported yet */
1519 r = amdgpu_device_parse_gpu_info_fw(adev);
1523 if (amdgpu_sriov_vf(adev)) {
1524 r = amdgpu_virt_request_full_gpu(adev, true);
1529 for (i = 0; i < adev->num_ip_blocks; i++) {
1530 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1531 DRM_ERROR("disabled ip block: %d <%s>\n",
1532 i, adev->ip_blocks[i].version->funcs->name);
1533 adev->ip_blocks[i].status.valid = false;
1535 if (adev->ip_blocks[i].version->funcs->early_init) {
1536 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1538 adev->ip_blocks[i].status.valid = false;
1540 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1541 adev->ip_blocks[i].version->funcs->name, r);
1544 adev->ip_blocks[i].status.valid = true;
1547 adev->ip_blocks[i].status.valid = true;
1552 adev->cg_flags &= amdgpu_cg_mask;
1553 adev->pg_flags &= amdgpu_pg_mask;
1558 static int amdgpu_init(struct amdgpu_device *adev)
1562 for (i = 0; i < adev->num_ip_blocks; i++) {
1563 if (!adev->ip_blocks[i].status.valid)
1565 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1567 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1568 adev->ip_blocks[i].version->funcs->name, r);
1571 adev->ip_blocks[i].status.sw = true;
1572 /* need to do gmc hw init early so we can allocate gpu mem */
1573 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1574 r = amdgpu_vram_scratch_init(adev);
1576 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1579 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1581 DRM_ERROR("hw_init %d failed %d\n", i, r);
1584 r = amdgpu_wb_init(adev);
1586 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1589 adev->ip_blocks[i].status.hw = true;
1591 /* right after GMC hw init, we create CSA */
1592 if (amdgpu_sriov_vf(adev)) {
1593 r = amdgpu_allocate_static_csa(adev);
1595 DRM_ERROR("allocate CSA failed %d\n", r);
1602 for (i = 0; i < adev->num_ip_blocks; i++) {
1603 if (!adev->ip_blocks[i].status.sw)
1605 /* gmc hw init is done early */
1606 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1608 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1610 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1611 adev->ip_blocks[i].version->funcs->name, r);
1614 adev->ip_blocks[i].status.hw = true;
1620 static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
1622 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1625 static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
1627 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1628 AMDGPU_RESET_MAGIC_NUM);
1631 static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
1635 for (i = 0; i < adev->num_ip_blocks; i++) {
1636 if (!adev->ip_blocks[i].status.valid)
1638 /* skip CG for VCE/UVD, it's handled specially */
1639 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1640 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1641 /* enable clockgating to save power */
1642 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1645 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1646 adev->ip_blocks[i].version->funcs->name, r);
1654 static int amdgpu_late_init(struct amdgpu_device *adev)
1658 for (i = 0; i < adev->num_ip_blocks; i++) {
1659 if (!adev->ip_blocks[i].status.valid)
1661 if (adev->ip_blocks[i].version->funcs->late_init) {
1662 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1664 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1665 adev->ip_blocks[i].version->funcs->name, r);
1668 adev->ip_blocks[i].status.late_initialized = true;
1672 mod_delayed_work(system_wq, &adev->late_init_work,
1673 msecs_to_jiffies(AMDGPU_RESUME_MS));
1675 amdgpu_fill_reset_magic(adev);
1680 static int amdgpu_fini(struct amdgpu_device *adev)
1684 /* need to disable SMC first */
1685 for (i = 0; i < adev->num_ip_blocks; i++) {
1686 if (!adev->ip_blocks[i].status.hw)
1688 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1689 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1690 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1691 AMD_CG_STATE_UNGATE);
1693 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1694 adev->ip_blocks[i].version->funcs->name, r);
1697 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1698 /* XXX handle errors */
1700 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1701 adev->ip_blocks[i].version->funcs->name, r);
1703 adev->ip_blocks[i].status.hw = false;
1708 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1709 if (!adev->ip_blocks[i].status.hw)
1711 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1712 amdgpu_wb_fini(adev);
1713 amdgpu_vram_scratch_fini(adev);
1716 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1717 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1718 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1719 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1720 AMD_CG_STATE_UNGATE);
1722 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1723 adev->ip_blocks[i].version->funcs->name, r);
1728 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1729 /* XXX handle errors */
1731 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1732 adev->ip_blocks[i].version->funcs->name, r);
1735 adev->ip_blocks[i].status.hw = false;
1738 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1739 if (!adev->ip_blocks[i].status.sw)
1741 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1742 /* XXX handle errors */
1744 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1745 adev->ip_blocks[i].version->funcs->name, r);
1747 adev->ip_blocks[i].status.sw = false;
1748 adev->ip_blocks[i].status.valid = false;
1751 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1752 if (!adev->ip_blocks[i].status.late_initialized)
1754 if (adev->ip_blocks[i].version->funcs->late_fini)
1755 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1756 adev->ip_blocks[i].status.late_initialized = false;
1759 if (amdgpu_sriov_vf(adev)) {
1760 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
1761 amdgpu_virt_release_full_gpu(adev, false);
1767 static void amdgpu_late_init_func_handler(struct work_struct *work)
1769 struct amdgpu_device *adev =
1770 container_of(work, struct amdgpu_device, late_init_work.work);
1771 amdgpu_late_set_cg_state(adev);
1774 int amdgpu_suspend(struct amdgpu_device *adev)
1778 if (amdgpu_sriov_vf(adev))
1779 amdgpu_virt_request_full_gpu(adev, false);
1781 /* ungate SMC block first */
1782 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1783 AMD_CG_STATE_UNGATE);
1785 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1788 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1789 if (!adev->ip_blocks[i].status.valid)
1791 /* ungate blocks so that suspend can properly shut them down */
1792 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1793 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1794 AMD_CG_STATE_UNGATE);
1796 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1797 adev->ip_blocks[i].version->funcs->name, r);
1800 /* XXX handle errors */
1801 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1802 /* XXX handle errors */
1804 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1805 adev->ip_blocks[i].version->funcs->name, r);
1809 if (amdgpu_sriov_vf(adev))
1810 amdgpu_virt_release_full_gpu(adev, false);
1815 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1819 static enum amd_ip_block_type ip_order[] = {
1820 AMD_IP_BLOCK_TYPE_GMC,
1821 AMD_IP_BLOCK_TYPE_COMMON,
1822 AMD_IP_BLOCK_TYPE_IH,
1825 for (i = 0; i < adev->num_ip_blocks; i++) {
1827 struct amdgpu_ip_block *block;
1829 for (j = 0; j < adev->num_ip_blocks; j++) {
1830 block = &adev->ip_blocks[j];
1832 if (block->version->type != ip_order[i] ||
1833 !block->status.valid)
1836 r = block->version->funcs->hw_init(adev);
1837 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1844 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1848 static enum amd_ip_block_type ip_order[] = {
1849 AMD_IP_BLOCK_TYPE_SMC,
1850 AMD_IP_BLOCK_TYPE_DCE,
1851 AMD_IP_BLOCK_TYPE_GFX,
1852 AMD_IP_BLOCK_TYPE_SDMA,
1853 AMD_IP_BLOCK_TYPE_UVD,
1854 AMD_IP_BLOCK_TYPE_VCE
1857 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1859 struct amdgpu_ip_block *block;
1861 for (j = 0; j < adev->num_ip_blocks; j++) {
1862 block = &adev->ip_blocks[j];
1864 if (block->version->type != ip_order[i] ||
1865 !block->status.valid)
1868 r = block->version->funcs->hw_init(adev);
1869 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1876 static int amdgpu_resume_phase1(struct amdgpu_device *adev)
1880 for (i = 0; i < adev->num_ip_blocks; i++) {
1881 if (!adev->ip_blocks[i].status.valid)
1883 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1884 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1885 adev->ip_blocks[i].version->type ==
1886 AMD_IP_BLOCK_TYPE_IH) {
1887 r = adev->ip_blocks[i].version->funcs->resume(adev);
1889 DRM_ERROR("resume of IP block <%s> failed %d\n",
1890 adev->ip_blocks[i].version->funcs->name, r);
1899 static int amdgpu_resume_phase2(struct amdgpu_device *adev)
1903 for (i = 0; i < adev->num_ip_blocks; i++) {
1904 if (!adev->ip_blocks[i].status.valid)
1906 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1907 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1908 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1910 r = adev->ip_blocks[i].version->funcs->resume(adev);
1912 DRM_ERROR("resume of IP block <%s> failed %d\n",
1913 adev->ip_blocks[i].version->funcs->name, r);
1921 static int amdgpu_resume(struct amdgpu_device *adev)
1925 r = amdgpu_resume_phase1(adev);
1928 r = amdgpu_resume_phase2(adev);
1933 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1935 if (adev->is_atom_fw) {
1936 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1937 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1939 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1940 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1945 * amdgpu_device_init - initialize the driver
1947 * @adev: amdgpu_device pointer
1948 * @pdev: drm dev pointer
1949 * @pdev: pci dev pointer
1950 * @flags: driver flags
1952 * Initializes the driver info and hw (all asics).
1953 * Returns 0 for success or an error on failure.
1954 * Called at driver startup.
1956 int amdgpu_device_init(struct amdgpu_device *adev,
1957 struct drm_device *ddev,
1958 struct pci_dev *pdev,
1962 bool runtime = false;
1965 adev->shutdown = false;
1966 adev->dev = &pdev->dev;
1969 adev->flags = flags;
1970 adev->asic_type = flags & AMD_ASIC_MASK;
1971 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1972 adev->mc.gart_size = 512 * 1024 * 1024;
1973 adev->accel_working = false;
1974 adev->num_rings = 0;
1975 adev->mman.buffer_funcs = NULL;
1976 adev->mman.buffer_funcs_ring = NULL;
1977 adev->vm_manager.vm_pte_funcs = NULL;
1978 adev->vm_manager.vm_pte_num_rings = 0;
1979 adev->gart.gart_funcs = NULL;
1980 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1982 adev->smc_rreg = &amdgpu_invalid_rreg;
1983 adev->smc_wreg = &amdgpu_invalid_wreg;
1984 adev->pcie_rreg = &amdgpu_invalid_rreg;
1985 adev->pcie_wreg = &amdgpu_invalid_wreg;
1986 adev->pciep_rreg = &amdgpu_invalid_rreg;
1987 adev->pciep_wreg = &amdgpu_invalid_wreg;
1988 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1989 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1990 adev->didt_rreg = &amdgpu_invalid_rreg;
1991 adev->didt_wreg = &amdgpu_invalid_wreg;
1992 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1993 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1994 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1995 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1998 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1999 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2000 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2002 /* mutex initialization are all done here so we
2003 * can recall function without having locking issues */
2004 atomic_set(&adev->irq.ih.lock, 0);
2005 mutex_init(&adev->firmware.mutex);
2006 mutex_init(&adev->pm.mutex);
2007 mutex_init(&adev->gfx.gpu_clock_mutex);
2008 mutex_init(&adev->srbm_mutex);
2009 mutex_init(&adev->grbm_idx_mutex);
2010 mutex_init(&adev->mn_lock);
2011 hash_init(adev->mn_hash);
2013 amdgpu_check_arguments(adev);
2015 spin_lock_init(&adev->mmio_idx_lock);
2016 spin_lock_init(&adev->smc_idx_lock);
2017 spin_lock_init(&adev->pcie_idx_lock);
2018 spin_lock_init(&adev->uvd_ctx_idx_lock);
2019 spin_lock_init(&adev->didt_idx_lock);
2020 spin_lock_init(&adev->gc_cac_idx_lock);
2021 spin_lock_init(&adev->se_cac_idx_lock);
2022 spin_lock_init(&adev->audio_endpt_idx_lock);
2023 spin_lock_init(&adev->mm_stats.lock);
2025 INIT_LIST_HEAD(&adev->shadow_list);
2026 mutex_init(&adev->shadow_list_lock);
2028 INIT_LIST_HEAD(&adev->gtt_list);
2029 spin_lock_init(&adev->gtt_list_lock);
2031 INIT_LIST_HEAD(&adev->ring_lru_list);
2032 spin_lock_init(&adev->ring_lru_list_lock);
2034 INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
2036 /* Registers mapping */
2037 /* TODO: block userspace mapping of io register */
2038 if (adev->asic_type >= CHIP_BONAIRE) {
2039 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2040 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2042 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2043 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2046 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2047 if (adev->rmmio == NULL) {
2050 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2051 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2053 if (adev->asic_type >= CHIP_BONAIRE)
2054 /* doorbell bar mapping */
2055 amdgpu_doorbell_init(adev);
2057 /* io port mapping */
2058 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2059 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2060 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2061 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2065 if (adev->rio_mem == NULL)
2066 DRM_INFO("PCI I/O BAR is not found.\n");
2068 /* early init functions */
2069 r = amdgpu_early_init(adev);
2073 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2074 /* this will fail for cards that aren't VGA class devices, just
2076 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
2078 if (amdgpu_device_is_px(ddev))
2080 if (!pci_is_thunderbolt_attached(adev->pdev))
2081 vga_switcheroo_register_client(adev->pdev,
2082 &amdgpu_switcheroo_ops, runtime);
2084 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2087 if (!amdgpu_get_bios(adev)) {
2092 r = amdgpu_atombios_init(adev);
2094 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2095 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2099 /* detect if we are with an SRIOV vbios */
2100 amdgpu_device_detect_sriov_bios(adev);
2102 /* Post card if necessary */
2103 if (amdgpu_vpost_needed(adev)) {
2105 dev_err(adev->dev, "no vBIOS found\n");
2106 amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2110 DRM_INFO("GPU posting now...\n");
2111 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2113 dev_err(adev->dev, "gpu post error!\n");
2114 amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0);
2118 DRM_INFO("GPU post is not needed\n");
2121 if (adev->is_atom_fw) {
2122 /* Initialize clocks */
2123 r = amdgpu_atomfirmware_get_clock_info(adev);
2125 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2126 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2130 /* Initialize clocks */
2131 r = amdgpu_atombios_get_clock_info(adev);
2133 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2134 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2137 /* init i2c buses */
2138 amdgpu_atombios_i2c_init(adev);
2142 r = amdgpu_fence_driver_init(adev);
2144 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2145 amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2149 /* init the mode config */
2150 drm_mode_config_init(adev->ddev);
2152 r = amdgpu_init(adev);
2154 dev_err(adev->dev, "amdgpu_init failed\n");
2155 amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2160 adev->accel_working = true;
2162 amdgpu_vm_check_compute_bug(adev);
2164 /* Initialize the buffer migration limit. */
2165 if (amdgpu_moverate >= 0)
2166 max_MBps = amdgpu_moverate;
2168 max_MBps = 8; /* Allow 8 MB/s. */
2169 /* Get a log2 for easy divisions. */
2170 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2172 r = amdgpu_ib_pool_init(adev);
2174 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2175 amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2179 r = amdgpu_ib_ring_tests(adev);
2181 DRM_ERROR("ib ring test failed (%d).\n", r);
2183 amdgpu_fbdev_init(adev);
2185 r = amdgpu_gem_debugfs_init(adev);
2187 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2189 r = amdgpu_debugfs_regs_init(adev);
2191 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2193 r = amdgpu_debugfs_test_ib_ring_init(adev);
2195 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
2197 r = amdgpu_debugfs_firmware_init(adev);
2199 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2201 if ((amdgpu_testing & 1)) {
2202 if (adev->accel_working)
2203 amdgpu_test_moves(adev);
2205 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2207 if (amdgpu_benchmarking) {
2208 if (adev->accel_working)
2209 amdgpu_benchmark(adev, amdgpu_benchmarking);
2211 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2214 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2215 * explicit gating rather than handling it automatically.
2217 r = amdgpu_late_init(adev);
2219 dev_err(adev->dev, "amdgpu_late_init failed\n");
2220 amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2227 amdgpu_vf_error_trans_all(adev);
2229 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2234 * amdgpu_device_fini - tear down the driver
2236 * @adev: amdgpu_device pointer
2238 * Tear down the driver info (all asics).
2239 * Called at driver shutdown.
2241 void amdgpu_device_fini(struct amdgpu_device *adev)
2245 DRM_INFO("amdgpu: finishing device.\n");
2246 adev->shutdown = true;
2247 if (adev->mode_info.mode_config_initialized)
2248 drm_crtc_force_disable_all(adev->ddev);
2249 /* evict vram memory */
2250 amdgpu_bo_evict_vram(adev);
2251 amdgpu_ib_pool_fini(adev);
2252 amdgpu_fence_driver_fini(adev);
2253 amdgpu_fbdev_fini(adev);
2254 r = amdgpu_fini(adev);
2255 if (adev->firmware.gpu_info_fw) {
2256 release_firmware(adev->firmware.gpu_info_fw);
2257 adev->firmware.gpu_info_fw = NULL;
2259 adev->accel_working = false;
2260 cancel_delayed_work_sync(&adev->late_init_work);
2261 /* free i2c buses */
2262 amdgpu_i2c_fini(adev);
2263 amdgpu_atombios_fini(adev);
2266 if (!pci_is_thunderbolt_attached(adev->pdev))
2267 vga_switcheroo_unregister_client(adev->pdev);
2268 if (adev->flags & AMD_IS_PX)
2269 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2270 vga_client_register(adev->pdev, NULL, NULL, NULL);
2272 pci_iounmap(adev->pdev, adev->rio_mem);
2273 adev->rio_mem = NULL;
2274 iounmap(adev->rmmio);
2276 if (adev->asic_type >= CHIP_BONAIRE)
2277 amdgpu_doorbell_fini(adev);
2278 amdgpu_debugfs_regs_cleanup(adev);
2286 * amdgpu_device_suspend - initiate device suspend
2288 * @pdev: drm dev pointer
2289 * @state: suspend state
2291 * Puts the hw in the suspend state (all asics).
2292 * Returns 0 for success or an error on failure.
2293 * Called at driver suspend.
2295 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2297 struct amdgpu_device *adev;
2298 struct drm_crtc *crtc;
2299 struct drm_connector *connector;
2302 if (dev == NULL || dev->dev_private == NULL) {
2306 adev = dev->dev_private;
2308 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2311 drm_kms_helper_poll_disable(dev);
2313 /* turn off display hw */
2314 drm_modeset_lock_all(dev);
2315 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2316 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2318 drm_modeset_unlock_all(dev);
2320 amdgpu_amdkfd_suspend(adev);
2322 /* unpin the front buffers and cursors */
2323 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2324 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2325 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2326 struct amdgpu_bo *robj;
2328 if (amdgpu_crtc->cursor_bo) {
2329 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2330 r = amdgpu_bo_reserve(aobj, true);
2332 amdgpu_bo_unpin(aobj);
2333 amdgpu_bo_unreserve(aobj);
2337 if (rfb == NULL || rfb->obj == NULL) {
2340 robj = gem_to_amdgpu_bo(rfb->obj);
2341 /* don't unpin kernel fb objects */
2342 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2343 r = amdgpu_bo_reserve(robj, true);
2345 amdgpu_bo_unpin(robj);
2346 amdgpu_bo_unreserve(robj);
2350 /* evict vram memory */
2351 amdgpu_bo_evict_vram(adev);
2353 amdgpu_fence_driver_suspend(adev);
2355 r = amdgpu_suspend(adev);
2357 /* evict remaining vram memory
2358 * This second call to evict vram is to evict the gart page table
2361 amdgpu_bo_evict_vram(adev);
2363 amdgpu_atombios_scratch_regs_save(adev);
2364 pci_save_state(dev->pdev);
2366 /* Shut down the device */
2367 pci_disable_device(dev->pdev);
2368 pci_set_power_state(dev->pdev, PCI_D3hot);
2370 r = amdgpu_asic_reset(adev);
2372 DRM_ERROR("amdgpu asic reset failed\n");
2377 amdgpu_fbdev_set_suspend(adev, 1);
2384 * amdgpu_device_resume - initiate device resume
2386 * @pdev: drm dev pointer
2388 * Bring the hw back to operating state (all asics).
2389 * Returns 0 for success or an error on failure.
2390 * Called at driver resume.
2392 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2394 struct drm_connector *connector;
2395 struct amdgpu_device *adev = dev->dev_private;
2396 struct drm_crtc *crtc;
2399 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2406 pci_set_power_state(dev->pdev, PCI_D0);
2407 pci_restore_state(dev->pdev);
2408 r = pci_enable_device(dev->pdev);
2412 amdgpu_atombios_scratch_regs_restore(adev);
2415 if (amdgpu_need_post(adev)) {
2416 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2418 DRM_ERROR("amdgpu asic init failed\n");
2421 r = amdgpu_resume(adev);
2423 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2426 amdgpu_fence_driver_resume(adev);
2429 r = amdgpu_ib_ring_tests(adev);
2431 DRM_ERROR("ib ring test failed (%d).\n", r);
2434 r = amdgpu_late_init(adev);
2439 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2440 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2442 if (amdgpu_crtc->cursor_bo) {
2443 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2444 r = amdgpu_bo_reserve(aobj, true);
2446 r = amdgpu_bo_pin(aobj,
2447 AMDGPU_GEM_DOMAIN_VRAM,
2448 &amdgpu_crtc->cursor_addr);
2450 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2451 amdgpu_bo_unreserve(aobj);
2455 r = amdgpu_amdkfd_resume(adev);
2459 /* blat the mode back in */
2461 drm_helper_resume_force_mode(dev);
2462 /* turn on display hw */
2463 drm_modeset_lock_all(dev);
2464 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2465 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2467 drm_modeset_unlock_all(dev);
2470 drm_kms_helper_poll_enable(dev);
2473 * Most of the connector probing functions try to acquire runtime pm
2474 * refs to ensure that the GPU is powered on when connector polling is
2475 * performed. Since we're calling this from a runtime PM callback,
2476 * trying to acquire rpm refs will cause us to deadlock.
2478 * Since we're guaranteed to be holding the rpm lock, it's safe to
2479 * temporarily disable the rpm helpers so this doesn't deadlock us.
2482 dev->dev->power.disable_depth++;
2484 drm_helper_hpd_irq_event(dev);
2486 dev->dev->power.disable_depth--;
2490 amdgpu_fbdev_set_suspend(adev, 0);
2499 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2502 bool asic_hang = false;
2504 for (i = 0; i < adev->num_ip_blocks; i++) {
2505 if (!adev->ip_blocks[i].status.valid)
2507 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2508 adev->ip_blocks[i].status.hang =
2509 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2510 if (adev->ip_blocks[i].status.hang) {
2511 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2518 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2522 for (i = 0; i < adev->num_ip_blocks; i++) {
2523 if (!adev->ip_blocks[i].status.valid)
2525 if (adev->ip_blocks[i].status.hang &&
2526 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2527 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2536 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2540 for (i = 0; i < adev->num_ip_blocks; i++) {
2541 if (!adev->ip_blocks[i].status.valid)
2543 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2544 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2545 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2546 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2547 if (adev->ip_blocks[i].status.hang) {
2548 DRM_INFO("Some block need full reset!\n");
2556 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2560 for (i = 0; i < adev->num_ip_blocks; i++) {
2561 if (!adev->ip_blocks[i].status.valid)
2563 if (adev->ip_blocks[i].status.hang &&
2564 adev->ip_blocks[i].version->funcs->soft_reset) {
2565 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2574 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2578 for (i = 0; i < adev->num_ip_blocks; i++) {
2579 if (!adev->ip_blocks[i].status.valid)
2581 if (adev->ip_blocks[i].status.hang &&
2582 adev->ip_blocks[i].version->funcs->post_soft_reset)
2583 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2591 bool amdgpu_need_backup(struct amdgpu_device *adev)
2593 if (adev->flags & AMD_IS_APU)
2596 return amdgpu_lockup_timeout > 0 ? true : false;
2599 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2600 struct amdgpu_ring *ring,
2601 struct amdgpu_bo *bo,
2602 struct dma_fence **fence)
2610 r = amdgpu_bo_reserve(bo, true);
2613 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2614 /* if bo has been evicted, then no need to recover */
2615 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2616 r = amdgpu_bo_validate(bo->shadow);
2618 DRM_ERROR("bo validate failed!\n");
2622 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2625 DRM_ERROR("recover page table failed!\n");
2630 amdgpu_bo_unreserve(bo);
2635 * amdgpu_sriov_gpu_reset - reset the asic
2637 * @adev: amdgpu device pointer
2638 * @job: which job trigger hang
2640 * Attempt the reset the GPU if it has hung (all asics).
2642 * Returns 0 for success or an error on failure.
2644 int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
2648 struct amdgpu_bo *bo, *tmp;
2649 struct amdgpu_ring *ring;
2650 struct dma_fence *fence = NULL, *next = NULL;
2652 mutex_lock(&adev->virt.lock_reset);
2653 atomic_inc(&adev->gpu_reset_counter);
2654 adev->gfx.in_reset = true;
2657 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2659 /* we start from the ring trigger GPU hang */
2660 j = job ? job->ring->idx : 0;
2662 /* block scheduler */
2663 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2664 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2665 if (!ring || !ring->sched.thread)
2668 kthread_park(ring->sched.thread);
2673 /* here give the last chance to check if job removed from mirror-list
2674 * since we already pay some time on kthread_park */
2675 if (job && list_empty(&job->base.node)) {
2676 kthread_unpark(ring->sched.thread);
2680 if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit))
2681 amd_sched_job_kickout(&job->base);
2683 /* only do job_reset on the hang ring if @job not NULL */
2684 amd_sched_hw_job_reset(&ring->sched);
2686 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2687 amdgpu_fence_driver_force_completion_ring(ring);
2690 /* request to take full control of GPU before re-initialization */
2692 amdgpu_virt_reset_gpu(adev);
2694 amdgpu_virt_request_full_gpu(adev, true);
2697 /* Resume IP prior to SMC */
2698 amdgpu_sriov_reinit_early(adev);
2700 /* we need recover gart prior to run SMC/CP/SDMA resume */
2701 amdgpu_ttm_recover_gart(adev);
2703 /* now we are okay to resume SMC/CP/SDMA */
2704 amdgpu_sriov_reinit_late(adev);
2706 amdgpu_irq_gpu_reset_resume_helper(adev);
2708 if (amdgpu_ib_ring_tests(adev))
2709 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2711 /* release full control of GPU after ib test */
2712 amdgpu_virt_release_full_gpu(adev, true);
2714 DRM_INFO("recover vram bo from shadow\n");
2716 ring = adev->mman.buffer_funcs_ring;
2717 mutex_lock(&adev->shadow_list_lock);
2718 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2720 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2722 r = dma_fence_wait(fence, false);
2724 WARN(r, "recovery from shadow isn't completed\n");
2729 dma_fence_put(fence);
2732 mutex_unlock(&adev->shadow_list_lock);
2735 r = dma_fence_wait(fence, false);
2737 WARN(r, "recovery from shadow isn't completed\n");
2739 dma_fence_put(fence);
2741 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2742 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2743 if (!ring || !ring->sched.thread)
2746 if (job && j != i) {
2747 kthread_unpark(ring->sched.thread);
2751 amd_sched_job_recovery(&ring->sched);
2752 kthread_unpark(ring->sched.thread);
2755 drm_helper_resume_force_mode(adev->ddev);
2757 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2759 /* bad news, how to tell it to userspace ? */
2760 dev_info(adev->dev, "GPU reset failed\n");
2762 dev_info(adev->dev, "GPU reset successed!\n");
2765 adev->gfx.in_reset = false;
2766 mutex_unlock(&adev->virt.lock_reset);
2771 * amdgpu_gpu_reset - reset the asic
2773 * @adev: amdgpu device pointer
2775 * Attempt the reset the GPU if it has hung (all asics).
2776 * Returns 0 for success or an error on failure.
2778 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2782 bool need_full_reset, vram_lost = false;
2784 if (!amdgpu_check_soft_reset(adev)) {
2785 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2789 atomic_inc(&adev->gpu_reset_counter);
2792 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2794 /* block scheduler */
2795 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2796 struct amdgpu_ring *ring = adev->rings[i];
2798 if (!ring || !ring->sched.thread)
2800 kthread_park(ring->sched.thread);
2801 amd_sched_hw_job_reset(&ring->sched);
2803 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2804 amdgpu_fence_driver_force_completion(adev);
2806 need_full_reset = amdgpu_need_full_reset(adev);
2808 if (!need_full_reset) {
2809 amdgpu_pre_soft_reset(adev);
2810 r = amdgpu_soft_reset(adev);
2811 amdgpu_post_soft_reset(adev);
2812 if (r || amdgpu_check_soft_reset(adev)) {
2813 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2814 need_full_reset = true;
2818 if (need_full_reset) {
2819 r = amdgpu_suspend(adev);
2822 amdgpu_atombios_scratch_regs_save(adev);
2823 r = amdgpu_asic_reset(adev);
2824 amdgpu_atombios_scratch_regs_restore(adev);
2826 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2829 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2830 r = amdgpu_resume_phase1(adev);
2833 vram_lost = amdgpu_check_vram_lost(adev);
2835 DRM_ERROR("VRAM is lost!\n");
2836 atomic_inc(&adev->vram_lost_counter);
2838 r = amdgpu_ttm_recover_gart(adev);
2841 r = amdgpu_resume_phase2(adev);
2845 amdgpu_fill_reset_magic(adev);
2850 amdgpu_irq_gpu_reset_resume_helper(adev);
2851 r = amdgpu_ib_ring_tests(adev);
2853 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2854 r = amdgpu_suspend(adev);
2855 need_full_reset = true;
2859 * recovery vm page tables, since we cannot depend on VRAM is
2860 * consistent after gpu full reset.
2862 if (need_full_reset && amdgpu_need_backup(adev)) {
2863 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2864 struct amdgpu_bo *bo, *tmp;
2865 struct dma_fence *fence = NULL, *next = NULL;
2867 DRM_INFO("recover vram bo from shadow\n");
2868 mutex_lock(&adev->shadow_list_lock);
2869 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2871 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2873 r = dma_fence_wait(fence, false);
2875 WARN(r, "recovery from shadow isn't completed\n");
2880 dma_fence_put(fence);
2883 mutex_unlock(&adev->shadow_list_lock);
2885 r = dma_fence_wait(fence, false);
2887 WARN(r, "recovery from shadow isn't completed\n");
2889 dma_fence_put(fence);
2891 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2892 struct amdgpu_ring *ring = adev->rings[i];
2894 if (!ring || !ring->sched.thread)
2897 amd_sched_job_recovery(&ring->sched);
2898 kthread_unpark(ring->sched.thread);
2901 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2902 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r);
2903 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2904 if (adev->rings[i] && adev->rings[i]->sched.thread) {
2905 kthread_unpark(adev->rings[i]->sched.thread);
2910 drm_helper_resume_force_mode(adev->ddev);
2912 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2914 /* bad news, how to tell it to userspace ? */
2915 dev_info(adev->dev, "GPU reset failed\n");
2916 amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
2919 dev_info(adev->dev, "GPU reset successed!\n");
2922 amdgpu_vf_error_trans_all(adev);
2926 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2931 if (amdgpu_pcie_gen_cap)
2932 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2934 if (amdgpu_pcie_lane_cap)
2935 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2937 /* covers APUs as well */
2938 if (pci_is_root_bus(adev->pdev->bus)) {
2939 if (adev->pm.pcie_gen_mask == 0)
2940 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2941 if (adev->pm.pcie_mlw_mask == 0)
2942 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2946 if (adev->pm.pcie_gen_mask == 0) {
2947 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2949 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2950 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2951 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2953 if (mask & DRM_PCIE_SPEED_25)
2954 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2955 if (mask & DRM_PCIE_SPEED_50)
2956 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2957 if (mask & DRM_PCIE_SPEED_80)
2958 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2960 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2963 if (adev->pm.pcie_mlw_mask == 0) {
2964 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2968 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2971 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2972 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2973 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2974 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2977 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2978 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2979 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2980 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2982 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2985 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2986 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2989 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2992 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2993 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2994 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2995 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2998 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2999 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3000 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3003 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3004 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3007 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3013 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3021 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3022 const struct drm_info_list *files,
3027 for (i = 0; i < adev->debugfs_count; i++) {
3028 if (adev->debugfs[i].files == files) {
3029 /* Already registered */
3034 i = adev->debugfs_count + 1;
3035 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
3036 DRM_ERROR("Reached maximum number of debugfs components.\n");
3037 DRM_ERROR("Report so we increase "
3038 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3041 adev->debugfs[adev->debugfs_count].files = files;
3042 adev->debugfs[adev->debugfs_count].num_files = nfiles;
3043 adev->debugfs_count = i;
3044 #if defined(CONFIG_DEBUG_FS)
3045 drm_debugfs_create_files(files, nfiles,
3046 adev->ddev->primary->debugfs_root,
3047 adev->ddev->primary);
3052 #if defined(CONFIG_DEBUG_FS)
3054 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3055 size_t size, loff_t *pos)
3057 struct amdgpu_device *adev = file_inode(f)->i_private;
3060 bool pm_pg_lock, use_bank;
3061 unsigned instance_bank, sh_bank, se_bank;
3063 if (size & 0x3 || *pos & 0x3)
3066 /* are we reading registers for which a PG lock is necessary? */
3067 pm_pg_lock = (*pos >> 23) & 1;
3069 if (*pos & (1ULL << 62)) {
3070 se_bank = (*pos >> 24) & 0x3FF;
3071 sh_bank = (*pos >> 34) & 0x3FF;
3072 instance_bank = (*pos >> 44) & 0x3FF;
3074 if (se_bank == 0x3FF)
3075 se_bank = 0xFFFFFFFF;
3076 if (sh_bank == 0x3FF)
3077 sh_bank = 0xFFFFFFFF;
3078 if (instance_bank == 0x3FF)
3079 instance_bank = 0xFFFFFFFF;
3085 *pos &= (1UL << 22) - 1;
3088 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3089 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3091 mutex_lock(&adev->grbm_idx_mutex);
3092 amdgpu_gfx_select_se_sh(adev, se_bank,
3093 sh_bank, instance_bank);
3097 mutex_lock(&adev->pm.mutex);
3102 if (*pos > adev->rmmio_size)
3105 value = RREG32(*pos >> 2);
3106 r = put_user(value, (uint32_t *)buf);
3120 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3121 mutex_unlock(&adev->grbm_idx_mutex);
3125 mutex_unlock(&adev->pm.mutex);
3130 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3131 size_t size, loff_t *pos)
3133 struct amdgpu_device *adev = file_inode(f)->i_private;
3136 bool pm_pg_lock, use_bank;
3137 unsigned instance_bank, sh_bank, se_bank;
3139 if (size & 0x3 || *pos & 0x3)
3142 /* are we reading registers for which a PG lock is necessary? */
3143 pm_pg_lock = (*pos >> 23) & 1;
3145 if (*pos & (1ULL << 62)) {
3146 se_bank = (*pos >> 24) & 0x3FF;
3147 sh_bank = (*pos >> 34) & 0x3FF;
3148 instance_bank = (*pos >> 44) & 0x3FF;
3150 if (se_bank == 0x3FF)
3151 se_bank = 0xFFFFFFFF;
3152 if (sh_bank == 0x3FF)
3153 sh_bank = 0xFFFFFFFF;
3154 if (instance_bank == 0x3FF)
3155 instance_bank = 0xFFFFFFFF;
3161 *pos &= (1UL << 22) - 1;
3164 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3165 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3167 mutex_lock(&adev->grbm_idx_mutex);
3168 amdgpu_gfx_select_se_sh(adev, se_bank,
3169 sh_bank, instance_bank);
3173 mutex_lock(&adev->pm.mutex);
3178 if (*pos > adev->rmmio_size)
3181 r = get_user(value, (uint32_t *)buf);
3185 WREG32(*pos >> 2, value);
3194 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3195 mutex_unlock(&adev->grbm_idx_mutex);
3199 mutex_unlock(&adev->pm.mutex);
3204 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3205 size_t size, loff_t *pos)
3207 struct amdgpu_device *adev = file_inode(f)->i_private;
3211 if (size & 0x3 || *pos & 0x3)
3217 value = RREG32_PCIE(*pos >> 2);
3218 r = put_user(value, (uint32_t *)buf);
3231 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3232 size_t size, loff_t *pos)
3234 struct amdgpu_device *adev = file_inode(f)->i_private;
3238 if (size & 0x3 || *pos & 0x3)
3244 r = get_user(value, (uint32_t *)buf);
3248 WREG32_PCIE(*pos >> 2, value);
3259 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3260 size_t size, loff_t *pos)
3262 struct amdgpu_device *adev = file_inode(f)->i_private;
3266 if (size & 0x3 || *pos & 0x3)
3272 value = RREG32_DIDT(*pos >> 2);
3273 r = put_user(value, (uint32_t *)buf);
3286 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3287 size_t size, loff_t *pos)
3289 struct amdgpu_device *adev = file_inode(f)->i_private;
3293 if (size & 0x3 || *pos & 0x3)
3299 r = get_user(value, (uint32_t *)buf);
3303 WREG32_DIDT(*pos >> 2, value);
3314 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3315 size_t size, loff_t *pos)
3317 struct amdgpu_device *adev = file_inode(f)->i_private;
3321 if (size & 0x3 || *pos & 0x3)
3327 value = RREG32_SMC(*pos);
3328 r = put_user(value, (uint32_t *)buf);
3341 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3342 size_t size, loff_t *pos)
3344 struct amdgpu_device *adev = file_inode(f)->i_private;
3348 if (size & 0x3 || *pos & 0x3)
3354 r = get_user(value, (uint32_t *)buf);
3358 WREG32_SMC(*pos, value);
3369 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3370 size_t size, loff_t *pos)
3372 struct amdgpu_device *adev = file_inode(f)->i_private;
3375 uint32_t *config, no_regs = 0;
3377 if (size & 0x3 || *pos & 0x3)
3380 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3384 /* version, increment each time something is added */
3385 config[no_regs++] = 3;
3386 config[no_regs++] = adev->gfx.config.max_shader_engines;
3387 config[no_regs++] = adev->gfx.config.max_tile_pipes;
3388 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3389 config[no_regs++] = adev->gfx.config.max_sh_per_se;
3390 config[no_regs++] = adev->gfx.config.max_backends_per_se;
3391 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3392 config[no_regs++] = adev->gfx.config.max_gprs;
3393 config[no_regs++] = adev->gfx.config.max_gs_threads;
3394 config[no_regs++] = adev->gfx.config.max_hw_contexts;
3395 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3396 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3397 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3398 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3399 config[no_regs++] = adev->gfx.config.num_tile_pipes;
3400 config[no_regs++] = adev->gfx.config.backend_enable_mask;
3401 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3402 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3403 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3404 config[no_regs++] = adev->gfx.config.num_gpus;
3405 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3406 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3407 config[no_regs++] = adev->gfx.config.gb_addr_config;
3408 config[no_regs++] = adev->gfx.config.num_rbs;
3411 config[no_regs++] = adev->rev_id;
3412 config[no_regs++] = adev->pg_flags;
3413 config[no_regs++] = adev->cg_flags;
3416 config[no_regs++] = adev->family;
3417 config[no_regs++] = adev->external_rev_id;
3420 config[no_regs++] = adev->pdev->device;
3421 config[no_regs++] = adev->pdev->revision;
3422 config[no_regs++] = adev->pdev->subsystem_device;
3423 config[no_regs++] = adev->pdev->subsystem_vendor;
3425 while (size && (*pos < no_regs * 4)) {
3428 value = config[*pos >> 2];
3429 r = put_user(value, (uint32_t *)buf);
3445 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3446 size_t size, loff_t *pos)
3448 struct amdgpu_device *adev = file_inode(f)->i_private;
3449 int idx, x, outsize, r, valuesize;
3450 uint32_t values[16];
3452 if (size & 3 || *pos & 0x3)
3455 if (amdgpu_dpm == 0)
3458 /* convert offset to sensor number */
3461 valuesize = sizeof(values);
3462 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3463 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
3464 else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
3465 r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
3470 if (size > valuesize)
3477 r = put_user(values[x++], (int32_t *)buf);
3484 return !r ? outsize : r;
3487 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3488 size_t size, loff_t *pos)
3490 struct amdgpu_device *adev = f->f_inode->i_private;
3493 uint32_t offset, se, sh, cu, wave, simd, data[32];
3495 if (size & 3 || *pos & 3)
3499 offset = (*pos & 0x7F);
3500 se = ((*pos >> 7) & 0xFF);
3501 sh = ((*pos >> 15) & 0xFF);
3502 cu = ((*pos >> 23) & 0xFF);
3503 wave = ((*pos >> 31) & 0xFF);
3504 simd = ((*pos >> 37) & 0xFF);
3506 /* switch to the specific se/sh/cu */
3507 mutex_lock(&adev->grbm_idx_mutex);
3508 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3511 if (adev->gfx.funcs->read_wave_data)
3512 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3514 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3515 mutex_unlock(&adev->grbm_idx_mutex);
3520 while (size && (offset < x * 4)) {
3523 value = data[offset >> 2];
3524 r = put_user(value, (uint32_t *)buf);
3537 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3538 size_t size, loff_t *pos)
3540 struct amdgpu_device *adev = f->f_inode->i_private;
3543 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3545 if (size & 3 || *pos & 3)
3549 offset = (*pos & 0xFFF); /* in dwords */
3550 se = ((*pos >> 12) & 0xFF);
3551 sh = ((*pos >> 20) & 0xFF);
3552 cu = ((*pos >> 28) & 0xFF);
3553 wave = ((*pos >> 36) & 0xFF);
3554 simd = ((*pos >> 44) & 0xFF);
3555 thread = ((*pos >> 52) & 0xFF);
3556 bank = ((*pos >> 60) & 1);
3558 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3562 /* switch to the specific se/sh/cu */
3563 mutex_lock(&adev->grbm_idx_mutex);
3564 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3567 if (adev->gfx.funcs->read_wave_vgprs)
3568 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3570 if (adev->gfx.funcs->read_wave_sgprs)
3571 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3574 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3575 mutex_unlock(&adev->grbm_idx_mutex);
3580 value = data[offset++];
3581 r = put_user(value, (uint32_t *)buf);
3597 static const struct file_operations amdgpu_debugfs_regs_fops = {
3598 .owner = THIS_MODULE,
3599 .read = amdgpu_debugfs_regs_read,
3600 .write = amdgpu_debugfs_regs_write,
3601 .llseek = default_llseek
3603 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3604 .owner = THIS_MODULE,
3605 .read = amdgpu_debugfs_regs_didt_read,
3606 .write = amdgpu_debugfs_regs_didt_write,
3607 .llseek = default_llseek
3609 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3610 .owner = THIS_MODULE,
3611 .read = amdgpu_debugfs_regs_pcie_read,
3612 .write = amdgpu_debugfs_regs_pcie_write,
3613 .llseek = default_llseek
3615 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3616 .owner = THIS_MODULE,
3617 .read = amdgpu_debugfs_regs_smc_read,
3618 .write = amdgpu_debugfs_regs_smc_write,
3619 .llseek = default_llseek
3622 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3623 .owner = THIS_MODULE,
3624 .read = amdgpu_debugfs_gca_config_read,
3625 .llseek = default_llseek
3628 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3629 .owner = THIS_MODULE,
3630 .read = amdgpu_debugfs_sensor_read,
3631 .llseek = default_llseek
3634 static const struct file_operations amdgpu_debugfs_wave_fops = {
3635 .owner = THIS_MODULE,
3636 .read = amdgpu_debugfs_wave_read,
3637 .llseek = default_llseek
3639 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3640 .owner = THIS_MODULE,
3641 .read = amdgpu_debugfs_gpr_read,
3642 .llseek = default_llseek
3645 static const struct file_operations *debugfs_regs[] = {
3646 &amdgpu_debugfs_regs_fops,
3647 &amdgpu_debugfs_regs_didt_fops,
3648 &amdgpu_debugfs_regs_pcie_fops,
3649 &amdgpu_debugfs_regs_smc_fops,
3650 &amdgpu_debugfs_gca_config_fops,
3651 &amdgpu_debugfs_sensors_fops,
3652 &amdgpu_debugfs_wave_fops,
3653 &amdgpu_debugfs_gpr_fops,
3656 static const char *debugfs_regs_names[] = {
3661 "amdgpu_gca_config",
3667 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3669 struct drm_minor *minor = adev->ddev->primary;
3670 struct dentry *ent, *root = minor->debugfs_root;
3673 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3674 ent = debugfs_create_file(debugfs_regs_names[i],
3675 S_IFREG | S_IRUGO, root,
3676 adev, debugfs_regs[i]);
3678 for (j = 0; j < i; j++) {
3679 debugfs_remove(adev->debugfs_regs[i]);
3680 adev->debugfs_regs[i] = NULL;
3682 return PTR_ERR(ent);
3686 i_size_write(ent->d_inode, adev->rmmio_size);
3687 adev->debugfs_regs[i] = ent;
3693 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3697 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3698 if (adev->debugfs_regs[i]) {
3699 debugfs_remove(adev->debugfs_regs[i]);
3700 adev->debugfs_regs[i] = NULL;
3705 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
3707 struct drm_info_node *node = (struct drm_info_node *) m->private;
3708 struct drm_device *dev = node->minor->dev;
3709 struct amdgpu_device *adev = dev->dev_private;
3712 /* hold on the scheduler */
3713 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3714 struct amdgpu_ring *ring = adev->rings[i];
3716 if (!ring || !ring->sched.thread)
3718 kthread_park(ring->sched.thread);
3721 seq_printf(m, "run ib test:\n");
3722 r = amdgpu_ib_ring_tests(adev);
3724 seq_printf(m, "ib ring tests failed (%d).\n", r);
3726 seq_printf(m, "ib ring tests passed.\n");
3728 /* go on the scheduler */
3729 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3730 struct amdgpu_ring *ring = adev->rings[i];
3732 if (!ring || !ring->sched.thread)
3734 kthread_unpark(ring->sched.thread);
3740 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
3741 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
3744 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3746 return amdgpu_debugfs_add_files(adev,
3747 amdgpu_debugfs_test_ib_ring_list, 1);
3750 int amdgpu_debugfs_init(struct drm_minor *minor)
3755 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3759 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3763 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }