drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/console.h>
  31 #include <linux/slab.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <linux/vgaarb.h>
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/efi.h>
  39 #include "amdgpu.h"
  40 #include "amdgpu_trace.h"
  41 #include "amdgpu_i2c.h"
  42 #include "atom.h"
  43 #include "amdgpu_atombios.h"
  44 #include "amdgpu_atomfirmware.h"
  45 #include "amd_pcie.h"
  46 #ifdef CONFIG_DRM_AMDGPU_SI
  47 #include "si.h"
  48 #endif
  49 #ifdef CONFIG_DRM_AMDGPU_CIK
  50 #include "cik.h"
  51 #endif
  52 #include "vi.h"
  53 #include "soc15.h"
  54 #include "bif/bif_4_1_d.h"
  55 #include <linux/pci.h>
  56 #include <linux/firmware.h>
  57 #include "amdgpu_vf_error.h"
  58
  59 #include "amdgpu_amdkfd.h"
  60 #include "amdgpu_pm.h"
  61
  62 /*(DEBLOBBED)*/
  63
  64 #define AMDGPU_RESUME_MS                2000
  65
  66 static const char *amdgpu_asic_name[] = {
  67         "TAHITI",
  68         "PITCAIRN",
  69         "VERDE",
  70         "OLAND",
  71         "HAINAN",
  72         "BONAIRE",
  73         "KAVERI",
  74         "KABINI",
  75         "HAWAII",
  76         "MULLINS",
  77         "TOPAZ",
  78         "TONGA",
  79         "FIJI",
  80         "CARRIZO",
  81         "STONEY",
  82         "POLARIS10",
  83         "POLARIS11",
  84         "POLARIS12",
  85         "VEGAM",
  86         "VEGA10",
  87         "VEGA12",
  88         "VEGA20",
  89         "RAVEN",
  90         "LAST",
  91 };
  92
  93 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
  94
  95 /**
  96  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
  97  *
  98  * @dev: drm_device pointer
  99  *
 100  * Returns true if the device is a dGPU with HG/PX power control,
 101  * otherwise return false.
 102  */
 103 bool amdgpu_device_is_px(struct drm_device *dev)
 104 {
 105         struct amdgpu_device *adev = dev->dev_private;
 106
 107         if (adev->flags & AMD_IS_PX)
 108                 return true;
 109         return false;
 110 }
 111
 112 /*
 113  * MMIO register access helper functions.
 114  */
 115 /**
 116  * amdgpu_mm_rreg - read a memory mapped IO register
 117  *
 118  * @adev: amdgpu_device pointer
 119  * @reg: dword aligned register offset
 120  * @acc_flags: access flags which require special behavior
 121  *
 122  * Returns the 32 bit value from the offset specified.
 123  */
 124 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 125                         uint32_t acc_flags)
 126 {
 127         uint32_t ret;
 128
 129         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 130                 return amdgpu_virt_kiq_rreg(adev, reg);
 131
 132         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 133                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 134         else {
 135                 unsigned long flags;
 136
 137                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 138                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 139                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 140                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 141         }
 142         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 143         return ret;
 144 }
 145
 146 /*
 147  * MMIO register read with bytes helper functions
 148  * @offset:bytes offset from MMIO start
 149  *
 150 */
 151
 152 /**
 153  * amdgpu_mm_rreg8 - read a memory mapped IO register
 154  *
 155  * @adev: amdgpu_device pointer
 156  * @offset: byte aligned register offset
 157  *
 158  * Returns the 8 bit value from the offset specified.
 159  */
 160 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 161         if (offset < adev->rmmio_size)
 162                 return (readb(adev->rmmio + offset));
 163         BUG();
 164 }
 165
 166 /*
 167  * MMIO register write with bytes helper functions
 168  * @offset:bytes offset from MMIO start
 169  * @value: the value want to be written to the register
 170  *
 171 */
 172 /**
 173  * amdgpu_mm_wreg8 - read a memory mapped IO register
 174  *
 175  * @adev: amdgpu_device pointer
 176  * @offset: byte aligned register offset
 177  * @value: 8 bit value to write
 178  *
 179  * Writes the value specified to the offset specified.
 180  */
 181 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 182         if (offset < adev->rmmio_size)
 183                 writeb(value, adev->rmmio + offset);
 184         else
 185                 BUG();
 186 }
 187
 188 /**
 189  * amdgpu_mm_wreg - write to a memory mapped IO register
 190  *
 191  * @adev: amdgpu_device pointer
 192  * @reg: dword aligned register offset
 193  * @v: 32 bit value to write to the register
 194  * @acc_flags: access flags which require special behavior
 195  *
 196  * Writes the value specified to the offset specified.
 197  */
 198 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 199                     uint32_t acc_flags)
 200 {
 201         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 202
 203         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 204                 adev->last_mm_index = v;
 205         }
 206
 207         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 208                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 209
 210         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 211                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 212         else {
 213                 unsigned long flags;
 214
 215                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 216                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 217                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 218                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 219         }
 220
 221         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 222                 udelay(500);
 223         }
 224 }
 225
 226 /**
 227  * amdgpu_io_rreg - read an IO register
 228  *
 229  * @adev: amdgpu_device pointer
 230  * @reg: dword aligned register offset
 231  *
 232  * Returns the 32 bit value from the offset specified.
 233  */
 234 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 235 {
 236         if ((reg * 4) < adev->rio_mem_size)
 237                 return ioread32(adev->rio_mem + (reg * 4));
 238         else {
 239                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 240                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 241         }
 242 }
 243
 244 /**
 245  * amdgpu_io_wreg - write to an IO register
 246  *
 247  * @adev: amdgpu_device pointer
 248  * @reg: dword aligned register offset
 249  * @v: 32 bit value to write to the register
 250  *
 251  * Writes the value specified to the offset specified.
 252  */
 253 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 254 {
 255         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 256                 adev->last_mm_index = v;
 257         }
 258
 259         if ((reg * 4) < adev->rio_mem_size)
 260                 iowrite32(v, adev->rio_mem + (reg * 4));
 261         else {
 262                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 263                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 264         }
 265
 266         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 267                 udelay(500);
 268         }
 269 }
 270
 271 /**
 272  * amdgpu_mm_rdoorbell - read a doorbell dword
 273  *
 274  * @adev: amdgpu_device pointer
 275  * @index: doorbell index
 276  *
 277  * Returns the value in the doorbell aperture at the
 278  * requested doorbell index (CIK).
 279  */
 280 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 281 {
 282         if (index < adev->doorbell.num_doorbells) {
 283                 return readl(adev->doorbell.ptr + index);
 284         } else {
 285                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 286                 return 0;
 287         }
 288 }
 289
 290 /**
 291  * amdgpu_mm_wdoorbell - write a doorbell dword
 292  *
 293  * @adev: amdgpu_device pointer
 294  * @index: doorbell index
 295  * @v: value to write
 296  *
 297  * Writes @v to the doorbell aperture at the
 298  * requested doorbell index (CIK).
 299  */
 300 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 301 {
 302         if (index < adev->doorbell.num_doorbells) {
 303                 writel(v, adev->doorbell.ptr + index);
 304         } else {
 305                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 306         }
 307 }
 308
 309 /**
 310  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 311  *
 312  * @adev: amdgpu_device pointer
 313  * @index: doorbell index
 314  *
 315  * Returns the value in the doorbell aperture at the
 316  * requested doorbell index (VEGA10+).
 317  */
 318 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 319 {
 320         if (index < adev->doorbell.num_doorbells) {
 321                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 322         } else {
 323                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 324                 return 0;
 325         }
 326 }
 327
 328 /**
 329  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 330  *
 331  * @adev: amdgpu_device pointer
 332  * @index: doorbell index
 333  * @v: value to write
 334  *
 335  * Writes @v to the doorbell aperture at the
 336  * requested doorbell index (VEGA10+).
 337  */
 338 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 339 {
 340         if (index < adev->doorbell.num_doorbells) {
 341                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 342         } else {
 343                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 344         }
 345 }
 346
 347 /**
 348  * amdgpu_invalid_rreg - dummy reg read function
 349  *
 350  * @adev: amdgpu device pointer
 351  * @reg: offset of register
 352  *
 353  * Dummy register read function.  Used for register blocks
 354  * that certain asics don't have (all asics).
 355  * Returns the value in the register.
 356  */
 357 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 358 {
 359         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 360         BUG();
 361         return 0;
 362 }
 363
 364 /**
 365  * amdgpu_invalid_wreg - dummy reg write function
 366  *
 367  * @adev: amdgpu device pointer
 368  * @reg: offset of register
 369  * @v: value to write to the register
 370  *
 371  * Dummy register read function.  Used for register blocks
 372  * that certain asics don't have (all asics).
 373  */
 374 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 375 {
 376         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 377                   reg, v);
 378         BUG();
 379 }
 380
 381 /**
 382  * amdgpu_block_invalid_rreg - dummy reg read function
 383  *
 384  * @adev: amdgpu device pointer
 385  * @block: offset of instance
 386  * @reg: offset of register
 387  *
 388  * Dummy register read function.  Used for register blocks
 389  * that certain asics don't have (all asics).
 390  * Returns the value in the register.
 391  */
 392 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 393                                           uint32_t block, uint32_t reg)
 394 {
 395         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 396                   reg, block);
 397         BUG();
 398         return 0;
 399 }
 400
 401 /**
 402  * amdgpu_block_invalid_wreg - dummy reg write function
 403  *
 404  * @adev: amdgpu device pointer
 405  * @block: offset of instance
 406  * @reg: offset of register
 407  * @v: value to write to the register
 408  *
 409  * Dummy register read function.  Used for register blocks
 410  * that certain asics don't have (all asics).
 411  */
 412 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 413                                       uint32_t block,
 414                                       uint32_t reg, uint32_t v)
 415 {
 416         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 417                   reg, block, v);
 418         BUG();
 419 }
 420
 421 /**
 422  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 423  *
 424  * @adev: amdgpu device pointer
 425  *
 426  * Allocates a scratch page of VRAM for use by various things in the
 427  * driver.
 428  */
 429 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 430 {
 431         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 432                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 433                                        &adev->vram_scratch.robj,
 434                                        &adev->vram_scratch.gpu_addr,
 435                                        (void **)&adev->vram_scratch.ptr);
 436 }
 437
 438 /**
 439  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 440  *
 441  * @adev: amdgpu device pointer
 442  *
 443  * Frees the VRAM scratch page.
 444  */
 445 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 446 {
 447         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 448 }
 449
 450 /**
 451  * amdgpu_device_program_register_sequence - program an array of registers.
 452  *
 453  * @adev: amdgpu_device pointer
 454  * @registers: pointer to the register array
 455  * @array_size: size of the register array
 456  *
 457  * Programs an array or registers with and and or masks.
 458  * This is a helper for setting golden registers.
 459  */
 460 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 461                                              const u32 *registers,
 462                                              const u32 array_size)
 463 {
 464         u32 tmp, reg, and_mask, or_mask;
 465         int i;
 466
 467         if (array_size % 3)
 468                 return;
 469
 470         for (i = 0; i < array_size; i +=3) {
 471                 reg = registers[i + 0];
 472                 and_mask = registers[i + 1];
 473                 or_mask = registers[i + 2];
 474
 475                 if (and_mask == 0xffffffff) {
 476                         tmp = or_mask;
 477                 } else {
 478                         tmp = RREG32(reg);
 479                         tmp &= ~and_mask;
 480                         tmp |= or_mask;
 481                 }
 482                 WREG32(reg, tmp);
 483         }
 484 }
 485
 486 /**
 487  * amdgpu_device_pci_config_reset - reset the GPU
 488  *
 489  * @adev: amdgpu_device pointer
 490  *
 491  * Resets the GPU using the pci config reset sequence.
 492  * Only applicable to asics prior to vega10.
 493  */
 494 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 495 {
 496         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 497 }
 498
 499 /*
 500  * GPU doorbell aperture helpers function.
 501  */
 502 /**
 503  * amdgpu_device_doorbell_init - Init doorbell driver information.
 504  *
 505  * @adev: amdgpu_device pointer
 506  *
 507  * Init doorbell driver information (CIK)
 508  * Returns 0 on success, error on failure.
 509  */
 510 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 511 {
 512         /* No doorbell on SI hardware generation */
 513         if (adev->asic_type < CHIP_BONAIRE) {
 514                 adev->doorbell.base = 0;
 515                 adev->doorbell.size = 0;
 516                 adev->doorbell.num_doorbells = 0;
 517                 adev->doorbell.ptr = NULL;
 518                 return 0;
 519         }
 520
 521         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 522                 return -EINVAL;
 523
 524         /* doorbell bar mapping */
 525         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 526         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 527
 528         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 529                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 530         if (adev->doorbell.num_doorbells == 0)
 531                 return -EINVAL;
 532
 533         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 534                                      adev->doorbell.num_doorbells *
 535                                      sizeof(u32));
 536         if (adev->doorbell.ptr == NULL)
 537                 return -ENOMEM;
 538
 539         return 0;
 540 }
 541
 542 /**
 543  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 544  *
 545  * @adev: amdgpu_device pointer
 546  *
 547  * Tear down doorbell driver information (CIK)
 548  */
 549 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 550 {
 551         iounmap(adev->doorbell.ptr);
 552         adev->doorbell.ptr = NULL;
 553 }
 554
 555
 556
 557 /*
 558  * amdgpu_device_wb_*()
 559  * Writeback is the method by which the GPU updates special pages in memory
 560  * with the status of certain GPU events (fences, ring pointers,etc.).
 561  */
 562
 563 /**
 564  * amdgpu_device_wb_fini - Disable Writeback and free memory
 565  *
 566  * @adev: amdgpu_device pointer
 567  *
 568  * Disables Writeback and frees the Writeback memory (all asics).
 569  * Used at driver shutdown.
 570  */
 571 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 572 {
 573         if (adev->wb.wb_obj) {
 574                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 575                                       &adev->wb.gpu_addr,
 576                                       (void **)&adev->wb.wb);
 577                 adev->wb.wb_obj = NULL;
 578         }
 579 }
 580
 581 /**
 582  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 583  *
 584  * @adev: amdgpu_device pointer
 585  *
 586  * Initializes writeback and allocates writeback memory (all asics).
 587  * Used at driver startup.
 588  * Returns 0 on success or an -error on failure.
 589  */
 590 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 591 {
 592         int r;
 593
 594         if (adev->wb.wb_obj == NULL) {
 595                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 596                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 597                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 598                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 599                                             (void **)&adev->wb.wb);
 600                 if (r) {
 601                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 602                         return r;
 603                 }
 604
 605                 adev->wb.num_wb = AMDGPU_MAX_WB;
 606                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 607
 608                 /* clear wb memory */
 609                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 610         }
 611
 612         return 0;
 613 }
 614
 615 /**
 616  * amdgpu_device_wb_get - Allocate a wb entry
 617  *
 618  * @adev: amdgpu_device pointer
 619  * @wb: wb index
 620  *
 621  * Allocate a wb slot for use by the driver (all asics).
 622  * Returns 0 on success or -EINVAL on failure.
 623  */
 624 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 625 {
 626         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 627
 628         if (offset < adev->wb.num_wb) {
 629                 __set_bit(offset, adev->wb.used);
 630                 *wb = offset << 3; /* convert to dw offset */
 631                 return 0;
 632         } else {
 633                 return -EINVAL;
 634         }
 635 }
 636
 637 /**
 638  * amdgpu_device_wb_free - Free a wb entry
 639  *
 640  * @adev: amdgpu_device pointer
 641  * @wb: wb index
 642  *
 643  * Free a wb slot allocated for use by the driver (all asics)
 644  */
 645 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 646 {
 647         wb >>= 3;
 648         if (wb < adev->wb.num_wb)
 649                 __clear_bit(wb, adev->wb.used);
 650 }
 651
 652 /**
 653  * amdgpu_device_vram_location - try to find VRAM location
 654  *
 655  * @adev: amdgpu device structure holding all necessary informations
 656  * @mc: memory controller structure holding memory informations
 657  * @base: base address at which to put VRAM
 658  *
 659  * Function will try to place VRAM at base address provided
 660  * as parameter.
 661  */
 662 void amdgpu_device_vram_location(struct amdgpu_device *adev,
 663                                  struct amdgpu_gmc *mc, u64 base)
 664 {
 665         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 666
 667         mc->vram_start = base;
 668         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 669         if (limit && limit < mc->real_vram_size)
 670                 mc->real_vram_size = limit;
 671         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 672                         mc->mc_vram_size >> 20, mc->vram_start,
 673                         mc->vram_end, mc->real_vram_size >> 20);
 674 }
 675
 676 /**
 677  * amdgpu_device_gart_location - try to find GART location
 678  *
 679  * @adev: amdgpu device structure holding all necessary informations
 680  * @mc: memory controller structure holding memory informations
 681  *
 682  * Function will place try to place GART before or after VRAM.
 683  *
 684  * If GART size is bigger than space left then we ajust GART size.
 685  * Thus function will never fails.
 686  */
 687 void amdgpu_device_gart_location(struct amdgpu_device *adev,
 688                                  struct amdgpu_gmc *mc)
 689 {
 690         u64 size_af, size_bf;
 691
 692         mc->gart_size += adev->pm.smu_prv_buffer_size;
 693
 694         size_af = adev->gmc.mc_mask - mc->vram_end;
 695         size_bf = mc->vram_start;
 696         if (size_bf > size_af) {
 697                 if (mc->gart_size > size_bf) {
 698                         dev_warn(adev->dev, "limiting GART\n");
 699                         mc->gart_size = size_bf;
 700                 }
 701                 mc->gart_start = 0;
 702         } else {
 703                 if (mc->gart_size > size_af) {
 704                         dev_warn(adev->dev, "limiting GART\n");
 705                         mc->gart_size = size_af;
 706                 }
 707                 /* VCE doesn't like it when BOs cross a 4GB segment, so align
 708                  * the GART base on a 4GB boundary as well.
 709                  */
 710                 mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
 711         }
 712         mc->gart_end = mc->gart_start + mc->gart_size - 1;
 713         dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
 714                         mc->gart_size >> 20, mc->gart_start, mc->gart_end);
 715 }
 716
 717 /**
 718  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 719  *
 720  * @adev: amdgpu_device pointer
 721  *
 722  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 723  * to fail, but if any of the BARs is not accessible after the size we abort
 724  * driver loading by returning -ENODEV.
 725  */
 726 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 727 {
 728         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 729         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 730         struct pci_bus *root;
 731         struct resource *res;
 732         unsigned i;
 733         u16 cmd;
 734         int r;
 735
 736         /* Bypass for VF */
 737         if (amdgpu_sriov_vf(adev))
 738                 return 0;
 739
 740         /* Check if the root BUS has 64bit memory resources */
 741         root = adev->pdev->bus;
 742         while (root->parent)
 743                 root = root->parent;
 744
 745         pci_bus_for_each_resource(root, res, i) {
 746                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 747                     res->start > 0x100000000ull)
 748                         break;
 749         }
 750
 751         /* Trying to resize is pointless without a root hub window above 4GB */
 752         if (!res)
 753                 return 0;
 754
 755         /* Disable memory decoding while we change the BAR addresses and size */
 756         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 757         pci_write_config_word(adev->pdev, PCI_COMMAND,
 758                               cmd & ~PCI_COMMAND_MEMORY);
 759
 760         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 761         amdgpu_device_doorbell_fini(adev);
 762         if (adev->asic_type >= CHIP_BONAIRE)
 763                 pci_release_resource(adev->pdev, 2);
 764
 765         pci_release_resource(adev->pdev, 0);
 766
 767         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 768         if (r == -ENOSPC)
 769                 DRM_INFO("Not enough PCI address space for a large BAR.");
 770         else if (r && r != -ENOTSUPP)
 771                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 772
 773         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 774
 775         /* When the doorbell or fb BAR isn't available we have no chance of
 776          * using the device.
 777          */
 778         r = amdgpu_device_doorbell_init(adev);
 779         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 780                 return -ENODEV;
 781
 782         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 783
 784         return 0;
 785 }
 786
 787 /*
 788  * GPU helpers function.
 789  */
 790 /**
 791  * amdgpu_device_need_post - check if the hw need post or not
 792  *
 793  * @adev: amdgpu_device pointer
 794  *
 795  * Check if the asic has been initialized (all asics) at driver startup
 796  * or post is needed if  hw reset is performed.
 797  * Returns true if need or false if not.
 798  */
 799 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 800 {
 801         uint32_t reg;
 802
 803         if (amdgpu_sriov_vf(adev))
 804                 return false;
 805
 806         if (amdgpu_passthrough(adev)) {
 807                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 808                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 809                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 810                  * vpost executed for smc version below 22.15
 811                  */
 812                 if (adev->asic_type == CHIP_FIJI) {
 813                         int err;
 814                         uint32_t fw_ver;
 815                         err = reject_firmware(&adev->pm.fw, "/*(DEBLOBBED)*/", adev->dev);
 816                         /* force vPost if error occured */
 817                         if (err)
 818                                 return true;
 819
 820                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 821                         if (fw_ver < 0x00160e00)
 822                                 return true;
 823                 }
 824         }
 825
 826         if (adev->has_hw_reset) {
 827                 adev->has_hw_reset = false;
 828                 return true;
 829         }
 830
 831         /* bios scratch used on CIK+ */
 832         if (adev->asic_type >= CHIP_BONAIRE)
 833                 return amdgpu_atombios_scratch_need_asic_init(adev);
 834
 835         /* check MEM_SIZE for older asics */
 836         reg = amdgpu_asic_get_config_memsize(adev);
 837
 838         if ((reg != 0) && (reg != 0xffffffff))
 839                 return false;
 840
 841         return true;
 842 }
 843
 844 /* if we get transitioned to only one device, take VGA back */
 845 /**
 846  * amdgpu_device_vga_set_decode - enable/disable vga decode
 847  *
 848  * @cookie: amdgpu_device pointer
 849  * @state: enable/disable vga decode
 850  *
 851  * Enable/disable vga decode (all asics).
 852  * Returns VGA resource flags.
 853  */
 854 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 855 {
 856         struct amdgpu_device *adev = cookie;
 857         amdgpu_asic_set_vga_state(adev, state);
 858         if (state)
 859                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 860                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 861         else
 862                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 863 }
 864
 865 /**
 866  * amdgpu_device_check_block_size - validate the vm block size
 867  *
 868  * @adev: amdgpu_device pointer
 869  *
 870  * Validates the vm block size specified via module parameter.
 871  * The vm block size defines number of bits in page table versus page directory,
 872  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 873  * page table and the remaining bits are in the page directory.
 874  */
 875 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 876 {
 877         /* defines number of bits in page table versus page directory,
 878          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 879          * page table and the remaining bits are in the page directory */
 880         if (amdgpu_vm_block_size == -1)
 881                 return;
 882
 883         if (amdgpu_vm_block_size < 9) {
 884                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 885                          amdgpu_vm_block_size);
 886                 amdgpu_vm_block_size = -1;
 887         }
 888 }
 889
 890 /**
 891  * amdgpu_device_check_vm_size - validate the vm size
 892  *
 893  * @adev: amdgpu_device pointer
 894  *
 895  * Validates the vm size in GB specified via module parameter.
 896  * The VM size is the size of the GPU virtual memory space in GB.
 897  */
 898 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 899 {
 900         /* no need to check the default value */
 901         if (amdgpu_vm_size == -1)
 902                 return;
 903
 904         if (amdgpu_vm_size < 1) {
 905                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 906                          amdgpu_vm_size);
 907                 amdgpu_vm_size = -1;
 908         }
 909 }
 910
 911 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 912 {
 913         struct sysinfo si;
 914         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 915         uint64_t total_memory;
 916         uint64_t dram_size_seven_GB = 0x1B8000000;
 917         uint64_t dram_size_three_GB = 0xB8000000;
 918
 919         if (amdgpu_smu_memory_pool_size == 0)
 920                 return;
 921
 922         if (!is_os_64) {
 923                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 924                 goto def_value;
 925         }
 926         si_meminfo(&si);
 927         total_memory = (uint64_t)si.totalram * si.mem_unit;
 928
 929         if ((amdgpu_smu_memory_pool_size == 1) ||
 930                 (amdgpu_smu_memory_pool_size == 2)) {
 931                 if (total_memory < dram_size_three_GB)
 932                         goto def_value1;
 933         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 934                 (amdgpu_smu_memory_pool_size == 8)) {
 935                 if (total_memory < dram_size_seven_GB)
 936                         goto def_value1;
 937         } else {
 938                 DRM_WARN("Smu memory pool size not supported\n");
 939                 goto def_value;
 940         }
 941         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 942
 943         return;
 944
 945 def_value1:
 946         DRM_WARN("No enough system memory\n");
 947 def_value:
 948         adev->pm.smu_prv_buffer_size = 0;
 949 }
 950
 951 /**
 952  * amdgpu_device_check_arguments - validate module params
 953  *
 954  * @adev: amdgpu_device pointer
 955  *
 956  * Validates certain module parameters and updates
 957  * the associated values used by the driver (all asics).
 958  */
 959 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
 960 {
 961         if (amdgpu_sched_jobs < 4) {
 962                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 963                          amdgpu_sched_jobs);
 964                 amdgpu_sched_jobs = 4;
 965         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 966                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 967                          amdgpu_sched_jobs);
 968                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 969         }
 970
 971         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 972                 /* gart size must be greater or equal to 32M */
 973                 dev_warn(adev->dev, "gart size (%d) too small\n",
 974                          amdgpu_gart_size);
 975                 amdgpu_gart_size = -1;
 976         }
 977
 978         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 979                 /* gtt size must be greater or equal to 32M */
 980                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 981                                  amdgpu_gtt_size);
 982                 amdgpu_gtt_size = -1;
 983         }
 984
 985         /* valid range is between 4 and 9 inclusive */
 986         if (amdgpu_vm_fragment_size != -1 &&
 987             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 988                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 989                 amdgpu_vm_fragment_size = -1;
 990         }
 991
 992         amdgpu_device_check_smu_prv_buffer_size(adev);
 993
 994         amdgpu_device_check_vm_size(adev);
 995
 996         amdgpu_device_check_block_size(adev);
 997
 998         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
 999             !is_power_of_2(amdgpu_vram_page_split))) {
1000                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1001                          amdgpu_vram_page_split);
1002                 amdgpu_vram_page_split = 1024;
1003         }
1004
1005         if (amdgpu_lockup_timeout == 0) {
1006                 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
1007                 amdgpu_lockup_timeout = 10000;
1008         }
1009
1010         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1011 }
1012
1013 /**
1014  * amdgpu_switcheroo_set_state - set switcheroo state
1015  *
1016  * @pdev: pci dev pointer
1017  * @state: vga_switcheroo state
1018  *
1019  * Callback for the switcheroo driver.  Suspends or resumes the
1020  * the asics before or after it is powered up using ACPI methods.
1021  */
1022 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1023 {
1024         struct drm_device *dev = pci_get_drvdata(pdev);
1025
1026         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1027                 return;
1028
1029         if (state == VGA_SWITCHEROO_ON) {
1030                 pr_info("amdgpu: switched on\n");
1031                 /* don't suspend or resume card normally */
1032                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1033
1034                 amdgpu_device_resume(dev, true, true);
1035
1036                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1037                 drm_kms_helper_poll_enable(dev);
1038         } else {
1039                 pr_info("amdgpu: switched off\n");
1040                 drm_kms_helper_poll_disable(dev);
1041                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1042                 amdgpu_device_suspend(dev, true, true);
1043                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1044         }
1045 }
1046
1047 /**
1048  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1049  *
1050  * @pdev: pci dev pointer
1051  *
1052  * Callback for the switcheroo driver.  Check of the switcheroo
1053  * state can be changed.
1054  * Returns true if the state can be changed, false if not.
1055  */
1056 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1057 {
1058         struct drm_device *dev = pci_get_drvdata(pdev);
1059
1060         /*
1061         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1062         * locking inversion with the driver load path. And the access here is
1063         * completely racy anyway. So don't bother with locking for now.
1064         */
1065         return dev->open_count == 0;
1066 }
1067
1068 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1069         .set_gpu_state = amdgpu_switcheroo_set_state,
1070         .reprobe = NULL,
1071         .can_switch = amdgpu_switcheroo_can_switch,
1072 };
1073
1074 /**
1075  * amdgpu_device_ip_set_clockgating_state - set the CG state
1076  *
1077  * @dev: amdgpu_device pointer
1078  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1079  * @state: clockgating state (gate or ungate)
1080  *
1081  * Sets the requested clockgating state for all instances of
1082  * the hardware IP specified.
1083  * Returns the error code from the last instance.
1084  */
1085 int amdgpu_device_ip_set_clockgating_state(void *dev,
1086                                            enum amd_ip_block_type block_type,
1087                                            enum amd_clockgating_state state)
1088 {
1089         struct amdgpu_device *adev = dev;
1090         int i, r = 0;
1091
1092         for (i = 0; i < adev->num_ip_blocks; i++) {
1093                 if (!adev->ip_blocks[i].status.valid)
1094                         continue;
1095                 if (adev->ip_blocks[i].version->type != block_type)
1096                         continue;
1097                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1098                         continue;
1099                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1100                         (void *)adev, state);
1101                 if (r)
1102                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1103                                   adev->ip_blocks[i].version->funcs->name, r);
1104         }
1105         return r;
1106 }
1107
1108 /**
1109  * amdgpu_device_ip_set_powergating_state - set the PG state
1110  *
1111  * @dev: amdgpu_device pointer
1112  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1113  * @state: powergating state (gate or ungate)
1114  *
1115  * Sets the requested powergating state for all instances of
1116  * the hardware IP specified.
1117  * Returns the error code from the last instance.
1118  */
1119 int amdgpu_device_ip_set_powergating_state(void *dev,
1120                                            enum amd_ip_block_type block_type,
1121                                            enum amd_powergating_state state)
1122 {
1123         struct amdgpu_device *adev = dev;
1124         int i, r = 0;
1125
1126         for (i = 0; i < adev->num_ip_blocks; i++) {
1127                 if (!adev->ip_blocks[i].status.valid)
1128                         continue;
1129                 if (adev->ip_blocks[i].version->type != block_type)
1130                         continue;
1131                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1132                         continue;
1133                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1134                         (void *)adev, state);
1135                 if (r)
1136                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1137                                   adev->ip_blocks[i].version->funcs->name, r);
1138         }
1139         return r;
1140 }
1141
1142 /**
1143  * amdgpu_device_ip_get_clockgating_state - get the CG state
1144  *
1145  * @adev: amdgpu_device pointer
1146  * @flags: clockgating feature flags
1147  *
1148  * Walks the list of IPs on the device and updates the clockgating
1149  * flags for each IP.
1150  * Updates @flags with the feature flags for each hardware IP where
1151  * clockgating is enabled.
1152  */
1153 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1154                                             u32 *flags)
1155 {
1156         int i;
1157
1158         for (i = 0; i < adev->num_ip_blocks; i++) {
1159                 if (!adev->ip_blocks[i].status.valid)
1160                         continue;
1161                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1162                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1163         }
1164 }
1165
1166 /**
1167  * amdgpu_device_ip_wait_for_idle - wait for idle
1168  *
1169  * @adev: amdgpu_device pointer
1170  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1171  *
1172  * Waits for the request hardware IP to be idle.
1173  * Returns 0 for success or a negative error code on failure.
1174  */
1175 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1176                                    enum amd_ip_block_type block_type)
1177 {
1178         int i, r;
1179
1180         for (i = 0; i < adev->num_ip_blocks; i++) {
1181                 if (!adev->ip_blocks[i].status.valid)
1182                         continue;
1183                 if (adev->ip_blocks[i].version->type == block_type) {
1184                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1185                         if (r)
1186                                 return r;
1187                         break;
1188                 }
1189         }
1190         return 0;
1191
1192 }
1193
1194 /**
1195  * amdgpu_device_ip_is_idle - is the hardware IP idle
1196  *
1197  * @adev: amdgpu_device pointer
1198  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1199  *
1200  * Check if the hardware IP is idle or not.
1201  * Returns true if it the IP is idle, false if not.
1202  */
1203 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1204                               enum amd_ip_block_type block_type)
1205 {
1206         int i;
1207
1208         for (i = 0; i < adev->num_ip_blocks; i++) {
1209                 if (!adev->ip_blocks[i].status.valid)
1210                         continue;
1211                 if (adev->ip_blocks[i].version->type == block_type)
1212                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1213         }
1214         return true;
1215
1216 }
1217
1218 /**
1219  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1220  *
1221  * @adev: amdgpu_device pointer
1222  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1223  *
1224  * Returns a pointer to the hardware IP block structure
1225  * if it exists for the asic, otherwise NULL.
1226  */
1227 struct amdgpu_ip_block *
1228 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1229                               enum amd_ip_block_type type)
1230 {
1231         int i;
1232
1233         for (i = 0; i < adev->num_ip_blocks; i++)
1234                 if (adev->ip_blocks[i].version->type == type)
1235                         return &adev->ip_blocks[i];
1236
1237         return NULL;
1238 }
1239
1240 /**
1241  * amdgpu_device_ip_block_version_cmp
1242  *
1243  * @adev: amdgpu_device pointer
1244  * @type: enum amd_ip_block_type
1245  * @major: major version
1246  * @minor: minor version
1247  *
1248  * return 0 if equal or greater
1249  * return 1 if smaller or the ip_block doesn't exist
1250  */
1251 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1252                                        enum amd_ip_block_type type,
1253                                        u32 major, u32 minor)
1254 {
1255         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1256
1257         if (ip_block && ((ip_block->version->major > major) ||
1258                         ((ip_block->version->major == major) &&
1259                         (ip_block->version->minor >= minor))))
1260                 return 0;
1261
1262         return 1;
1263 }
1264
1265 /**
1266  * amdgpu_device_ip_block_add
1267  *
1268  * @adev: amdgpu_device pointer
1269  * @ip_block_version: pointer to the IP to add
1270  *
1271  * Adds the IP block driver information to the collection of IPs
1272  * on the asic.
1273  */
1274 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1275                                const struct amdgpu_ip_block_version *ip_block_version)
1276 {
1277         if (!ip_block_version)
1278                 return -EINVAL;
1279
1280         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1281                   ip_block_version->funcs->name);
1282
1283         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1284
1285         return 0;
1286 }
1287
1288 /**
1289  * amdgpu_device_enable_virtual_display - enable virtual display feature
1290  *
1291  * @adev: amdgpu_device pointer
1292  *
1293  * Enabled the virtual display feature if the user has enabled it via
1294  * the module parameter virtual_display.  This feature provides a virtual
1295  * display hardware on headless boards or in virtualized environments.
1296  * This function parses and validates the configuration string specified by
1297  * the user and configues the virtual display configuration (number of
1298  * virtual connectors, crtcs, etc.) specified.
1299  */
1300 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1301 {
1302         adev->enable_virtual_display = false;
1303
1304         if (amdgpu_virtual_display) {
1305                 struct drm_device *ddev = adev->ddev;
1306                 const char *pci_address_name = pci_name(ddev->pdev);
1307                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1308
1309                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1310                 pciaddstr_tmp = pciaddstr;
1311                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1312                         pciaddname = strsep(&pciaddname_tmp, ",");
1313                         if (!strcmp("all", pciaddname)
1314                             || !strcmp(pci_address_name, pciaddname)) {
1315                                 long num_crtc;
1316                                 int res = -1;
1317
1318                                 adev->enable_virtual_display = true;
1319
1320                                 if (pciaddname_tmp)
1321                                         res = kstrtol(pciaddname_tmp, 10,
1322                                                       &num_crtc);
1323
1324                                 if (!res) {
1325                                         if (num_crtc < 1)
1326                                                 num_crtc = 1;
1327                                         if (num_crtc > 6)
1328                                                 num_crtc = 6;
1329                                         adev->mode_info.num_crtc = num_crtc;
1330                                 } else {
1331                                         adev->mode_info.num_crtc = 1;
1332                                 }
1333                                 break;
1334                         }
1335                 }
1336
1337                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1338                          amdgpu_virtual_display, pci_address_name,
1339                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1340
1341                 kfree(pciaddstr);
1342         }
1343 }
1344
1345 /**
1346  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1347  *
1348  * @adev: amdgpu_device pointer
1349  *
1350  * Parses the asic configuration parameters specified in the gpu info
1351  * firmware and makes them availale to the driver for use in configuring
1352  * the asic.
1353  * Returns 0 on success, -EINVAL on failure.
1354  */
1355 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1356 {
1357         const char *chip_name;
1358         char fw_name[30];
1359         int err;
1360         const struct gpu_info_firmware_header_v1_0 *hdr;
1361
1362         adev->firmware.gpu_info_fw = NULL;
1363
1364         switch (adev->asic_type) {
1365         case CHIP_TOPAZ:
1366         case CHIP_TONGA:
1367         case CHIP_FIJI:
1368         case CHIP_POLARIS10:
1369         case CHIP_POLARIS11:
1370         case CHIP_POLARIS12:
1371         case CHIP_VEGAM:
1372         case CHIP_CARRIZO:
1373         case CHIP_STONEY:
1374 #ifdef CONFIG_DRM_AMDGPU_SI
1375         case CHIP_VERDE:
1376         case CHIP_TAHITI:
1377         case CHIP_PITCAIRN:
1378         case CHIP_OLAND:
1379         case CHIP_HAINAN:
1380 #endif
1381 #ifdef CONFIG_DRM_AMDGPU_CIK
1382         case CHIP_BONAIRE:
1383         case CHIP_HAWAII:
1384         case CHIP_KAVERI:
1385         case CHIP_KABINI:
1386         case CHIP_MULLINS:
1387 #endif
1388         case CHIP_VEGA20:
1389         default:
1390                 return 0;
1391         case CHIP_VEGA10:
1392                 chip_name = "vega10";
1393                 break;
1394         case CHIP_VEGA12:
1395                 chip_name = "vega12";
1396                 break;
1397         case CHIP_RAVEN:
1398                 chip_name = "raven";
1399                 break;
1400         }
1401
1402         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1403         err = reject_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1404         if (err) {
1405                 dev_err(adev->dev,
1406                         "Failed to load gpu_info firmware \"%s\"\n",
1407                         fw_name);
1408                 goto out;
1409         }
1410         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1411         if (err) {
1412                 dev_err(adev->dev,
1413                         "Failed to validate gpu_info firmware \"%s\"\n",
1414                         fw_name);
1415                 goto out;
1416         }
1417
1418         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1419         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1420
1421         switch (hdr->version_major) {
1422         case 1:
1423         {
1424                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1425                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1426                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1427
1428                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1429                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1430                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1431                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1432                 adev->gfx.config.max_texture_channel_caches =
1433                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1434                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1435                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1436                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1437                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1438                 adev->gfx.config.double_offchip_lds_buf =
1439                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1440                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1441                 adev->gfx.cu_info.max_waves_per_simd =
1442                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1443                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1444                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1445                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1446                 break;
1447         }
1448         default:
1449                 dev_err(adev->dev,
1450                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1451                 err = -EINVAL;
1452                 goto out;
1453         }
1454 out:
1455         return err;
1456 }
1457
1458 /**
1459  * amdgpu_device_ip_early_init - run early init for hardware IPs
1460  *
1461  * @adev: amdgpu_device pointer
1462  *
1463  * Early initialization pass for hardware IPs.  The hardware IPs that make
1464  * up each asic are discovered each IP's early_init callback is run.  This
1465  * is the first stage in initializing the asic.
1466  * Returns 0 on success, negative error code on failure.
1467  */
1468 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1469 {
1470         int i, r;
1471
1472         amdgpu_device_enable_virtual_display(adev);
1473
1474         switch (adev->asic_type) {
1475         case CHIP_TOPAZ:
1476         case CHIP_TONGA:
1477         case CHIP_FIJI:
1478         case CHIP_POLARIS10:
1479         case CHIP_POLARIS11:
1480         case CHIP_POLARIS12:
1481         case CHIP_VEGAM:
1482         case CHIP_CARRIZO:
1483         case CHIP_STONEY:
1484                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1485                         adev->family = AMDGPU_FAMILY_CZ;
1486                 else
1487                         adev->family = AMDGPU_FAMILY_VI;
1488
1489                 r = vi_set_ip_blocks(adev);
1490                 if (r)
1491                         return r;
1492                 break;
1493 #ifdef CONFIG_DRM_AMDGPU_SI
1494         case CHIP_VERDE:
1495         case CHIP_TAHITI:
1496         case CHIP_PITCAIRN:
1497         case CHIP_OLAND:
1498         case CHIP_HAINAN:
1499                 adev->family = AMDGPU_FAMILY_SI;
1500                 r = si_set_ip_blocks(adev);
1501                 if (r)
1502                         return r;
1503                 break;
1504 #endif
1505 #ifdef CONFIG_DRM_AMDGPU_CIK
1506         case CHIP_BONAIRE:
1507         case CHIP_HAWAII:
1508         case CHIP_KAVERI:
1509         case CHIP_KABINI:
1510         case CHIP_MULLINS:
1511                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1512                         adev->family = AMDGPU_FAMILY_CI;
1513                 else
1514                         adev->family = AMDGPU_FAMILY_KV;
1515
1516                 r = cik_set_ip_blocks(adev);
1517                 if (r)
1518                         return r;
1519                 break;
1520 #endif
1521         case CHIP_VEGA10:
1522         case CHIP_VEGA12:
1523         case CHIP_VEGA20:
1524         case CHIP_RAVEN:
1525                 if (adev->asic_type == CHIP_RAVEN)
1526                         adev->family = AMDGPU_FAMILY_RV;
1527                 else
1528                         adev->family = AMDGPU_FAMILY_AI;
1529
1530                 r = soc15_set_ip_blocks(adev);
1531                 if (r)
1532                         return r;
1533                 break;
1534         default:
1535                 /* FIXME: not supported yet */
1536                 return -EINVAL;
1537         }
1538
1539         r = amdgpu_device_parse_gpu_info_fw(adev);
1540         if (r)
1541                 return r;
1542
1543         amdgpu_amdkfd_device_probe(adev);
1544
1545         if (amdgpu_sriov_vf(adev)) {
1546                 r = amdgpu_virt_request_full_gpu(adev, true);
1547                 if (r)
1548                         return -EAGAIN;
1549         }
1550
1551         adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
1552
1553         for (i = 0; i < adev->num_ip_blocks; i++) {
1554                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1555                         DRM_ERROR("disabled ip block: %d <%s>\n",
1556                                   i, adev->ip_blocks[i].version->funcs->name);
1557                         adev->ip_blocks[i].status.valid = false;
1558                 } else {
1559                         if (adev->ip_blocks[i].version->funcs->early_init) {
1560                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1561                                 if (r == -ENOENT) {
1562                                         adev->ip_blocks[i].status.valid = false;
1563                                 } else if (r) {
1564                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1565                                                   adev->ip_blocks[i].version->funcs->name, r);
1566                                         return r;
1567                                 } else {
1568                                         adev->ip_blocks[i].status.valid = true;
1569                                 }
1570                         } else {
1571                                 adev->ip_blocks[i].status.valid = true;
1572                         }
1573                 }
1574         }
1575
1576         adev->cg_flags &= amdgpu_cg_mask;
1577         adev->pg_flags &= amdgpu_pg_mask;
1578
1579         return 0;
1580 }
1581
1582 /**
1583  * amdgpu_device_ip_init - run init for hardware IPs
1584  *
1585  * @adev: amdgpu_device pointer
1586  *
1587  * Main initialization pass for hardware IPs.  The list of all the hardware
1588  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1589  * are run.  sw_init initializes the software state associated with each IP
1590  * and hw_init initializes the hardware associated with each IP.
1591  * Returns 0 on success, negative error code on failure.
1592  */
1593 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1594 {
1595         int i, r;
1596
1597         for (i = 0; i < adev->num_ip_blocks; i++) {
1598                 if (!adev->ip_blocks[i].status.valid)
1599                         continue;
1600                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1601                 if (r) {
1602                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1603                                   adev->ip_blocks[i].version->funcs->name, r);
1604                         return r;
1605                 }
1606                 adev->ip_blocks[i].status.sw = true;
1607
1608                 /* need to do gmc hw init early so we can allocate gpu mem */
1609                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1610                         r = amdgpu_device_vram_scratch_init(adev);
1611                         if (r) {
1612                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1613                                 return r;
1614                         }
1615                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1616                         if (r) {
1617                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1618                                 return r;
1619                         }
1620                         r = amdgpu_device_wb_init(adev);
1621                         if (r) {
1622                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1623                                 return r;
1624                         }
1625                         adev->ip_blocks[i].status.hw = true;
1626
1627                         /* right after GMC hw init, we create CSA */
1628                         if (amdgpu_sriov_vf(adev)) {
1629                                 r = amdgpu_allocate_static_csa(adev);
1630                                 if (r) {
1631                                         DRM_ERROR("allocate CSA failed %d\n", r);
1632                                         return r;
1633                                 }
1634                         }
1635                 }
1636         }
1637
1638         for (i = 0; i < adev->num_ip_blocks; i++) {
1639                 if (!adev->ip_blocks[i].status.sw)
1640                         continue;
1641                 if (adev->ip_blocks[i].status.hw)
1642                         continue;
1643                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1644                 if (r) {
1645                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1646                                   adev->ip_blocks[i].version->funcs->name, r);
1647                         return r;
1648                 }
1649                 adev->ip_blocks[i].status.hw = true;
1650         }
1651
1652         amdgpu_amdkfd_device_init(adev);
1653
1654         if (amdgpu_sriov_vf(adev)) {
1655                 amdgpu_virt_init_data_exchange(adev);
1656                 amdgpu_virt_release_full_gpu(adev, true);
1657         }
1658
1659         return 0;
1660 }
1661
1662 /**
1663  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1664  *
1665  * @adev: amdgpu_device pointer
1666  *
1667  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1668  * this function before a GPU reset.  If the value is retained after a
1669  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1670  */
1671 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1672 {
1673         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1674 }
1675
1676 /**
1677  * amdgpu_device_check_vram_lost - check if vram is valid
1678  *
1679  * @adev: amdgpu_device pointer
1680  *
1681  * Checks the reset magic value written to the gart pointer in VRAM.
1682  * The driver calls this after a GPU reset to see if the contents of
1683  * VRAM is lost or now.
1684  * returns true if vram is lost, false if not.
1685  */
1686 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1687 {
1688         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1689                         AMDGPU_RESET_MAGIC_NUM);
1690 }
1691
1692 /**
1693  * amdgpu_device_ip_late_set_cg_state - late init for clockgating
1694  *
1695  * @adev: amdgpu_device pointer
1696  *
1697  * Late initialization pass enabling clockgating for hardware IPs.
1698  * The list of all the hardware IPs that make up the asic is walked and the
1699  * set_clockgating_state callbacks are run.  This stage is run late
1700  * in the init process.
1701  * Returns 0 on success, negative error code on failure.
1702  */
1703 static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
1704 {
1705         int i = 0, r;
1706
1707         if (amdgpu_emu_mode == 1)
1708                 return 0;
1709
1710         for (i = 0; i < adev->num_ip_blocks; i++) {
1711                 if (!adev->ip_blocks[i].status.valid)
1712                         continue;
1713                 /* skip CG for VCE/UVD, it's handled specially */
1714                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1715                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1716                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1717                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1718                         /* enable clockgating to save power */
1719                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1720                                                                                      AMD_CG_STATE_GATE);
1721                         if (r) {
1722                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1723                                           adev->ip_blocks[i].version->funcs->name, r);
1724                                 return r;
1725                         }
1726                 }
1727         }
1728
1729         return 0;
1730 }
1731
1732 static int amdgpu_device_ip_late_set_pg_state(struct amdgpu_device *adev)
1733 {
1734         int i = 0, r;
1735
1736         if (amdgpu_emu_mode == 1)
1737                 return 0;
1738
1739         for (i = 0; i < adev->num_ip_blocks; i++) {
1740                 if (!adev->ip_blocks[i].status.valid)
1741                         continue;
1742                 /* skip CG for VCE/UVD, it's handled specially */
1743                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1744                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1745                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1746                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1747                         /* enable powergating to save power */
1748                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1749                                                                                      AMD_PG_STATE_GATE);
1750                         if (r) {
1751                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1752                                           adev->ip_blocks[i].version->funcs->name, r);
1753                                 return r;
1754                         }
1755                 }
1756         }
1757         return 0;
1758 }
1759
1760 /**
1761  * amdgpu_device_ip_late_init - run late init for hardware IPs
1762  *
1763  * @adev: amdgpu_device pointer
1764  *
1765  * Late initialization pass for hardware IPs.  The list of all the hardware
1766  * IPs that make up the asic is walked and the late_init callbacks are run.
1767  * late_init covers any special initialization that an IP requires
1768  * after all of the have been initialized or something that needs to happen
1769  * late in the init process.
1770  * Returns 0 on success, negative error code on failure.
1771  */
1772 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1773 {
1774         int i = 0, r;
1775
1776         for (i = 0; i < adev->num_ip_blocks; i++) {
1777                 if (!adev->ip_blocks[i].status.valid)
1778                         continue;
1779                 if (adev->ip_blocks[i].version->funcs->late_init) {
1780                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1781                         if (r) {
1782                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1783                                           adev->ip_blocks[i].version->funcs->name, r);
1784                                 return r;
1785                         }
1786                         adev->ip_blocks[i].status.late_initialized = true;
1787                 }
1788         }
1789
1790         amdgpu_device_ip_late_set_cg_state(adev);
1791         amdgpu_device_ip_late_set_pg_state(adev);
1792
1793         queue_delayed_work(system_wq, &adev->late_init_work,
1794                            msecs_to_jiffies(AMDGPU_RESUME_MS));
1795
1796         amdgpu_device_fill_reset_magic(adev);
1797
1798         return 0;
1799 }
1800
1801 /**
1802  * amdgpu_device_ip_fini - run fini for hardware IPs
1803  *
1804  * @adev: amdgpu_device pointer
1805  *
1806  * Main teardown pass for hardware IPs.  The list of all the hardware
1807  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1808  * are run.  hw_fini tears down the hardware associated with each IP
1809  * and sw_fini tears down any software state associated with each IP.
1810  * Returns 0 on success, negative error code on failure.
1811  */
1812 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1813 {
1814         int i, r;
1815
1816         amdgpu_amdkfd_device_fini(adev);
1817         /* need to disable SMC first */
1818         for (i = 0; i < adev->num_ip_blocks; i++) {
1819                 if (!adev->ip_blocks[i].status.hw)
1820                         continue;
1821                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC &&
1822                         adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1823                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1824                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1825                                                                                      AMD_CG_STATE_UNGATE);
1826                         if (r) {
1827                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1828                                           adev->ip_blocks[i].version->funcs->name, r);
1829                                 return r;
1830                         }
1831                         if (adev->powerplay.pp_funcs->set_powergating_by_smu)
1832                                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
1833                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1834                         /* XXX handle errors */
1835                         if (r) {
1836                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1837                                           adev->ip_blocks[i].version->funcs->name, r);
1838                         }
1839                         adev->ip_blocks[i].status.hw = false;
1840                         break;
1841                 }
1842         }
1843
1844         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1845                 if (!adev->ip_blocks[i].status.hw)
1846                         continue;
1847
1848                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1849                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1850                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1851                         adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1852                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1853                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1854                                                                                      AMD_CG_STATE_UNGATE);
1855                         if (r) {
1856                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1857                                           adev->ip_blocks[i].version->funcs->name, r);
1858                                 return r;
1859                         }
1860                 }
1861
1862                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1863                 /* XXX handle errors */
1864                 if (r) {
1865                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1866                                   adev->ip_blocks[i].version->funcs->name, r);
1867                 }
1868
1869                 adev->ip_blocks[i].status.hw = false;
1870         }
1871
1872
1873         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1874                 if (!adev->ip_blocks[i].status.sw)
1875                         continue;
1876
1877                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1878                         amdgpu_free_static_csa(adev);
1879                         amdgpu_device_wb_fini(adev);
1880                         amdgpu_device_vram_scratch_fini(adev);
1881                 }
1882
1883                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1884                 /* XXX handle errors */
1885                 if (r) {
1886                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1887                                   adev->ip_blocks[i].version->funcs->name, r);
1888                 }
1889                 adev->ip_blocks[i].status.sw = false;
1890                 adev->ip_blocks[i].status.valid = false;
1891         }
1892
1893         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1894                 if (!adev->ip_blocks[i].status.late_initialized)
1895                         continue;
1896                 if (adev->ip_blocks[i].version->funcs->late_fini)
1897                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1898                 adev->ip_blocks[i].status.late_initialized = false;
1899         }
1900
1901         if (amdgpu_sriov_vf(adev))
1902                 if (amdgpu_virt_release_full_gpu(adev, false))
1903                         DRM_ERROR("failed to release exclusive mode on fini\n");
1904
1905         return 0;
1906 }
1907
1908 /**
1909  * amdgpu_device_ip_late_init_func_handler - work handler for clockgating
1910  *
1911  * @work: work_struct
1912  *
1913  * Work handler for amdgpu_device_ip_late_set_cg_state.  We put the
1914  * clockgating setup into a worker thread to speed up driver init and
1915  * resume from suspend.
1916  */
1917 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1918 {
1919         struct amdgpu_device *adev =
1920                 container_of(work, struct amdgpu_device, late_init_work.work);
1921         int r;
1922
1923         r = amdgpu_ib_ring_tests(adev);
1924         if (r)
1925                 DRM_ERROR("ib ring test failed (%d).\n", r);
1926 }
1927
1928 /**
1929  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
1930  *
1931  * @adev: amdgpu_device pointer
1932  *
1933  * Main suspend function for hardware IPs.  The list of all the hardware
1934  * IPs that make up the asic is walked, clockgating is disabled and the
1935  * suspend callbacks are run.  suspend puts the hardware and software state
1936  * in each IP into a state suitable for suspend.
1937  * Returns 0 on success, negative error code on failure.
1938  */
1939 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
1940 {
1941         int i, r;
1942
1943         if (amdgpu_sriov_vf(adev))
1944                 amdgpu_virt_request_full_gpu(adev, false);
1945
1946         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1947                 if (!adev->ip_blocks[i].status.valid)
1948                         continue;
1949                 /* displays are handled separately */
1950                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
1951                         /* ungate blocks so that suspend can properly shut them down */
1952                         if (adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1953                                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1954                                                                                              AMD_CG_STATE_UNGATE);
1955                                 if (r) {
1956                                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1957                                                   adev->ip_blocks[i].version->funcs->name, r);
1958                                 }
1959                         }
1960                         /* XXX handle errors */
1961                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
1962                         /* XXX handle errors */
1963                         if (r) {
1964                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1965                                           adev->ip_blocks[i].version->funcs->name, r);
1966                         }
1967                 }
1968         }
1969
1970         if (amdgpu_sriov_vf(adev))
1971                 amdgpu_virt_release_full_gpu(adev, false);
1972
1973         return 0;
1974 }
1975
1976 /**
1977  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
1978  *
1979  * @adev: amdgpu_device pointer
1980  *
1981  * Main suspend function for hardware IPs.  The list of all the hardware
1982  * IPs that make up the asic is walked, clockgating is disabled and the
1983  * suspend callbacks are run.  suspend puts the hardware and software state
1984  * in each IP into a state suitable for suspend.
1985  * Returns 0 on success, negative error code on failure.
1986  */
1987 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
1988 {
1989         int i, r;
1990
1991         if (amdgpu_sriov_vf(adev))
1992                 amdgpu_virt_request_full_gpu(adev, false);
1993
1994         /* ungate SMC block first */
1995         r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1996                                                    AMD_CG_STATE_UNGATE);
1997         if (r) {
1998                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
1999         }
2000
2001         /* call smu to disable gfx off feature first when suspend */
2002         if (adev->powerplay.pp_funcs->set_powergating_by_smu)
2003                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
2004
2005         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2006                 if (!adev->ip_blocks[i].status.valid)
2007                         continue;
2008                 /* displays are handled in phase1 */
2009                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2010                         continue;
2011                 /* ungate blocks so that suspend can properly shut them down */
2012                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_SMC &&
2013                         adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2014                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2015                                                                                      AMD_CG_STATE_UNGATE);
2016                         if (r) {
2017                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
2018                                           adev->ip_blocks[i].version->funcs->name, r);
2019                         }
2020                 }
2021                 /* XXX handle errors */
2022                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2023                 /* XXX handle errors */
2024                 if (r) {
2025                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2026                                   adev->ip_blocks[i].version->funcs->name, r);
2027                 }
2028         }
2029
2030         if (amdgpu_sriov_vf(adev))
2031                 amdgpu_virt_release_full_gpu(adev, false);
2032
2033         return 0;
2034 }
2035
2036 /**
2037  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2038  *
2039  * @adev: amdgpu_device pointer
2040  *
2041  * Main suspend function for hardware IPs.  The list of all the hardware
2042  * IPs that make up the asic is walked, clockgating is disabled and the
2043  * suspend callbacks are run.  suspend puts the hardware and software state
2044  * in each IP into a state suitable for suspend.
2045  * Returns 0 on success, negative error code on failure.
2046  */
2047 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2048 {
2049         int r;
2050
2051         r = amdgpu_device_ip_suspend_phase1(adev);
2052         if (r)
2053                 return r;
2054         r = amdgpu_device_ip_suspend_phase2(adev);
2055
2056         return r;
2057 }
2058
2059 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2060 {
2061         int i, r;
2062
2063         static enum amd_ip_block_type ip_order[] = {
2064                 AMD_IP_BLOCK_TYPE_GMC,
2065                 AMD_IP_BLOCK_TYPE_COMMON,
2066                 AMD_IP_BLOCK_TYPE_PSP,
2067                 AMD_IP_BLOCK_TYPE_IH,
2068         };
2069
2070         for (i = 0; i < adev->num_ip_blocks; i++) {
2071                 int j;
2072                 struct amdgpu_ip_block *block;
2073
2074                 for (j = 0; j < adev->num_ip_blocks; j++) {
2075                         block = &adev->ip_blocks[j];
2076
2077                         if (block->version->type != ip_order[i] ||
2078                                 !block->status.valid)
2079                                 continue;
2080
2081                         r = block->version->funcs->hw_init(adev);
2082                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2083                         if (r)
2084                                 return r;
2085                 }
2086         }
2087
2088         return 0;
2089 }
2090
2091 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2092 {
2093         int i, r;
2094
2095         static enum amd_ip_block_type ip_order[] = {
2096                 AMD_IP_BLOCK_TYPE_SMC,
2097                 AMD_IP_BLOCK_TYPE_DCE,
2098                 AMD_IP_BLOCK_TYPE_GFX,
2099                 AMD_IP_BLOCK_TYPE_SDMA,
2100                 AMD_IP_BLOCK_TYPE_UVD,
2101                 AMD_IP_BLOCK_TYPE_VCE
2102         };
2103
2104         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2105                 int j;
2106                 struct amdgpu_ip_block *block;
2107
2108                 for (j = 0; j < adev->num_ip_blocks; j++) {
2109                         block = &adev->ip_blocks[j];
2110
2111                         if (block->version->type != ip_order[i] ||
2112                                 !block->status.valid)
2113                                 continue;
2114
2115                         r = block->version->funcs->hw_init(adev);
2116                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2117                         if (r)
2118                                 return r;
2119                 }
2120         }
2121
2122         return 0;
2123 }
2124
2125 /**
2126  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2127  *
2128  * @adev: amdgpu_device pointer
2129  *
2130  * First resume function for hardware IPs.  The list of all the hardware
2131  * IPs that make up the asic is walked and the resume callbacks are run for
2132  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2133  * after a suspend and updates the software state as necessary.  This
2134  * function is also used for restoring the GPU after a GPU reset.
2135  * Returns 0 on success, negative error code on failure.
2136  */
2137 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2138 {
2139         int i, r;
2140
2141         for (i = 0; i < adev->num_ip_blocks; i++) {
2142                 if (!adev->ip_blocks[i].status.valid)
2143                         continue;
2144                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2145                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2146                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2147                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2148                         if (r) {
2149                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2150                                           adev->ip_blocks[i].version->funcs->name, r);
2151                                 return r;
2152                         }
2153                 }
2154         }
2155
2156         return 0;
2157 }
2158
2159 /**
2160  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2161  *
2162  * @adev: amdgpu_device pointer
2163  *
2164  * First resume function for hardware IPs.  The list of all the hardware
2165  * IPs that make up the asic is walked and the resume callbacks are run for
2166  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2167  * functional state after a suspend and updates the software state as
2168  * necessary.  This function is also used for restoring the GPU after a GPU
2169  * reset.
2170  * Returns 0 on success, negative error code on failure.
2171  */
2172 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2173 {
2174         int i, r;
2175
2176         for (i = 0; i < adev->num_ip_blocks; i++) {
2177                 if (!adev->ip_blocks[i].status.valid)
2178                         continue;
2179                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2180                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2181                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
2182                         continue;
2183                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2184                 if (r) {
2185                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2186                                   adev->ip_blocks[i].version->funcs->name, r);
2187                         return r;
2188                 }
2189         }
2190
2191         return 0;
2192 }
2193
2194 /**
2195  * amdgpu_device_ip_resume - run resume for hardware IPs
2196  *
2197  * @adev: amdgpu_device pointer
2198  *
2199  * Main resume function for hardware IPs.  The hardware IPs
2200  * are split into two resume functions because they are
2201  * are also used in in recovering from a GPU reset and some additional
2202  * steps need to be take between them.  In this case (S3/S4) they are
2203  * run sequentially.
2204  * Returns 0 on success, negative error code on failure.
2205  */
2206 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2207 {
2208         int r;
2209
2210         r = amdgpu_device_ip_resume_phase1(adev);
2211         if (r)
2212                 return r;
2213         r = amdgpu_device_ip_resume_phase2(adev);
2214
2215         return r;
2216 }
2217
2218 /**
2219  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2220  *
2221  * @adev: amdgpu_device pointer
2222  *
2223  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2224  */
2225 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2226 {
2227         if (amdgpu_sriov_vf(adev)) {
2228                 if (adev->is_atom_fw) {
2229                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2230                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2231                 } else {
2232                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2233                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2234                 }
2235
2236                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2237                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2238         }
2239 }
2240
2241 /**
2242  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2243  *
2244  * @asic_type: AMD asic type
2245  *
2246  * Check if there is DC (new modesetting infrastructre) support for an asic.
2247  * returns true if DC has support, false if not.
2248  */
2249 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2250 {
2251         switch (asic_type) {
2252 #if defined(CONFIG_DRM_AMD_DC)
2253         case CHIP_BONAIRE:
2254         case CHIP_KAVERI:
2255         case CHIP_KABINI:
2256         case CHIP_MULLINS:
2257                 /*
2258                  * We have systems in the wild with these ASICs that require
2259                  * LVDS and VGA support which is not supported with DC.
2260                  *
2261                  * Fallback to the non-DC driver here by default so as not to
2262                  * cause regressions.
2263                  */
2264                 return amdgpu_dc > 0;
2265         case CHIP_HAWAII:
2266         case CHIP_CARRIZO:
2267         case CHIP_STONEY:
2268         case CHIP_POLARIS10:
2269         case CHIP_POLARIS11:
2270         case CHIP_POLARIS12:
2271         case CHIP_VEGAM:
2272         case CHIP_TONGA:
2273         case CHIP_FIJI:
2274         case CHIP_VEGA10:
2275         case CHIP_VEGA12:
2276         case CHIP_VEGA20:
2277 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2278         case CHIP_RAVEN:
2279 #endif
2280                 return amdgpu_dc != 0;
2281 #endif
2282         default:
2283                 return false;
2284         }
2285 }
2286
2287 /**
2288  * amdgpu_device_has_dc_support - check if dc is supported
2289  *
2290  * @adev: amdgpu_device_pointer
2291  *
2292  * Returns true for supported, false for not supported
2293  */
2294 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2295 {
2296         if (amdgpu_sriov_vf(adev))
2297                 return false;
2298
2299         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2300 }
2301
2302 /**
2303  * amdgpu_device_init - initialize the driver
2304  *
2305  * @adev: amdgpu_device pointer
2306  * @ddev: drm dev pointer
2307  * @pdev: pci dev pointer
2308  * @flags: driver flags
2309  *
2310  * Initializes the driver info and hw (all asics).
2311  * Returns 0 for success or an error on failure.
2312  * Called at driver startup.
2313  */
2314 int amdgpu_device_init(struct amdgpu_device *adev,
2315                        struct drm_device *ddev,
2316                        struct pci_dev *pdev,
2317                        uint32_t flags)
2318 {
2319         int r, i;
2320         bool runtime = false;
2321         u32 max_MBps;
2322
2323         adev->shutdown = false;
2324         adev->dev = &pdev->dev;
2325         adev->ddev = ddev;
2326         adev->pdev = pdev;
2327         adev->flags = flags;
2328         adev->asic_type = flags & AMD_ASIC_MASK;
2329         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2330         if (amdgpu_emu_mode == 1)
2331                 adev->usec_timeout *= 2;
2332         adev->gmc.gart_size = 512 * 1024 * 1024;
2333         adev->accel_working = false;
2334         adev->num_rings = 0;
2335         adev->mman.buffer_funcs = NULL;
2336         adev->mman.buffer_funcs_ring = NULL;
2337         adev->vm_manager.vm_pte_funcs = NULL;
2338         adev->vm_manager.vm_pte_num_rings = 0;
2339         adev->gmc.gmc_funcs = NULL;
2340         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2341         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2342
2343         adev->smc_rreg = &amdgpu_invalid_rreg;
2344         adev->smc_wreg = &amdgpu_invalid_wreg;
2345         adev->pcie_rreg = &amdgpu_invalid_rreg;
2346         adev->pcie_wreg = &amdgpu_invalid_wreg;
2347         adev->pciep_rreg = &amdgpu_invalid_rreg;
2348         adev->pciep_wreg = &amdgpu_invalid_wreg;
2349         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2350         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2351         adev->didt_rreg = &amdgpu_invalid_rreg;
2352         adev->didt_wreg = &amdgpu_invalid_wreg;
2353         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2354         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2355         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2356         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2357
2358         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2359                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2360                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2361
2362         /* mutex initialization are all done here so we
2363          * can recall function without having locking issues */
2364         atomic_set(&adev->irq.ih.lock, 0);
2365         mutex_init(&adev->firmware.mutex);
2366         mutex_init(&adev->pm.mutex);
2367         mutex_init(&adev->gfx.gpu_clock_mutex);
2368         mutex_init(&adev->srbm_mutex);
2369         mutex_init(&adev->gfx.pipe_reserve_mutex);
2370         mutex_init(&adev->grbm_idx_mutex);
2371         mutex_init(&adev->mn_lock);
2372         mutex_init(&adev->virt.vf_errors.lock);
2373         hash_init(adev->mn_hash);
2374         mutex_init(&adev->lock_reset);
2375
2376         amdgpu_device_check_arguments(adev);
2377
2378         spin_lock_init(&adev->mmio_idx_lock);
2379         spin_lock_init(&adev->smc_idx_lock);
2380         spin_lock_init(&adev->pcie_idx_lock);
2381         spin_lock_init(&adev->uvd_ctx_idx_lock);
2382         spin_lock_init(&adev->didt_idx_lock);
2383         spin_lock_init(&adev->gc_cac_idx_lock);
2384         spin_lock_init(&adev->se_cac_idx_lock);
2385         spin_lock_init(&adev->audio_endpt_idx_lock);
2386         spin_lock_init(&adev->mm_stats.lock);
2387
2388         INIT_LIST_HEAD(&adev->shadow_list);
2389         mutex_init(&adev->shadow_list_lock);
2390
2391         INIT_LIST_HEAD(&adev->ring_lru_list);
2392         spin_lock_init(&adev->ring_lru_list_lock);
2393
2394         INIT_DELAYED_WORK(&adev->late_init_work,
2395                           amdgpu_device_ip_late_init_func_handler);
2396
2397         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2398
2399         /* Registers mapping */
2400         /* TODO: block userspace mapping of io register */
2401         if (adev->asic_type >= CHIP_BONAIRE) {
2402                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2403                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2404         } else {
2405                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2406                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2407         }
2408
2409         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2410         if (adev->rmmio == NULL) {
2411                 return -ENOMEM;
2412         }
2413         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2414         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2415
2416         /* doorbell bar mapping */
2417         amdgpu_device_doorbell_init(adev);
2418
2419         /* io port mapping */
2420         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2421                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2422                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2423                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2424                         break;
2425                 }
2426         }
2427         if (adev->rio_mem == NULL)
2428                 DRM_INFO("PCI I/O BAR is not found.\n");
2429
2430         amdgpu_device_get_pcie_info(adev);
2431
2432         /* early init functions */
2433         r = amdgpu_device_ip_early_init(adev);
2434         if (r)
2435                 return r;
2436
2437         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2438         /* this will fail for cards that aren't VGA class devices, just
2439          * ignore it */
2440         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2441
2442         if (amdgpu_device_is_px(ddev))
2443                 runtime = true;
2444         if (!pci_is_thunderbolt_attached(adev->pdev))
2445                 vga_switcheroo_register_client(adev->pdev,
2446                                                &amdgpu_switcheroo_ops, runtime);
2447         if (runtime)
2448                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2449
2450         if (amdgpu_emu_mode == 1) {
2451                 /* post the asic on emulation mode */
2452                 emu_soc_asic_init(adev);
2453                 goto fence_driver_init;
2454         }
2455
2456         /* Read BIOS */
2457         if (!amdgpu_get_bios(adev)) {
2458                 r = -EINVAL;
2459                 goto failed;
2460         }
2461
2462         r = amdgpu_atombios_init(adev);
2463         if (r) {
2464                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2465                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2466                 goto failed;
2467         }
2468
2469         /* detect if we are with an SRIOV vbios */
2470         amdgpu_device_detect_sriov_bios(adev);
2471
2472         /* Post card if necessary */
2473         if (amdgpu_device_need_post(adev)) {
2474                 if (!adev->bios) {
2475                         dev_err(adev->dev, "no vBIOS found\n");
2476                         r = -EINVAL;
2477                         goto failed;
2478                 }
2479                 DRM_INFO("GPU posting now...\n");
2480                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2481                 if (r) {
2482                         dev_err(adev->dev, "gpu post error!\n");
2483                         goto failed;
2484                 }
2485         }
2486
2487         if (adev->is_atom_fw) {
2488                 /* Initialize clocks */
2489                 r = amdgpu_atomfirmware_get_clock_info(adev);
2490                 if (r) {
2491                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2492                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2493                         goto failed;
2494                 }
2495         } else {
2496                 /* Initialize clocks */
2497                 r = amdgpu_atombios_get_clock_info(adev);
2498                 if (r) {
2499                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2500                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2501                         goto failed;
2502                 }
2503                 /* init i2c buses */
2504                 if (!amdgpu_device_has_dc_support(adev))
2505                         amdgpu_atombios_i2c_init(adev);
2506         }
2507
2508 fence_driver_init:
2509         /* Fence driver */
2510         r = amdgpu_fence_driver_init(adev);
2511         if (r) {
2512                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2513                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2514                 goto failed;
2515         }
2516
2517         /* init the mode config */
2518         drm_mode_config_init(adev->ddev);
2519
2520         r = amdgpu_device_ip_init(adev);
2521         if (r) {
2522                 /* failed in exclusive mode due to timeout */
2523                 if (amdgpu_sriov_vf(adev) &&
2524                     !amdgpu_sriov_runtime(adev) &&
2525                     amdgpu_virt_mmio_blocked(adev) &&
2526                     !amdgpu_virt_wait_reset(adev)) {
2527                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2528                         /* Don't send request since VF is inactive. */
2529                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2530                         adev->virt.ops = NULL;
2531                         r = -EAGAIN;
2532                         goto failed;
2533                 }
2534                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2535                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2536                 goto failed;
2537         }
2538
2539         adev->accel_working = true;
2540
2541         amdgpu_vm_check_compute_bug(adev);
2542
2543         /* Initialize the buffer migration limit. */
2544         if (amdgpu_moverate >= 0)
2545                 max_MBps = amdgpu_moverate;
2546         else
2547                 max_MBps = 8; /* Allow 8 MB/s. */
2548         /* Get a log2 for easy divisions. */
2549         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2550
2551         r = amdgpu_ib_pool_init(adev);
2552         if (r) {
2553                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2554                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2555                 goto failed;
2556         }
2557
2558         amdgpu_fbdev_init(adev);
2559
2560         r = amdgpu_pm_sysfs_init(adev);
2561         if (r)
2562                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2563
2564         r = amdgpu_debugfs_gem_init(adev);
2565         if (r)
2566                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2567
2568         r = amdgpu_debugfs_regs_init(adev);
2569         if (r)
2570                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2571
2572         r = amdgpu_debugfs_firmware_init(adev);
2573         if (r)
2574                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2575
2576         r = amdgpu_debugfs_init(adev);
2577         if (r)
2578                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2579
2580         if ((amdgpu_testing & 1)) {
2581                 if (adev->accel_working)
2582                         amdgpu_test_moves(adev);
2583                 else
2584                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2585         }
2586         if (amdgpu_benchmarking) {
2587                 if (adev->accel_working)
2588                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2589                 else
2590                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2591         }
2592
2593         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2594          * explicit gating rather than handling it automatically.
2595          */
2596         r = amdgpu_device_ip_late_init(adev);
2597         if (r) {
2598                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2599                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2600                 goto failed;
2601         }
2602
2603         return 0;
2604
2605 failed:
2606         amdgpu_vf_error_trans_all(adev);
2607         if (runtime)
2608                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2609
2610         return r;
2611 }
2612
2613 /**
2614  * amdgpu_device_fini - tear down the driver
2615  *
2616  * @adev: amdgpu_device pointer
2617  *
2618  * Tear down the driver info (all asics).
2619  * Called at driver shutdown.
2620  */
2621 void amdgpu_device_fini(struct amdgpu_device *adev)
2622 {
2623         int r;
2624
2625         DRM_INFO("amdgpu: finishing device.\n");
2626         adev->shutdown = true;
2627         /* disable all interrupts */
2628         amdgpu_irq_disable_all(adev);
2629         if (adev->mode_info.mode_config_initialized){
2630                 if (!amdgpu_device_has_dc_support(adev))
2631                         drm_crtc_force_disable_all(adev->ddev);
2632                 else
2633                         drm_atomic_helper_shutdown(adev->ddev);
2634         }
2635         amdgpu_ib_pool_fini(adev);
2636         amdgpu_fence_driver_fini(adev);
2637         amdgpu_pm_sysfs_fini(adev);
2638         amdgpu_fbdev_fini(adev);
2639         r = amdgpu_device_ip_fini(adev);
2640         if (adev->firmware.gpu_info_fw) {
2641                 release_firmware(adev->firmware.gpu_info_fw);
2642                 adev->firmware.gpu_info_fw = NULL;
2643         }
2644         adev->accel_working = false;
2645         cancel_delayed_work_sync(&adev->late_init_work);
2646         /* free i2c buses */
2647         if (!amdgpu_device_has_dc_support(adev))
2648                 amdgpu_i2c_fini(adev);
2649
2650         if (amdgpu_emu_mode != 1)
2651                 amdgpu_atombios_fini(adev);
2652
2653         kfree(adev->bios);
2654         adev->bios = NULL;
2655         if (!pci_is_thunderbolt_attached(adev->pdev))
2656                 vga_switcheroo_unregister_client(adev->pdev);
2657         if (adev->flags & AMD_IS_PX)
2658                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2659         vga_client_register(adev->pdev, NULL, NULL, NULL);
2660         if (adev->rio_mem)
2661                 pci_iounmap(adev->pdev, adev->rio_mem);
2662         adev->rio_mem = NULL;
2663         iounmap(adev->rmmio);
2664         adev->rmmio = NULL;
2665         amdgpu_device_doorbell_fini(adev);
2666         amdgpu_debugfs_regs_cleanup(adev);
2667 }
2668
2669
2670 /*
2671  * Suspend & resume.
2672  */
2673 /**
2674  * amdgpu_device_suspend - initiate device suspend
2675  *
2676  * @dev: drm dev pointer
2677  * @suspend: suspend state
2678  * @fbcon : notify the fbdev of suspend
2679  *
2680  * Puts the hw in the suspend state (all asics).
2681  * Returns 0 for success or an error on failure.
2682  * Called at driver suspend.
2683  */
2684 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2685 {
2686         struct amdgpu_device *adev;
2687         struct drm_crtc *crtc;
2688         struct drm_connector *connector;
2689         int r;
2690
2691         if (dev == NULL || dev->dev_private == NULL) {
2692                 return -ENODEV;
2693         }
2694
2695         adev = dev->dev_private;
2696
2697         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2698                 return 0;
2699
2700         drm_kms_helper_poll_disable(dev);
2701
2702         if (fbcon)
2703                 amdgpu_fbdev_set_suspend(adev, 1);
2704
2705         if (!amdgpu_device_has_dc_support(adev)) {
2706                 /* turn off display hw */
2707                 drm_modeset_lock_all(dev);
2708                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2709                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2710                 }
2711                 drm_modeset_unlock_all(dev);
2712                         /* unpin the front buffers and cursors */
2713                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2714                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2715                         struct drm_framebuffer *fb = crtc->primary->fb;
2716                         struct amdgpu_bo *robj;
2717
2718                         if (amdgpu_crtc->cursor_bo) {
2719                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2720                                 r = amdgpu_bo_reserve(aobj, true);
2721                                 if (r == 0) {
2722                                         amdgpu_bo_unpin(aobj);
2723                                         amdgpu_bo_unreserve(aobj);
2724                                 }
2725                         }
2726
2727                         if (fb == NULL || fb->obj[0] == NULL) {
2728                                 continue;
2729                         }
2730                         robj = gem_to_amdgpu_bo(fb->obj[0]);
2731                         /* don't unpin kernel fb objects */
2732                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2733                                 r = amdgpu_bo_reserve(robj, true);
2734                                 if (r == 0) {
2735                                         amdgpu_bo_unpin(robj);
2736                                         amdgpu_bo_unreserve(robj);
2737                                 }
2738                         }
2739                 }
2740         }
2741
2742         amdgpu_amdkfd_suspend(adev);
2743
2744         r = amdgpu_device_ip_suspend_phase1(adev);
2745
2746         /* evict vram memory */
2747         amdgpu_bo_evict_vram(adev);
2748
2749         amdgpu_fence_driver_suspend(adev);
2750
2751         r = amdgpu_device_ip_suspend_phase2(adev);
2752
2753         /* evict remaining vram memory
2754          * This second call to evict vram is to evict the gart page table
2755          * using the CPU.
2756          */
2757         amdgpu_bo_evict_vram(adev);
2758
2759         pci_save_state(dev->pdev);
2760         if (suspend) {
2761                 /* Shut down the device */
2762                 pci_disable_device(dev->pdev);
2763                 pci_set_power_state(dev->pdev, PCI_D3hot);
2764         } else {
2765                 r = amdgpu_asic_reset(adev);
2766                 if (r)
2767                         DRM_ERROR("amdgpu asic reset failed\n");
2768         }
2769
2770         return 0;
2771 }
2772
2773 /**
2774  * amdgpu_device_resume - initiate device resume
2775  *
2776  * @dev: drm dev pointer
2777  * @resume: resume state
2778  * @fbcon : notify the fbdev of resume
2779  *
2780  * Bring the hw back to operating state (all asics).
2781  * Returns 0 for success or an error on failure.
2782  * Called at driver resume.
2783  */
2784 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2785 {
2786         struct drm_connector *connector;
2787         struct amdgpu_device *adev = dev->dev_private;
2788         struct drm_crtc *crtc;
2789         int r = 0;
2790
2791         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2792                 return 0;
2793
2794         if (resume) {
2795                 pci_set_power_state(dev->pdev, PCI_D0);
2796                 pci_restore_state(dev->pdev);
2797                 r = pci_enable_device(dev->pdev);
2798                 if (r)
2799                         return r;
2800         }
2801
2802         /* post card */
2803         if (amdgpu_device_need_post(adev)) {
2804                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2805                 if (r)
2806                         DRM_ERROR("amdgpu asic init failed\n");
2807         }
2808
2809         r = amdgpu_device_ip_resume(adev);
2810         if (r) {
2811                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2812                 return r;
2813         }
2814         amdgpu_fence_driver_resume(adev);
2815
2816
2817         r = amdgpu_device_ip_late_init(adev);
2818         if (r)
2819                 return r;
2820
2821         if (!amdgpu_device_has_dc_support(adev)) {
2822                 /* pin cursors */
2823                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2824                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2825
2826                         if (amdgpu_crtc->cursor_bo) {
2827                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2828                                 r = amdgpu_bo_reserve(aobj, true);
2829                                 if (r == 0) {
2830                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2831                                         if (r != 0)
2832                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2833                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2834                                         amdgpu_bo_unreserve(aobj);
2835                                 }
2836                         }
2837                 }
2838         }
2839         r = amdgpu_amdkfd_resume(adev);
2840         if (r)
2841                 return r;
2842
2843         /* Make sure IB tests flushed */
2844         flush_delayed_work(&adev->late_init_work);
2845
2846         /* blat the mode back in */
2847         if (fbcon) {
2848                 if (!amdgpu_device_has_dc_support(adev)) {
2849                         /* pre DCE11 */
2850                         drm_helper_resume_force_mode(dev);
2851
2852                         /* turn on display hw */
2853                         drm_modeset_lock_all(dev);
2854                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2855                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2856                         }
2857                         drm_modeset_unlock_all(dev);
2858                 }
2859                 amdgpu_fbdev_set_suspend(adev, 0);
2860         }
2861
2862         drm_kms_helper_poll_enable(dev);
2863
2864         /*
2865          * Most of the connector probing functions try to acquire runtime pm
2866          * refs to ensure that the GPU is powered on when connector polling is
2867          * performed. Since we're calling this from a runtime PM callback,
2868          * trying to acquire rpm refs will cause us to deadlock.
2869          *
2870          * Since we're guaranteed to be holding the rpm lock, it's safe to
2871          * temporarily disable the rpm helpers so this doesn't deadlock us.
2872          */
2873 #ifdef CONFIG_PM
2874         dev->dev->power.disable_depth++;
2875 #endif
2876         if (!amdgpu_device_has_dc_support(adev))
2877                 drm_helper_hpd_irq_event(dev);
2878         else
2879                 drm_kms_helper_hotplug_event(dev);
2880 #ifdef CONFIG_PM
2881         dev->dev->power.disable_depth--;
2882 #endif
2883         return 0;
2884 }
2885
2886 /**
2887  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
2888  *
2889  * @adev: amdgpu_device pointer
2890  *
2891  * The list of all the hardware IPs that make up the asic is walked and
2892  * the check_soft_reset callbacks are run.  check_soft_reset determines
2893  * if the asic is still hung or not.
2894  * Returns true if any of the IPs are still in a hung state, false if not.
2895  */
2896 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2897 {
2898         int i;
2899         bool asic_hang = false;
2900
2901         if (amdgpu_sriov_vf(adev))
2902                 return true;
2903
2904         if (amdgpu_asic_need_full_reset(adev))
2905                 return true;
2906
2907         for (i = 0; i < adev->num_ip_blocks; i++) {
2908                 if (!adev->ip_blocks[i].status.valid)
2909                         continue;
2910                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2911                         adev->ip_blocks[i].status.hang =
2912                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2913                 if (adev->ip_blocks[i].status.hang) {
2914                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2915                         asic_hang = true;
2916                 }
2917         }
2918         return asic_hang;
2919 }
2920
2921 /**
2922  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
2923  *
2924  * @adev: amdgpu_device pointer
2925  *
2926  * The list of all the hardware IPs that make up the asic is walked and the
2927  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
2928  * handles any IP specific hardware or software state changes that are
2929  * necessary for a soft reset to succeed.
2930  * Returns 0 on success, negative error code on failure.
2931  */
2932 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
2933 {
2934         int i, r = 0;
2935
2936         for (i = 0; i < adev->num_ip_blocks; i++) {
2937                 if (!adev->ip_blocks[i].status.valid)
2938                         continue;
2939                 if (adev->ip_blocks[i].status.hang &&
2940                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2941                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2942                         if (r)
2943                                 return r;
2944                 }
2945         }
2946
2947         return 0;
2948 }
2949
2950 /**
2951  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
2952  *
2953  * @adev: amdgpu_device pointer
2954  *
2955  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
2956  * reset is necessary to recover.
2957  * Returns true if a full asic reset is required, false if not.
2958  */
2959 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
2960 {
2961         int i;
2962
2963         if (amdgpu_asic_need_full_reset(adev))
2964                 return true;
2965
2966         for (i = 0; i < adev->num_ip_blocks; i++) {
2967                 if (!adev->ip_blocks[i].status.valid)
2968                         continue;
2969                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2970                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2971                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2972                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2973                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2974                         if (adev->ip_blocks[i].status.hang) {
2975                                 DRM_INFO("Some block need full reset!\n");
2976                                 return true;
2977                         }
2978                 }
2979         }
2980         return false;
2981 }
2982
2983 /**
2984  * amdgpu_device_ip_soft_reset - do a soft reset
2985  *
2986  * @adev: amdgpu_device pointer
2987  *
2988  * The list of all the hardware IPs that make up the asic is walked and the
2989  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
2990  * IP specific hardware or software state changes that are necessary to soft
2991  * reset the IP.
2992  * Returns 0 on success, negative error code on failure.
2993  */
2994 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
2995 {
2996         int i, r = 0;
2997
2998         for (i = 0; i < adev->num_ip_blocks; i++) {
2999                 if (!adev->ip_blocks[i].status.valid)
3000                         continue;
3001                 if (adev->ip_blocks[i].status.hang &&
3002                     adev->ip_blocks[i].version->funcs->soft_reset) {
3003                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3004                         if (r)
3005                                 return r;
3006                 }
3007         }
3008
3009         return 0;
3010 }
3011
3012 /**
3013  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3014  *
3015  * @adev: amdgpu_device pointer
3016  *
3017  * The list of all the hardware IPs that make up the asic is walked and the
3018  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3019  * handles any IP specific hardware or software state changes that are
3020  * necessary after the IP has been soft reset.
3021  * Returns 0 on success, negative error code on failure.
3022  */
3023 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3024 {
3025         int i, r = 0;
3026
3027         for (i = 0; i < adev->num_ip_blocks; i++) {
3028                 if (!adev->ip_blocks[i].status.valid)
3029                         continue;
3030                 if (adev->ip_blocks[i].status.hang &&
3031                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3032                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3033                 if (r)
3034                         return r;
3035         }
3036
3037         return 0;
3038 }
3039
3040 /**
3041  * amdgpu_device_recover_vram_from_shadow - restore shadowed VRAM buffers
3042  *
3043  * @adev: amdgpu_device pointer
3044  * @ring: amdgpu_ring for the engine handling the buffer operations
3045  * @bo: amdgpu_bo buffer whose shadow is being restored
3046  * @fence: dma_fence associated with the operation
3047  *
3048  * Restores the VRAM buffer contents from the shadow in GTT.  Used to
3049  * restore things like GPUVM page tables after a GPU reset where
3050  * the contents of VRAM might be lost.
3051  * Returns 0 on success, negative error code on failure.
3052  */
3053 static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
3054                                                   struct amdgpu_ring *ring,
3055                                                   struct amdgpu_bo *bo,
3056                                                   struct dma_fence **fence)
3057 {
3058         uint32_t domain;
3059         int r;
3060
3061         if (!bo->shadow)
3062                 return 0;
3063
3064         r = amdgpu_bo_reserve(bo, true);
3065         if (r)
3066                 return r;
3067         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
3068         /* if bo has been evicted, then no need to recover */
3069         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
3070                 r = amdgpu_bo_validate(bo->shadow);
3071                 if (r) {
3072                         DRM_ERROR("bo validate failed!\n");
3073                         goto err;
3074                 }
3075
3076                 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
3077                                                  NULL, fence, true);
3078                 if (r) {
3079                         DRM_ERROR("recover page table failed!\n");
3080                         goto err;
3081                 }
3082         }
3083 err:
3084         amdgpu_bo_unreserve(bo);
3085         return r;
3086 }
3087
3088 /**
3089  * amdgpu_device_handle_vram_lost - Handle the loss of VRAM contents
3090  *
3091  * @adev: amdgpu_device pointer
3092  *
3093  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3094  * restore things like GPUVM page tables after a GPU reset where
3095  * the contents of VRAM might be lost.
3096  * Returns 0 on success, 1 on failure.
3097  */
3098 static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev)
3099 {
3100         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
3101         struct amdgpu_bo *bo, *tmp;
3102         struct dma_fence *fence = NULL, *next = NULL;
3103         long r = 1;
3104         int i = 0;
3105         long tmo;
3106
3107         if (amdgpu_sriov_runtime(adev))
3108                 tmo = msecs_to_jiffies(8000);
3109         else
3110                 tmo = msecs_to_jiffies(100);
3111
3112         DRM_INFO("recover vram bo from shadow start\n");
3113         mutex_lock(&adev->shadow_list_lock);
3114         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
3115                 next = NULL;
3116                 amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next);
3117                 if (fence) {
3118                         r = dma_fence_wait_timeout(fence, false, tmo);
3119                         if (r == 0)
3120                                 pr_err("wait fence %p[%d] timeout\n", fence, i);
3121                         else if (r < 0)
3122                                 pr_err("wait fence %p[%d] interrupted\n", fence, i);
3123                         if (r < 1) {
3124                                 dma_fence_put(fence);
3125                                 fence = next;
3126                                 break;
3127                         }
3128                         i++;
3129                 }
3130
3131                 dma_fence_put(fence);
3132                 fence = next;
3133         }
3134         mutex_unlock(&adev->shadow_list_lock);
3135
3136         if (fence) {
3137                 r = dma_fence_wait_timeout(fence, false, tmo);
3138                 if (r == 0)
3139                         pr_err("wait fence %p[%d] timeout\n", fence, i);
3140                 else if (r < 0)
3141                         pr_err("wait fence %p[%d] interrupted\n", fence, i);
3142
3143         }
3144         dma_fence_put(fence);
3145
3146         if (r > 0)
3147                 DRM_INFO("recover vram bo from shadow done\n");
3148         else
3149                 DRM_ERROR("recover vram bo from shadow failed\n");
3150
3151         return (r > 0) ? 0 : 1;
3152 }
3153
3154 /**
3155  * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
3156  *
3157  * @adev: amdgpu device pointer
3158  *
3159  * attempt to do soft-reset or full-reset and reinitialize Asic
3160  * return 0 means succeeded otherwise failed
3161  */
3162 static int amdgpu_device_reset(struct amdgpu_device *adev)
3163 {
3164         bool need_full_reset, vram_lost = 0;
3165         int r;
3166
3167         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3168
3169         if (!need_full_reset) {
3170                 amdgpu_device_ip_pre_soft_reset(adev);
3171                 r = amdgpu_device_ip_soft_reset(adev);
3172                 amdgpu_device_ip_post_soft_reset(adev);
3173                 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3174                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
3175                         need_full_reset = true;
3176                 }
3177         }
3178
3179         if (need_full_reset) {
3180                 r = amdgpu_device_ip_suspend(adev);
3181
3182 retry:
3183                 r = amdgpu_asic_reset(adev);
3184                 /* post card */
3185                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
3186
3187                 if (!r) {
3188                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
3189                         r = amdgpu_device_ip_resume_phase1(adev);
3190                         if (r)
3191                                 goto out;
3192
3193                         vram_lost = amdgpu_device_check_vram_lost(adev);
3194                         if (vram_lost) {
3195                                 DRM_ERROR("VRAM is lost!\n");
3196                                 atomic_inc(&adev->vram_lost_counter);
3197                         }
3198
3199                         r = amdgpu_gtt_mgr_recover(
3200                                 &adev->mman.bdev.man[TTM_PL_TT]);
3201                         if (r)
3202                                 goto out;
3203
3204                         r = amdgpu_device_ip_resume_phase2(adev);
3205                         if (r)
3206                                 goto out;
3207
3208                         if (vram_lost)
3209                                 amdgpu_device_fill_reset_magic(adev);
3210                 }
3211         }
3212
3213 out:
3214         if (!r) {
3215                 amdgpu_irq_gpu_reset_resume_helper(adev);
3216                 r = amdgpu_ib_ring_tests(adev);
3217                 if (r) {
3218                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
3219                         r = amdgpu_device_ip_suspend(adev);
3220                         need_full_reset = true;
3221                         goto retry;
3222                 }
3223         }
3224
3225         if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost))
3226                 r = amdgpu_device_handle_vram_lost(adev);
3227
3228         return r;
3229 }
3230
3231 /**
3232  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3233  *
3234  * @adev: amdgpu device pointer
3235  * @from_hypervisor: request from hypervisor
3236  *
3237  * do VF FLR and reinitialize Asic
3238  * return 0 means succeeded otherwise failed
3239  */
3240 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3241                                      bool from_hypervisor)
3242 {
3243         int r;
3244
3245         if (from_hypervisor)
3246                 r = amdgpu_virt_request_full_gpu(adev, true);
3247         else
3248                 r = amdgpu_virt_reset_gpu(adev);
3249         if (r)
3250                 return r;
3251
3252         /* Resume IP prior to SMC */
3253         r = amdgpu_device_ip_reinit_early_sriov(adev);
3254         if (r)
3255                 goto error;
3256
3257         /* we need recover gart prior to run SMC/CP/SDMA resume */
3258         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3259
3260         /* now we are okay to resume SMC/CP/SDMA */
3261         r = amdgpu_device_ip_reinit_late_sriov(adev);
3262         if (r)
3263                 goto error;
3264
3265         amdgpu_irq_gpu_reset_resume_helper(adev);
3266         r = amdgpu_ib_ring_tests(adev);
3267
3268 error:
3269         amdgpu_virt_init_data_exchange(adev);
3270         amdgpu_virt_release_full_gpu(adev, true);
3271         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3272                 atomic_inc(&adev->vram_lost_counter);
3273                 r = amdgpu_device_handle_vram_lost(adev);
3274         }
3275
3276         return r;
3277 }
3278
3279 /**
3280  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3281  *
3282  * @adev: amdgpu device pointer
3283  * @job: which job trigger hang
3284  * @force: forces reset regardless of amdgpu_gpu_recovery
3285  *
3286  * Attempt to reset the GPU if it has hung (all asics).
3287  * Returns 0 for success or an error on failure.
3288  */
3289 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3290                               struct amdgpu_job *job, bool force)
3291 {
3292         int i, r, resched;
3293
3294         if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
3295                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
3296                 return 0;
3297         }
3298
3299         if (!force && (amdgpu_gpu_recovery == 0 ||
3300                         (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))) {
3301                 DRM_INFO("GPU recovery disabled.\n");
3302                 return 0;
3303         }
3304
3305         dev_info(adev->dev, "GPU reset begin!\n");
3306
3307         mutex_lock(&adev->lock_reset);
3308         atomic_inc(&adev->gpu_reset_counter);
3309         adev->in_gpu_reset = 1;
3310
3311         /* Block kfd */
3312         amdgpu_amdkfd_pre_reset(adev);
3313
3314         /* block TTM */
3315         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3316
3317         /* block all schedulers and reset given job's ring */
3318         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3319                 struct amdgpu_ring *ring = adev->rings[i];
3320
3321                 if (!ring || !ring->sched.thread)
3322                         continue;
3323
3324                 kthread_park(ring->sched.thread);
3325
3326                 if (job && job->base.sched == &ring->sched)
3327                         continue;
3328
3329                 drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL);
3330
3331                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3332                 amdgpu_fence_driver_force_completion(ring);
3333         }
3334
3335         if (amdgpu_sriov_vf(adev))
3336                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3337         else
3338                 r = amdgpu_device_reset(adev);
3339
3340         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3341                 struct amdgpu_ring *ring = adev->rings[i];
3342
3343                 if (!ring || !ring->sched.thread)
3344                         continue;
3345
3346                 /* only need recovery sched of the given job's ring
3347                  * or all rings (in the case @job is NULL)
3348                  * after above amdgpu_reset accomplished
3349                  */
3350                 if ((!job || job->base.sched == &ring->sched) && !r)
3351                         drm_sched_job_recovery(&ring->sched);
3352
3353                 kthread_unpark(ring->sched.thread);
3354         }
3355
3356         if (!amdgpu_device_has_dc_support(adev)) {
3357                 drm_helper_resume_force_mode(adev->ddev);
3358         }
3359
3360         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3361
3362         if (r) {
3363                 /* bad news, how to tell it to userspace ? */
3364                 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3365                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3366         } else {
3367                 dev_info(adev->dev, "GPU reset(%d) succeeded!\n",atomic_read(&adev->gpu_reset_counter));
3368         }
3369
3370         /*unlock kfd */
3371         amdgpu_amdkfd_post_reset(adev);
3372         amdgpu_vf_error_trans_all(adev);
3373         adev->in_gpu_reset = 0;
3374         mutex_unlock(&adev->lock_reset);
3375         return r;
3376 }
3377
3378 /**
3379  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3380  *
3381  * @adev: amdgpu_device pointer
3382  *
3383  * Fetchs and stores in the driver the PCIE capabilities (gen speed
3384  * and lanes) of the slot the device is in. Handles APUs and
3385  * virtualized environments where PCIE config space may not be available.
3386  */
3387 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3388 {
3389         struct pci_dev *pdev;
3390         enum pci_bus_speed speed_cap;
3391         enum pcie_link_width link_width;
3392
3393         if (amdgpu_pcie_gen_cap)
3394                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3395
3396         if (amdgpu_pcie_lane_cap)
3397                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3398
3399         /* covers APUs as well */
3400         if (pci_is_root_bus(adev->pdev->bus)) {
3401                 if (adev->pm.pcie_gen_mask == 0)
3402                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3403                 if (adev->pm.pcie_mlw_mask == 0)
3404                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3405                 return;
3406         }
3407
3408         if (adev->pm.pcie_gen_mask == 0) {
3409                 /* asic caps */
3410                 pdev = adev->pdev;
3411                 speed_cap = pcie_get_speed_cap(pdev);
3412                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3413                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3414                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3415                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3416                 } else {
3417                         if (speed_cap == PCIE_SPEED_16_0GT)
3418                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3419                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3420                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3421                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3422                         else if (speed_cap == PCIE_SPEED_8_0GT)
3423                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3424                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3425                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3426                         else if (speed_cap == PCIE_SPEED_5_0GT)
3427                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3428                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3429                         else
3430                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3431                 }
3432                 /* platform caps */
3433                 pdev = adev->ddev->pdev->bus->self;
3434                 speed_cap = pcie_get_speed_cap(pdev);
3435                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3436                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3437                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3438                 } else {
3439                         if (speed_cap == PCIE_SPEED_16_0GT)
3440                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3441                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3442                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3443                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3444                         else if (speed_cap == PCIE_SPEED_8_0GT)
3445                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3446                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3447                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3448                         else if (speed_cap == PCIE_SPEED_5_0GT)
3449                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3450                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3451                         else
3452                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3453
3454                 }
3455         }
3456         if (adev->pm.pcie_mlw_mask == 0) {
3457                 pdev = adev->ddev->pdev->bus->self;
3458                 link_width = pcie_get_width_cap(pdev);
3459                 if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3460                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3461                 } else {
3462                         switch (link_width) {
3463                         case PCIE_LNK_X32:
3464                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3465                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3466                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3467                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3468                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3469                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3470                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3471                                 break;
3472                         case PCIE_LNK_X16:
3473                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3474                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3475                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3476                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3477                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3478                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3479                                 break;
3480                         case PCIE_LNK_X12:
3481                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3482                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3483                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3484                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3485                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3486                                 break;
3487                         case PCIE_LNK_X8:
3488                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3489                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3490                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3491                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3492                                 break;
3493                         case PCIE_LNK_X4:
3494                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3495                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3496                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3497                                 break;
3498                         case PCIE_LNK_X2:
3499                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3500                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3501                                 break;
3502                         case PCIE_LNK_X1:
3503                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3504                                 break;
3505                         default:
3506                                 break;
3507                         }
3508                 }
3509         }
3510 }
3511