drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <drm/drmP.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40
  41 /*
  42  * Fences
  43  * Fences mark an event in the GPUs pipeline and are used
  44  * for GPU/CPU synchronization.  When the fence is written,
  45  * it is expected that all buffers associated with that fence
  46  * are no longer in use by the associated ring on the GPU and
  47  * that the the relevant GPU caches have been flushed.
  48  */
  49
  50 struct amdgpu_fence {
  51         struct dma_fence base;
  52
  53         /* RB, DMA, etc. */
  54         struct amdgpu_ring              *ring;
  55 };
  56
  57 static struct kmem_cache *amdgpu_fence_slab;
  58
  59 int amdgpu_fence_slab_init(void)
  60 {
  61         amdgpu_fence_slab = kmem_cache_create(
  62                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  63                 SLAB_HWCACHE_ALIGN, NULL);
  64         if (!amdgpu_fence_slab)
  65                 return -ENOMEM;
  66         return 0;
  67 }
  68
  69 void amdgpu_fence_slab_fini(void)
  70 {
  71         rcu_barrier();
  72         kmem_cache_destroy(amdgpu_fence_slab);
  73 }
  74 /*
  75  * Cast helper
  76  */
  77 static const struct dma_fence_ops amdgpu_fence_ops;
  78 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  79 {
  80         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  81
  82         if (__f->base.ops == &amdgpu_fence_ops)
  83                 return __f;
  84
  85         return NULL;
  86 }
  87
  88 /**
  89  * amdgpu_fence_write - write a fence value
  90  *
  91  * @ring: ring the fence is associated with
  92  * @seq: sequence number to write
  93  *
  94  * Writes a fence value to memory (all asics).
  95  */
  96 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  97 {
  98         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  99
 100         if (drv->cpu_addr)
 101                 *drv->cpu_addr = cpu_to_le32(seq);
 102 }
 103
 104 /**
 105  * amdgpu_fence_read - read a fence value
 106  *
 107  * @ring: ring the fence is associated with
 108  *
 109  * Reads a fence value from memory (all asics).
 110  * Returns the value of the fence read from memory.
 111  */
 112 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 113 {
 114         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 115         u32 seq = 0;
 116
 117         if (drv->cpu_addr)
 118                 seq = le32_to_cpu(*drv->cpu_addr);
 119         else
 120                 seq = atomic_read(&drv->last_seq);
 121
 122         return seq;
 123 }
 124
 125 /**
 126  * amdgpu_fence_emit - emit a fence on the requested ring
 127  *
 128  * @ring: ring the fence is associated with
 129  * @f: resulting fence object
 130  *
 131  * Emits a fence command on the requested ring (all asics).
 132  * Returns 0 on success, -ENOMEM on failure.
 133  */
 134 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f)
 135 {
 136         struct amdgpu_device *adev = ring->adev;
 137         struct amdgpu_fence *fence;
 138         struct dma_fence __rcu **ptr;
 139         uint32_t seq;
 140         int r;
 141
 142         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
 143         if (fence == NULL)
 144                 return -ENOMEM;
 145
 146         seq = ++ring->fence_drv.sync_seq;
 147         fence->ring = ring;
 148         dma_fence_init(&fence->base, &amdgpu_fence_ops,
 149                        &ring->fence_drv.lock,
 150                        adev->fence_context + ring->idx,
 151                        seq);
 152         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 153                                seq, AMDGPU_FENCE_FLAG_INT);
 154
 155         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 156         if (unlikely(rcu_dereference_protected(*ptr, 1))) {
 157                 struct dma_fence *old;
 158
 159                 rcu_read_lock();
 160                 old = dma_fence_get_rcu_safe(ptr);
 161                 rcu_read_unlock();
 162
 163                 if (old) {
 164                         r = dma_fence_wait(old, false);
 165                         dma_fence_put(old);
 166                         if (r)
 167                                 return r;
 168                 }
 169         }
 170
 171         /* This function can't be called concurrently anyway, otherwise
 172          * emitting the fence would mess up the hardware ring buffer.
 173          */
 174         rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
 175
 176         *f = &fence->base;
 177
 178         return 0;
 179 }
 180
 181 /**
 182  * amdgpu_fence_schedule_fallback - schedule fallback check
 183  *
 184  * @ring: pointer to struct amdgpu_ring
 185  *
 186  * Start a timer as fallback to our interrupts.
 187  */
 188 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 189 {
 190         mod_timer(&ring->fence_drv.fallback_timer,
 191                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 192 }
 193
 194 /**
 195  * amdgpu_fence_process - check for fence activity
 196  *
 197  * @ring: pointer to struct amdgpu_ring
 198  *
 199  * Checks the current fence value and calculates the last
 200  * signalled fence value. Wakes the fence queue if the
 201  * sequence number has increased.
 202  */
 203 void amdgpu_fence_process(struct amdgpu_ring *ring)
 204 {
 205         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 206         uint32_t seq, last_seq;
 207         int r;
 208
 209         do {
 210                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 211                 seq = amdgpu_fence_read(ring);
 212
 213         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 214
 215         if (seq != ring->fence_drv.sync_seq)
 216                 amdgpu_fence_schedule_fallback(ring);
 217
 218         if (unlikely(seq == last_seq))
 219                 return;
 220
 221         last_seq &= drv->num_fences_mask;
 222         seq &= drv->num_fences_mask;
 223
 224         do {
 225                 struct dma_fence *fence, **ptr;
 226
 227                 ++last_seq;
 228                 last_seq &= drv->num_fences_mask;
 229                 ptr = &drv->fences[last_seq];
 230
 231                 /* There is always exactly one thread signaling this fence slot */
 232                 fence = rcu_dereference_protected(*ptr, 1);
 233                 RCU_INIT_POINTER(*ptr, NULL);
 234
 235                 if (!fence)
 236                         continue;
 237
 238                 r = dma_fence_signal(fence);
 239                 if (!r)
 240                         DMA_FENCE_TRACE(fence, "signaled from irq context\n");
 241                 else
 242                         BUG();
 243
 244                 dma_fence_put(fence);
 245         } while (last_seq != seq);
 246 }
 247
 248 /**
 249  * amdgpu_fence_fallback - fallback for hardware interrupts
 250  *
 251  * @work: delayed work item
 252  *
 253  * Checks for fence activity.
 254  */
 255 static void amdgpu_fence_fallback(unsigned long arg)
 256 {
 257         struct amdgpu_ring *ring = (void *)arg;
 258
 259         amdgpu_fence_process(ring);
 260 }
 261
 262 /**
 263  * amdgpu_fence_wait_empty - wait for all fences to signal
 264  *
 265  * @adev: amdgpu device pointer
 266  * @ring: ring index the fence is associated with
 267  *
 268  * Wait for all fences on the requested ring to signal (all asics).
 269  * Returns 0 if the fences have passed, error for all other cases.
 270  */
 271 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 272 {
 273         uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq);
 274         struct dma_fence *fence, **ptr;
 275         int r;
 276
 277         if (!seq)
 278                 return 0;
 279
 280         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 281         rcu_read_lock();
 282         fence = rcu_dereference(*ptr);
 283         if (!fence || !dma_fence_get_rcu(fence)) {
 284                 rcu_read_unlock();
 285                 return 0;
 286         }
 287         rcu_read_unlock();
 288
 289         r = dma_fence_wait(fence, false);
 290         dma_fence_put(fence);
 291         return r;
 292 }
 293
 294 /**
 295  * amdgpu_fence_count_emitted - get the count of emitted fences
 296  *
 297  * @ring: ring the fence is associated with
 298  *
 299  * Get the number of fences emitted on the requested ring (all asics).
 300  * Returns the number of emitted fences on the ring.  Used by the
 301  * dynpm code to ring track activity.
 302  */
 303 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 304 {
 305         uint64_t emitted;
 306
 307         /* We are not protected by ring lock when reading the last sequence
 308          * but it's ok to report slightly wrong fence count here.
 309          */
 310         amdgpu_fence_process(ring);
 311         emitted = 0x100000000ull;
 312         emitted -= atomic_read(&ring->fence_drv.last_seq);
 313         emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
 314         return lower_32_bits(emitted);
 315 }
 316
 317 /**
 318  * amdgpu_fence_driver_start_ring - make the fence driver
 319  * ready for use on the requested ring.
 320  *
 321  * @ring: ring to start the fence driver on
 322  * @irq_src: interrupt source to use for this ring
 323  * @irq_type: interrupt type to use for this ring
 324  *
 325  * Make the fence driver ready for processing (all asics).
 326  * Not all asics have all rings, so each asic will only
 327  * start the fence driver on the rings it has.
 328  * Returns 0 for success, errors for failure.
 329  */
 330 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 331                                    struct amdgpu_irq_src *irq_src,
 332                                    unsigned irq_type)
 333 {
 334         struct amdgpu_device *adev = ring->adev;
 335         uint64_t index;
 336
 337         if (ring != &adev->uvd.ring) {
 338                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 339                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 340         } else {
 341                 /* put fence directly behind firmware */
 342                 index = ALIGN(adev->uvd.fw->size, 8);
 343                 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
 344                 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
 345         }
 346         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 347         amdgpu_irq_get(adev, irq_src, irq_type);
 348
 349         ring->fence_drv.irq_src = irq_src;
 350         ring->fence_drv.irq_type = irq_type;
 351         ring->fence_drv.initialized = true;
 352
 353         dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
 354                  "cpu addr 0x%p\n", ring->idx,
 355                  ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 356         return 0;
 357 }
 358
 359 /**
 360  * amdgpu_fence_driver_init_ring - init the fence driver
 361  * for the requested ring.
 362  *
 363  * @ring: ring to init the fence driver on
 364  * @num_hw_submission: number of entries on the hardware queue
 365  *
 366  * Init the fence driver for the requested ring (all asics).
 367  * Helper function for amdgpu_fence_driver_init().
 368  */
 369 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 370                                   unsigned num_hw_submission)
 371 {
 372         long timeout;
 373         int r;
 374
 375         /* Check that num_hw_submission is a power of two */
 376         if ((num_hw_submission & (num_hw_submission - 1)) != 0)
 377                 return -EINVAL;
 378
 379         ring->fence_drv.cpu_addr = NULL;
 380         ring->fence_drv.gpu_addr = 0;
 381         ring->fence_drv.sync_seq = 0;
 382         atomic_set(&ring->fence_drv.last_seq, 0);
 383         ring->fence_drv.initialized = false;
 384
 385         setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
 386                     (unsigned long)ring);
 387
 388         ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
 389         spin_lock_init(&ring->fence_drv.lock);
 390         ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
 391                                          GFP_KERNEL);
 392         if (!ring->fence_drv.fences)
 393                 return -ENOMEM;
 394
 395         /* No need to setup the GPU scheduler for KIQ ring */
 396         if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
 397                 timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
 398                 if (timeout == 0) {
 399                         /*
 400                          * FIXME:
 401                          * Delayed workqueue cannot use it directly,
 402                          * so the scheduler will not use delayed workqueue if
 403                          * MAX_SCHEDULE_TIMEOUT is set.
 404                          * Currently keep it simple and silly.
 405                          */
 406                         timeout = MAX_SCHEDULE_TIMEOUT;
 407                 }
 408                 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
 409                                    num_hw_submission,
 410                                    timeout, ring->name);
 411                 if (r) {
 412                         DRM_ERROR("Failed to create scheduler on ring %s.\n",
 413                                   ring->name);
 414                         return r;
 415                 }
 416         }
 417
 418         return 0;
 419 }
 420
 421 /**
 422  * amdgpu_fence_driver_init - init the fence driver
 423  * for all possible rings.
 424  *
 425  * @adev: amdgpu device pointer
 426  *
 427  * Init the fence driver for all possible rings (all asics).
 428  * Not all asics have all rings, so each asic will only
 429  * start the fence driver on the rings it has using
 430  * amdgpu_fence_driver_start_ring().
 431  * Returns 0 for success.
 432  */
 433 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 434 {
 435         if (amdgpu_debugfs_fence_init(adev))
 436                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 437
 438         return 0;
 439 }
 440
 441 /**
 442  * amdgpu_fence_driver_fini - tear down the fence driver
 443  * for all possible rings.
 444  *
 445  * @adev: amdgpu device pointer
 446  *
 447  * Tear down the fence driver for all possible rings (all asics).
 448  */
 449 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 450 {
 451         unsigned i, j;
 452         int r;
 453
 454         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 455                 struct amdgpu_ring *ring = adev->rings[i];
 456
 457                 if (!ring || !ring->fence_drv.initialized)
 458                         continue;
 459                 r = amdgpu_fence_wait_empty(ring);
 460                 if (r) {
 461                         /* no need to trigger GPU reset as we are unloading */
 462                         amdgpu_fence_driver_force_completion(adev);
 463                 }
 464                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 465                                ring->fence_drv.irq_type);
 466                 amd_sched_fini(&ring->sched);
 467                 del_timer_sync(&ring->fence_drv.fallback_timer);
 468                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 469                         dma_fence_put(ring->fence_drv.fences[j]);
 470                 kfree(ring->fence_drv.fences);
 471                 ring->fence_drv.fences = NULL;
 472                 ring->fence_drv.initialized = false;
 473         }
 474 }
 475
 476 /**
 477  * amdgpu_fence_driver_suspend - suspend the fence driver
 478  * for all possible rings.
 479  *
 480  * @adev: amdgpu device pointer
 481  *
 482  * Suspend the fence driver for all possible rings (all asics).
 483  */
 484 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
 485 {
 486         int i, r;
 487
 488         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 489                 struct amdgpu_ring *ring = adev->rings[i];
 490                 if (!ring || !ring->fence_drv.initialized)
 491                         continue;
 492
 493                 /* wait for gpu to finish processing current batch */
 494                 r = amdgpu_fence_wait_empty(ring);
 495                 if (r) {
 496                         /* delay GPU reset to resume */
 497                         amdgpu_fence_driver_force_completion(adev);
 498                 }
 499
 500                 /* disable the interrupt */
 501                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 502                                ring->fence_drv.irq_type);
 503         }
 504 }
 505
 506 /**
 507  * amdgpu_fence_driver_resume - resume the fence driver
 508  * for all possible rings.
 509  *
 510  * @adev: amdgpu device pointer
 511  *
 512  * Resume the fence driver for all possible rings (all asics).
 513  * Not all asics have all rings, so each asic will only
 514  * start the fence driver on the rings it has using
 515  * amdgpu_fence_driver_start_ring().
 516  * Returns 0 for success.
 517  */
 518 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
 519 {
 520         int i;
 521
 522         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 523                 struct amdgpu_ring *ring = adev->rings[i];
 524                 if (!ring || !ring->fence_drv.initialized)
 525                         continue;
 526
 527                 /* enable the interrupt */
 528                 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 529                                ring->fence_drv.irq_type);
 530         }
 531 }
 532
 533 /**
 534  * amdgpu_fence_driver_force_completion - force all fence waiter to complete
 535  *
 536  * @adev: amdgpu device pointer
 537  *
 538  * In case of GPU reset failure make sure no process keep waiting on fence
 539  * that will never complete.
 540  */
 541 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
 542 {
 543         int i;
 544
 545         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 546                 struct amdgpu_ring *ring = adev->rings[i];
 547                 if (!ring || !ring->fence_drv.initialized)
 548                         continue;
 549
 550                 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 551         }
 552 }
 553
 554 void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring)
 555 {
 556         if (ring)
 557                 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 558 }
 559
 560 /*
 561  * Common fence implementation
 562  */
 563
 564 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 565 {
 566         return "amdgpu";
 567 }
 568
 569 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 570 {
 571         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 572         return (const char *)fence->ring->name;
 573 }
 574
 575 /**
 576  * amdgpu_fence_enable_signaling - enable signalling on fence
 577  * @fence: fence
 578  *
 579  * This function is called with fence_queue lock held, and adds a callback
 580  * to fence_queue that checks if this fence is signaled, and if so it
 581  * signals the fence and removes itself.
 582  */
 583 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
 584 {
 585         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 586         struct amdgpu_ring *ring = fence->ring;
 587
 588         if (!timer_pending(&ring->fence_drv.fallback_timer))
 589                 amdgpu_fence_schedule_fallback(ring);
 590
 591         DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 592
 593         return true;
 594 }
 595
 596 /**
 597  * amdgpu_fence_free - free up the fence memory
 598  *
 599  * @rcu: RCU callback head
 600  *
 601  * Free up the fence memory after the RCU grace period.
 602  */
 603 static void amdgpu_fence_free(struct rcu_head *rcu)
 604 {
 605         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 606         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 607         kmem_cache_free(amdgpu_fence_slab, fence);
 608 }
 609
 610 /**
 611  * amdgpu_fence_release - callback that fence can be freed
 612  *
 613  * @fence: fence
 614  *
 615  * This function is called when the reference count becomes zero.
 616  * It just RCU schedules freeing up the fence.
 617  */
 618 static void amdgpu_fence_release(struct dma_fence *f)
 619 {
 620         call_rcu(&f->rcu, amdgpu_fence_free);
 621 }
 622
 623 static const struct dma_fence_ops amdgpu_fence_ops = {
 624         .get_driver_name = amdgpu_fence_get_driver_name,
 625         .get_timeline_name = amdgpu_fence_get_timeline_name,
 626         .enable_signaling = amdgpu_fence_enable_signaling,
 627         .wait = dma_fence_default_wait,
 628         .release = amdgpu_fence_release,
 629 };
 630
 631 /*
 632  * Fence debugfs
 633  */
 634 #if defined(CONFIG_DEBUG_FS)
 635 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
 636 {
 637         struct drm_info_node *node = (struct drm_info_node *)m->private;
 638         struct drm_device *dev = node->minor->dev;
 639         struct amdgpu_device *adev = dev->dev_private;
 640         int i;
 641
 642         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 643                 struct amdgpu_ring *ring = adev->rings[i];
 644                 if (!ring || !ring->fence_drv.initialized)
 645                         continue;
 646
 647                 amdgpu_fence_process(ring);
 648
 649                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 650                 seq_printf(m, "Last signaled fence 0x%08x\n",
 651                            atomic_read(&ring->fence_drv.last_seq));
 652                 seq_printf(m, "Last emitted        0x%08x\n",
 653                            ring->fence_drv.sync_seq);
 654         }
 655         return 0;
 656 }
 657
 658 /**
 659  * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
 660  *
 661  * Manually trigger a gpu reset at the next fence wait.
 662  */
 663 static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
 664 {
 665         struct drm_info_node *node = (struct drm_info_node *) m->private;
 666         struct drm_device *dev = node->minor->dev;
 667         struct amdgpu_device *adev = dev->dev_private;
 668
 669         seq_printf(m, "gpu reset\n");
 670         amdgpu_gpu_reset(adev);
 671
 672         return 0;
 673 }
 674
 675 static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
 676         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 677         {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
 678 };
 679
 680 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
 681         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 682 };
 683 #endif
 684
 685 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 686 {
 687 #if defined(CONFIG_DEBUG_FS)
 688         if (amdgpu_sriov_vf(adev))
 689                 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1);
 690         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
 691 #else
 692         return 0;
 693 #endif
 694 }
 695