2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
31 #include <linux/seq_file.h>
32 #include <linux/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/kref.h>
35 #include <linux/slab.h>
36 #include <linux/firmware.h>
39 #include "amdgpu_trace.h"
43 * Fences mark an event in the GPUs pipeline and are used
44 * for GPU/CPU synchronization. When the fence is written,
45 * it is expected that all buffers associated with that fence
46 * are no longer in use by the associated ring on the GPU and
47 * that the the relevant GPU caches have been flushed.
54 struct amdgpu_ring *ring;
57 static struct kmem_cache *amdgpu_fence_slab;
59 int amdgpu_fence_slab_init(void)
61 amdgpu_fence_slab = kmem_cache_create(
62 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
63 SLAB_HWCACHE_ALIGN, NULL);
64 if (!amdgpu_fence_slab)
69 void amdgpu_fence_slab_fini(void)
72 kmem_cache_destroy(amdgpu_fence_slab);
77 static const struct fence_ops amdgpu_fence_ops;
78 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
80 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
82 if (__f->base.ops == &amdgpu_fence_ops)
89 * amdgpu_fence_write - write a fence value
91 * @ring: ring the fence is associated with
92 * @seq: sequence number to write
94 * Writes a fence value to memory (all asics).
96 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
98 struct amdgpu_fence_driver *drv = &ring->fence_drv;
101 *drv->cpu_addr = cpu_to_le32(seq);
105 * amdgpu_fence_read - read a fence value
107 * @ring: ring the fence is associated with
109 * Reads a fence value from memory (all asics).
110 * Returns the value of the fence read from memory.
112 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
114 struct amdgpu_fence_driver *drv = &ring->fence_drv;
118 seq = le32_to_cpu(*drv->cpu_addr);
120 seq = atomic_read(&drv->last_seq);
126 * amdgpu_fence_emit - emit a fence on the requested ring
128 * @ring: ring the fence is associated with
129 * @f: resulting fence object
131 * Emits a fence command on the requested ring (all asics).
132 * Returns 0 on success, -ENOMEM on failure.
134 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
136 struct amdgpu_device *adev = ring->adev;
137 struct amdgpu_fence *fence;
138 struct fence *old, **ptr;
141 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
145 seq = ++ring->fence_drv.sync_seq;
147 fence_init(&fence->base, &amdgpu_fence_ops,
148 &ring->fence_drv.lock,
149 adev->fence_context + ring->idx,
151 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
152 seq, AMDGPU_FENCE_FLAG_INT);
154 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
155 /* This function can't be called concurrently anyway, otherwise
156 * emitting the fence would mess up the hardware ring buffer.
158 old = rcu_dereference_protected(*ptr, 1);
159 if (old && !fence_is_signaled(old)) {
160 DRM_INFO("rcu slot is busy\n");
161 fence_wait(old, false);
164 rcu_assign_pointer(*ptr, fence_get(&fence->base));
172 * amdgpu_fence_schedule_fallback - schedule fallback check
174 * @ring: pointer to struct amdgpu_ring
176 * Start a timer as fallback to our interrupts.
178 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
180 mod_timer(&ring->fence_drv.fallback_timer,
181 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
185 * amdgpu_fence_process - check for fence activity
187 * @ring: pointer to struct amdgpu_ring
189 * Checks the current fence value and calculates the last
190 * signalled fence value. Wakes the fence queue if the
191 * sequence number has increased.
193 void amdgpu_fence_process(struct amdgpu_ring *ring)
195 struct amdgpu_fence_driver *drv = &ring->fence_drv;
196 uint32_t seq, last_seq;
200 last_seq = atomic_read(&ring->fence_drv.last_seq);
201 seq = amdgpu_fence_read(ring);
203 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
205 if (seq != ring->fence_drv.sync_seq)
206 amdgpu_fence_schedule_fallback(ring);
208 if (unlikely(seq == last_seq))
211 last_seq &= drv->num_fences_mask;
212 seq &= drv->num_fences_mask;
215 struct fence *fence, **ptr;
218 last_seq &= drv->num_fences_mask;
219 ptr = &drv->fences[last_seq];
221 /* There is always exactly one thread signaling this fence slot */
222 fence = rcu_dereference_protected(*ptr, 1);
223 RCU_INIT_POINTER(*ptr, NULL);
228 r = fence_signal(fence);
230 FENCE_TRACE(fence, "signaled from irq context\n");
235 } while (last_seq != seq);
239 * amdgpu_fence_fallback - fallback for hardware interrupts
241 * @work: delayed work item
243 * Checks for fence activity.
245 static void amdgpu_fence_fallback(unsigned long arg)
247 struct amdgpu_ring *ring = (void *)arg;
249 amdgpu_fence_process(ring);
253 * amdgpu_fence_wait_empty - wait for all fences to signal
255 * @adev: amdgpu device pointer
256 * @ring: ring index the fence is associated with
258 * Wait for all fences on the requested ring to signal (all asics).
259 * Returns 0 if the fences have passed, error for all other cases.
261 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
263 uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq);
264 struct fence *fence, **ptr;
270 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
272 fence = rcu_dereference(*ptr);
273 if (!fence || !fence_get_rcu(fence)) {
279 r = fence_wait(fence, false);
285 * amdgpu_fence_count_emitted - get the count of emitted fences
287 * @ring: ring the fence is associated with
289 * Get the number of fences emitted on the requested ring (all asics).
290 * Returns the number of emitted fences on the ring. Used by the
291 * dynpm code to ring track activity.
293 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
297 /* We are not protected by ring lock when reading the last sequence
298 * but it's ok to report slightly wrong fence count here.
300 amdgpu_fence_process(ring);
301 emitted = 0x100000000ull;
302 emitted -= atomic_read(&ring->fence_drv.last_seq);
303 emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
304 return lower_32_bits(emitted);
308 * amdgpu_fence_driver_start_ring - make the fence driver
309 * ready for use on the requested ring.
311 * @ring: ring to start the fence driver on
312 * @irq_src: interrupt source to use for this ring
313 * @irq_type: interrupt type to use for this ring
315 * Make the fence driver ready for processing (all asics).
316 * Not all asics have all rings, so each asic will only
317 * start the fence driver on the rings it has.
318 * Returns 0 for success, errors for failure.
320 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
321 struct amdgpu_irq_src *irq_src,
324 struct amdgpu_device *adev = ring->adev;
327 if (ring != &adev->uvd.ring) {
328 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
329 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
331 /* put fence directly behind firmware */
332 index = ALIGN(adev->uvd.fw->size, 8);
333 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
334 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
336 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
337 amdgpu_irq_get(adev, irq_src, irq_type);
339 ring->fence_drv.irq_src = irq_src;
340 ring->fence_drv.irq_type = irq_type;
341 ring->fence_drv.initialized = true;
343 dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
344 "cpu addr 0x%p\n", ring->idx,
345 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
350 * amdgpu_fence_driver_init_ring - init the fence driver
351 * for the requested ring.
353 * @ring: ring to init the fence driver on
354 * @num_hw_submission: number of entries on the hardware queue
356 * Init the fence driver for the requested ring (all asics).
357 * Helper function for amdgpu_fence_driver_init().
359 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
360 unsigned num_hw_submission)
365 /* Check that num_hw_submission is a power of two */
366 if ((num_hw_submission & (num_hw_submission - 1)) != 0)
369 ring->fence_drv.cpu_addr = NULL;
370 ring->fence_drv.gpu_addr = 0;
371 ring->fence_drv.sync_seq = 0;
372 atomic_set(&ring->fence_drv.last_seq, 0);
373 ring->fence_drv.initialized = false;
375 setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
376 (unsigned long)ring);
378 ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
379 spin_lock_init(&ring->fence_drv.lock);
380 ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
382 if (!ring->fence_drv.fences)
385 timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
389 * Delayed workqueue cannot use it directly,
390 * so the scheduler will not use delayed workqueue if
391 * MAX_SCHEDULE_TIMEOUT is set.
392 * Currently keep it simple and silly.
394 timeout = MAX_SCHEDULE_TIMEOUT;
396 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
398 timeout, ring->name);
400 DRM_ERROR("Failed to create scheduler on ring %s.\n",
409 * amdgpu_fence_driver_init - init the fence driver
410 * for all possible rings.
412 * @adev: amdgpu device pointer
414 * Init the fence driver for all possible rings (all asics).
415 * Not all asics have all rings, so each asic will only
416 * start the fence driver on the rings it has using
417 * amdgpu_fence_driver_start_ring().
418 * Returns 0 for success.
420 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
422 if (amdgpu_debugfs_fence_init(adev))
423 dev_err(adev->dev, "fence debugfs file creation failed\n");
429 * amdgpu_fence_driver_fini - tear down the fence driver
430 * for all possible rings.
432 * @adev: amdgpu device pointer
434 * Tear down the fence driver for all possible rings (all asics).
436 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
441 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
442 struct amdgpu_ring *ring = adev->rings[i];
444 if (!ring || !ring->fence_drv.initialized)
446 r = amdgpu_fence_wait_empty(ring);
448 /* no need to trigger GPU reset as we are unloading */
449 amdgpu_fence_driver_force_completion(adev);
451 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
452 ring->fence_drv.irq_type);
453 amd_sched_fini(&ring->sched);
454 del_timer_sync(&ring->fence_drv.fallback_timer);
455 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
456 fence_put(ring->fence_drv.fences[j]);
457 kfree(ring->fence_drv.fences);
458 ring->fence_drv.fences = NULL;
459 ring->fence_drv.initialized = false;
464 * amdgpu_fence_driver_suspend - suspend the fence driver
465 * for all possible rings.
467 * @adev: amdgpu device pointer
469 * Suspend the fence driver for all possible rings (all asics).
471 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
475 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
476 struct amdgpu_ring *ring = adev->rings[i];
477 if (!ring || !ring->fence_drv.initialized)
480 /* wait for gpu to finish processing current batch */
481 r = amdgpu_fence_wait_empty(ring);
483 /* delay GPU reset to resume */
484 amdgpu_fence_driver_force_completion(adev);
487 /* disable the interrupt */
488 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
489 ring->fence_drv.irq_type);
494 * amdgpu_fence_driver_resume - resume the fence driver
495 * for all possible rings.
497 * @adev: amdgpu device pointer
499 * Resume the fence driver for all possible rings (all asics).
500 * Not all asics have all rings, so each asic will only
501 * start the fence driver on the rings it has using
502 * amdgpu_fence_driver_start_ring().
503 * Returns 0 for success.
505 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
509 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
510 struct amdgpu_ring *ring = adev->rings[i];
511 if (!ring || !ring->fence_drv.initialized)
514 /* enable the interrupt */
515 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
516 ring->fence_drv.irq_type);
521 * amdgpu_fence_driver_force_completion - force all fence waiter to complete
523 * @adev: amdgpu device pointer
525 * In case of GPU reset failure make sure no process keep waiting on fence
526 * that will never complete.
528 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
532 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
533 struct amdgpu_ring *ring = adev->rings[i];
534 if (!ring || !ring->fence_drv.initialized)
537 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
542 * Common fence implementation
545 static const char *amdgpu_fence_get_driver_name(struct fence *fence)
550 static const char *amdgpu_fence_get_timeline_name(struct fence *f)
552 struct amdgpu_fence *fence = to_amdgpu_fence(f);
553 return (const char *)fence->ring->name;
557 * amdgpu_fence_enable_signaling - enable signalling on fence
560 * This function is called with fence_queue lock held, and adds a callback
561 * to fence_queue that checks if this fence is signaled, and if so it
562 * signals the fence and removes itself.
564 static bool amdgpu_fence_enable_signaling(struct fence *f)
566 struct amdgpu_fence *fence = to_amdgpu_fence(f);
567 struct amdgpu_ring *ring = fence->ring;
569 if (!timer_pending(&ring->fence_drv.fallback_timer))
570 amdgpu_fence_schedule_fallback(ring);
572 FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
578 * amdgpu_fence_free - free up the fence memory
580 * @rcu: RCU callback head
582 * Free up the fence memory after the RCU grace period.
584 static void amdgpu_fence_free(struct rcu_head *rcu)
586 struct fence *f = container_of(rcu, struct fence, rcu);
587 struct amdgpu_fence *fence = to_amdgpu_fence(f);
588 kmem_cache_free(amdgpu_fence_slab, fence);
592 * amdgpu_fence_release - callback that fence can be freed
596 * This function is called when the reference count becomes zero.
597 * It just RCU schedules freeing up the fence.
599 static void amdgpu_fence_release(struct fence *f)
601 call_rcu(&f->rcu, amdgpu_fence_free);
604 static const struct fence_ops amdgpu_fence_ops = {
605 .get_driver_name = amdgpu_fence_get_driver_name,
606 .get_timeline_name = amdgpu_fence_get_timeline_name,
607 .enable_signaling = amdgpu_fence_enable_signaling,
608 .wait = fence_default_wait,
609 .release = amdgpu_fence_release,
615 #if defined(CONFIG_DEBUG_FS)
616 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
618 struct drm_info_node *node = (struct drm_info_node *)m->private;
619 struct drm_device *dev = node->minor->dev;
620 struct amdgpu_device *adev = dev->dev_private;
623 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
624 struct amdgpu_ring *ring = adev->rings[i];
625 if (!ring || !ring->fence_drv.initialized)
628 amdgpu_fence_process(ring);
630 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
631 seq_printf(m, "Last signaled fence 0x%08x\n",
632 atomic_read(&ring->fence_drv.last_seq));
633 seq_printf(m, "Last emitted 0x%08x\n",
634 ring->fence_drv.sync_seq);
640 * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
642 * Manually trigger a gpu reset at the next fence wait.
644 static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
646 struct drm_info_node *node = (struct drm_info_node *) m->private;
647 struct drm_device *dev = node->minor->dev;
648 struct amdgpu_device *adev = dev->dev_private;
650 seq_printf(m, "gpu reset\n");
651 amdgpu_gpu_reset(adev);
656 static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
657 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
658 {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
662 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
664 #if defined(CONFIG_DEBUG_FS)
665 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);