drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  35 {
  36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  37
  38         if (robj) {
  39                 amdgpu_mn_unregister(robj);
  40                 amdgpu_bo_unref(&robj);
  41         }
  42 }
  43
  44 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  45                                 int alignment, u32 initial_domain,
  46                                 u64 flags, bool kernel,
  47                                 struct drm_gem_object **obj)
  48 {
  49         struct amdgpu_bo *robj;
  50         unsigned long max_size;
  51         int r;
  52
  53         *obj = NULL;
  54         /* At least align on page size */
  55         if (alignment < PAGE_SIZE) {
  56                 alignment = PAGE_SIZE;
  57         }
  58
  59         if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
  60                 /* Maximum bo size is the unpinned gtt size since we use the gtt to
  61                  * handle vram to system pool migrations.
  62                  */
  63                 max_size = adev->mc.gtt_size - adev->gart_pin_size;
  64                 if (size > max_size) {
  65                         DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
  66                                   size >> 20, max_size >> 20);
  67                         return -ENOMEM;
  68                 }
  69         }
  70 retry:
  71         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  72                              flags, NULL, NULL, &robj);
  73         if (r) {
  74                 if (r != -ERESTARTSYS) {
  75                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  76                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  77                                 goto retry;
  78                         }
  79                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  80                                   size, initial_domain, alignment, r);
  81                 }
  82                 return r;
  83         }
  84         *obj = &robj->gem_base;
  85
  86         return 0;
  87 }
  88
  89 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  90 {
  91         struct drm_device *ddev = adev->ddev;
  92         struct drm_file *file;
  93
  94         mutex_lock(&ddev->filelist_mutex);
  95
  96         list_for_each_entry(file, &ddev->filelist, lhead) {
  97                 struct drm_gem_object *gobj;
  98                 int handle;
  99
 100                 WARN_ONCE(1, "Still active user space clients!\n");
 101                 spin_lock(&file->table_lock);
 102                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 103                         WARN_ONCE(1, "And also active allocations!\n");
 104                         drm_gem_object_unreference_unlocked(gobj);
 105                 }
 106                 idr_destroy(&file->object_idr);
 107                 spin_unlock(&file->table_lock);
 108         }
 109
 110         mutex_unlock(&ddev->filelist_mutex);
 111 }
 112
 113 /*
 114  * Call from drm_gem_handle_create which appear in both new and open ioctl
 115  * case.
 116  */
 117 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
 118 {
 119         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 120         struct amdgpu_device *adev = abo->adev;
 121         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 122         struct amdgpu_vm *vm = &fpriv->vm;
 123         struct amdgpu_bo_va *bo_va;
 124         int r;
 125         r = amdgpu_bo_reserve(abo, false);
 126         if (r)
 127                 return r;
 128
 129         bo_va = amdgpu_vm_bo_find(vm, abo);
 130         if (!bo_va) {
 131                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 132         } else {
 133                 ++bo_va->ref_count;
 134         }
 135         amdgpu_bo_unreserve(abo);
 136         return 0;
 137 }
 138
 139 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 140                              struct drm_file *file_priv)
 141 {
 142         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 143         struct amdgpu_device *adev = bo->adev;
 144         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 145         struct amdgpu_vm *vm = &fpriv->vm;
 146
 147         struct amdgpu_bo_list_entry vm_pd;
 148         struct list_head list, duplicates;
 149         struct ttm_validate_buffer tv;
 150         struct ww_acquire_ctx ticket;
 151         struct amdgpu_bo_va *bo_va;
 152         int r;
 153
 154         INIT_LIST_HEAD(&list);
 155         INIT_LIST_HEAD(&duplicates);
 156
 157         tv.bo = &bo->tbo;
 158         tv.shared = true;
 159         list_add(&tv.head, &list);
 160
 161         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 162
 163         r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
 164         if (r) {
 165                 dev_err(adev->dev, "leaking bo va because "
 166                         "we fail to reserve bo (%d)\n", r);
 167                 return;
 168         }
 169         bo_va = amdgpu_vm_bo_find(vm, bo);
 170         if (bo_va) {
 171                 if (--bo_va->ref_count == 0) {
 172                         amdgpu_vm_bo_rmv(adev, bo_va);
 173                 }
 174         }
 175         ttm_eu_backoff_reservation(&ticket, &list);
 176 }
 177
 178 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
 179 {
 180         if (r == -EDEADLK) {
 181                 r = amdgpu_gpu_reset(adev);
 182                 if (!r)
 183                         r = -EAGAIN;
 184         }
 185         return r;
 186 }
 187
 188 /*
 189  * GEM ioctls.
 190  */
 191 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 192                             struct drm_file *filp)
 193 {
 194         struct amdgpu_device *adev = dev->dev_private;
 195         union drm_amdgpu_gem_create *args = data;
 196         uint64_t size = args->in.bo_size;
 197         struct drm_gem_object *gobj;
 198         uint32_t handle;
 199         bool kernel = false;
 200         int r;
 201
 202         /* create a gem object to contain this object in */
 203         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 204             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 205                 kernel = true;
 206                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 207                         size = size << AMDGPU_GDS_SHIFT;
 208                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 209                         size = size << AMDGPU_GWS_SHIFT;
 210                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 211                         size = size << AMDGPU_OA_SHIFT;
 212                 else {
 213                         r = -EINVAL;
 214                         goto error_unlock;
 215                 }
 216         }
 217         size = roundup(size, PAGE_SIZE);
 218
 219         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 220                                      (u32)(0xffffffff & args->in.domains),
 221                                      args->in.domain_flags,
 222                                      kernel, &gobj);
 223         if (r)
 224                 goto error_unlock;
 225
 226         r = drm_gem_handle_create(filp, gobj, &handle);
 227         /* drop reference from allocate - handle holds it now */
 228         drm_gem_object_unreference_unlocked(gobj);
 229         if (r)
 230                 goto error_unlock;
 231
 232         memset(args, 0, sizeof(*args));
 233         args->out.handle = handle;
 234         return 0;
 235
 236 error_unlock:
 237         r = amdgpu_gem_handle_lockup(adev, r);
 238         return r;
 239 }
 240
 241 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 242                              struct drm_file *filp)
 243 {
 244         struct amdgpu_device *adev = dev->dev_private;
 245         struct drm_amdgpu_gem_userptr *args = data;
 246         struct drm_gem_object *gobj;
 247         struct amdgpu_bo *bo;
 248         uint32_t handle;
 249         int r;
 250
 251         if (offset_in_page(args->addr | args->size))
 252                 return -EINVAL;
 253
 254         /* reject unknown flag values */
 255         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 256             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 257             AMDGPU_GEM_USERPTR_REGISTER))
 258                 return -EINVAL;
 259
 260         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 261              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 262
 263                 /* if we want to write to it we must install a MMU notifier */
 264                 return -EACCES;
 265         }
 266
 267         /* create a gem object to contain this object in */
 268         r = amdgpu_gem_object_create(adev, args->size, 0,
 269                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 270                                      0, &gobj);
 271         if (r)
 272                 goto handle_lockup;
 273
 274         bo = gem_to_amdgpu_bo(gobj);
 275         bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
 276         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 277         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 278         if (r)
 279                 goto release_object;
 280
 281         r = amdgpu_mn_register(bo, args->addr);
 282         if (r)
 283                 goto release_object;
 284
 285         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 286                 down_read(&current->mm->mmap_sem);
 287
 288                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 289                                                  bo->tbo.ttm->pages);
 290                 if (r)
 291                         goto unlock_mmap_sem;
 292
 293                 r = amdgpu_bo_reserve(bo, true);
 294                 if (r)
 295                         goto free_pages;
 296
 297                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 298                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 299                 amdgpu_bo_unreserve(bo);
 300                 if (r)
 301                         goto free_pages;
 302
 303                 up_read(&current->mm->mmap_sem);
 304         }
 305
 306         r = drm_gem_handle_create(filp, gobj, &handle);
 307         /* drop reference from allocate - handle holds it now */
 308         drm_gem_object_unreference_unlocked(gobj);
 309         if (r)
 310                 goto handle_lockup;
 311
 312         args->handle = handle;
 313         return 0;
 314
 315 free_pages:
 316         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
 317
 318 unlock_mmap_sem:
 319         up_read(&current->mm->mmap_sem);
 320
 321 release_object:
 322         drm_gem_object_unreference_unlocked(gobj);
 323
 324 handle_lockup:
 325         r = amdgpu_gem_handle_lockup(adev, r);
 326
 327         return r;
 328 }
 329
 330 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 331                           struct drm_device *dev,
 332                           uint32_t handle, uint64_t *offset_p)
 333 {
 334         struct drm_gem_object *gobj;
 335         struct amdgpu_bo *robj;
 336
 337         gobj = drm_gem_object_lookup(filp, handle);
 338         if (gobj == NULL) {
 339                 return -ENOENT;
 340         }
 341         robj = gem_to_amdgpu_bo(gobj);
 342         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 343             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 344                 drm_gem_object_unreference_unlocked(gobj);
 345                 return -EPERM;
 346         }
 347         *offset_p = amdgpu_bo_mmap_offset(robj);
 348         drm_gem_object_unreference_unlocked(gobj);
 349         return 0;
 350 }
 351
 352 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 353                           struct drm_file *filp)
 354 {
 355         union drm_amdgpu_gem_mmap *args = data;
 356         uint32_t handle = args->in.handle;
 357         memset(args, 0, sizeof(*args));
 358         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 359 }
 360
 361 /**
 362  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 363  *
 364  * @timeout_ns: timeout in ns
 365  *
 366  * Calculate the timeout in jiffies from an absolute timeout in ns.
 367  */
 368 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 369 {
 370         unsigned long timeout_jiffies;
 371         ktime_t timeout;
 372
 373         /* clamp timeout if it's to large */
 374         if (((int64_t)timeout_ns) < 0)
 375                 return MAX_SCHEDULE_TIMEOUT;
 376
 377         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 378         if (ktime_to_ns(timeout) < 0)
 379                 return 0;
 380
 381         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 382         /*  clamp timeout to avoid unsigned-> signed overflow */
 383         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 384                 return MAX_SCHEDULE_TIMEOUT - 1;
 385
 386         return timeout_jiffies;
 387 }
 388
 389 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 390                               struct drm_file *filp)
 391 {
 392         struct amdgpu_device *adev = dev->dev_private;
 393         union drm_amdgpu_gem_wait_idle *args = data;
 394         struct drm_gem_object *gobj;
 395         struct amdgpu_bo *robj;
 396         uint32_t handle = args->in.handle;
 397         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 398         int r = 0;
 399         long ret;
 400
 401         gobj = drm_gem_object_lookup(filp, handle);
 402         if (gobj == NULL) {
 403                 return -ENOENT;
 404         }
 405         robj = gem_to_amdgpu_bo(gobj);
 406         if (timeout == 0)
 407                 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
 408         else
 409                 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);
 410
 411         /* ret == 0 means not signaled,
 412          * ret > 0 means signaled
 413          * ret < 0 means interrupted before timeout
 414          */
 415         if (ret >= 0) {
 416                 memset(args, 0, sizeof(*args));
 417                 args->out.status = (ret == 0);
 418         } else
 419                 r = ret;
 420
 421         drm_gem_object_unreference_unlocked(gobj);
 422         r = amdgpu_gem_handle_lockup(adev, r);
 423         return r;
 424 }
 425
 426 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 427                                 struct drm_file *filp)
 428 {
 429         struct drm_amdgpu_gem_metadata *args = data;
 430         struct drm_gem_object *gobj;
 431         struct amdgpu_bo *robj;
 432         int r = -1;
 433
 434         DRM_DEBUG("%d \n", args->handle);
 435         gobj = drm_gem_object_lookup(filp, args->handle);
 436         if (gobj == NULL)
 437                 return -ENOENT;
 438         robj = gem_to_amdgpu_bo(gobj);
 439
 440         r = amdgpu_bo_reserve(robj, false);
 441         if (unlikely(r != 0))
 442                 goto out;
 443
 444         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 445                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 446                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 447                                            sizeof(args->data.data),
 448                                            &args->data.data_size_bytes,
 449                                            &args->data.flags);
 450         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 451                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 452                         r = -EINVAL;
 453                         goto unreserve;
 454                 }
 455                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 456                 if (!r)
 457                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 458                                                    args->data.data_size_bytes,
 459                                                    args->data.flags);
 460         }
 461
 462 unreserve:
 463         amdgpu_bo_unreserve(robj);
 464 out:
 465         drm_gem_object_unreference_unlocked(gobj);
 466         return r;
 467 }
 468
 469 /**
 470  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 471  *
 472  * @adev: amdgpu_device pointer
 473  * @bo_va: bo_va to update
 474  *
 475  * Update the bo_va directly after setting it's address. Errors are not
 476  * vital here, so they are not reported back to userspace.
 477  */
 478 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 479                                     struct amdgpu_bo_va *bo_va, uint32_t operation)
 480 {
 481         struct ttm_validate_buffer tv, *entry;
 482         struct amdgpu_bo_list_entry vm_pd;
 483         struct ww_acquire_ctx ticket;
 484         struct list_head list, duplicates;
 485         unsigned domain;
 486         int r;
 487
 488         INIT_LIST_HEAD(&list);
 489         INIT_LIST_HEAD(&duplicates);
 490
 491         tv.bo = &bo_va->bo->tbo;
 492         tv.shared = true;
 493         list_add(&tv.head, &list);
 494
 495         amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
 496
 497         /* Provide duplicates to avoid -EALREADY */
 498         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 499         if (r)
 500                 goto error_print;
 501
 502         amdgpu_vm_get_pt_bos(adev, bo_va->vm, &duplicates);
 503         list_for_each_entry(entry, &list, head) {
 504                 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
 505                 /* if anything is swapped out don't swap it in here,
 506                    just abort and wait for the next CS */
 507                 if (domain == AMDGPU_GEM_DOMAIN_CPU)
 508                         goto error_unreserve;
 509         }
 510         list_for_each_entry(entry, &duplicates, head) {
 511                 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
 512                 /* if anything is swapped out don't swap it in here,
 513                    just abort and wait for the next CS */
 514                 if (domain == AMDGPU_GEM_DOMAIN_CPU)
 515                         goto error_unreserve;
 516         }
 517
 518         r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
 519         if (r)
 520                 goto error_unreserve;
 521
 522         r = amdgpu_vm_clear_freed(adev, bo_va->vm);
 523         if (r)
 524                 goto error_unreserve;
 525
 526         if (operation == AMDGPU_VA_OP_MAP)
 527                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 528
 529 error_unreserve:
 530         ttm_eu_backoff_reservation(&ticket, &list);
 531
 532 error_print:
 533         if (r && r != -ERESTARTSYS)
 534                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 535 }
 536
 537
 538
 539 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 540                           struct drm_file *filp)
 541 {
 542         struct drm_amdgpu_gem_va *args = data;
 543         struct drm_gem_object *gobj;
 544         struct amdgpu_device *adev = dev->dev_private;
 545         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 546         struct amdgpu_bo *abo;
 547         struct amdgpu_bo_va *bo_va;
 548         struct ttm_validate_buffer tv, tv_pd;
 549         struct ww_acquire_ctx ticket;
 550         struct list_head list, duplicates;
 551         uint32_t invalid_flags, va_flags = 0;
 552         int r = 0;
 553
 554         if (!adev->vm_manager.enabled)
 555                 return -ENOTTY;
 556
 557         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 558                 dev_err(&dev->pdev->dev,
 559                         "va_address 0x%lX is in reserved area 0x%X\n",
 560                         (unsigned long)args->va_address,
 561                         AMDGPU_VA_RESERVED_SIZE);
 562                 return -EINVAL;
 563         }
 564
 565         invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
 566                         AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
 567         if ((args->flags & invalid_flags)) {
 568                 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
 569                         args->flags, invalid_flags);
 570                 return -EINVAL;
 571         }
 572
 573         switch (args->operation) {
 574         case AMDGPU_VA_OP_MAP:
 575         case AMDGPU_VA_OP_UNMAP:
 576                 break;
 577         default:
 578                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 579                         args->operation);
 580                 return -EINVAL;
 581         }
 582
 583         gobj = drm_gem_object_lookup(filp, args->handle);
 584         if (gobj == NULL)
 585                 return -ENOENT;
 586         abo = gem_to_amdgpu_bo(gobj);
 587         INIT_LIST_HEAD(&list);
 588         INIT_LIST_HEAD(&duplicates);
 589         tv.bo = &abo->tbo;
 590         tv.shared = true;
 591         list_add(&tv.head, &list);
 592
 593         tv_pd.bo = &fpriv->vm.page_directory->tbo;
 594         tv_pd.shared = true;
 595         list_add(&tv_pd.head, &list);
 596
 597         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 598         if (r) {
 599                 drm_gem_object_unreference_unlocked(gobj);
 600                 return r;
 601         }
 602
 603         bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 604         if (!bo_va) {
 605                 ttm_eu_backoff_reservation(&ticket, &list);
 606                 drm_gem_object_unreference_unlocked(gobj);
 607                 return -ENOENT;
 608         }
 609
 610         switch (args->operation) {
 611         case AMDGPU_VA_OP_MAP:
 612                 if (args->flags & AMDGPU_VM_PAGE_READABLE)
 613                         va_flags |= AMDGPU_PTE_READABLE;
 614                 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
 615                         va_flags |= AMDGPU_PTE_WRITEABLE;
 616                 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
 617                         va_flags |= AMDGPU_PTE_EXECUTABLE;
 618                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 619                                      args->offset_in_bo, args->map_size,
 620                                      va_flags);
 621                 break;
 622         case AMDGPU_VA_OP_UNMAP:
 623                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 624                 break;
 625         default:
 626                 break;
 627         }
 628         ttm_eu_backoff_reservation(&ticket, &list);
 629         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
 630             !amdgpu_vm_debug)
 631                 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
 632
 633         drm_gem_object_unreference_unlocked(gobj);
 634         return r;
 635 }
 636
 637 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 638                         struct drm_file *filp)
 639 {
 640         struct drm_amdgpu_gem_op *args = data;
 641         struct drm_gem_object *gobj;
 642         struct amdgpu_bo *robj;
 643         int r;
 644
 645         gobj = drm_gem_object_lookup(filp, args->handle);
 646         if (gobj == NULL) {
 647                 return -ENOENT;
 648         }
 649         robj = gem_to_amdgpu_bo(gobj);
 650
 651         r = amdgpu_bo_reserve(robj, false);
 652         if (unlikely(r))
 653                 goto out;
 654
 655         switch (args->op) {
 656         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 657                 struct drm_amdgpu_gem_create_in info;
 658                 void __user *out = (void __user *)(long)args->value;
 659
 660                 info.bo_size = robj->gem_base.size;
 661                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 662                 info.domains = robj->prefered_domains;
 663                 info.domain_flags = robj->flags;
 664                 amdgpu_bo_unreserve(robj);
 665                 if (copy_to_user(out, &info, sizeof(info)))
 666                         r = -EFAULT;
 667                 break;
 668         }
 669         case AMDGPU_GEM_OP_SET_PLACEMENT:
 670                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 671                         r = -EPERM;
 672                         amdgpu_bo_unreserve(robj);
 673                         break;
 674                 }
 675                 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 676                                                         AMDGPU_GEM_DOMAIN_GTT |
 677                                                         AMDGPU_GEM_DOMAIN_CPU);
 678                 robj->allowed_domains = robj->prefered_domains;
 679                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 680                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 681
 682                 amdgpu_bo_unreserve(robj);
 683                 break;
 684         default:
 685                 amdgpu_bo_unreserve(robj);
 686                 r = -EINVAL;
 687         }
 688
 689 out:
 690         drm_gem_object_unreference_unlocked(gobj);
 691         return r;
 692 }
 693
 694 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 695                             struct drm_device *dev,
 696                             struct drm_mode_create_dumb *args)
 697 {
 698         struct amdgpu_device *adev = dev->dev_private;
 699         struct drm_gem_object *gobj;
 700         uint32_t handle;
 701         int r;
 702
 703         args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
 704         args->size = (u64)args->pitch * args->height;
 705         args->size = ALIGN(args->size, PAGE_SIZE);
 706
 707         r = amdgpu_gem_object_create(adev, args->size, 0,
 708                                      AMDGPU_GEM_DOMAIN_VRAM,
 709                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 710                                      ttm_bo_type_device,
 711                                      &gobj);
 712         if (r)
 713                 return -ENOMEM;
 714
 715         r = drm_gem_handle_create(file_priv, gobj, &handle);
 716         /* drop reference from allocate - handle holds it now */
 717         drm_gem_object_unreference_unlocked(gobj);
 718         if (r) {
 719                 return r;
 720         }
 721         args->handle = handle;
 722         return 0;
 723 }
 724
 725 #if defined(CONFIG_DEBUG_FS)
 726 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 727 {
 728         struct drm_gem_object *gobj = ptr;
 729         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 730         struct seq_file *m = data;
 731
 732         unsigned domain;
 733         const char *placement;
 734         unsigned pin_count;
 735
 736         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 737         switch (domain) {
 738         case AMDGPU_GEM_DOMAIN_VRAM:
 739                 placement = "VRAM";
 740                 break;
 741         case AMDGPU_GEM_DOMAIN_GTT:
 742                 placement = " GTT";
 743                 break;
 744         case AMDGPU_GEM_DOMAIN_CPU:
 745         default:
 746                 placement = " CPU";
 747                 break;
 748         }
 749         seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
 750                    id, amdgpu_bo_size(bo), placement,
 751                    amdgpu_bo_gpu_offset(bo));
 752
 753         pin_count = ACCESS_ONCE(bo->pin_count);
 754         if (pin_count)
 755                 seq_printf(m, " pin count %d", pin_count);
 756         seq_printf(m, "\n");
 757
 758         return 0;
 759 }
 760
 761 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 762 {
 763         struct drm_info_node *node = (struct drm_info_node *)m->private;
 764         struct drm_device *dev = node->minor->dev;
 765         struct drm_file *file;
 766         int r;
 767
 768         r = mutex_lock_interruptible(&dev->filelist_mutex);
 769         if (r)
 770                 return r;
 771
 772         list_for_each_entry(file, &dev->filelist, lhead) {
 773                 struct task_struct *task;
 774
 775                 /*
 776                  * Although we have a valid reference on file->pid, that does
 777                  * not guarantee that the task_struct who called get_pid() is
 778                  * still alive (e.g. get_pid(current) => fork() => exit()).
 779                  * Therefore, we need to protect this ->comm access using RCU.
 780                  */
 781                 rcu_read_lock();
 782                 task = pid_task(file->pid, PIDTYPE_PID);
 783                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 784                            task ? task->comm : "<unknown>");
 785                 rcu_read_unlock();
 786
 787                 spin_lock(&file->table_lock);
 788                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 789                 spin_unlock(&file->table_lock);
 790         }
 791
 792         mutex_unlock(&dev->filelist_mutex);
 793         return 0;
 794 }
 795
 796 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 797         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 798 };
 799 #endif
 800
 801 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 802 {
 803 #if defined(CONFIG_DEBUG_FS)
 804         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 805 #endif
 806         return 0;
 807 }