drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <ttm/ttm_memory.h>
  38 #include <drm/drmP.h>
  39 #include <drm/amdgpu_drm.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/slab.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include <linux/debugfs.h>
  46 #include "amdgpu.h"
  47 #include "bif/bif_4_1_d.h"
  48
  49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  50
  51 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  52 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  53
  54 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  55 {
  56         struct amdgpu_mman *mman;
  57         struct amdgpu_device *adev;
  58
  59         mman = container_of(bdev, struct amdgpu_mman, bdev);
  60         adev = container_of(mman, struct amdgpu_device, mman);
  61         return adev;
  62 }
  63
  64
  65 /*
  66  * Global memory.
  67  */
  68 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  69 {
  70         return ttm_mem_global_init(ref->object);
  71 }
  72
  73 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  74 {
  75         ttm_mem_global_release(ref->object);
  76 }
  77
  78 int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  79 {
  80         struct drm_global_reference *global_ref;
  81         struct amdgpu_ring *ring;
  82         struct amd_sched_rq *rq;
  83         int r;
  84
  85         adev->mman.mem_global_referenced = false;
  86         global_ref = &adev->mman.mem_global_ref;
  87         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  88         global_ref->size = sizeof(struct ttm_mem_global);
  89         global_ref->init = &amdgpu_ttm_mem_global_init;
  90         global_ref->release = &amdgpu_ttm_mem_global_release;
  91         r = drm_global_item_ref(global_ref);
  92         if (r) {
  93                 DRM_ERROR("Failed setting up TTM memory accounting "
  94                           "subsystem.\n");
  95                 goto error_mem;
  96         }
  97
  98         adev->mman.bo_global_ref.mem_glob =
  99                 adev->mman.mem_global_ref.object;
 100         global_ref = &adev->mman.bo_global_ref.ref;
 101         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 102         global_ref->size = sizeof(struct ttm_bo_global);
 103         global_ref->init = &ttm_bo_global_init;
 104         global_ref->release = &ttm_bo_global_release;
 105         r = drm_global_item_ref(global_ref);
 106         if (r) {
 107                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 108                 goto error_bo;
 109         }
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 113         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, amdgpu_sched_jobs);
 115         if (r) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 goto error_entity;
 118         }
 119
 120         adev->mman.mem_global_referenced = true;
 121
 122         return 0;
 123
 124 error_entity:
 125         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 126 error_bo:
 127         drm_global_item_unref(&adev->mman.mem_global_ref);
 128 error_mem:
 129         return r;
 130 }
 131
 132 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 133 {
 134         if (adev->mman.mem_global_referenced) {
 135                 amd_sched_entity_fini(adev->mman.entity.sched,
 136                                       &adev->mman.entity);
 137                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 138                 drm_global_item_unref(&adev->mman.mem_global_ref);
 139                 adev->mman.mem_global_referenced = false;
 140         }
 141 }
 142
 143 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 144 {
 145         return 0;
 146 }
 147
 148 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 149                                 struct ttm_mem_type_manager *man)
 150 {
 151         struct amdgpu_device *adev;
 152
 153         adev = amdgpu_get_adev(bdev);
 154
 155         switch (type) {
 156         case TTM_PL_SYSTEM:
 157                 /* System memory */
 158                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 159                 man->available_caching = TTM_PL_MASK_CACHING;
 160                 man->default_caching = TTM_PL_FLAG_CACHED;
 161                 break;
 162         case TTM_PL_TT:
 163                 man->func = &amdgpu_gtt_mgr_func;
 164                 man->gpu_offset = adev->mc.gtt_start;
 165                 man->available_caching = TTM_PL_MASK_CACHING;
 166                 man->default_caching = TTM_PL_FLAG_CACHED;
 167                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 168                 break;
 169         case TTM_PL_VRAM:
 170                 /* "On-card" video ram */
 171                 man->func = &ttm_bo_manager_func;
 172                 man->gpu_offset = adev->mc.vram_start;
 173                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 174                              TTM_MEMTYPE_FLAG_MAPPABLE;
 175                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 176                 man->default_caching = TTM_PL_FLAG_WC;
 177                 break;
 178         case AMDGPU_PL_GDS:
 179         case AMDGPU_PL_GWS:
 180         case AMDGPU_PL_OA:
 181                 /* On-chip GDS memory*/
 182                 man->func = &ttm_bo_manager_func;
 183                 man->gpu_offset = 0;
 184                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 185                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 186                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 187                 break;
 188         default:
 189                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 190                 return -EINVAL;
 191         }
 192         return 0;
 193 }
 194
 195 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 196                                 struct ttm_placement *placement)
 197 {
 198         struct amdgpu_bo *abo;
 199         static struct ttm_place placements = {
 200                 .fpfn = 0,
 201                 .lpfn = 0,
 202                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 203         };
 204         unsigned i;
 205
 206         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 207                 placement->placement = &placements;
 208                 placement->busy_placement = &placements;
 209                 placement->num_placement = 1;
 210                 placement->num_busy_placement = 1;
 211                 return;
 212         }
 213         abo = container_of(bo, struct amdgpu_bo, tbo);
 214         switch (bo->mem.mem_type) {
 215         case TTM_PL_VRAM:
 216                 if (abo->adev->mman.buffer_funcs_ring->ready == false) {
 217                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 218                 } else {
 219                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 220                         for (i = 0; i < abo->placement.num_placement; ++i) {
 221                                 if (!(abo->placements[i].flags &
 222                                       TTM_PL_FLAG_TT))
 223                                         continue;
 224
 225                                 if (abo->placements[i].lpfn)
 226                                         continue;
 227
 228                                 /* set an upper limit to force directly
 229                                  * allocating address space for the BO.
 230                                  */
 231                                 abo->placements[i].lpfn =
 232                                         abo->adev->mc.gtt_size >> PAGE_SHIFT;
 233                         }
 234                 }
 235                 break;
 236         case TTM_PL_TT:
 237         default:
 238                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 239         }
 240         *placement = abo->placement;
 241 }
 242
 243 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 244 {
 245         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 246
 247         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 248                 return -EPERM;
 249         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 250                                           filp->private_data);
 251 }
 252
 253 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 254                              struct ttm_mem_reg *new_mem)
 255 {
 256         struct ttm_mem_reg *old_mem = &bo->mem;
 257
 258         BUG_ON(old_mem->mm_node != NULL);
 259         *old_mem = *new_mem;
 260         new_mem->mm_node = NULL;
 261 }
 262
 263 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 264                         bool evict, bool no_wait_gpu,
 265                         struct ttm_mem_reg *new_mem,
 266                         struct ttm_mem_reg *old_mem)
 267 {
 268         struct amdgpu_device *adev;
 269         struct amdgpu_ring *ring;
 270         uint64_t old_start, new_start;
 271         struct fence *fence;
 272         int r;
 273
 274         adev = amdgpu_get_adev(bo->bdev);
 275         ring = adev->mman.buffer_funcs_ring;
 276
 277         switch (old_mem->mem_type) {
 278         case TTM_PL_TT:
 279                 r = amdgpu_ttm_bind(bo, old_mem);
 280                 if (r)
 281                         return r;
 282
 283         case TTM_PL_VRAM:
 284                 old_start = (u64)old_mem->start << PAGE_SHIFT;
 285                 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
 286                 break;
 287         default:
 288                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 289                 return -EINVAL;
 290         }
 291         switch (new_mem->mem_type) {
 292         case TTM_PL_TT:
 293                 r = amdgpu_ttm_bind(bo, new_mem);
 294                 if (r)
 295                         return r;
 296
 297         case TTM_PL_VRAM:
 298                 new_start = (u64)new_mem->start << PAGE_SHIFT;
 299                 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
 300                 break;
 301         default:
 302                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 303                 return -EINVAL;
 304         }
 305         if (!ring->ready) {
 306                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 307                 return -EINVAL;
 308         }
 309
 310         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 311
 312         r = amdgpu_copy_buffer(ring, old_start, new_start,
 313                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 314                                bo->resv, &fence, false);
 315         if (r)
 316                 return r;
 317
 318         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 319         fence_put(fence);
 320         return r;
 321 }
 322
 323 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 324                                 bool evict, bool interruptible,
 325                                 bool no_wait_gpu,
 326                                 struct ttm_mem_reg *new_mem)
 327 {
 328         struct amdgpu_device *adev;
 329         struct ttm_mem_reg *old_mem = &bo->mem;
 330         struct ttm_mem_reg tmp_mem;
 331         struct ttm_place placements;
 332         struct ttm_placement placement;
 333         int r;
 334
 335         adev = amdgpu_get_adev(bo->bdev);
 336         tmp_mem = *new_mem;
 337         tmp_mem.mm_node = NULL;
 338         placement.num_placement = 1;
 339         placement.placement = &placements;
 340         placement.num_busy_placement = 1;
 341         placement.busy_placement = &placements;
 342         placements.fpfn = 0;
 343         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 344         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 345         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 346                              interruptible, no_wait_gpu);
 347         if (unlikely(r)) {
 348                 return r;
 349         }
 350
 351         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 352         if (unlikely(r)) {
 353                 goto out_cleanup;
 354         }
 355
 356         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 357         if (unlikely(r)) {
 358                 goto out_cleanup;
 359         }
 360         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 361         if (unlikely(r)) {
 362                 goto out_cleanup;
 363         }
 364         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 365 out_cleanup:
 366         ttm_bo_mem_put(bo, &tmp_mem);
 367         return r;
 368 }
 369
 370 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 371                                 bool evict, bool interruptible,
 372                                 bool no_wait_gpu,
 373                                 struct ttm_mem_reg *new_mem)
 374 {
 375         struct amdgpu_device *adev;
 376         struct ttm_mem_reg *old_mem = &bo->mem;
 377         struct ttm_mem_reg tmp_mem;
 378         struct ttm_placement placement;
 379         struct ttm_place placements;
 380         int r;
 381
 382         adev = amdgpu_get_adev(bo->bdev);
 383         tmp_mem = *new_mem;
 384         tmp_mem.mm_node = NULL;
 385         placement.num_placement = 1;
 386         placement.placement = &placements;
 387         placement.num_busy_placement = 1;
 388         placement.busy_placement = &placements;
 389         placements.fpfn = 0;
 390         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 391         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 392         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 393                              interruptible, no_wait_gpu);
 394         if (unlikely(r)) {
 395                 return r;
 396         }
 397         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 398         if (unlikely(r)) {
 399                 goto out_cleanup;
 400         }
 401         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 402         if (unlikely(r)) {
 403                 goto out_cleanup;
 404         }
 405 out_cleanup:
 406         ttm_bo_mem_put(bo, &tmp_mem);
 407         return r;
 408 }
 409
 410 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 411                         bool evict, bool interruptible,
 412                         bool no_wait_gpu,
 413                         struct ttm_mem_reg *new_mem)
 414 {
 415         struct amdgpu_device *adev;
 416         struct amdgpu_bo *abo;
 417         struct ttm_mem_reg *old_mem = &bo->mem;
 418         int r;
 419
 420         /* Can't move a pinned BO */
 421         abo = container_of(bo, struct amdgpu_bo, tbo);
 422         if (WARN_ON_ONCE(abo->pin_count > 0))
 423                 return -EINVAL;
 424
 425         adev = amdgpu_get_adev(bo->bdev);
 426
 427         /* remember the eviction */
 428         if (evict)
 429                 atomic64_inc(&adev->num_evictions);
 430
 431         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 432                 amdgpu_move_null(bo, new_mem);
 433                 return 0;
 434         }
 435         if ((old_mem->mem_type == TTM_PL_TT &&
 436              new_mem->mem_type == TTM_PL_SYSTEM) ||
 437             (old_mem->mem_type == TTM_PL_SYSTEM &&
 438              new_mem->mem_type == TTM_PL_TT)) {
 439                 /* bind is enough */
 440                 amdgpu_move_null(bo, new_mem);
 441                 return 0;
 442         }
 443         if (adev->mman.buffer_funcs == NULL ||
 444             adev->mman.buffer_funcs_ring == NULL ||
 445             !adev->mman.buffer_funcs_ring->ready) {
 446                 /* use memcpy */
 447                 goto memcpy;
 448         }
 449
 450         if (old_mem->mem_type == TTM_PL_VRAM &&
 451             new_mem->mem_type == TTM_PL_SYSTEM) {
 452                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 453                                         no_wait_gpu, new_mem);
 454         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 455                    new_mem->mem_type == TTM_PL_VRAM) {
 456                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 457                                             no_wait_gpu, new_mem);
 458         } else {
 459                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 460         }
 461
 462         if (r) {
 463 memcpy:
 464                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 465                 if (r) {
 466                         return r;
 467                 }
 468         }
 469
 470         /* update statistics */
 471         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 472         return 0;
 473 }
 474
 475 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 476 {
 477         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 478         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 479
 480         mem->bus.addr = NULL;
 481         mem->bus.offset = 0;
 482         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 483         mem->bus.base = 0;
 484         mem->bus.is_iomem = false;
 485         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 486                 return -EINVAL;
 487         switch (mem->mem_type) {
 488         case TTM_PL_SYSTEM:
 489                 /* system memory */
 490                 return 0;
 491         case TTM_PL_TT:
 492                 break;
 493         case TTM_PL_VRAM:
 494                 if (mem->start == AMDGPU_BO_INVALID_OFFSET)
 495                         return -EINVAL;
 496
 497                 mem->bus.offset = mem->start << PAGE_SHIFT;
 498                 /* check if it's visible */
 499                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 500                         return -EINVAL;
 501                 mem->bus.base = adev->mc.aper_base;
 502                 mem->bus.is_iomem = true;
 503 #ifdef __alpha__
 504                 /*
 505                  * Alpha: use bus.addr to hold the ioremap() return,
 506                  * so we can modify bus.base below.
 507                  */
 508                 if (mem->placement & TTM_PL_FLAG_WC)
 509                         mem->bus.addr =
 510                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 511                                            mem->bus.size);
 512                 else
 513                         mem->bus.addr =
 514                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 515                                                 mem->bus.size);
 516
 517                 /*
 518                  * Alpha: Use just the bus offset plus
 519                  * the hose/domain memory base for bus.base.
 520                  * It then can be used to build PTEs for VRAM
 521                  * access, as done in ttm_bo_vm_fault().
 522                  */
 523                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 524                         adev->ddev->hose->dense_mem_base;
 525 #endif
 526                 break;
 527         default:
 528                 return -EINVAL;
 529         }
 530         return 0;
 531 }
 532
 533 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 534 {
 535 }
 536
 537 /*
 538  * TTM backend functions.
 539  */
 540 struct amdgpu_ttm_gup_task_list {
 541         struct list_head        list;
 542         struct task_struct      *task;
 543 };
 544
 545 struct amdgpu_ttm_tt {
 546         struct ttm_dma_tt       ttm;
 547         struct amdgpu_device    *adev;
 548         u64                     offset;
 549         uint64_t                userptr;
 550         struct mm_struct        *usermm;
 551         uint32_t                userflags;
 552         spinlock_t              guptasklock;
 553         struct list_head        guptasks;
 554         atomic_t                mmu_invalidations;
 555         struct list_head        list;
 556 };
 557
 558 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 559 {
 560         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 561         unsigned int flags = 0;
 562         unsigned pinned = 0;
 563         int r;
 564
 565         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 566                 flags |= FOLL_WRITE;
 567
 568         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 569                 /* check that we only use anonymous memory
 570                    to prevent problems with writeback */
 571                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 572                 struct vm_area_struct *vma;
 573
 574                 vma = find_vma(gtt->usermm, gtt->userptr);
 575                 if (!vma || vma->vm_file || vma->vm_end < end)
 576                         return -EPERM;
 577         }
 578
 579         do {
 580                 unsigned num_pages = ttm->num_pages - pinned;
 581                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 582                 struct page **p = pages + pinned;
 583                 struct amdgpu_ttm_gup_task_list guptask;
 584
 585                 guptask.task = current;
 586                 spin_lock(&gtt->guptasklock);
 587                 list_add(&guptask.list, &gtt->guptasks);
 588                 spin_unlock(&gtt->guptasklock);
 589
 590                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 591
 592                 spin_lock(&gtt->guptasklock);
 593                 list_del(&guptask.list);
 594                 spin_unlock(&gtt->guptasklock);
 595
 596                 if (r < 0)
 597                         goto release_pages;
 598
 599                 pinned += r;
 600
 601         } while (pinned < ttm->num_pages);
 602
 603         return 0;
 604
 605 release_pages:
 606         release_pages(pages, pinned, 0);
 607         return r;
 608 }
 609
 610 /* prepare the sg table with the user pages */
 611 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 612 {
 613         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 614         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 615         unsigned nents;
 616         int r;
 617
 618         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 619         enum dma_data_direction direction = write ?
 620                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 621
 622         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 623                                       ttm->num_pages << PAGE_SHIFT,
 624                                       GFP_KERNEL);
 625         if (r)
 626                 goto release_sg;
 627
 628         r = -ENOMEM;
 629         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 630         if (nents != ttm->sg->nents)
 631                 goto release_sg;
 632
 633         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 634                                          gtt->ttm.dma_address, ttm->num_pages);
 635
 636         return 0;
 637
 638 release_sg:
 639         kfree(ttm->sg);
 640         ttm->sg = NULL;
 641         return r;
 642 }
 643
 644 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 645 {
 646         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 647         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 648         struct sg_page_iter sg_iter;
 649
 650         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 651         enum dma_data_direction direction = write ?
 652                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 653
 654         /* double check that we don't free the table twice */
 655         if (!ttm->sg || !ttm->sg->sgl)
 656                 return;
 657
 658         /* free the sg table and pages again */
 659         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 660
 661         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 662                 struct page *page = sg_page_iter_page(&sg_iter);
 663                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 664                         set_page_dirty(page);
 665
 666                 mark_page_accessed(page);
 667                 put_page(page);
 668         }
 669
 670         sg_free_table(ttm->sg);
 671 }
 672
 673 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 674                                    struct ttm_mem_reg *bo_mem)
 675 {
 676         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 677         int r;
 678
 679         if (gtt->userptr) {
 680                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 681                 if (r) {
 682                         DRM_ERROR("failed to pin userptr\n");
 683                         return r;
 684                 }
 685         }
 686         if (!ttm->num_pages) {
 687                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 688                      ttm->num_pages, bo_mem, ttm);
 689         }
 690
 691         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 692             bo_mem->mem_type == AMDGPU_PL_GWS ||
 693             bo_mem->mem_type == AMDGPU_PL_OA)
 694                 return -EINVAL;
 695
 696         return 0;
 697 }
 698
 699 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 700 {
 701         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 702
 703         return gtt && !list_empty(&gtt->list);
 704 }
 705
 706 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 707 {
 708         struct ttm_tt *ttm = bo->ttm;
 709         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 710         uint32_t flags;
 711         int r;
 712
 713         if (!ttm || amdgpu_ttm_is_bound(ttm))
 714                 return 0;
 715
 716         r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
 717                                  NULL, bo_mem);
 718         if (r) {
 719                 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
 720                 return r;
 721         }
 722
 723         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 724         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 725         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 726                 ttm->pages, gtt->ttm.dma_address, flags);
 727
 728         if (r) {
 729                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 730                           ttm->num_pages, gtt->offset);
 731                 return r;
 732         }
 733         spin_lock(&gtt->adev->gtt_list_lock);
 734         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 735         spin_unlock(&gtt->adev->gtt_list_lock);
 736         return 0;
 737 }
 738
 739 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 740 {
 741         struct amdgpu_ttm_tt *gtt, *tmp;
 742         struct ttm_mem_reg bo_mem;
 743         uint32_t flags;
 744         int r;
 745
 746         bo_mem.mem_type = TTM_PL_TT;
 747         spin_lock(&adev->gtt_list_lock);
 748         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 749                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 750                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 751                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 752                                      flags);
 753                 if (r) {
 754                         spin_unlock(&adev->gtt_list_lock);
 755                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 756                                   gtt->ttm.ttm.num_pages, gtt->offset);
 757                         return r;
 758                 }
 759         }
 760         spin_unlock(&adev->gtt_list_lock);
 761         return 0;
 762 }
 763
 764 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 765 {
 766         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 767
 768         if (gtt->userptr)
 769                 amdgpu_ttm_tt_unpin_userptr(ttm);
 770
 771         if (!amdgpu_ttm_is_bound(ttm))
 772                 return 0;
 773
 774         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 775         if (gtt->adev->gart.ready)
 776                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 777
 778         spin_lock(&gtt->adev->gtt_list_lock);
 779         list_del_init(&gtt->list);
 780         spin_unlock(&gtt->adev->gtt_list_lock);
 781
 782         return 0;
 783 }
 784
 785 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 786 {
 787         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 788
 789         ttm_dma_tt_fini(&gtt->ttm);
 790         kfree(gtt);
 791 }
 792
 793 static struct ttm_backend_func amdgpu_backend_func = {
 794         .bind = &amdgpu_ttm_backend_bind,
 795         .unbind = &amdgpu_ttm_backend_unbind,
 796         .destroy = &amdgpu_ttm_backend_destroy,
 797 };
 798
 799 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 800                                     unsigned long size, uint32_t page_flags,
 801                                     struct page *dummy_read_page)
 802 {
 803         struct amdgpu_device *adev;
 804         struct amdgpu_ttm_tt *gtt;
 805
 806         adev = amdgpu_get_adev(bdev);
 807
 808         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 809         if (gtt == NULL) {
 810                 return NULL;
 811         }
 812         gtt->ttm.ttm.func = &amdgpu_backend_func;
 813         gtt->adev = adev;
 814         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 815                 kfree(gtt);
 816                 return NULL;
 817         }
 818         INIT_LIST_HEAD(&gtt->list);
 819         return &gtt->ttm.ttm;
 820 }
 821
 822 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 823 {
 824         struct amdgpu_device *adev;
 825         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 826         unsigned i;
 827         int r;
 828         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 829
 830         if (ttm->state != tt_unpopulated)
 831                 return 0;
 832
 833         if (gtt && gtt->userptr) {
 834                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 835                 if (!ttm->sg)
 836                         return -ENOMEM;
 837
 838                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 839                 ttm->state = tt_unbound;
 840                 return 0;
 841         }
 842
 843         if (slave && ttm->sg) {
 844                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 845                                                  gtt->ttm.dma_address, ttm->num_pages);
 846                 ttm->state = tt_unbound;
 847                 return 0;
 848         }
 849
 850         adev = amdgpu_get_adev(ttm->bdev);
 851
 852 #ifdef CONFIG_SWIOTLB
 853         if (swiotlb_nr_tbl()) {
 854                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 855         }
 856 #endif
 857
 858         r = ttm_pool_populate(ttm);
 859         if (r) {
 860                 return r;
 861         }
 862
 863         for (i = 0; i < ttm->num_pages; i++) {
 864                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 865                                                        0, PAGE_SIZE,
 866                                                        PCI_DMA_BIDIRECTIONAL);
 867                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 868                         while (i--) {
 869                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 870                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 871                                 gtt->ttm.dma_address[i] = 0;
 872                         }
 873                         ttm_pool_unpopulate(ttm);
 874                         return -EFAULT;
 875                 }
 876         }
 877         return 0;
 878 }
 879
 880 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 881 {
 882         struct amdgpu_device *adev;
 883         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 884         unsigned i;
 885         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 886
 887         if (gtt && gtt->userptr) {
 888                 kfree(ttm->sg);
 889                 ttm->sg = NULL;
 890                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 891                 return;
 892         }
 893
 894         if (slave)
 895                 return;
 896
 897         adev = amdgpu_get_adev(ttm->bdev);
 898
 899 #ifdef CONFIG_SWIOTLB
 900         if (swiotlb_nr_tbl()) {
 901                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 902                 return;
 903         }
 904 #endif
 905
 906         for (i = 0; i < ttm->num_pages; i++) {
 907                 if (gtt->ttm.dma_address[i]) {
 908                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 909                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 910                 }
 911         }
 912
 913         ttm_pool_unpopulate(ttm);
 914 }
 915
 916 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 917                               uint32_t flags)
 918 {
 919         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 920
 921         if (gtt == NULL)
 922                 return -EINVAL;
 923
 924         gtt->userptr = addr;
 925         gtt->usermm = current->mm;
 926         gtt->userflags = flags;
 927         spin_lock_init(&gtt->guptasklock);
 928         INIT_LIST_HEAD(&gtt->guptasks);
 929         atomic_set(&gtt->mmu_invalidations, 0);
 930
 931         return 0;
 932 }
 933
 934 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 935 {
 936         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 937
 938         if (gtt == NULL)
 939                 return NULL;
 940
 941         return gtt->usermm;
 942 }
 943
 944 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 945                                   unsigned long end)
 946 {
 947         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 948         struct amdgpu_ttm_gup_task_list *entry;
 949         unsigned long size;
 950
 951         if (gtt == NULL || !gtt->userptr)
 952                 return false;
 953
 954         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 955         if (gtt->userptr > end || gtt->userptr + size <= start)
 956                 return false;
 957
 958         spin_lock(&gtt->guptasklock);
 959         list_for_each_entry(entry, &gtt->guptasks, list) {
 960                 if (entry->task == current) {
 961                         spin_unlock(&gtt->guptasklock);
 962                         return false;
 963                 }
 964         }
 965         spin_unlock(&gtt->guptasklock);
 966
 967         atomic_inc(&gtt->mmu_invalidations);
 968
 969         return true;
 970 }
 971
 972 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 973                                        int *last_invalidated)
 974 {
 975         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 976         int prev_invalidated = *last_invalidated;
 977
 978         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
 979         return prev_invalidated != *last_invalidated;
 980 }
 981
 982 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 983 {
 984         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 985
 986         if (gtt == NULL)
 987                 return false;
 988
 989         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 990 }
 991
 992 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 993                                  struct ttm_mem_reg *mem)
 994 {
 995         uint32_t flags = 0;
 996
 997         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 998                 flags |= AMDGPU_PTE_VALID;
 999
1000         if (mem && mem->mem_type == TTM_PL_TT) {
1001                 flags |= AMDGPU_PTE_SYSTEM;
1002
1003                 if (ttm->caching_state == tt_cached)
1004                         flags |= AMDGPU_PTE_SNOOPED;
1005         }
1006
1007         if (adev->asic_type >= CHIP_TONGA)
1008                 flags |= AMDGPU_PTE_EXECUTABLE;
1009
1010         flags |= AMDGPU_PTE_READABLE;
1011
1012         if (!amdgpu_ttm_tt_is_readonly(ttm))
1013                 flags |= AMDGPU_PTE_WRITEABLE;
1014
1015         return flags;
1016 }
1017
1018 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1019 {
1020         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1021         unsigned i, j;
1022
1023         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1024                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1025
1026                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1027                         if (&tbo->lru == lru->lru[j])
1028                                 lru->lru[j] = tbo->lru.prev;
1029
1030                 if (&tbo->swap == lru->swap_lru)
1031                         lru->swap_lru = tbo->swap.prev;
1032         }
1033 }
1034
1035 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1036 {
1037         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1038         unsigned log2_size = min(ilog2(tbo->num_pages),
1039                                  AMDGPU_TTM_LRU_SIZE - 1);
1040
1041         return &adev->mman.log2_size[log2_size];
1042 }
1043
1044 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1045 {
1046         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1047         struct list_head *res = lru->lru[tbo->mem.mem_type];
1048
1049         lru->lru[tbo->mem.mem_type] = &tbo->lru;
1050         while ((++lru)->lru[tbo->mem.mem_type] == res)
1051                 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1052
1053         return res;
1054 }
1055
1056 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1057 {
1058         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1059         struct list_head *res = lru->swap_lru;
1060
1061         lru->swap_lru = &tbo->swap;
1062         while ((++lru)->swap_lru == res)
1063                 lru->swap_lru = &tbo->swap;
1064
1065         return res;
1066 }
1067
1068 static struct ttm_bo_driver amdgpu_bo_driver = {
1069         .ttm_tt_create = &amdgpu_ttm_tt_create,
1070         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1071         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1072         .invalidate_caches = &amdgpu_invalidate_caches,
1073         .init_mem_type = &amdgpu_init_mem_type,
1074         .evict_flags = &amdgpu_evict_flags,
1075         .move = &amdgpu_bo_move,
1076         .verify_access = &amdgpu_verify_access,
1077         .move_notify = &amdgpu_bo_move_notify,
1078         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1079         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1080         .io_mem_free = &amdgpu_ttm_io_mem_free,
1081         .lru_removal = &amdgpu_ttm_lru_removal,
1082         .lru_tail = &amdgpu_ttm_lru_tail,
1083         .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
1084 };
1085
1086 int amdgpu_ttm_init(struct amdgpu_device *adev)
1087 {
1088         unsigned i, j;
1089         int r;
1090
1091         /* No others user of address space so set it to 0 */
1092         r = ttm_bo_device_init(&adev->mman.bdev,
1093                                adev->mman.bo_global_ref.ref.object,
1094                                &amdgpu_bo_driver,
1095                                adev->ddev->anon_inode->i_mapping,
1096                                DRM_FILE_PAGE_OFFSET,
1097                                adev->need_dma32);
1098         if (r) {
1099                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1100                 return r;
1101         }
1102
1103         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1104                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1105
1106                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1107                         lru->lru[j] = &adev->mman.bdev.man[j].lru;
1108                 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1109         }
1110
1111         for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1112                 adev->mman.guard.lru[j] = NULL;
1113         adev->mman.guard.swap_lru = NULL;
1114
1115         adev->mman.initialized = true;
1116         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1117                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1118         if (r) {
1119                 DRM_ERROR("Failed initializing VRAM heap.\n");
1120                 return r;
1121         }
1122         /* Change the size here instead of the init above so only lpfn is affected */
1123         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1124
1125         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1126                              AMDGPU_GEM_DOMAIN_VRAM,
1127                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1128                              NULL, NULL, &adev->stollen_vga_memory);
1129         if (r) {
1130                 return r;
1131         }
1132         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1133         if (r)
1134                 return r;
1135         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1136         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1137         if (r) {
1138                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1139                 return r;
1140         }
1141         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1142                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1143         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1144                                 adev->mc.gtt_size >> PAGE_SHIFT);
1145         if (r) {
1146                 DRM_ERROR("Failed initializing GTT heap.\n");
1147                 return r;
1148         }
1149         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1150                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1151
1152         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1153         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1154         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1155         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1156         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1157         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1158         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1159         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1160         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1161         /* GDS Memory */
1162         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1163                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1164         if (r) {
1165                 DRM_ERROR("Failed initializing GDS heap.\n");
1166                 return r;
1167         }
1168
1169         /* GWS */
1170         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1171                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1172         if (r) {
1173                 DRM_ERROR("Failed initializing gws heap.\n");
1174                 return r;
1175         }
1176
1177         /* OA */
1178         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1179                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1180         if (r) {
1181                 DRM_ERROR("Failed initializing oa heap.\n");
1182                 return r;
1183         }
1184
1185         r = amdgpu_ttm_debugfs_init(adev);
1186         if (r) {
1187                 DRM_ERROR("Failed to init debugfs\n");
1188                 return r;
1189         }
1190         return 0;
1191 }
1192
1193 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1194 {
1195         int r;
1196
1197         if (!adev->mman.initialized)
1198                 return;
1199         amdgpu_ttm_debugfs_fini(adev);
1200         if (adev->stollen_vga_memory) {
1201                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1202                 if (r == 0) {
1203                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1204                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1205                 }
1206                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1207         }
1208         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1209         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1210         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1211         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1212         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1213         ttm_bo_device_release(&adev->mman.bdev);
1214         amdgpu_gart_fini(adev);
1215         amdgpu_ttm_global_fini(adev);
1216         adev->mman.initialized = false;
1217         DRM_INFO("amdgpu: ttm finalized\n");
1218 }
1219
1220 /* this should only be called at bootup or when userspace
1221  * isn't running */
1222 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1223 {
1224         struct ttm_mem_type_manager *man;
1225
1226         if (!adev->mman.initialized)
1227                 return;
1228
1229         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1230         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1231         man->size = size >> PAGE_SHIFT;
1232 }
1233
1234 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1235 {
1236         struct drm_file *file_priv;
1237         struct amdgpu_device *adev;
1238
1239         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1240                 return -EINVAL;
1241
1242         file_priv = filp->private_data;
1243         adev = file_priv->minor->dev->dev_private;
1244         if (adev == NULL)
1245                 return -EINVAL;
1246
1247         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1248 }
1249
1250 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1251                        uint64_t src_offset,
1252                        uint64_t dst_offset,
1253                        uint32_t byte_count,
1254                        struct reservation_object *resv,
1255                        struct fence **fence, bool direct_submit)
1256 {
1257         struct amdgpu_device *adev = ring->adev;
1258         struct amdgpu_job *job;
1259
1260         uint32_t max_bytes;
1261         unsigned num_loops, num_dw;
1262         unsigned i;
1263         int r;
1264
1265         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1266         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1267         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1268
1269         /* for IB padding */
1270         while (num_dw & 0x7)
1271                 num_dw++;
1272
1273         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1274         if (r)
1275                 return r;
1276
1277         if (resv) {
1278                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1279                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1280                 if (r) {
1281                         DRM_ERROR("sync failed (%d).\n", r);
1282                         goto error_free;
1283                 }
1284         }
1285
1286         for (i = 0; i < num_loops; i++) {
1287                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1288
1289                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1290                                         dst_offset, cur_size_in_bytes);
1291
1292                 src_offset += cur_size_in_bytes;
1293                 dst_offset += cur_size_in_bytes;
1294                 byte_count -= cur_size_in_bytes;
1295         }
1296
1297         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1298         WARN_ON(job->ibs[0].length_dw > num_dw);
1299         if (direct_submit) {
1300                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1301                                        NULL, NULL, fence);
1302                 job->fence = fence_get(*fence);
1303                 if (r)
1304                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1305                 amdgpu_job_free(job);
1306         } else {
1307                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1308                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1309                 if (r)
1310                         goto error_free;
1311         }
1312
1313         return r;
1314
1315 error_free:
1316         amdgpu_job_free(job);
1317         return r;
1318 }
1319
1320 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1321                 uint32_t src_data,
1322                 struct reservation_object *resv,
1323                 struct fence **fence)
1324 {
1325         struct amdgpu_device *adev = bo->adev;
1326         struct amdgpu_job *job;
1327         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1328
1329         uint32_t max_bytes, byte_count;
1330         uint64_t dst_offset;
1331         unsigned int num_loops, num_dw;
1332         unsigned int i;
1333         int r;
1334
1335         byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1336         max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1337         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1338         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1339
1340         /* for IB padding */
1341         while (num_dw & 0x7)
1342                 num_dw++;
1343
1344         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1345         if (r)
1346                 return r;
1347
1348         if (resv) {
1349                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1350                                 AMDGPU_FENCE_OWNER_UNDEFINED);
1351                 if (r) {
1352                         DRM_ERROR("sync failed (%d).\n", r);
1353                         goto error_free;
1354                 }
1355         }
1356
1357         dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1358         for (i = 0; i < num_loops; i++) {
1359                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1360
1361                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1362                                 dst_offset, cur_size_in_bytes);
1363
1364                 dst_offset += cur_size_in_bytes;
1365                 byte_count -= cur_size_in_bytes;
1366         }
1367
1368         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1369         WARN_ON(job->ibs[0].length_dw > num_dw);
1370         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1371                         AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1372         if (r)
1373                 goto error_free;
1374
1375         return 0;
1376
1377 error_free:
1378         amdgpu_job_free(job);
1379         return r;
1380 }
1381
1382 #if defined(CONFIG_DEBUG_FS)
1383
1384 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1385 {
1386         struct drm_info_node *node = (struct drm_info_node *)m->private;
1387         unsigned ttm_pl = *(int *)node->info_ent->data;
1388         struct drm_device *dev = node->minor->dev;
1389         struct amdgpu_device *adev = dev->dev_private;
1390         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1391         int ret;
1392         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1393
1394         spin_lock(&glob->lru_lock);
1395         ret = drm_mm_dump_table(m, mm);
1396         spin_unlock(&glob->lru_lock);
1397         if (ttm_pl == TTM_PL_VRAM)
1398                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1399                            adev->mman.bdev.man[ttm_pl].size,
1400                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1401                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1402         return ret;
1403 }
1404
1405 static int ttm_pl_vram = TTM_PL_VRAM;
1406 static int ttm_pl_tt = TTM_PL_TT;
1407
1408 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1409         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1410         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1411         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1412 #ifdef CONFIG_SWIOTLB
1413         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1414 #endif
1415 };
1416
1417 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1418                                     size_t size, loff_t *pos)
1419 {
1420         struct amdgpu_device *adev = f->f_inode->i_private;
1421         ssize_t result = 0;
1422         int r;
1423
1424         if (size & 0x3 || *pos & 0x3)
1425                 return -EINVAL;
1426
1427         if (*pos >= adev->mc.mc_vram_size)
1428                 return -ENXIO;
1429
1430         while (size) {
1431                 unsigned long flags;
1432                 uint32_t value;
1433
1434                 if (*pos >= adev->mc.mc_vram_size)
1435                         return result;
1436
1437                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1438                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1439                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1440                 value = RREG32(mmMM_DATA);
1441                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1442
1443                 r = put_user(value, (uint32_t *)buf);
1444                 if (r)
1445                         return r;
1446
1447                 result += 4;
1448                 buf += 4;
1449                 *pos += 4;
1450                 size -= 4;
1451         }
1452
1453         return result;
1454 }
1455
1456 static const struct file_operations amdgpu_ttm_vram_fops = {
1457         .owner = THIS_MODULE,
1458         .read = amdgpu_ttm_vram_read,
1459         .llseek = default_llseek
1460 };
1461
1462 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1463
1464 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1465                                    size_t size, loff_t *pos)
1466 {
1467         struct amdgpu_device *adev = f->f_inode->i_private;
1468         ssize_t result = 0;
1469         int r;
1470
1471         while (size) {
1472                 loff_t p = *pos / PAGE_SIZE;
1473                 unsigned off = *pos & ~PAGE_MASK;
1474                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1475                 struct page *page;
1476                 void *ptr;
1477
1478                 if (p >= adev->gart.num_cpu_pages)
1479                         return result;
1480
1481                 page = adev->gart.pages[p];
1482                 if (page) {
1483                         ptr = kmap(page);
1484                         ptr += off;
1485
1486                         r = copy_to_user(buf, ptr, cur_size);
1487                         kunmap(adev->gart.pages[p]);
1488                 } else
1489                         r = clear_user(buf, cur_size);
1490
1491                 if (r)
1492                         return -EFAULT;
1493
1494                 result += cur_size;
1495                 buf += cur_size;
1496                 *pos += cur_size;
1497                 size -= cur_size;
1498         }
1499
1500         return result;
1501 }
1502
1503 static const struct file_operations amdgpu_ttm_gtt_fops = {
1504         .owner = THIS_MODULE,
1505         .read = amdgpu_ttm_gtt_read,
1506         .llseek = default_llseek
1507 };
1508
1509 #endif
1510
1511 #endif
1512
1513 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1514 {
1515 #if defined(CONFIG_DEBUG_FS)
1516         unsigned count;
1517
1518         struct drm_minor *minor = adev->ddev->primary;
1519         struct dentry *ent, *root = minor->debugfs_root;
1520
1521         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1522                                   adev, &amdgpu_ttm_vram_fops);
1523         if (IS_ERR(ent))
1524                 return PTR_ERR(ent);
1525         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1526         adev->mman.vram = ent;
1527
1528 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1529         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1530                                   adev, &amdgpu_ttm_gtt_fops);
1531         if (IS_ERR(ent))
1532                 return PTR_ERR(ent);
1533         i_size_write(ent->d_inode, adev->mc.gtt_size);
1534         adev->mman.gtt = ent;
1535
1536 #endif
1537         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1538
1539 #ifdef CONFIG_SWIOTLB
1540         if (!swiotlb_nr_tbl())
1541                 --count;
1542 #endif
1543
1544         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1545 #else
1546
1547         return 0;
1548 #endif
1549 }
1550
1551 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1552 {
1553 #if defined(CONFIG_DEBUG_FS)
1554
1555         debugfs_remove(adev->mman.vram);
1556         adev->mman.vram = NULL;
1557
1558 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1559         debugfs_remove(adev->mman.gtt);
1560         adev->mman.gtt = NULL;
1561 #endif
1562
1563 #endif
1564 }
1565
1566 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1567 {
1568         return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1569 }