drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT_MS     1000
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_KABINI         "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_KAVERI         "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_HAWAII         "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_MULLINS        "/*(DEBLOBBED)*/"
  48 #endif
  49 #define FIRMWARE_TONGA          "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_CARRIZO        "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_FIJI           "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_STONEY         "/*(DEBLOBBED)*/"
  53
  54 #ifdef CONFIG_DRM_AMDGPU_CIK
  55 /*(DEBLOBBED)*/
  56 #endif
  57 /*(DEBLOBBED)*/
  58
  59 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  60
  61 /**
  62  * amdgpu_vce_init - allocate memory, load vce firmware
  63  *
  64  * @adev: amdgpu_device pointer
  65  *
  66  * First step to get VCE online, allocate memory and load the firmware
  67  */
  68 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  69 {
  70         const char *fw_name;
  71         const struct common_firmware_header *hdr;
  72         unsigned ucode_version, version_major, version_minor, binary_id;
  73         int i, r;
  74
  75         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
  76
  77         switch (adev->asic_type) {
  78 #ifdef CONFIG_DRM_AMDGPU_CIK
  79         case CHIP_BONAIRE:
  80                 fw_name = FIRMWARE_BONAIRE;
  81                 break;
  82         case CHIP_KAVERI:
  83                 fw_name = FIRMWARE_KAVERI;
  84                 break;
  85         case CHIP_KABINI:
  86                 fw_name = FIRMWARE_KABINI;
  87                 break;
  88         case CHIP_HAWAII:
  89                 fw_name = FIRMWARE_HAWAII;
  90                 break;
  91         case CHIP_MULLINS:
  92                 fw_name = FIRMWARE_MULLINS;
  93                 break;
  94 #endif
  95         case CHIP_TONGA:
  96                 fw_name = FIRMWARE_TONGA;
  97                 break;
  98         case CHIP_CARRIZO:
  99                 fw_name = FIRMWARE_CARRIZO;
 100                 break;
 101         case CHIP_FIJI:
 102                 fw_name = FIRMWARE_FIJI;
 103                 break;
 104         case CHIP_STONEY:
 105                 fw_name = FIRMWARE_STONEY;
 106                 break;
 107
 108         default:
 109                 return -EINVAL;
 110         }
 111
 112         r = reject_firmware(&adev->vce.fw, fw_name, adev->dev);
 113         if (r) {
 114                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 115                         fw_name);
 116                 return r;
 117         }
 118
 119         r = amdgpu_ucode_validate(adev->vce.fw);
 120         if (r) {
 121                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 122                         fw_name);
 123                 release_firmware(adev->vce.fw);
 124                 adev->vce.fw = NULL;
 125                 return r;
 126         }
 127
 128         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 129
 130         ucode_version = le32_to_cpu(hdr->ucode_version);
 131         version_major = (ucode_version >> 20) & 0xfff;
 132         version_minor = (ucode_version >> 8) & 0xfff;
 133         binary_id = ucode_version & 0xff;
 134         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 135                 version_major, version_minor, binary_id);
 136         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 137                                 (binary_id << 8));
 138
 139         /* allocate firmware, stack and heap BO */
 140
 141         r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
 142                              AMDGPU_GEM_DOMAIN_VRAM,
 143                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 144                              NULL, NULL, &adev->vce.vcpu_bo);
 145         if (r) {
 146                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 147                 return r;
 148         }
 149
 150         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 151         if (r) {
 152                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 153                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 154                 return r;
 155         }
 156
 157         r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 158                           &adev->vce.gpu_addr);
 159         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 160         if (r) {
 161                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 162                 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
 163                 return r;
 164         }
 165
 166         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 167                 atomic_set(&adev->vce.handles[i], 0);
 168                 adev->vce.filp[i] = NULL;
 169         }
 170
 171         return 0;
 172 }
 173
 174 /**
 175  * amdgpu_vce_fini - free memory
 176  *
 177  * @adev: amdgpu_device pointer
 178  *
 179  * Last step on VCE teardown, free firmware memory
 180  */
 181 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 182 {
 183         if (adev->vce.vcpu_bo == NULL)
 184                 return 0;
 185
 186         amdgpu_bo_unref(&adev->vce.vcpu_bo);
 187
 188         amdgpu_ring_fini(&adev->vce.ring[0]);
 189         amdgpu_ring_fini(&adev->vce.ring[1]);
 190
 191         release_firmware(adev->vce.fw);
 192
 193         return 0;
 194 }
 195
 196 /**
 197  * amdgpu_vce_suspend - unpin VCE fw memory
 198  *
 199  * @adev: amdgpu_device pointer
 200  *
 201  */
 202 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 203 {
 204         int i;
 205
 206         if (adev->vce.vcpu_bo == NULL)
 207                 return 0;
 208
 209         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 210                 if (atomic_read(&adev->vce.handles[i]))
 211                         break;
 212
 213         if (i == AMDGPU_MAX_VCE_HANDLES)
 214                 return 0;
 215
 216         cancel_delayed_work_sync(&adev->vce.idle_work);
 217         /* TODO: suspending running encoding sessions isn't supported */
 218         return -EINVAL;
 219 }
 220
 221 /**
 222  * amdgpu_vce_resume - pin VCE fw memory
 223  *
 224  * @adev: amdgpu_device pointer
 225  *
 226  */
 227 int amdgpu_vce_resume(struct amdgpu_device *adev)
 228 {
 229         void *cpu_addr;
 230         const struct common_firmware_header *hdr;
 231         unsigned offset;
 232         int r;
 233
 234         if (adev->vce.vcpu_bo == NULL)
 235                 return -EINVAL;
 236
 237         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 238         if (r) {
 239                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 240                 return r;
 241         }
 242
 243         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 244         if (r) {
 245                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 246                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 247                 return r;
 248         }
 249
 250         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 251         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 252         memcpy(cpu_addr, (adev->vce.fw->data) + offset,
 253                 (adev->vce.fw->size) - offset);
 254
 255         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 256
 257         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 258
 259         return 0;
 260 }
 261
 262 /**
 263  * amdgpu_vce_idle_work_handler - power off VCE
 264  *
 265  * @work: pointer to work structure
 266  *
 267  * power of VCE when it's not used any more
 268  */
 269 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 270 {
 271         struct amdgpu_device *adev =
 272                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 273
 274         if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&
 275             (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {
 276                 if (adev->pm.dpm_enabled) {
 277                         amdgpu_dpm_enable_vce(adev, false);
 278                 } else {
 279                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 280                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 281                                                             AMD_PG_STATE_GATE);
 282                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 283                                                             AMD_CG_STATE_GATE);
 284                 }
 285         } else {
 286                 schedule_delayed_work(&adev->vce.idle_work,
 287                                       msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
 288         }
 289 }
 290
 291 /**
 292  * amdgpu_vce_note_usage - power up VCE
 293  *
 294  * @adev: amdgpu_device pointer
 295  *
 296  * Make sure VCE is powerd up when we want to use it
 297  */
 298 static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
 299 {
 300         bool streams_changed = false;
 301         bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 302         set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
 303                                             msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
 304
 305         if (adev->pm.dpm_enabled) {
 306                 /* XXX figure out if the streams changed */
 307                 streams_changed = false;
 308         }
 309
 310         if (set_clocks || streams_changed) {
 311                 if (adev->pm.dpm_enabled) {
 312                         amdgpu_dpm_enable_vce(adev, true);
 313                 } else {
 314                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 315                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 316                                                             AMD_CG_STATE_UNGATE);
 317                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 318                                                             AMD_PG_STATE_UNGATE);
 319
 320                 }
 321         }
 322 }
 323
 324 /**
 325  * amdgpu_vce_free_handles - free still open VCE handles
 326  *
 327  * @adev: amdgpu_device pointer
 328  * @filp: drm file pointer
 329  *
 330  * Close all VCE handles still open by this file pointer
 331  */
 332 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 333 {
 334         struct amdgpu_ring *ring = &adev->vce.ring[0];
 335         int i, r;
 336         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 337                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 338                 if (!handle || adev->vce.filp[i] != filp)
 339                         continue;
 340
 341                 amdgpu_vce_note_usage(adev);
 342
 343                 r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);
 344                 if (r)
 345                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 346
 347                 adev->vce.filp[i] = NULL;
 348                 atomic_set(&adev->vce.handles[i], 0);
 349         }
 350 }
 351
 352 static int amdgpu_vce_free_job(
 353         struct amdgpu_job *job)
 354 {
 355         amdgpu_ib_free(job->adev, job->ibs);
 356         kfree(job->ibs);
 357         return 0;
 358 }
 359
 360 /**
 361  * amdgpu_vce_get_create_msg - generate a VCE create msg
 362  *
 363  * @adev: amdgpu_device pointer
 364  * @ring: ring we should submit the msg to
 365  * @handle: VCE session handle to use
 366  * @fence: optional fence to return
 367  *
 368  * Open up a stream for HW test
 369  */
 370 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 371                               struct fence **fence)
 372 {
 373         const unsigned ib_size_dw = 1024;
 374         struct amdgpu_ib *ib = NULL;
 375         struct fence *f = NULL;
 376         struct amdgpu_device *adev = ring->adev;
 377         uint64_t dummy;
 378         int i, r;
 379
 380         ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
 381         if (!ib)
 382                 return -ENOMEM;
 383         r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
 384         if (r) {
 385                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 386                 kfree(ib);
 387                 return r;
 388         }
 389
 390         dummy = ib->gpu_addr + 1024;
 391
 392         /* stitch together an VCE create msg */
 393         ib->length_dw = 0;
 394         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 395         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 396         ib->ptr[ib->length_dw++] = handle;
 397
 398         if ((ring->adev->vce.fw_version >> 24) >= 52)
 399                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 400         else
 401                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 402         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 403         ib->ptr[ib->length_dw++] = 0x00000000;
 404         ib->ptr[ib->length_dw++] = 0x00000042;
 405         ib->ptr[ib->length_dw++] = 0x0000000a;
 406         ib->ptr[ib->length_dw++] = 0x00000001;
 407         ib->ptr[ib->length_dw++] = 0x00000080;
 408         ib->ptr[ib->length_dw++] = 0x00000060;
 409         ib->ptr[ib->length_dw++] = 0x00000100;
 410         ib->ptr[ib->length_dw++] = 0x00000100;
 411         ib->ptr[ib->length_dw++] = 0x0000000c;
 412         ib->ptr[ib->length_dw++] = 0x00000000;
 413         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 414                 ib->ptr[ib->length_dw++] = 0x00000000;
 415                 ib->ptr[ib->length_dw++] = 0x00000000;
 416                 ib->ptr[ib->length_dw++] = 0x00000000;
 417                 ib->ptr[ib->length_dw++] = 0x00000000;
 418         }
 419
 420         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 421         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 422         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 423         ib->ptr[ib->length_dw++] = dummy;
 424         ib->ptr[ib->length_dw++] = 0x00000001;
 425
 426         for (i = ib->length_dw; i < ib_size_dw; ++i)
 427                 ib->ptr[i] = 0x0;
 428
 429         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
 430                                                  &amdgpu_vce_free_job,
 431                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 432                                                  &f);
 433         if (r)
 434                 goto err;
 435         if (fence)
 436                 *fence = fence_get(f);
 437         fence_put(f);
 438         if (amdgpu_enable_scheduler)
 439                 return 0;
 440 err:
 441         amdgpu_ib_free(adev, ib);
 442         kfree(ib);
 443         return r;
 444 }
 445
 446 /**
 447  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 448  *
 449  * @adev: amdgpu_device pointer
 450  * @ring: ring we should submit the msg to
 451  * @handle: VCE session handle to use
 452  * @fence: optional fence to return
 453  *
 454  * Close up a stream for HW test or if userspace failed to do so
 455  */
 456 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 457                                struct fence **fence)
 458 {
 459         const unsigned ib_size_dw = 1024;
 460         struct amdgpu_ib *ib = NULL;
 461         struct fence *f = NULL;
 462         struct amdgpu_device *adev = ring->adev;
 463         uint64_t dummy;
 464         int i, r;
 465
 466         ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
 467         if (!ib)
 468                 return -ENOMEM;
 469
 470         r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
 471         if (r) {
 472                 kfree(ib);
 473                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 474                 return r;
 475         }
 476
 477         dummy = ib->gpu_addr + 1024;
 478
 479         /* stitch together an VCE destroy msg */
 480         ib->length_dw = 0;
 481         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 482         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 483         ib->ptr[ib->length_dw++] = handle;
 484
 485         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 486         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 487         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 488         ib->ptr[ib->length_dw++] = dummy;
 489         ib->ptr[ib->length_dw++] = 0x00000001;
 490
 491         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 492         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 493
 494         for (i = ib->length_dw; i < ib_size_dw; ++i)
 495                 ib->ptr[i] = 0x0;
 496         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
 497                                                  &amdgpu_vce_free_job,
 498                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 499                                                  &f);
 500         if (r)
 501                 goto err;
 502         if (fence)
 503                 *fence = fence_get(f);
 504         fence_put(f);
 505         if (amdgpu_enable_scheduler)
 506                 return 0;
 507 err:
 508         amdgpu_ib_free(adev, ib);
 509         kfree(ib);
 510         return r;
 511 }
 512
 513 /**
 514  * amdgpu_vce_cs_reloc - command submission relocation
 515  *
 516  * @p: parser context
 517  * @lo: address of lower dword
 518  * @hi: address of higher dword
 519  * @size: minimum size
 520  *
 521  * Patch relocation inside command stream with real buffer address
 522  */
 523 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 524                                int lo, int hi, unsigned size, uint32_t index)
 525 {
 526         struct amdgpu_bo_va_mapping *mapping;
 527         struct amdgpu_ib *ib = &p->ibs[ib_idx];
 528         struct amdgpu_bo *bo;
 529         uint64_t addr;
 530
 531         if (index == 0xffffffff)
 532                 index = 0;
 533
 534         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 535                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 536         addr += ((uint64_t)size) * ((uint64_t)index);
 537
 538         mapping = amdgpu_cs_find_mapping(p, addr, &bo);
 539         if (mapping == NULL) {
 540                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 541                           addr, lo, hi, size, index);
 542                 return -EINVAL;
 543         }
 544
 545         if ((addr + (uint64_t)size) >
 546             ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 547                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 548                           addr, lo, hi);
 549                 return -EINVAL;
 550         }
 551
 552         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 553         addr += amdgpu_bo_gpu_offset(bo);
 554         addr -= ((uint64_t)size) * ((uint64_t)index);
 555
 556         ib->ptr[lo] = addr & 0xFFFFFFFF;
 557         ib->ptr[hi] = addr >> 32;
 558
 559         return 0;
 560 }
 561
 562 /**
 563  * amdgpu_vce_validate_handle - validate stream handle
 564  *
 565  * @p: parser context
 566  * @handle: handle to validate
 567  * @allocated: allocated a new handle?
 568  *
 569  * Validates the handle and return the found session index or -EINVAL
 570  * we we don't have another free session index.
 571  */
 572 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 573                                       uint32_t handle, bool *allocated)
 574 {
 575         unsigned i;
 576
 577         *allocated = false;
 578
 579         /* validate the handle */
 580         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 581                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 582                         if (p->adev->vce.filp[i] != p->filp) {
 583                                 DRM_ERROR("VCE handle collision detected!\n");
 584                                 return -EINVAL;
 585                         }
 586                         return i;
 587                 }
 588         }
 589
 590         /* handle not found try to alloc a new one */
 591         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 592                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 593                         p->adev->vce.filp[i] = p->filp;
 594                         p->adev->vce.img_size[i] = 0;
 595                         *allocated = true;
 596                         return i;
 597                 }
 598         }
 599
 600         DRM_ERROR("No more free VCE handles!\n");
 601         return -EINVAL;
 602 }
 603
 604 /**
 605  * amdgpu_vce_cs_parse - parse and validate the command stream
 606  *
 607  * @p: parser context
 608  *
 609  */
 610 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 611 {
 612         struct amdgpu_ib *ib = &p->ibs[ib_idx];
 613         unsigned fb_idx = 0, bs_idx = 0;
 614         int session_idx = -1;
 615         bool destroyed = false;
 616         bool created = false;
 617         bool allocated = false;
 618         uint32_t tmp, handle = 0;
 619         uint32_t *size = &tmp;
 620         int i, r = 0, idx = 0;
 621
 622         amdgpu_vce_note_usage(p->adev);
 623
 624         while (idx < ib->length_dw) {
 625                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 626                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 627
 628                 if ((len < 8) || (len & 3)) {
 629                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 630                         r = -EINVAL;
 631                         goto out;
 632                 }
 633
 634                 if (destroyed) {
 635                         DRM_ERROR("No other command allowed after destroy!\n");
 636                         r = -EINVAL;
 637                         goto out;
 638                 }
 639
 640                 switch (cmd) {
 641                 case 0x00000001: // session
 642                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 643                         session_idx = amdgpu_vce_validate_handle(p, handle,
 644                                                                  &allocated);
 645                         if (session_idx < 0)
 646                                 return session_idx;
 647                         size = &p->adev->vce.img_size[session_idx];
 648                         break;
 649
 650                 case 0x00000002: // task info
 651                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 652                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 653                         break;
 654
 655                 case 0x01000001: // create
 656                         created = true;
 657                         if (!allocated) {
 658                                 DRM_ERROR("Handle already in use!\n");
 659                                 r = -EINVAL;
 660                                 goto out;
 661                         }
 662
 663                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 664                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 665                                 8 * 3 / 2;
 666                         break;
 667
 668                 case 0x04000001: // config extension
 669                 case 0x04000002: // pic control
 670                 case 0x04000005: // rate control
 671                 case 0x04000007: // motion estimation
 672                 case 0x04000008: // rdo
 673                 case 0x04000009: // vui
 674                 case 0x05000002: // auxiliary buffer
 675                         break;
 676
 677                 case 0x03000001: // encode
 678                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 679                                                 *size, 0);
 680                         if (r)
 681                                 goto out;
 682
 683                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 684                                                 *size / 3, 0);
 685                         if (r)
 686                                 goto out;
 687                         break;
 688
 689                 case 0x02000001: // destroy
 690                         destroyed = true;
 691                         break;
 692
 693                 case 0x05000001: // context buffer
 694                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 695                                                 *size * 2, 0);
 696                         if (r)
 697                                 goto out;
 698                         break;
 699
 700                 case 0x05000004: // video bitstream buffer
 701                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 702                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 703                                                 tmp, bs_idx);
 704                         if (r)
 705                                 goto out;
 706                         break;
 707
 708                 case 0x05000005: // feedback buffer
 709                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 710                                                 4096, fb_idx);
 711                         if (r)
 712                                 goto out;
 713                         break;
 714
 715                 default:
 716                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 717                         r = -EINVAL;
 718                         goto out;
 719                 }
 720
 721                 if (session_idx == -1) {
 722                         DRM_ERROR("no session command at start of IB\n");
 723                         r = -EINVAL;
 724                         goto out;
 725                 }
 726
 727                 idx += len / 4;
 728         }
 729
 730         if (allocated && !created) {
 731                 DRM_ERROR("New session without create command!\n");
 732                 r = -ENOENT;
 733         }
 734
 735 out:
 736         if ((!r && destroyed) || (r && allocated)) {
 737                 /*
 738                  * IB contains a destroy msg or we have allocated an
 739                  * handle and got an error, anyway free the handle
 740                  */
 741                 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 742                         atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
 743         }
 744
 745         return r;
 746 }
 747
 748 /**
 749  * amdgpu_vce_ring_emit_semaphore - emit a semaphore command
 750  *
 751  * @ring: engine to use
 752  * @semaphore: address of semaphore
 753  * @emit_wait: true=emit wait, false=emit signal
 754  *
 755  */
 756 bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
 757                                     struct amdgpu_semaphore *semaphore,
 758                                     bool emit_wait)
 759 {
 760         uint64_t addr = semaphore->gpu_addr;
 761
 762         amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
 763         amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
 764         amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
 765         amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
 766         if (!emit_wait)
 767                 amdgpu_ring_write(ring, VCE_CMD_END);
 768
 769         return true;
 770 }
 771
 772 /**
 773  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 774  *
 775  * @ring: engine to use
 776  * @ib: the IB to execute
 777  *
 778  */
 779 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 780 {
 781         amdgpu_ring_write(ring, VCE_CMD_IB);
 782         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 783         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 784         amdgpu_ring_write(ring, ib->length_dw);
 785 }
 786
 787 /**
 788  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
 789  *
 790  * @ring: engine to use
 791  * @fence: the fence
 792  *
 793  */
 794 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 795                                 unsigned flags)
 796 {
 797         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 798
 799         amdgpu_ring_write(ring, VCE_CMD_FENCE);
 800         amdgpu_ring_write(ring, addr);
 801         amdgpu_ring_write(ring, upper_32_bits(addr));
 802         amdgpu_ring_write(ring, seq);
 803         amdgpu_ring_write(ring, VCE_CMD_TRAP);
 804         amdgpu_ring_write(ring, VCE_CMD_END);
 805 }
 806
 807 /**
 808  * amdgpu_vce_ring_test_ring - test if VCE ring is working
 809  *
 810  * @ring: the engine to test on
 811  *
 812  */
 813 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
 814 {
 815         struct amdgpu_device *adev = ring->adev;
 816         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 817         unsigned i;
 818         int r;
 819
 820         r = amdgpu_ring_lock(ring, 16);
 821         if (r) {
 822                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
 823                           ring->idx, r);
 824                 return r;
 825         }
 826         amdgpu_ring_write(ring, VCE_CMD_END);
 827         amdgpu_ring_unlock_commit(ring);
 828
 829         for (i = 0; i < adev->usec_timeout; i++) {
 830                 if (amdgpu_ring_get_rptr(ring) != rptr)
 831                         break;
 832                 DRM_UDELAY(1);
 833         }
 834
 835         if (i < adev->usec_timeout) {
 836                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 837                          ring->idx, i);
 838         } else {
 839                 DRM_ERROR("amdgpu: ring %d test failed\n",
 840                           ring->idx);
 841                 r = -ETIMEDOUT;
 842         }
 843
 844         return r;
 845 }
 846
 847 /**
 848  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
 849  *
 850  * @ring: the engine to test on
 851  *
 852  */
 853 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
 854 {
 855         struct fence *fence = NULL;
 856         int r;
 857
 858         /* skip vce ring1 ib test for now, since it's not reliable */
 859         if (ring == &ring->adev->vce.ring[1])
 860                 return 0;
 861
 862         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
 863         if (r) {
 864                 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
 865                 goto error;
 866         }
 867
 868         r = amdgpu_vce_get_destroy_msg(ring, 1, &fence);
 869         if (r) {
 870                 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
 871                 goto error;
 872         }
 873
 874         r = fence_wait(fence, false);
 875         if (r) {
 876                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 877         } else {
 878                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 879         }
 880 error:
 881         fence_put(fence);
 882         return r;
 883 }