drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_KABINI "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_KAVERI "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_HAWAII "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_MULLINS        "/*(DEBLOBBED)*/"
  48 #endif
  49 #define FIRMWARE_TONGA          "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_CARRIZO        "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_FIJI           "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_STONEY         "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_POLARIS10      "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_POLARIS11         "/*(DEBLOBBED)*/"
  55
  56 #ifdef CONFIG_DRM_AMDGPU_CIK
  57 /*(DEBLOBBED)*/
  58 #endif
  59 /*(DEBLOBBED)*/
  60
  61 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  62
  63 /**
  64  * amdgpu_vce_init - allocate memory, load vce firmware
  65  *
  66  * @adev: amdgpu_device pointer
  67  *
  68  * First step to get VCE online, allocate memory and load the firmware
  69  */
  70 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  71 {
  72         struct amdgpu_ring *ring;
  73         struct amd_sched_rq *rq;
  74         const char *fw_name;
  75         const struct common_firmware_header *hdr;
  76         unsigned ucode_version, version_major, version_minor, binary_id;
  77         int i, r;
  78
  79         switch (adev->asic_type) {
  80 #ifdef CONFIG_DRM_AMDGPU_CIK
  81         case CHIP_BONAIRE:
  82                 fw_name = FIRMWARE_BONAIRE;
  83                 break;
  84         case CHIP_KAVERI:
  85                 fw_name = FIRMWARE_KAVERI;
  86                 break;
  87         case CHIP_KABINI:
  88                 fw_name = FIRMWARE_KABINI;
  89                 break;
  90         case CHIP_HAWAII:
  91                 fw_name = FIRMWARE_HAWAII;
  92                 break;
  93         case CHIP_MULLINS:
  94                 fw_name = FIRMWARE_MULLINS;
  95                 break;
  96 #endif
  97         case CHIP_TONGA:
  98                 fw_name = FIRMWARE_TONGA;
  99                 break;
 100         case CHIP_CARRIZO:
 101                 fw_name = FIRMWARE_CARRIZO;
 102                 break;
 103         case CHIP_FIJI:
 104                 fw_name = FIRMWARE_FIJI;
 105                 break;
 106         case CHIP_STONEY:
 107                 fw_name = FIRMWARE_STONEY;
 108                 break;
 109         case CHIP_POLARIS10:
 110                 fw_name = FIRMWARE_POLARIS10;
 111                 break;
 112         case CHIP_POLARIS11:
 113                 fw_name = FIRMWARE_POLARIS11;
 114                 break;
 115
 116         default:
 117                 return -EINVAL;
 118         }
 119
 120         r = reject_firmware(&adev->vce.fw, fw_name, adev->dev);
 121         if (r) {
 122                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 123                         fw_name);
 124                 return r;
 125         }
 126
 127         r = amdgpu_ucode_validate(adev->vce.fw);
 128         if (r) {
 129                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 130                         fw_name);
 131                 release_firmware(adev->vce.fw);
 132                 adev->vce.fw = NULL;
 133                 return r;
 134         }
 135
 136         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 137
 138         ucode_version = le32_to_cpu(hdr->ucode_version);
 139         version_major = (ucode_version >> 20) & 0xfff;
 140         version_minor = (ucode_version >> 8) & 0xfff;
 141         binary_id = ucode_version & 0xff;
 142         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 143                 version_major, version_minor, binary_id);
 144         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 145                                 (binary_id << 8));
 146
 147         /* allocate firmware, stack and heap BO */
 148
 149         r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
 150                              AMDGPU_GEM_DOMAIN_VRAM,
 151                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 152                              NULL, NULL, &adev->vce.vcpu_bo);
 153         if (r) {
 154                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 155                 return r;
 156         }
 157
 158         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 159         if (r) {
 160                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 161                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 162                 return r;
 163         }
 164
 165         r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 166                           &adev->vce.gpu_addr);
 167         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 168         if (r) {
 169                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 170                 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
 171                 return r;
 172         }
 173
 174
 175         ring = &adev->vce.ring[0];
 176         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 177         r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
 178                                   rq, amdgpu_sched_jobs);
 179         if (r != 0) {
 180                 DRM_ERROR("Failed setting up VCE run queue.\n");
 181                 return r;
 182         }
 183
 184         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 185                 atomic_set(&adev->vce.handles[i], 0);
 186                 adev->vce.filp[i] = NULL;
 187         }
 188
 189         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 190         mutex_init(&adev->vce.idle_mutex);
 191
 192         return 0;
 193 }
 194
 195 /**
 196  * amdgpu_vce_fini - free memory
 197  *
 198  * @adev: amdgpu_device pointer
 199  *
 200  * Last step on VCE teardown, free firmware memory
 201  */
 202 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 203 {
 204         unsigned i;
 205
 206         if (adev->vce.vcpu_bo == NULL)
 207                 return 0;
 208
 209         amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
 210
 211         amdgpu_bo_unref(&adev->vce.vcpu_bo);
 212
 213         for (i = 0; i < adev->vce.num_rings; i++)
 214                 amdgpu_ring_fini(&adev->vce.ring[i]);
 215
 216         release_firmware(adev->vce.fw);
 217         mutex_destroy(&adev->vce.idle_mutex);
 218
 219         return 0;
 220 }
 221
 222 /**
 223  * amdgpu_vce_suspend - unpin VCE fw memory
 224  *
 225  * @adev: amdgpu_device pointer
 226  *
 227  */
 228 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 229 {
 230         int i;
 231
 232         if (adev->vce.vcpu_bo == NULL)
 233                 return 0;
 234
 235         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 236                 if (atomic_read(&adev->vce.handles[i]))
 237                         break;
 238
 239         if (i == AMDGPU_MAX_VCE_HANDLES)
 240                 return 0;
 241
 242         cancel_delayed_work_sync(&adev->vce.idle_work);
 243         /* TODO: suspending running encoding sessions isn't supported */
 244         return -EINVAL;
 245 }
 246
 247 /**
 248  * amdgpu_vce_resume - pin VCE fw memory
 249  *
 250  * @adev: amdgpu_device pointer
 251  *
 252  */
 253 int amdgpu_vce_resume(struct amdgpu_device *adev)
 254 {
 255         void *cpu_addr;
 256         const struct common_firmware_header *hdr;
 257         unsigned offset;
 258         int r;
 259
 260         if (adev->vce.vcpu_bo == NULL)
 261                 return -EINVAL;
 262
 263         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 264         if (r) {
 265                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 266                 return r;
 267         }
 268
 269         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 270         if (r) {
 271                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 272                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 273                 return r;
 274         }
 275
 276         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 277         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 278         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 279                     adev->vce.fw->size - offset);
 280
 281         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 282
 283         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 284
 285         return 0;
 286 }
 287
 288 /**
 289  * amdgpu_vce_idle_work_handler - power off VCE
 290  *
 291  * @work: pointer to work structure
 292  *
 293  * power of VCE when it's not used any more
 294  */
 295 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 296 {
 297         struct amdgpu_device *adev =
 298                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 299         unsigned i, count = 0;
 300
 301         for (i = 0; i < adev->vce.num_rings; i++)
 302                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 303
 304         if (count == 0) {
 305                 if (adev->pm.dpm_enabled) {
 306                         amdgpu_dpm_enable_vce(adev, false);
 307                 } else {
 308                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 309                 }
 310         } else {
 311                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 312         }
 313 }
 314
 315 /**
 316  * amdgpu_vce_ring_begin_use - power up VCE
 317  *
 318  * @ring: amdgpu ring
 319  *
 320  * Make sure VCE is powerd up when we want to use it
 321  */
 322 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 323 {
 324         struct amdgpu_device *adev = ring->adev;
 325         bool set_clocks;
 326
 327         mutex_lock(&adev->vce.idle_mutex);
 328         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 329         if (set_clocks) {
 330                 if (adev->pm.dpm_enabled) {
 331                         amdgpu_dpm_enable_vce(adev, true);
 332                 } else {
 333                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 334                 }
 335         }
 336         mutex_unlock(&adev->vce.idle_mutex);
 337 }
 338
 339 /**
 340  * amdgpu_vce_ring_end_use - power VCE down
 341  *
 342  * @ring: amdgpu ring
 343  *
 344  * Schedule work to power VCE down again
 345  */
 346 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 347 {
 348         schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 349 }
 350
 351 /**
 352  * amdgpu_vce_free_handles - free still open VCE handles
 353  *
 354  * @adev: amdgpu_device pointer
 355  * @filp: drm file pointer
 356  *
 357  * Close all VCE handles still open by this file pointer
 358  */
 359 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 360 {
 361         struct amdgpu_ring *ring = &adev->vce.ring[0];
 362         int i, r;
 363         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 364                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 365
 366                 if (!handle || adev->vce.filp[i] != filp)
 367                         continue;
 368
 369                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 370                 if (r)
 371                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 372
 373                 adev->vce.filp[i] = NULL;
 374                 atomic_set(&adev->vce.handles[i], 0);
 375         }
 376 }
 377
 378 /**
 379  * amdgpu_vce_get_create_msg - generate a VCE create msg
 380  *
 381  * @adev: amdgpu_device pointer
 382  * @ring: ring we should submit the msg to
 383  * @handle: VCE session handle to use
 384  * @fence: optional fence to return
 385  *
 386  * Open up a stream for HW test
 387  */
 388 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 389                               struct fence **fence)
 390 {
 391         const unsigned ib_size_dw = 1024;
 392         struct amdgpu_job *job;
 393         struct amdgpu_ib *ib;
 394         struct fence *f = NULL;
 395         uint64_t dummy;
 396         int i, r;
 397
 398         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 399         if (r)
 400                 return r;
 401
 402         ib = &job->ibs[0];
 403
 404         dummy = ib->gpu_addr + 1024;
 405
 406         /* stitch together an VCE create msg */
 407         ib->length_dw = 0;
 408         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 409         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 410         ib->ptr[ib->length_dw++] = handle;
 411
 412         if ((ring->adev->vce.fw_version >> 24) >= 52)
 413                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 414         else
 415                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 416         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 417         ib->ptr[ib->length_dw++] = 0x00000000;
 418         ib->ptr[ib->length_dw++] = 0x00000042;
 419         ib->ptr[ib->length_dw++] = 0x0000000a;
 420         ib->ptr[ib->length_dw++] = 0x00000001;
 421         ib->ptr[ib->length_dw++] = 0x00000080;
 422         ib->ptr[ib->length_dw++] = 0x00000060;
 423         ib->ptr[ib->length_dw++] = 0x00000100;
 424         ib->ptr[ib->length_dw++] = 0x00000100;
 425         ib->ptr[ib->length_dw++] = 0x0000000c;
 426         ib->ptr[ib->length_dw++] = 0x00000000;
 427         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 428                 ib->ptr[ib->length_dw++] = 0x00000000;
 429                 ib->ptr[ib->length_dw++] = 0x00000000;
 430                 ib->ptr[ib->length_dw++] = 0x00000000;
 431                 ib->ptr[ib->length_dw++] = 0x00000000;
 432         }
 433
 434         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 435         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 436         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 437         ib->ptr[ib->length_dw++] = dummy;
 438         ib->ptr[ib->length_dw++] = 0x00000001;
 439
 440         for (i = ib->length_dw; i < ib_size_dw; ++i)
 441                 ib->ptr[i] = 0x0;
 442
 443         r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
 444         job->fence = fence_get(f);
 445         if (r)
 446                 goto err;
 447
 448         amdgpu_job_free(job);
 449         if (fence)
 450                 *fence = fence_get(f);
 451         fence_put(f);
 452         return 0;
 453
 454 err:
 455         amdgpu_job_free(job);
 456         return r;
 457 }
 458
 459 /**
 460  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 461  *
 462  * @adev: amdgpu_device pointer
 463  * @ring: ring we should submit the msg to
 464  * @handle: VCE session handle to use
 465  * @fence: optional fence to return
 466  *
 467  * Close up a stream for HW test or if userspace failed to do so
 468  */
 469 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 470                                bool direct, struct fence **fence)
 471 {
 472         const unsigned ib_size_dw = 1024;
 473         struct amdgpu_job *job;
 474         struct amdgpu_ib *ib;
 475         struct fence *f = NULL;
 476         int i, r;
 477
 478         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 479         if (r)
 480                 return r;
 481
 482         ib = &job->ibs[0];
 483
 484         /* stitch together an VCE destroy msg */
 485         ib->length_dw = 0;
 486         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 487         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 488         ib->ptr[ib->length_dw++] = handle;
 489
 490         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 491         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 492         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 493         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 494         ib->ptr[ib->length_dw++] = 0x00000000;
 495         ib->ptr[ib->length_dw++] = 0x00000000;
 496         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 497         ib->ptr[ib->length_dw++] = 0x00000000;
 498
 499         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 500         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 501
 502         for (i = ib->length_dw; i < ib_size_dw; ++i)
 503                 ib->ptr[i] = 0x0;
 504
 505         if (direct) {
 506                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
 507                 job->fence = fence_get(f);
 508                 if (r)
 509                         goto err;
 510
 511                 amdgpu_job_free(job);
 512         } else {
 513                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 514                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 515                 if (r)
 516                         goto err;
 517         }
 518
 519         if (fence)
 520                 *fence = fence_get(f);
 521         fence_put(f);
 522         return 0;
 523
 524 err:
 525         amdgpu_job_free(job);
 526         return r;
 527 }
 528
 529 /**
 530  * amdgpu_vce_cs_reloc - command submission relocation
 531  *
 532  * @p: parser context
 533  * @lo: address of lower dword
 534  * @hi: address of higher dword
 535  * @size: minimum size
 536  *
 537  * Patch relocation inside command stream with real buffer address
 538  */
 539 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 540                                int lo, int hi, unsigned size, uint32_t index)
 541 {
 542         struct amdgpu_bo_va_mapping *mapping;
 543         struct amdgpu_bo *bo;
 544         uint64_t addr;
 545
 546         if (index == 0xffffffff)
 547                 index = 0;
 548
 549         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 550                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 551         addr += ((uint64_t)size) * ((uint64_t)index);
 552
 553         mapping = amdgpu_cs_find_mapping(p, addr, &bo);
 554         if (mapping == NULL) {
 555                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 556                           addr, lo, hi, size, index);
 557                 return -EINVAL;
 558         }
 559
 560         if ((addr + (uint64_t)size) >
 561             ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 562                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 563                           addr, lo, hi);
 564                 return -EINVAL;
 565         }
 566
 567         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 568         addr += amdgpu_bo_gpu_offset(bo);
 569         addr -= ((uint64_t)size) * ((uint64_t)index);
 570
 571         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 572         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 573
 574         return 0;
 575 }
 576
 577 /**
 578  * amdgpu_vce_validate_handle - validate stream handle
 579  *
 580  * @p: parser context
 581  * @handle: handle to validate
 582  * @allocated: allocated a new handle?
 583  *
 584  * Validates the handle and return the found session index or -EINVAL
 585  * we we don't have another free session index.
 586  */
 587 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 588                                       uint32_t handle, uint32_t *allocated)
 589 {
 590         unsigned i;
 591
 592         /* validate the handle */
 593         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 594                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 595                         if (p->adev->vce.filp[i] != p->filp) {
 596                                 DRM_ERROR("VCE handle collision detected!\n");
 597                                 return -EINVAL;
 598                         }
 599                         return i;
 600                 }
 601         }
 602
 603         /* handle not found try to alloc a new one */
 604         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 605                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 606                         p->adev->vce.filp[i] = p->filp;
 607                         p->adev->vce.img_size[i] = 0;
 608                         *allocated |= 1 << i;
 609                         return i;
 610                 }
 611         }
 612
 613         DRM_ERROR("No more free VCE handles!\n");
 614         return -EINVAL;
 615 }
 616
 617 /**
 618  * amdgpu_vce_cs_parse - parse and validate the command stream
 619  *
 620  * @p: parser context
 621  *
 622  */
 623 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 624 {
 625         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 626         unsigned fb_idx = 0, bs_idx = 0;
 627         int session_idx = -1;
 628         uint32_t destroyed = 0;
 629         uint32_t created = 0;
 630         uint32_t allocated = 0;
 631         uint32_t tmp, handle = 0;
 632         uint32_t *size = &tmp;
 633         int i, r, idx = 0;
 634
 635         r = amdgpu_cs_sysvm_access_required(p);
 636         if (r)
 637                 return r;
 638
 639         while (idx < ib->length_dw) {
 640                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 641                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 642
 643                 if ((len < 8) || (len & 3)) {
 644                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 645                         r = -EINVAL;
 646                         goto out;
 647                 }
 648
 649                 switch (cmd) {
 650                 case 0x00000001: /* session */
 651                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 652                         session_idx = amdgpu_vce_validate_handle(p, handle,
 653                                                                  &allocated);
 654                         if (session_idx < 0) {
 655                                 r = session_idx;
 656                                 goto out;
 657                         }
 658                         size = &p->adev->vce.img_size[session_idx];
 659                         break;
 660
 661                 case 0x00000002: /* task info */
 662                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 663                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 664                         break;
 665
 666                 case 0x01000001: /* create */
 667                         created |= 1 << session_idx;
 668                         if (destroyed & (1 << session_idx)) {
 669                                 destroyed &= ~(1 << session_idx);
 670                                 allocated |= 1 << session_idx;
 671
 672                         } else if (!(allocated & (1 << session_idx))) {
 673                                 DRM_ERROR("Handle already in use!\n");
 674                                 r = -EINVAL;
 675                                 goto out;
 676                         }
 677
 678                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 679                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 680                                 8 * 3 / 2;
 681                         break;
 682
 683                 case 0x04000001: /* config extension */
 684                 case 0x04000002: /* pic control */
 685                 case 0x04000005: /* rate control */
 686                 case 0x04000007: /* motion estimation */
 687                 case 0x04000008: /* rdo */
 688                 case 0x04000009: /* vui */
 689                 case 0x05000002: /* auxiliary buffer */
 690                 case 0x05000009: /* clock table */
 691                         break;
 692
 693                 case 0x0500000c: /* hw config */
 694                         switch (p->adev->asic_type) {
 695 #ifdef CONFIG_DRM_AMDGPU_CIK
 696                         case CHIP_KAVERI:
 697                         case CHIP_MULLINS:
 698 #endif
 699                         case CHIP_CARRIZO:
 700                                 break;
 701                         default:
 702                                 r = -EINVAL;
 703                                 goto out;
 704                         }
 705                         break;
 706
 707                 case 0x03000001: /* encode */
 708                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 709                                                 *size, 0);
 710                         if (r)
 711                                 goto out;
 712
 713                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 714                                                 *size / 3, 0);
 715                         if (r)
 716                                 goto out;
 717                         break;
 718
 719                 case 0x02000001: /* destroy */
 720                         destroyed |= 1 << session_idx;
 721                         break;
 722
 723                 case 0x05000001: /* context buffer */
 724                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 725                                                 *size * 2, 0);
 726                         if (r)
 727                                 goto out;
 728                         break;
 729
 730                 case 0x05000004: /* video bitstream buffer */
 731                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 732                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 733                                                 tmp, bs_idx);
 734                         if (r)
 735                                 goto out;
 736                         break;
 737
 738                 case 0x05000005: /* feedback buffer */
 739                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 740                                                 4096, fb_idx);
 741                         if (r)
 742                                 goto out;
 743                         break;
 744
 745                 default:
 746                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 747                         r = -EINVAL;
 748                         goto out;
 749                 }
 750
 751                 if (session_idx == -1) {
 752                         DRM_ERROR("no session command at start of IB\n");
 753                         r = -EINVAL;
 754                         goto out;
 755                 }
 756
 757                 idx += len / 4;
 758         }
 759
 760         if (allocated & ~created) {
 761                 DRM_ERROR("New session without create command!\n");
 762                 r = -ENOENT;
 763         }
 764
 765 out:
 766         if (!r) {
 767                 /* No error, free all destroyed handle slots */
 768                 tmp = destroyed;
 769         } else {
 770                 /* Error during parsing, free all allocated handle slots */
 771                 tmp = allocated;
 772         }
 773
 774         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 775                 if (tmp & (1 << i))
 776                         atomic_set(&p->adev->vce.handles[i], 0);
 777
 778         return r;
 779 }
 780
 781 /**
 782  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 783  *
 784  * @ring: engine to use
 785  * @ib: the IB to execute
 786  *
 787  */
 788 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
 789                              unsigned vm_id, bool ctx_switch)
 790 {
 791         amdgpu_ring_write(ring, VCE_CMD_IB);
 792         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 793         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 794         amdgpu_ring_write(ring, ib->length_dw);
 795 }
 796
 797 /**
 798  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
 799  *
 800  * @ring: engine to use
 801  * @fence: the fence
 802  *
 803  */
 804 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 805                                 unsigned flags)
 806 {
 807         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 808
 809         amdgpu_ring_write(ring, VCE_CMD_FENCE);
 810         amdgpu_ring_write(ring, addr);
 811         amdgpu_ring_write(ring, upper_32_bits(addr));
 812         amdgpu_ring_write(ring, seq);
 813         amdgpu_ring_write(ring, VCE_CMD_TRAP);
 814         amdgpu_ring_write(ring, VCE_CMD_END);
 815 }
 816
 817 unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring)
 818 {
 819         return
 820                 4; /* amdgpu_vce_ring_emit_ib */
 821 }
 822
 823 unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring)
 824 {
 825         return
 826                 6; /* amdgpu_vce_ring_emit_fence  x1 no user fence */
 827 }
 828
 829 /**
 830  * amdgpu_vce_ring_test_ring - test if VCE ring is working
 831  *
 832  * @ring: the engine to test on
 833  *
 834  */
 835 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
 836 {
 837         struct amdgpu_device *adev = ring->adev;
 838         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 839         unsigned i;
 840         int r;
 841
 842         r = amdgpu_ring_alloc(ring, 16);
 843         if (r) {
 844                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
 845                           ring->idx, r);
 846                 return r;
 847         }
 848         amdgpu_ring_write(ring, VCE_CMD_END);
 849         amdgpu_ring_commit(ring);
 850
 851         for (i = 0; i < adev->usec_timeout; i++) {
 852                 if (amdgpu_ring_get_rptr(ring) != rptr)
 853                         break;
 854                 DRM_UDELAY(1);
 855         }
 856
 857         if (i < adev->usec_timeout) {
 858                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 859                          ring->idx, i);
 860         } else {
 861                 DRM_ERROR("amdgpu: ring %d test failed\n",
 862                           ring->idx);
 863                 r = -ETIMEDOUT;
 864         }
 865
 866         return r;
 867 }
 868
 869 /**
 870  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
 871  *
 872  * @ring: the engine to test on
 873  *
 874  */
 875 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 876 {
 877         struct fence *fence = NULL;
 878         long r;
 879
 880         /* skip vce ring1/2 ib test for now, since it's not reliable */
 881         if (ring != &ring->adev->vce.ring[0])
 882                 return 0;
 883
 884         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
 885         if (r) {
 886                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 887                 goto error;
 888         }
 889
 890         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
 891         if (r) {
 892                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 893                 goto error;
 894         }
 895
 896         r = fence_wait_timeout(fence, false, timeout);
 897         if (r == 0) {
 898                 DRM_ERROR("amdgpu: IB test timed out.\n");
 899                 r = -ETIMEDOUT;
 900         } else if (r < 0) {
 901                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 902         } else {
 903                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 904                 r = 0;
 905         }
 906 error:
 907         fence_put(fence);
 908         return r;
 909 }