2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #define MAX_KIQ_REG_WAIT 100000
27 int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
32 r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
33 AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj,
34 &adev->virt.csa_vmid0_addr, &ptr);
38 memset(ptr, 0, AMDGPU_CSA_SIZE);
43 * amdgpu_map_static_csa should be called during amdgpu_vm_init
44 * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"
45 * to this VM, and each command submission of GFX should use this virtual
46 * address within META_DATA init package to support SRIOV gfx preemption.
49 int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
50 struct amdgpu_bo_va **bo_va)
52 struct ww_acquire_ctx ticket;
53 struct list_head list;
54 struct amdgpu_bo_list_entry pd;
55 struct ttm_validate_buffer csa_tv;
58 INIT_LIST_HEAD(&list);
59 INIT_LIST_HEAD(&csa_tv.head);
60 csa_tv.bo = &adev->virt.csa_obj->tbo;
63 list_add(&csa_tv.head, &list);
64 amdgpu_vm_get_pd_bo(vm, &list, &pd);
66 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
68 DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
72 *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj);
74 ttm_eu_backoff_reservation(&ticket, &list);
75 DRM_ERROR("failed to create bo_va for static CSA\n");
79 r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, AMDGPU_CSA_VADDR,
82 DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r);
83 amdgpu_vm_bo_rmv(adev, *bo_va);
84 ttm_eu_backoff_reservation(&ticket, &list);
88 r = amdgpu_vm_bo_map(adev, *bo_va, AMDGPU_CSA_VADDR, 0, AMDGPU_CSA_SIZE,
89 AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
90 AMDGPU_PTE_EXECUTABLE);
93 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
94 amdgpu_vm_bo_rmv(adev, *bo_va);
95 ttm_eu_backoff_reservation(&ticket, &list);
99 ttm_eu_backoff_reservation(&ticket, &list);
103 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
105 /* enable virtual display */
106 adev->mode_info.num_crtc = 1;
107 adev->enable_virtual_display = true;
111 mutex_init(&adev->virt.lock_reset);
114 uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
119 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
120 struct amdgpu_ring *ring = &kiq->ring;
122 BUG_ON(!ring->funcs->emit_rreg);
124 mutex_lock(&kiq->ring_mutex);
125 amdgpu_ring_alloc(ring, 32);
126 amdgpu_ring_emit_rreg(ring, reg);
127 amdgpu_fence_emit(ring, &f);
128 amdgpu_ring_commit(ring);
129 mutex_unlock(&kiq->ring_mutex);
131 r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
134 DRM_ERROR("wait for kiq fence error: %ld.\n", r);
138 val = adev->wb.wb[adev->virt.reg_val_offs];
143 void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
147 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
148 struct amdgpu_ring *ring = &kiq->ring;
150 BUG_ON(!ring->funcs->emit_wreg);
152 mutex_lock(&kiq->ring_mutex);
153 amdgpu_ring_alloc(ring, 32);
154 amdgpu_ring_emit_wreg(ring, reg, v);
155 amdgpu_fence_emit(ring, &f);
156 amdgpu_ring_commit(ring);
157 mutex_unlock(&kiq->ring_mutex);
159 r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
161 DRM_ERROR("wait for kiq fence error: %ld.\n", r);
166 * amdgpu_virt_request_full_gpu() - request full gpu access
167 * @amdgpu: amdgpu device.
168 * @init: is driver init time.
169 * When start to init/fini driver, first need to request full gpu access.
170 * Return: Zero if request success, otherwise will return error.
172 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
174 struct amdgpu_virt *virt = &adev->virt;
177 if (virt->ops && virt->ops->req_full_gpu) {
178 r = virt->ops->req_full_gpu(adev, init);
182 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
189 * amdgpu_virt_release_full_gpu() - release full gpu access
190 * @amdgpu: amdgpu device.
191 * @init: is driver init time.
192 * When finishing driver init/fini, need to release full gpu access.
193 * Return: Zero if release success, otherwise will returen error.
195 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
197 struct amdgpu_virt *virt = &adev->virt;
200 if (virt->ops && virt->ops->rel_full_gpu) {
201 r = virt->ops->rel_full_gpu(adev, init);
205 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
211 * amdgpu_virt_reset_gpu() - reset gpu
212 * @amdgpu: amdgpu device.
213 * Send reset command to GPU hypervisor to reset GPU that VM is using
214 * Return: Zero if reset success, otherwise will return error.
216 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
218 struct amdgpu_virt *virt = &adev->virt;
221 if (virt->ops && virt->ops->reset_gpu) {
222 r = virt->ops->reset_gpu(adev);
226 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
233 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
234 * @amdgpu: amdgpu device.
235 * MM table is used by UVD and VCE for its initialization
236 * Return: Zero if allocate success.
238 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
242 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
245 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
246 AMDGPU_GEM_DOMAIN_VRAM,
247 &adev->virt.mm_table.bo,
248 &adev->virt.mm_table.gpu_addr,
249 (void *)&adev->virt.mm_table.cpu_addr);
251 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
255 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
256 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
257 adev->virt.mm_table.gpu_addr,
258 adev->virt.mm_table.cpu_addr);
263 * amdgpu_virt_free_mm_table() - free mm table memory
264 * @amdgpu: amdgpu device.
265 * Free MM table memory
267 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
269 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
272 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
273 &adev->virt.mm_table.gpu_addr,
274 (void *)&adev->virt.mm_table.cpu_addr);
275 adev->virt.mm_table.gpu_addr = 0;