drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static int cik_sdma_soft_reset(void *handle);
  56
  57 /*(DEBLOBBED)*/
  58
  59 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  60
  61 /*
  62  * sDMA - System DMA
  63  * Starting with CIK, the GPU has new asynchronous
  64  * DMA engines.  These engines are used for compute
  65  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  66  * and each one supports 1 ring buffer used for gfx
  67  * and 2 queues used for compute.
  68  *
  69  * The programming model is very similar to the CP
  70  * (ring buffer, IBs, etc.), but sDMA has it's own
  71  * packet format that is different from the PM4 format
  72  * used by the CP. sDMA supports copying data, writing
  73  * embedded data, solid fills, and a number of other
  74  * things.  It also has support for tiling/detiling of
  75  * buffers.
  76  */
  77
  78 /**
  79  * cik_sdma_init_microcode - load ucode images from disk
  80  *
  81  * @adev: amdgpu_device pointer
  82  *
  83  * Use the firmware interface to load the ucode images into
  84  * the driver (not loaded into hw).
  85  * Returns 0 on success, error on failure.
  86  */
  87 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  88 {
  89         const char *chip_name;
  90         char fw_name[30];
  91         int err = 0, i;
  92
  93         DRM_DEBUG("\n");
  94
  95         switch (adev->asic_type) {
  96         case CHIP_BONAIRE:
  97                 chip_name = "bonaire";
  98                 break;
  99         case CHIP_HAWAII:
 100                 chip_name = "hawaii";
 101                 break;
 102         case CHIP_KAVERI:
 103                 chip_name = "kaveri";
 104                 break;
 105         case CHIP_KABINI:
 106                 chip_name = "kabini";
 107                 break;
 108         case CHIP_MULLINS:
 109                 chip_name = "mullins";
 110                 break;
 111         default: BUG();
 112         }
 113
 114         for (i = 0; i < adev->sdma.num_instances; i++) {
 115                 if (i == 0)
 116                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 117                 else
 118                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 119                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 120                 if (err)
 121                         goto out;
 122                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 123         }
 124 out:
 125         if (err) {
 126                 printk(KERN_ERR
 127                        "cik_sdma: Failed to load firmware \"%s\"\n",
 128                        fw_name);
 129                 for (i = 0; i < adev->sdma.num_instances; i++) {
 130                         release_firmware(adev->sdma.instance[i].fw);
 131                         adev->sdma.instance[i].fw = NULL;
 132                 }
 133         }
 134         return err;
 135 }
 136
 137 /**
 138  * cik_sdma_ring_get_rptr - get the current read pointer
 139  *
 140  * @ring: amdgpu ring pointer
 141  *
 142  * Get the current rptr from the hardware (CIK+).
 143  */
 144 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 145 {
 146         u32 rptr;
 147
 148         rptr = ring->adev->wb.wb[ring->rptr_offs];
 149
 150         return (rptr & 0x3fffc) >> 2;
 151 }
 152
 153 /**
 154  * cik_sdma_ring_get_wptr - get the current write pointer
 155  *
 156  * @ring: amdgpu ring pointer
 157  *
 158  * Get the current wptr from the hardware (CIK+).
 159  */
 160 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 161 {
 162         struct amdgpu_device *adev = ring->adev;
 163         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 164
 165         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 166 }
 167
 168 /**
 169  * cik_sdma_ring_set_wptr - commit the write pointer
 170  *
 171  * @ring: amdgpu ring pointer
 172  *
 173  * Write the wptr back to the hardware (CIK+).
 174  */
 175 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 179
 180         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 181 }
 182
 183 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 184 {
 185         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 186         int i;
 187
 188         for (i = 0; i < count; i++)
 189                 if (sdma && sdma->burst_nop && (i == 0))
 190                         amdgpu_ring_write(ring, ring->nop |
 191                                           SDMA_NOP_COUNT(count - 1));
 192                 else
 193                         amdgpu_ring_write(ring, ring->nop);
 194 }
 195
 196 /**
 197  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 198  *
 199  * @ring: amdgpu ring pointer
 200  * @ib: IB object to schedule
 201  *
 202  * Schedule an IB in the DMA ring (CIK).
 203  */
 204 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 205                            struct amdgpu_ib *ib)
 206 {
 207         u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 208         u32 next_rptr = ring->wptr + 5;
 209
 210         while ((next_rptr & 7) != 4)
 211                 next_rptr++;
 212
 213         next_rptr += 4;
 214         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 215         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
 216         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
 217         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 218         amdgpu_ring_write(ring, next_rptr);
 219
 220         /* IB packet must end on a 8 DW boundary */
 221         cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
 222
 223         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 224         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 225         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 226         amdgpu_ring_write(ring, ib->length_dw);
 227
 228 }
 229
 230 /**
 231  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 232  *
 233  * @ring: amdgpu ring pointer
 234  *
 235  * Emit an hdp flush packet on the requested DMA ring.
 236  */
 237 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 238 {
 239         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 240                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 241         u32 ref_and_mask;
 242
 243         if (ring == &ring->adev->sdma.instance[0].ring)
 244                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 245         else
 246                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 247
 248         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 249         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 250         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 251         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 252         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 253         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 254 }
 255
 256 /**
 257  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 258  *
 259  * @ring: amdgpu ring pointer
 260  * @fence: amdgpu fence object
 261  *
 262  * Add a DMA fence packet to the ring to write
 263  * the fence seq number and DMA trap packet to generate
 264  * an interrupt if needed (CIK).
 265  */
 266 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 267                                      unsigned flags)
 268 {
 269         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 270         /* write the fence */
 271         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 272         amdgpu_ring_write(ring, lower_32_bits(addr));
 273         amdgpu_ring_write(ring, upper_32_bits(addr));
 274         amdgpu_ring_write(ring, lower_32_bits(seq));
 275
 276         /* optionally write high bits as well */
 277         if (write64bit) {
 278                 addr += 4;
 279                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 280                 amdgpu_ring_write(ring, lower_32_bits(addr));
 281                 amdgpu_ring_write(ring, upper_32_bits(addr));
 282                 amdgpu_ring_write(ring, upper_32_bits(seq));
 283         }
 284
 285         /* generate an interrupt */
 286         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 287 }
 288
 289 /**
 290  * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
 291  *
 292  * @ring: amdgpu_ring structure holding ring information
 293  * @semaphore: amdgpu semaphore object
 294  * @emit_wait: wait or signal semaphore
 295  *
 296  * Add a DMA semaphore packet to the ring wait on or signal
 297  * other rings (CIK).
 298  */
 299 static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
 300                                          struct amdgpu_semaphore *semaphore,
 301                                          bool emit_wait)
 302 {
 303         u64 addr = semaphore->gpu_addr;
 304         u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
 305
 306         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
 307         amdgpu_ring_write(ring, addr & 0xfffffff8);
 308         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 309
 310         return true;
 311 }
 312
 313 /**
 314  * cik_sdma_gfx_stop - stop the gfx async dma engines
 315  *
 316  * @adev: amdgpu_device pointer
 317  *
 318  * Stop the gfx async dma ring buffers (CIK).
 319  */
 320 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 321 {
 322         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 323         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 324         u32 rb_cntl;
 325         int i;
 326
 327         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 328             (adev->mman.buffer_funcs_ring == sdma1))
 329                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 330
 331         for (i = 0; i < adev->sdma.num_instances; i++) {
 332                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 333                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 334                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 335                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 336         }
 337         sdma0->ready = false;
 338         sdma1->ready = false;
 339 }
 340
 341 /**
 342  * cik_sdma_rlc_stop - stop the compute async dma engines
 343  *
 344  * @adev: amdgpu_device pointer
 345  *
 346  * Stop the compute async dma queues (CIK).
 347  */
 348 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 349 {
 350         /* XXX todo */
 351 }
 352
 353 /**
 354  * cik_sdma_enable - stop the async dma engines
 355  *
 356  * @adev: amdgpu_device pointer
 357  * @enable: enable/disable the DMA MEs.
 358  *
 359  * Halt or unhalt the async dma engines (CIK).
 360  */
 361 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 362 {
 363         u32 me_cntl;
 364         int i;
 365
 366         if (enable == false) {
 367                 cik_sdma_gfx_stop(adev);
 368                 cik_sdma_rlc_stop(adev);
 369         }
 370
 371         for (i = 0; i < adev->sdma.num_instances; i++) {
 372                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 373                 if (enable)
 374                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 375                 else
 376                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 377                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 378         }
 379 }
 380
 381 /**
 382  * cik_sdma_gfx_resume - setup and start the async dma engines
 383  *
 384  * @adev: amdgpu_device pointer
 385  *
 386  * Set up the gfx DMA ring buffers and enable them (CIK).
 387  * Returns 0 for success, error for failure.
 388  */
 389 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 390 {
 391         struct amdgpu_ring *ring;
 392         u32 rb_cntl, ib_cntl;
 393         u32 rb_bufsz;
 394         u32 wb_offset;
 395         int i, j, r;
 396
 397         for (i = 0; i < adev->sdma.num_instances; i++) {
 398                 ring = &adev->sdma.instance[i].ring;
 399                 wb_offset = (ring->rptr_offs * 4);
 400
 401                 mutex_lock(&adev->srbm_mutex);
 402                 for (j = 0; j < 16; j++) {
 403                         cik_srbm_select(adev, 0, 0, 0, j);
 404                         /* SDMA GFX */
 405                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 406                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 407                         /* XXX SDMA RLC - todo */
 408                 }
 409                 cik_srbm_select(adev, 0, 0, 0, 0);
 410                 mutex_unlock(&adev->srbm_mutex);
 411
 412                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 413                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 414
 415                 /* Set ring buffer size in dwords */
 416                 rb_bufsz = order_base_2(ring->ring_size / 4);
 417                 rb_cntl = rb_bufsz << 1;
 418 #ifdef __BIG_ENDIAN
 419                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 420                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 421 #endif
 422                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 423
 424                 /* Initialize the ring buffer's read and write pointers */
 425                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 426                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 427
 428                 /* set the wb address whether it's enabled or not */
 429                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 430                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 431                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 432                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 433
 434                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 435
 436                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 437                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 438
 439                 ring->wptr = 0;
 440                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 441
 442                 /* enable DMA RB */
 443                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 444                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 445
 446                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 447 #ifdef __BIG_ENDIAN
 448                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 449 #endif
 450                 /* enable DMA IBs */
 451                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 452
 453                 ring->ready = true;
 454
 455                 r = amdgpu_ring_test_ring(ring);
 456                 if (r) {
 457                         ring->ready = false;
 458                         return r;
 459                 }
 460
 461                 if (adev->mman.buffer_funcs_ring == ring)
 462                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 463         }
 464
 465         return 0;
 466 }
 467
 468 /**
 469  * cik_sdma_rlc_resume - setup and start the async dma engines
 470  *
 471  * @adev: amdgpu_device pointer
 472  *
 473  * Set up the compute DMA queues and enable them (CIK).
 474  * Returns 0 for success, error for failure.
 475  */
 476 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 477 {
 478         /* XXX todo */
 479         return 0;
 480 }
 481
 482 /**
 483  * cik_sdma_load_microcode - load the sDMA ME ucode
 484  *
 485  * @adev: amdgpu_device pointer
 486  *
 487  * Loads the sDMA0/1 ucode.
 488  * Returns 0 for success, -EINVAL if the ucode is not available.
 489  */
 490 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 491 {
 492         const struct sdma_firmware_header_v1_0 *hdr;
 493         const __le32 *fw_data;
 494         u32 fw_size;
 495         int i, j;
 496
 497         /* halt the MEs */
 498         cik_sdma_enable(adev, false);
 499
 500         for (i = 0; i < adev->sdma.num_instances; i++) {
 501                 if (!adev->sdma.instance[i].fw)
 502                         return -EINVAL;
 503                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 504                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 505                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 506                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 507                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 508                 if (adev->sdma.instance[i].feature_version >= 20)
 509                         adev->sdma.instance[i].burst_nop = true;
 510                 fw_data = (const __le32 *)
 511                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 512                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 513                 for (j = 0; j < fw_size; j++)
 514                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 515                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 516         }
 517
 518         return 0;
 519 }
 520
 521 /**
 522  * cik_sdma_start - setup and start the async dma engines
 523  *
 524  * @adev: amdgpu_device pointer
 525  *
 526  * Set up the DMA engines and enable them (CIK).
 527  * Returns 0 for success, error for failure.
 528  */
 529 static int cik_sdma_start(struct amdgpu_device *adev)
 530 {
 531         int r;
 532
 533         r = cik_sdma_load_microcode(adev);
 534         if (r)
 535                 return r;
 536
 537         /* unhalt the MEs */
 538         cik_sdma_enable(adev, true);
 539
 540         /* start the gfx rings and rlc compute queues */
 541         r = cik_sdma_gfx_resume(adev);
 542         if (r)
 543                 return r;
 544         r = cik_sdma_rlc_resume(adev);
 545         if (r)
 546                 return r;
 547
 548         return 0;
 549 }
 550
 551 /**
 552  * cik_sdma_ring_test_ring - simple async dma engine test
 553  *
 554  * @ring: amdgpu_ring structure holding ring information
 555  *
 556  * Test the DMA engine by writing using it to write an
 557  * value to memory. (CIK).
 558  * Returns 0 for success, error for failure.
 559  */
 560 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 561 {
 562         struct amdgpu_device *adev = ring->adev;
 563         unsigned i;
 564         unsigned index;
 565         int r;
 566         u32 tmp;
 567         u64 gpu_addr;
 568
 569         r = amdgpu_wb_get(adev, &index);
 570         if (r) {
 571                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 572                 return r;
 573         }
 574
 575         gpu_addr = adev->wb.gpu_addr + (index * 4);
 576         tmp = 0xCAFEDEAD;
 577         adev->wb.wb[index] = cpu_to_le32(tmp);
 578
 579         r = amdgpu_ring_lock(ring, 5);
 580         if (r) {
 581                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 582                 amdgpu_wb_free(adev, index);
 583                 return r;
 584         }
 585         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 586         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 587         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 588         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 589         amdgpu_ring_write(ring, 0xDEADBEEF);
 590         amdgpu_ring_unlock_commit(ring);
 591
 592         for (i = 0; i < adev->usec_timeout; i++) {
 593                 tmp = le32_to_cpu(adev->wb.wb[index]);
 594                 if (tmp == 0xDEADBEEF)
 595                         break;
 596                 DRM_UDELAY(1);
 597         }
 598
 599         if (i < adev->usec_timeout) {
 600                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 601         } else {
 602                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 603                           ring->idx, tmp);
 604                 r = -EINVAL;
 605         }
 606         amdgpu_wb_free(adev, index);
 607
 608         return r;
 609 }
 610
 611 /**
 612  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 613  *
 614  * @ring: amdgpu_ring structure holding ring information
 615  *
 616  * Test a simple IB in the DMA ring (CIK).
 617  * Returns 0 on success, error on failure.
 618  */
 619 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 620 {
 621         struct amdgpu_device *adev = ring->adev;
 622         struct amdgpu_ib ib;
 623         struct fence *f = NULL;
 624         unsigned i;
 625         unsigned index;
 626         int r;
 627         u32 tmp = 0;
 628         u64 gpu_addr;
 629
 630         r = amdgpu_wb_get(adev, &index);
 631         if (r) {
 632                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 633                 return r;
 634         }
 635
 636         gpu_addr = adev->wb.gpu_addr + (index * 4);
 637         tmp = 0xCAFEDEAD;
 638         adev->wb.wb[index] = cpu_to_le32(tmp);
 639         memset(&ib, 0, sizeof(ib));
 640         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 641         if (r) {
 642                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 643                 goto err0;
 644         }
 645
 646         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 647         ib.ptr[1] = lower_32_bits(gpu_addr);
 648         ib.ptr[2] = upper_32_bits(gpu_addr);
 649         ib.ptr[3] = 1;
 650         ib.ptr[4] = 0xDEADBEEF;
 651         ib.length_dw = 5;
 652         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 653                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 654                                                  &f);
 655         if (r)
 656                 goto err1;
 657
 658         r = fence_wait(f, false);
 659         if (r) {
 660                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 661                 goto err1;
 662         }
 663         for (i = 0; i < adev->usec_timeout; i++) {
 664                 tmp = le32_to_cpu(adev->wb.wb[index]);
 665                 if (tmp == 0xDEADBEEF)
 666                         break;
 667                 DRM_UDELAY(1);
 668         }
 669         if (i < adev->usec_timeout) {
 670                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 671                          ring->idx, i);
 672                 goto err1;
 673         } else {
 674                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 675                 r = -EINVAL;
 676         }
 677
 678 err1:
 679         fence_put(f);
 680         amdgpu_ib_free(adev, &ib);
 681 err0:
 682         amdgpu_wb_free(adev, index);
 683         return r;
 684 }
 685
 686 /**
 687  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 688  *
 689  * @ib: indirect buffer to fill with commands
 690  * @pe: addr of the page entry
 691  * @src: src addr to copy from
 692  * @count: number of page entries to update
 693  *
 694  * Update PTEs by copying them from the GART using sDMA (CIK).
 695  */
 696 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 697                                  uint64_t pe, uint64_t src,
 698                                  unsigned count)
 699 {
 700         while (count) {
 701                 unsigned bytes = count * 8;
 702                 if (bytes > 0x1FFFF8)
 703                         bytes = 0x1FFFF8;
 704
 705                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 706                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 707                 ib->ptr[ib->length_dw++] = bytes;
 708                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 709                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 710                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 711                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 712                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 713
 714                 pe += bytes;
 715                 src += bytes;
 716                 count -= bytes / 8;
 717         }
 718 }
 719
 720 /**
 721  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 722  *
 723  * @ib: indirect buffer to fill with commands
 724  * @pe: addr of the page entry
 725  * @addr: dst addr to write into pe
 726  * @count: number of page entries to update
 727  * @incr: increase next addr by incr bytes
 728  * @flags: access flags
 729  *
 730  * Update PTEs by writing them manually using sDMA (CIK).
 731  */
 732 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
 733                                   uint64_t pe,
 734                                   uint64_t addr, unsigned count,
 735                                   uint32_t incr, uint32_t flags)
 736 {
 737         uint64_t value;
 738         unsigned ndw;
 739
 740         while (count) {
 741                 ndw = count * 2;
 742                 if (ndw > 0xFFFFE)
 743                         ndw = 0xFFFFE;
 744
 745                 /* for non-physically contiguous pages (system) */
 746                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 747                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 748                 ib->ptr[ib->length_dw++] = pe;
 749                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 750                 ib->ptr[ib->length_dw++] = ndw;
 751                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 752                         if (flags & AMDGPU_PTE_SYSTEM) {
 753                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 754                                 value &= 0xFFFFFFFFFFFFF000ULL;
 755                         } else if (flags & AMDGPU_PTE_VALID) {
 756                                 value = addr;
 757                         } else {
 758                                 value = 0;
 759                         }
 760                         addr += incr;
 761                         value |= flags;
 762                         ib->ptr[ib->length_dw++] = value;
 763                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 764                 }
 765         }
 766 }
 767
 768 /**
 769  * cik_sdma_vm_set_pages - update the page tables using sDMA
 770  *
 771  * @ib: indirect buffer to fill with commands
 772  * @pe: addr of the page entry
 773  * @addr: dst addr to write into pe
 774  * @count: number of page entries to update
 775  * @incr: increase next addr by incr bytes
 776  * @flags: access flags
 777  *
 778  * Update the page tables using sDMA (CIK).
 779  */
 780 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
 781                                     uint64_t pe,
 782                                     uint64_t addr, unsigned count,
 783                                     uint32_t incr, uint32_t flags)
 784 {
 785         uint64_t value;
 786         unsigned ndw;
 787
 788         while (count) {
 789                 ndw = count;
 790                 if (ndw > 0x7FFFF)
 791                         ndw = 0x7FFFF;
 792
 793                 if (flags & AMDGPU_PTE_VALID)
 794                         value = addr;
 795                 else
 796                         value = 0;
 797
 798                 /* for physically contiguous pages (vram) */
 799                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 800                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 801                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 802                 ib->ptr[ib->length_dw++] = flags; /* mask */
 803                 ib->ptr[ib->length_dw++] = 0;
 804                 ib->ptr[ib->length_dw++] = value; /* value */
 805                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 806                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 807                 ib->ptr[ib->length_dw++] = 0;
 808                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 809
 810                 pe += ndw * 8;
 811                 addr += ndw * incr;
 812                 count -= ndw;
 813         }
 814 }
 815
 816 /**
 817  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 818  *
 819  * @ib: indirect buffer to fill with padding
 820  *
 821  */
 822 static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
 823 {
 824         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
 825         u32 pad_count;
 826         int i;
 827
 828         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 829         for (i = 0; i < pad_count; i++)
 830                 if (sdma && sdma->burst_nop && (i == 0))
 831                         ib->ptr[ib->length_dw++] =
 832                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 833                                         SDMA_NOP_COUNT(pad_count - 1);
 834                 else
 835                         ib->ptr[ib->length_dw++] =
 836                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 837 }
 838
 839 /**
 840  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 841  *
 842  * @ring: amdgpu_ring pointer
 843  * @vm: amdgpu_vm pointer
 844  *
 845  * Update the page table base and flush the VM TLB
 846  * using sDMA (CIK).
 847  */
 848 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 849                                         unsigned vm_id, uint64_t pd_addr)
 850 {
 851         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 852                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 853
 854         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 855         if (vm_id < 8) {
 856                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 857         } else {
 858                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 859         }
 860         amdgpu_ring_write(ring, pd_addr >> 12);
 861
 862         /* flush TLB */
 863         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 864         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 865         amdgpu_ring_write(ring, 1 << vm_id);
 866
 867         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 868         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 869         amdgpu_ring_write(ring, 0);
 870         amdgpu_ring_write(ring, 0); /* reference */
 871         amdgpu_ring_write(ring, 0); /* mask */
 872         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 873 }
 874
 875 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 876                                  bool enable)
 877 {
 878         u32 orig, data;
 879
 880         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
 881                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 882                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 883         } else {
 884                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 885                 data |= 0xff000000;
 886                 if (data != orig)
 887                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 888
 889                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 890                 data |= 0xff000000;
 891                 if (data != orig)
 892                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 893         }
 894 }
 895
 896 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 897                                  bool enable)
 898 {
 899         u32 orig, data;
 900
 901         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
 902                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 903                 data |= 0x100;
 904                 if (orig != data)
 905                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 906
 907                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 908                 data |= 0x100;
 909                 if (orig != data)
 910                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 911         } else {
 912                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 913                 data &= ~0x100;
 914                 if (orig != data)
 915                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 916
 917                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 918                 data &= ~0x100;
 919                 if (orig != data)
 920                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 921         }
 922 }
 923
 924 static int cik_sdma_early_init(void *handle)
 925 {
 926         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 927
 928         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 929
 930         cik_sdma_set_ring_funcs(adev);
 931         cik_sdma_set_irq_funcs(adev);
 932         cik_sdma_set_buffer_funcs(adev);
 933         cik_sdma_set_vm_pte_funcs(adev);
 934
 935         return 0;
 936 }
 937
 938 static int cik_sdma_sw_init(void *handle)
 939 {
 940         struct amdgpu_ring *ring;
 941         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 942         int r, i;
 943
 944         r = cik_sdma_init_microcode(adev);
 945         if (r) {
 946                 DRM_ERROR("Failed to load sdma firmware!\n");
 947                 return r;
 948         }
 949
 950         /* SDMA trap event */
 951         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 952         if (r)
 953                 return r;
 954
 955         /* SDMA Privileged inst */
 956         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 957         if (r)
 958                 return r;
 959
 960         /* SDMA Privileged inst */
 961         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 962         if (r)
 963                 return r;
 964
 965         for (i = 0; i < adev->sdma.num_instances; i++) {
 966                 ring = &adev->sdma.instance[i].ring;
 967                 ring->ring_obj = NULL;
 968                 sprintf(ring->name, "sdma%d", i);
 969                 r = amdgpu_ring_init(adev, ring, 256 * 1024,
 970                                      SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 971                                      &adev->sdma.trap_irq,
 972                                      (i == 0) ?
 973                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 974                                      AMDGPU_RING_TYPE_SDMA);
 975                 if (r)
 976                         return r;
 977         }
 978
 979         return r;
 980 }
 981
 982 static int cik_sdma_sw_fini(void *handle)
 983 {
 984         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 985         int i;
 986
 987         for (i = 0; i < adev->sdma.num_instances; i++)
 988                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 989
 990         return 0;
 991 }
 992
 993 static int cik_sdma_hw_init(void *handle)
 994 {
 995         int r;
 996         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 997
 998         r = cik_sdma_start(adev);
 999         if (r)
1000                 return r;
1001
1002         return r;
1003 }
1004
1005 static int cik_sdma_hw_fini(void *handle)
1006 {
1007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008
1009         cik_sdma_enable(adev, false);
1010
1011         return 0;
1012 }
1013
1014 static int cik_sdma_suspend(void *handle)
1015 {
1016         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
1018         return cik_sdma_hw_fini(adev);
1019 }
1020
1021 static int cik_sdma_resume(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         cik_sdma_soft_reset(handle);
1026
1027         return cik_sdma_hw_init(adev);
1028 }
1029
1030 static bool cik_sdma_is_idle(void *handle)
1031 {
1032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033         u32 tmp = RREG32(mmSRBM_STATUS2);
1034
1035         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1036                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1037             return false;
1038
1039         return true;
1040 }
1041
1042 static int cik_sdma_wait_for_idle(void *handle)
1043 {
1044         unsigned i;
1045         u32 tmp;
1046         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1047
1048         for (i = 0; i < adev->usec_timeout; i++) {
1049                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1050                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1051
1052                 if (!tmp)
1053                         return 0;
1054                 udelay(1);
1055         }
1056         return -ETIMEDOUT;
1057 }
1058
1059 static void cik_sdma_print_status(void *handle)
1060 {
1061         int i, j;
1062         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1063
1064         dev_info(adev->dev, "CIK SDMA registers\n");
1065         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1066                  RREG32(mmSRBM_STATUS2));
1067         for (i = 0; i < adev->sdma.num_instances; i++) {
1068                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1069                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1070                 dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
1071                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1072                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1073                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1074                 dev_info(adev->dev, "  SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1075                          i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1076                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1077                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1078                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1079                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1080                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1081                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1082                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1083                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1084                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1085                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1086                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1087                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1088                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1089                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1090                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1091                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1092                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1093                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1094                 mutex_lock(&adev->srbm_mutex);
1095                 for (j = 0; j < 16; j++) {
1096                         cik_srbm_select(adev, 0, 0, 0, j);
1097                         dev_info(adev->dev, "  VM %d:\n", j);
1098                         dev_info(adev->dev, "  SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1099                                  RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1100                         dev_info(adev->dev, "  SDMA0_GFX_APE1_CNTL=0x%08X\n",
1101                                  RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1102                 }
1103                 cik_srbm_select(adev, 0, 0, 0, 0);
1104                 mutex_unlock(&adev->srbm_mutex);
1105         }
1106 }
1107
1108 static int cik_sdma_soft_reset(void *handle)
1109 {
1110         u32 srbm_soft_reset = 0;
1111         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1112         u32 tmp;
1113
1114         /* sdma0 */
1115         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1116         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1117         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1118         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1119
1120         /* sdma1 */
1121         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1122         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1123         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1124         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1125
1126         if (srbm_soft_reset) {
1127                 cik_sdma_print_status((void *)adev);
1128
1129                 tmp = RREG32(mmSRBM_SOFT_RESET);
1130                 tmp |= srbm_soft_reset;
1131                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1132                 WREG32(mmSRBM_SOFT_RESET, tmp);
1133                 tmp = RREG32(mmSRBM_SOFT_RESET);
1134
1135                 udelay(50);
1136
1137                 tmp &= ~srbm_soft_reset;
1138                 WREG32(mmSRBM_SOFT_RESET, tmp);
1139                 tmp = RREG32(mmSRBM_SOFT_RESET);
1140
1141                 /* Wait a little for things to settle down */
1142                 udelay(50);
1143
1144                 cik_sdma_print_status((void *)adev);
1145         }
1146
1147         return 0;
1148 }
1149
1150 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1151                                        struct amdgpu_irq_src *src,
1152                                        unsigned type,
1153                                        enum amdgpu_interrupt_state state)
1154 {
1155         u32 sdma_cntl;
1156
1157         switch (type) {
1158         case AMDGPU_SDMA_IRQ_TRAP0:
1159                 switch (state) {
1160                 case AMDGPU_IRQ_STATE_DISABLE:
1161                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1162                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1163                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1164                         break;
1165                 case AMDGPU_IRQ_STATE_ENABLE:
1166                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1167                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1168                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1169                         break;
1170                 default:
1171                         break;
1172                 }
1173                 break;
1174         case AMDGPU_SDMA_IRQ_TRAP1:
1175                 switch (state) {
1176                 case AMDGPU_IRQ_STATE_DISABLE:
1177                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1178                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1179                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1180                         break;
1181                 case AMDGPU_IRQ_STATE_ENABLE:
1182                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1183                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1184                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1185                         break;
1186                 default:
1187                         break;
1188                 }
1189                 break;
1190         default:
1191                 break;
1192         }
1193         return 0;
1194 }
1195
1196 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1197                                      struct amdgpu_irq_src *source,
1198                                      struct amdgpu_iv_entry *entry)
1199 {
1200         u8 instance_id, queue_id;
1201
1202         instance_id = (entry->ring_id & 0x3) >> 0;
1203         queue_id = (entry->ring_id & 0xc) >> 2;
1204         DRM_DEBUG("IH: SDMA trap\n");
1205         switch (instance_id) {
1206         case 0:
1207                 switch (queue_id) {
1208                 case 0:
1209                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1210                         break;
1211                 case 1:
1212                         /* XXX compute */
1213                         break;
1214                 case 2:
1215                         /* XXX compute */
1216                         break;
1217                 }
1218                 break;
1219         case 1:
1220                 switch (queue_id) {
1221                 case 0:
1222                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1223                         break;
1224                 case 1:
1225                         /* XXX compute */
1226                         break;
1227                 case 2:
1228                         /* XXX compute */
1229                         break;
1230                 }
1231                 break;
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1238                                              struct amdgpu_irq_src *source,
1239                                              struct amdgpu_iv_entry *entry)
1240 {
1241         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1242         schedule_work(&adev->reset_work);
1243         return 0;
1244 }
1245
1246 static int cik_sdma_set_clockgating_state(void *handle,
1247                                           enum amd_clockgating_state state)
1248 {
1249         bool gate = false;
1250         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1251
1252         if (state == AMD_CG_STATE_GATE)
1253                 gate = true;
1254
1255         cik_enable_sdma_mgcg(adev, gate);
1256         cik_enable_sdma_mgls(adev, gate);
1257
1258         return 0;
1259 }
1260
1261 static int cik_sdma_set_powergating_state(void *handle,
1262                                           enum amd_powergating_state state)
1263 {
1264         return 0;
1265 }
1266
1267 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1268         .early_init = cik_sdma_early_init,
1269         .late_init = NULL,
1270         .sw_init = cik_sdma_sw_init,
1271         .sw_fini = cik_sdma_sw_fini,
1272         .hw_init = cik_sdma_hw_init,
1273         .hw_fini = cik_sdma_hw_fini,
1274         .suspend = cik_sdma_suspend,
1275         .resume = cik_sdma_resume,
1276         .is_idle = cik_sdma_is_idle,
1277         .wait_for_idle = cik_sdma_wait_for_idle,
1278         .soft_reset = cik_sdma_soft_reset,
1279         .print_status = cik_sdma_print_status,
1280         .set_clockgating_state = cik_sdma_set_clockgating_state,
1281         .set_powergating_state = cik_sdma_set_powergating_state,
1282 };
1283
1284 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1285         .get_rptr = cik_sdma_ring_get_rptr,
1286         .get_wptr = cik_sdma_ring_get_wptr,
1287         .set_wptr = cik_sdma_ring_set_wptr,
1288         .parse_cs = NULL,
1289         .emit_ib = cik_sdma_ring_emit_ib,
1290         .emit_fence = cik_sdma_ring_emit_fence,
1291         .emit_semaphore = cik_sdma_ring_emit_semaphore,
1292         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1293         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1294         .test_ring = cik_sdma_ring_test_ring,
1295         .test_ib = cik_sdma_ring_test_ib,
1296         .insert_nop = cik_sdma_ring_insert_nop,
1297 };
1298
1299 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1300 {
1301         int i;
1302
1303         for (i = 0; i < adev->sdma.num_instances; i++)
1304                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1305 }
1306
1307 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1308         .set = cik_sdma_set_trap_irq_state,
1309         .process = cik_sdma_process_trap_irq,
1310 };
1311
1312 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1313         .process = cik_sdma_process_illegal_inst_irq,
1314 };
1315
1316 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1317 {
1318         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1319         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1320         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1321 }
1322
1323 /**
1324  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1325  *
1326  * @ring: amdgpu_ring structure holding ring information
1327  * @src_offset: src GPU address
1328  * @dst_offset: dst GPU address
1329  * @byte_count: number of bytes to xfer
1330  *
1331  * Copy GPU buffers using the DMA engine (CIK).
1332  * Used by the amdgpu ttm implementation to move pages if
1333  * registered as the asic copy callback.
1334  */
1335 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1336                                       uint64_t src_offset,
1337                                       uint64_t dst_offset,
1338                                       uint32_t byte_count)
1339 {
1340         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1341         ib->ptr[ib->length_dw++] = byte_count;
1342         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1343         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1344         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1345         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1346         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1347 }
1348
1349 /**
1350  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1351  *
1352  * @ring: amdgpu_ring structure holding ring information
1353  * @src_data: value to write to buffer
1354  * @dst_offset: dst GPU address
1355  * @byte_count: number of bytes to xfer
1356  *
1357  * Fill GPU buffers using the DMA engine (CIK).
1358  */
1359 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1360                                       uint32_t src_data,
1361                                       uint64_t dst_offset,
1362                                       uint32_t byte_count)
1363 {
1364         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1365         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1366         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1367         ib->ptr[ib->length_dw++] = src_data;
1368         ib->ptr[ib->length_dw++] = byte_count;
1369 }
1370
1371 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1372         .copy_max_bytes = 0x1fffff,
1373         .copy_num_dw = 7,
1374         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1375
1376         .fill_max_bytes = 0x1fffff,
1377         .fill_num_dw = 5,
1378         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1379 };
1380
1381 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1382 {
1383         if (adev->mman.buffer_funcs == NULL) {
1384                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1385                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1386         }
1387 }
1388
1389 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1390         .copy_pte = cik_sdma_vm_copy_pte,
1391         .write_pte = cik_sdma_vm_write_pte,
1392         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1393         .pad_ib = cik_sdma_vm_pad_ib,
1394 };
1395
1396 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1397 {
1398         if (adev->vm_manager.vm_pte_funcs == NULL) {
1399                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1400                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1401                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1402         }
1403 }