drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static int cik_sdma_soft_reset(void *handle);
  56
  57 /*(DEBLOBBED)*/
  58
  59 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  60
  61
  62 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  63 {
  64         int i;
  65         for (i = 0; i < adev->sdma.num_instances; i++) {
  66                         release_firmware(adev->sdma.instance[i].fw);
  67                         adev->sdma.instance[i].fw = NULL;
  68         }
  69 }
  70
  71 /*
  72  * sDMA - System DMA
  73  * Starting with CIK, the GPU has new asynchronous
  74  * DMA engines.  These engines are used for compute
  75  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  76  * and each one supports 1 ring buffer used for gfx
  77  * and 2 queues used for compute.
  78  *
  79  * The programming model is very similar to the CP
  80  * (ring buffer, IBs, etc.), but sDMA has it's own
  81  * packet format that is different from the PM4 format
  82  * used by the CP. sDMA supports copying data, writing
  83  * embedded data, solid fills, and a number of other
  84  * things.  It also has support for tiling/detiling of
  85  * buffers.
  86  */
  87
  88 /**
  89  * cik_sdma_init_microcode - load ucode images from disk
  90  *
  91  * @adev: amdgpu_device pointer
  92  *
  93  * Use the firmware interface to load the ucode images into
  94  * the driver (not loaded into hw).
  95  * Returns 0 on success, error on failure.
  96  */
  97 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  98 {
  99         const char *chip_name;
 100         char fw_name[30];
 101         int err = 0, i;
 102
 103         DRM_DEBUG("\n");
 104
 105         switch (adev->asic_type) {
 106         case CHIP_BONAIRE:
 107                 chip_name = "bonaire";
 108                 break;
 109         case CHIP_HAWAII:
 110                 chip_name = "hawaii";
 111                 break;
 112         case CHIP_KAVERI:
 113                 chip_name = "kaveri";
 114                 break;
 115         case CHIP_KABINI:
 116                 chip_name = "kabini";
 117                 break;
 118         case CHIP_MULLINS:
 119                 chip_name = "mullins";
 120                 break;
 121         default: BUG();
 122         }
 123
 124         for (i = 0; i < adev->sdma.num_instances; i++) {
 125                 if (i == 0)
 126                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 127                 else
 128                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 129                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 130                 if (err)
 131                         goto out;
 132                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 133         }
 134 out:
 135         if (err) {
 136                 printk(KERN_ERR
 137                        "cik_sdma: Failed to load firmware \"%s\"\n",
 138                        fw_name);
 139                 for (i = 0; i < adev->sdma.num_instances; i++) {
 140                         release_firmware(adev->sdma.instance[i].fw);
 141                         adev->sdma.instance[i].fw = NULL;
 142                 }
 143         }
 144         return err;
 145 }
 146
 147 /**
 148  * cik_sdma_ring_get_rptr - get the current read pointer
 149  *
 150  * @ring: amdgpu ring pointer
 151  *
 152  * Get the current rptr from the hardware (CIK+).
 153  */
 154 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 155 {
 156         u32 rptr;
 157
 158         rptr = ring->adev->wb.wb[ring->rptr_offs];
 159
 160         return (rptr & 0x3fffc) >> 2;
 161 }
 162
 163 /**
 164  * cik_sdma_ring_get_wptr - get the current write pointer
 165  *
 166  * @ring: amdgpu ring pointer
 167  *
 168  * Get the current wptr from the hardware (CIK+).
 169  */
 170 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 171 {
 172         struct amdgpu_device *adev = ring->adev;
 173         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 174
 175         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 176 }
 177
 178 /**
 179  * cik_sdma_ring_set_wptr - commit the write pointer
 180  *
 181  * @ring: amdgpu ring pointer
 182  *
 183  * Write the wptr back to the hardware (CIK+).
 184  */
 185 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 186 {
 187         struct amdgpu_device *adev = ring->adev;
 188         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 189
 190         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 191 }
 192
 193 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 194 {
 195         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 196         int i;
 197
 198         for (i = 0; i < count; i++)
 199                 if (sdma && sdma->burst_nop && (i == 0))
 200                         amdgpu_ring_write(ring, ring->nop |
 201                                           SDMA_NOP_COUNT(count - 1));
 202                 else
 203                         amdgpu_ring_write(ring, ring->nop);
 204 }
 205
 206 /**
 207  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 208  *
 209  * @ring: amdgpu ring pointer
 210  * @ib: IB object to schedule
 211  *
 212  * Schedule an IB in the DMA ring (CIK).
 213  */
 214 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 215                                   struct amdgpu_ib *ib,
 216                                   unsigned vm_id, bool ctx_switch)
 217 {
 218         u32 extra_bits = vm_id & 0xf;
 219
 220         /* IB packet must end on a 8 DW boundary */
 221         cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
 222
 223         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 224         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 225         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 226         amdgpu_ring_write(ring, ib->length_dw);
 227
 228 }
 229
 230 /**
 231  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 232  *
 233  * @ring: amdgpu ring pointer
 234  *
 235  * Emit an hdp flush packet on the requested DMA ring.
 236  */
 237 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 238 {
 239         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 240                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 241         u32 ref_and_mask;
 242
 243         if (ring == &ring->adev->sdma.instance[0].ring)
 244                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 245         else
 246                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 247
 248         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 249         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 250         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 251         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 252         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 253         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 254 }
 255
 256 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 257 {
 258         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 259         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 260         amdgpu_ring_write(ring, 1);
 261 }
 262
 263 /**
 264  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 265  *
 266  * @ring: amdgpu ring pointer
 267  * @fence: amdgpu fence object
 268  *
 269  * Add a DMA fence packet to the ring to write
 270  * the fence seq number and DMA trap packet to generate
 271  * an interrupt if needed (CIK).
 272  */
 273 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 274                                      unsigned flags)
 275 {
 276         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 277         /* write the fence */
 278         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 279         amdgpu_ring_write(ring, lower_32_bits(addr));
 280         amdgpu_ring_write(ring, upper_32_bits(addr));
 281         amdgpu_ring_write(ring, lower_32_bits(seq));
 282
 283         /* optionally write high bits as well */
 284         if (write64bit) {
 285                 addr += 4;
 286                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 287                 amdgpu_ring_write(ring, lower_32_bits(addr));
 288                 amdgpu_ring_write(ring, upper_32_bits(addr));
 289                 amdgpu_ring_write(ring, upper_32_bits(seq));
 290         }
 291
 292         /* generate an interrupt */
 293         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 294 }
 295
 296 /**
 297  * cik_sdma_gfx_stop - stop the gfx async dma engines
 298  *
 299  * @adev: amdgpu_device pointer
 300  *
 301  * Stop the gfx async dma ring buffers (CIK).
 302  */
 303 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 304 {
 305         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 306         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 307         u32 rb_cntl;
 308         int i;
 309
 310         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 311             (adev->mman.buffer_funcs_ring == sdma1))
 312                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 313
 314         for (i = 0; i < adev->sdma.num_instances; i++) {
 315                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 316                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 317                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 318                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 319         }
 320         sdma0->ready = false;
 321         sdma1->ready = false;
 322 }
 323
 324 /**
 325  * cik_sdma_rlc_stop - stop the compute async dma engines
 326  *
 327  * @adev: amdgpu_device pointer
 328  *
 329  * Stop the compute async dma queues (CIK).
 330  */
 331 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 332 {
 333         /* XXX todo */
 334 }
 335
 336 /**
 337  * cik_sdma_enable - stop the async dma engines
 338  *
 339  * @adev: amdgpu_device pointer
 340  * @enable: enable/disable the DMA MEs.
 341  *
 342  * Halt or unhalt the async dma engines (CIK).
 343  */
 344 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 345 {
 346         u32 me_cntl;
 347         int i;
 348
 349         if (!enable) {
 350                 cik_sdma_gfx_stop(adev);
 351                 cik_sdma_rlc_stop(adev);
 352         }
 353
 354         for (i = 0; i < adev->sdma.num_instances; i++) {
 355                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 356                 if (enable)
 357                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 358                 else
 359                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 360                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 361         }
 362 }
 363
 364 /**
 365  * cik_sdma_gfx_resume - setup and start the async dma engines
 366  *
 367  * @adev: amdgpu_device pointer
 368  *
 369  * Set up the gfx DMA ring buffers and enable them (CIK).
 370  * Returns 0 for success, error for failure.
 371  */
 372 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 373 {
 374         struct amdgpu_ring *ring;
 375         u32 rb_cntl, ib_cntl;
 376         u32 rb_bufsz;
 377         u32 wb_offset;
 378         int i, j, r;
 379
 380         for (i = 0; i < adev->sdma.num_instances; i++) {
 381                 ring = &adev->sdma.instance[i].ring;
 382                 wb_offset = (ring->rptr_offs * 4);
 383
 384                 mutex_lock(&adev->srbm_mutex);
 385                 for (j = 0; j < 16; j++) {
 386                         cik_srbm_select(adev, 0, 0, 0, j);
 387                         /* SDMA GFX */
 388                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 389                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 390                         /* XXX SDMA RLC - todo */
 391                 }
 392                 cik_srbm_select(adev, 0, 0, 0, 0);
 393                 mutex_unlock(&adev->srbm_mutex);
 394
 395                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 396                        adev->gfx.config.gb_addr_config & 0x70);
 397
 398                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 399                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 400
 401                 /* Set ring buffer size in dwords */
 402                 rb_bufsz = order_base_2(ring->ring_size / 4);
 403                 rb_cntl = rb_bufsz << 1;
 404 #ifdef __BIG_ENDIAN
 405                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 406                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 407 #endif
 408                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 409
 410                 /* Initialize the ring buffer's read and write pointers */
 411                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 412                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 413                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 414                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 415
 416                 /* set the wb address whether it's enabled or not */
 417                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 418                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 419                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 420                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 421
 422                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 423
 424                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 425                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 426
 427                 ring->wptr = 0;
 428                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 429
 430                 /* enable DMA RB */
 431                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 432                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 433
 434                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 435 #ifdef __BIG_ENDIAN
 436                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 437 #endif
 438                 /* enable DMA IBs */
 439                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 440
 441                 ring->ready = true;
 442         }
 443
 444         cik_sdma_enable(adev, true);
 445
 446         for (i = 0; i < adev->sdma.num_instances; i++) {
 447                 ring = &adev->sdma.instance[i].ring;
 448                 r = amdgpu_ring_test_ring(ring);
 449                 if (r) {
 450                         ring->ready = false;
 451                         return r;
 452                 }
 453
 454                 if (adev->mman.buffer_funcs_ring == ring)
 455                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 456         }
 457
 458         return 0;
 459 }
 460
 461 /**
 462  * cik_sdma_rlc_resume - setup and start the async dma engines
 463  *
 464  * @adev: amdgpu_device pointer
 465  *
 466  * Set up the compute DMA queues and enable them (CIK).
 467  * Returns 0 for success, error for failure.
 468  */
 469 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 470 {
 471         /* XXX todo */
 472         return 0;
 473 }
 474
 475 /**
 476  * cik_sdma_load_microcode - load the sDMA ME ucode
 477  *
 478  * @adev: amdgpu_device pointer
 479  *
 480  * Loads the sDMA0/1 ucode.
 481  * Returns 0 for success, -EINVAL if the ucode is not available.
 482  */
 483 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 484 {
 485         const struct sdma_firmware_header_v1_0 *hdr;
 486         const __le32 *fw_data;
 487         u32 fw_size;
 488         int i, j;
 489
 490         /* halt the MEs */
 491         cik_sdma_enable(adev, false);
 492
 493         for (i = 0; i < adev->sdma.num_instances; i++) {
 494                 if (!adev->sdma.instance[i].fw)
 495                         return -EINVAL;
 496                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 497                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 498                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 499                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 500                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 501                 if (adev->sdma.instance[i].feature_version >= 20)
 502                         adev->sdma.instance[i].burst_nop = true;
 503                 fw_data = (const __le32 *)
 504                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 505                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 506                 for (j = 0; j < fw_size; j++)
 507                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 508                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 509         }
 510
 511         return 0;
 512 }
 513
 514 /**
 515  * cik_sdma_start - setup and start the async dma engines
 516  *
 517  * @adev: amdgpu_device pointer
 518  *
 519  * Set up the DMA engines and enable them (CIK).
 520  * Returns 0 for success, error for failure.
 521  */
 522 static int cik_sdma_start(struct amdgpu_device *adev)
 523 {
 524         int r;
 525
 526         r = cik_sdma_load_microcode(adev);
 527         if (r)
 528                 return r;
 529
 530         /* halt the engine before programing */
 531         cik_sdma_enable(adev, false);
 532
 533         /* start the gfx rings and rlc compute queues */
 534         r = cik_sdma_gfx_resume(adev);
 535         if (r)
 536                 return r;
 537         r = cik_sdma_rlc_resume(adev);
 538         if (r)
 539                 return r;
 540
 541         return 0;
 542 }
 543
 544 /**
 545  * cik_sdma_ring_test_ring - simple async dma engine test
 546  *
 547  * @ring: amdgpu_ring structure holding ring information
 548  *
 549  * Test the DMA engine by writing using it to write an
 550  * value to memory. (CIK).
 551  * Returns 0 for success, error for failure.
 552  */
 553 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 554 {
 555         struct amdgpu_device *adev = ring->adev;
 556         unsigned i;
 557         unsigned index;
 558         int r;
 559         u32 tmp;
 560         u64 gpu_addr;
 561
 562         r = amdgpu_wb_get(adev, &index);
 563         if (r) {
 564                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 565                 return r;
 566         }
 567
 568         gpu_addr = adev->wb.gpu_addr + (index * 4);
 569         tmp = 0xCAFEDEAD;
 570         adev->wb.wb[index] = cpu_to_le32(tmp);
 571
 572         r = amdgpu_ring_alloc(ring, 5);
 573         if (r) {
 574                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 575                 amdgpu_wb_free(adev, index);
 576                 return r;
 577         }
 578         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 579         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 580         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 581         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 582         amdgpu_ring_write(ring, 0xDEADBEEF);
 583         amdgpu_ring_commit(ring);
 584
 585         for (i = 0; i < adev->usec_timeout; i++) {
 586                 tmp = le32_to_cpu(adev->wb.wb[index]);
 587                 if (tmp == 0xDEADBEEF)
 588                         break;
 589                 DRM_UDELAY(1);
 590         }
 591
 592         if (i < adev->usec_timeout) {
 593                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 594         } else {
 595                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 596                           ring->idx, tmp);
 597                 r = -EINVAL;
 598         }
 599         amdgpu_wb_free(adev, index);
 600
 601         return r;
 602 }
 603
 604 /**
 605  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 606  *
 607  * @ring: amdgpu_ring structure holding ring information
 608  *
 609  * Test a simple IB in the DMA ring (CIK).
 610  * Returns 0 on success, error on failure.
 611  */
 612 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 613 {
 614         struct amdgpu_device *adev = ring->adev;
 615         struct amdgpu_ib ib;
 616         struct fence *f = NULL;
 617         unsigned index;
 618         u32 tmp = 0;
 619         u64 gpu_addr;
 620         long r;
 621
 622         r = amdgpu_wb_get(adev, &index);
 623         if (r) {
 624                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 625                 return r;
 626         }
 627
 628         gpu_addr = adev->wb.gpu_addr + (index * 4);
 629         tmp = 0xCAFEDEAD;
 630         adev->wb.wb[index] = cpu_to_le32(tmp);
 631         memset(&ib, 0, sizeof(ib));
 632         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 633         if (r) {
 634                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 635                 goto err0;
 636         }
 637
 638         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 639                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 640         ib.ptr[1] = lower_32_bits(gpu_addr);
 641         ib.ptr[2] = upper_32_bits(gpu_addr);
 642         ib.ptr[3] = 1;
 643         ib.ptr[4] = 0xDEADBEEF;
 644         ib.length_dw = 5;
 645         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 646         if (r)
 647                 goto err1;
 648
 649         r = fence_wait_timeout(f, false, timeout);
 650         if (r == 0) {
 651                 DRM_ERROR("amdgpu: IB test timed out\n");
 652                 r = -ETIMEDOUT;
 653                 goto err1;
 654         } else if (r < 0) {
 655                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 656                 goto err1;
 657         }
 658         tmp = le32_to_cpu(adev->wb.wb[index]);
 659         if (tmp == 0xDEADBEEF) {
 660                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 661                 r = 0;
 662         } else {
 663                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 664                 r = -EINVAL;
 665         }
 666
 667 err1:
 668         amdgpu_ib_free(adev, &ib, NULL);
 669         fence_put(f);
 670 err0:
 671         amdgpu_wb_free(adev, index);
 672         return r;
 673 }
 674
 675 /**
 676  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 677  *
 678  * @ib: indirect buffer to fill with commands
 679  * @pe: addr of the page entry
 680  * @src: src addr to copy from
 681  * @count: number of page entries to update
 682  *
 683  * Update PTEs by copying them from the GART using sDMA (CIK).
 684  */
 685 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 686                                  uint64_t pe, uint64_t src,
 687                                  unsigned count)
 688 {
 689         unsigned bytes = count * 8;
 690
 691         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 692                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 693         ib->ptr[ib->length_dw++] = bytes;
 694         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 695         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 696         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 697         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 698         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 699 }
 700
 701 /**
 702  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 703  *
 704  * @ib: indirect buffer to fill with commands
 705  * @pe: addr of the page entry
 706  * @value: dst addr to write into pe
 707  * @count: number of page entries to update
 708  * @incr: increase next addr by incr bytes
 709  *
 710  * Update PTEs by writing them manually using sDMA (CIK).
 711  */
 712 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 713                                   uint64_t value, unsigned count,
 714                                   uint32_t incr)
 715 {
 716         unsigned ndw = count * 2;
 717
 718         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 719                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 720         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 721         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 722         ib->ptr[ib->length_dw++] = ndw;
 723         for (; ndw > 0; ndw -= 2) {
 724                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 725                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 726                 value += incr;
 727         }
 728 }
 729
 730 /**
 731  * cik_sdma_vm_set_pages - update the page tables using sDMA
 732  *
 733  * @ib: indirect buffer to fill with commands
 734  * @pe: addr of the page entry
 735  * @addr: dst addr to write into pe
 736  * @count: number of page entries to update
 737  * @incr: increase next addr by incr bytes
 738  * @flags: access flags
 739  *
 740  * Update the page tables using sDMA (CIK).
 741  */
 742 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 743                                     uint64_t addr, unsigned count,
 744                                     uint32_t incr, uint32_t flags)
 745 {
 746         /* for physically contiguous pages (vram) */
 747         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 748         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 749         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 750         ib->ptr[ib->length_dw++] = flags; /* mask */
 751         ib->ptr[ib->length_dw++] = 0;
 752         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 753         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 754         ib->ptr[ib->length_dw++] = incr; /* increment size */
 755         ib->ptr[ib->length_dw++] = 0;
 756         ib->ptr[ib->length_dw++] = count; /* number of entries */
 757 }
 758
 759 /**
 760  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 761  *
 762  * @ib: indirect buffer to fill with padding
 763  *
 764  */
 765 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 766 {
 767         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 768         u32 pad_count;
 769         int i;
 770
 771         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 772         for (i = 0; i < pad_count; i++)
 773                 if (sdma && sdma->burst_nop && (i == 0))
 774                         ib->ptr[ib->length_dw++] =
 775                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 776                                         SDMA_NOP_COUNT(pad_count - 1);
 777                 else
 778                         ib->ptr[ib->length_dw++] =
 779                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 780 }
 781
 782 /**
 783  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 784  *
 785  * @ring: amdgpu_ring pointer
 786  *
 787  * Make sure all previous operations are completed (CIK).
 788  */
 789 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 790 {
 791         uint32_t seq = ring->fence_drv.sync_seq;
 792         uint64_t addr = ring->fence_drv.gpu_addr;
 793
 794         /* wait for idle */
 795         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 796                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 797                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 798                                             SDMA_POLL_REG_MEM_EXTRA_M));
 799         amdgpu_ring_write(ring, addr & 0xfffffffc);
 800         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 801         amdgpu_ring_write(ring, seq); /* reference */
 802         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 803         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 804 }
 805
 806 /**
 807  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 808  *
 809  * @ring: amdgpu_ring pointer
 810  * @vm: amdgpu_vm pointer
 811  *
 812  * Update the page table base and flush the VM TLB
 813  * using sDMA (CIK).
 814  */
 815 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 816                                         unsigned vm_id, uint64_t pd_addr)
 817 {
 818         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 819                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 820
 821         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 822         if (vm_id < 8) {
 823                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 824         } else {
 825                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 826         }
 827         amdgpu_ring_write(ring, pd_addr >> 12);
 828
 829         /* flush TLB */
 830         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 831         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 832         amdgpu_ring_write(ring, 1 << vm_id);
 833
 834         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 835         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 836         amdgpu_ring_write(ring, 0);
 837         amdgpu_ring_write(ring, 0); /* reference */
 838         amdgpu_ring_write(ring, 0); /* mask */
 839         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 840 }
 841
 842 static unsigned cik_sdma_ring_get_emit_ib_size(struct amdgpu_ring *ring)
 843 {
 844         return
 845                 7 + 4; /* cik_sdma_ring_emit_ib */
 846 }
 847
 848 static unsigned cik_sdma_ring_get_dma_frame_size(struct amdgpu_ring *ring)
 849 {
 850         return
 851                 6 + /* cik_sdma_ring_emit_hdp_flush */
 852                 3 + /* cik_sdma_ring_emit_hdp_invalidate */
 853                 6 + /* cik_sdma_ring_emit_pipeline_sync */
 854                 12 + /* cik_sdma_ring_emit_vm_flush */
 855                 9 + 9 + 9; /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
 856 }
 857
 858 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 859                                  bool enable)
 860 {
 861         u32 orig, data;
 862
 863         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 864                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 865                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 866         } else {
 867                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 868                 data |= 0xff000000;
 869                 if (data != orig)
 870                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 871
 872                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 873                 data |= 0xff000000;
 874                 if (data != orig)
 875                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 876         }
 877 }
 878
 879 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 880                                  bool enable)
 881 {
 882         u32 orig, data;
 883
 884         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 885                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 886                 data |= 0x100;
 887                 if (orig != data)
 888                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 889
 890                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 891                 data |= 0x100;
 892                 if (orig != data)
 893                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 894         } else {
 895                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 896                 data &= ~0x100;
 897                 if (orig != data)
 898                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 899
 900                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 901                 data &= ~0x100;
 902                 if (orig != data)
 903                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 904         }
 905 }
 906
 907 static int cik_sdma_early_init(void *handle)
 908 {
 909         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 910
 911         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 912
 913         cik_sdma_set_ring_funcs(adev);
 914         cik_sdma_set_irq_funcs(adev);
 915         cik_sdma_set_buffer_funcs(adev);
 916         cik_sdma_set_vm_pte_funcs(adev);
 917
 918         return 0;
 919 }
 920
 921 static int cik_sdma_sw_init(void *handle)
 922 {
 923         struct amdgpu_ring *ring;
 924         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 925         int r, i;
 926
 927         r = cik_sdma_init_microcode(adev);
 928         if (r) {
 929                 DRM_ERROR("Failed to load sdma firmware!\n");
 930                 return r;
 931         }
 932
 933         /* SDMA trap event */
 934         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 935         if (r)
 936                 return r;
 937
 938         /* SDMA Privileged inst */
 939         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 940         if (r)
 941                 return r;
 942
 943         /* SDMA Privileged inst */
 944         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 945         if (r)
 946                 return r;
 947
 948         for (i = 0; i < adev->sdma.num_instances; i++) {
 949                 ring = &adev->sdma.instance[i].ring;
 950                 ring->ring_obj = NULL;
 951                 sprintf(ring->name, "sdma%d", i);
 952                 r = amdgpu_ring_init(adev, ring, 1024,
 953                                      SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 954                                      &adev->sdma.trap_irq,
 955                                      (i == 0) ?
 956                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 957                                      AMDGPU_RING_TYPE_SDMA);
 958                 if (r)
 959                         return r;
 960         }
 961
 962         return r;
 963 }
 964
 965 static int cik_sdma_sw_fini(void *handle)
 966 {
 967         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 968         int i;
 969
 970         for (i = 0; i < adev->sdma.num_instances; i++)
 971                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 972
 973         cik_sdma_free_microcode(adev);
 974         return 0;
 975 }
 976
 977 static int cik_sdma_hw_init(void *handle)
 978 {
 979         int r;
 980         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 981
 982         r = cik_sdma_start(adev);
 983         if (r)
 984                 return r;
 985
 986         return r;
 987 }
 988
 989 static int cik_sdma_hw_fini(void *handle)
 990 {
 991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 992
 993         cik_sdma_enable(adev, false);
 994
 995         return 0;
 996 }
 997
 998 static int cik_sdma_suspend(void *handle)
 999 {
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         return cik_sdma_hw_fini(adev);
1003 }
1004
1005 static int cik_sdma_resume(void *handle)
1006 {
1007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008
1009         cik_sdma_soft_reset(handle);
1010
1011         return cik_sdma_hw_init(adev);
1012 }
1013
1014 static bool cik_sdma_is_idle(void *handle)
1015 {
1016         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017         u32 tmp = RREG32(mmSRBM_STATUS2);
1018
1019         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1020                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1021             return false;
1022
1023         return true;
1024 }
1025
1026 static int cik_sdma_wait_for_idle(void *handle)
1027 {
1028         unsigned i;
1029         u32 tmp;
1030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031
1032         for (i = 0; i < adev->usec_timeout; i++) {
1033                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1034                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1035
1036                 if (!tmp)
1037                         return 0;
1038                 udelay(1);
1039         }
1040         return -ETIMEDOUT;
1041 }
1042
1043 static int cik_sdma_soft_reset(void *handle)
1044 {
1045         u32 srbm_soft_reset = 0;
1046         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1047         u32 tmp = RREG32(mmSRBM_STATUS2);
1048
1049         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1050                 /* sdma0 */
1051                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1052                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1053                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1054                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1055         }
1056         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1057                 /* sdma1 */
1058                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1059                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1060                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1061                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1062         }
1063
1064         if (srbm_soft_reset) {
1065                 tmp = RREG32(mmSRBM_SOFT_RESET);
1066                 tmp |= srbm_soft_reset;
1067                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1068                 WREG32(mmSRBM_SOFT_RESET, tmp);
1069                 tmp = RREG32(mmSRBM_SOFT_RESET);
1070
1071                 udelay(50);
1072
1073                 tmp &= ~srbm_soft_reset;
1074                 WREG32(mmSRBM_SOFT_RESET, tmp);
1075                 tmp = RREG32(mmSRBM_SOFT_RESET);
1076
1077                 /* Wait a little for things to settle down */
1078                 udelay(50);
1079         }
1080
1081         return 0;
1082 }
1083
1084 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1085                                        struct amdgpu_irq_src *src,
1086                                        unsigned type,
1087                                        enum amdgpu_interrupt_state state)
1088 {
1089         u32 sdma_cntl;
1090
1091         switch (type) {
1092         case AMDGPU_SDMA_IRQ_TRAP0:
1093                 switch (state) {
1094                 case AMDGPU_IRQ_STATE_DISABLE:
1095                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1096                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1097                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1098                         break;
1099                 case AMDGPU_IRQ_STATE_ENABLE:
1100                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1101                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1102                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1103                         break;
1104                 default:
1105                         break;
1106                 }
1107                 break;
1108         case AMDGPU_SDMA_IRQ_TRAP1:
1109                 switch (state) {
1110                 case AMDGPU_IRQ_STATE_DISABLE:
1111                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1112                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1113                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1114                         break;
1115                 case AMDGPU_IRQ_STATE_ENABLE:
1116                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1117                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1118                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1119                         break;
1120                 default:
1121                         break;
1122                 }
1123                 break;
1124         default:
1125                 break;
1126         }
1127         return 0;
1128 }
1129
1130 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1131                                      struct amdgpu_irq_src *source,
1132                                      struct amdgpu_iv_entry *entry)
1133 {
1134         u8 instance_id, queue_id;
1135
1136         instance_id = (entry->ring_id & 0x3) >> 0;
1137         queue_id = (entry->ring_id & 0xc) >> 2;
1138         DRM_DEBUG("IH: SDMA trap\n");
1139         switch (instance_id) {
1140         case 0:
1141                 switch (queue_id) {
1142                 case 0:
1143                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1144                         break;
1145                 case 1:
1146                         /* XXX compute */
1147                         break;
1148                 case 2:
1149                         /* XXX compute */
1150                         break;
1151                 }
1152                 break;
1153         case 1:
1154                 switch (queue_id) {
1155                 case 0:
1156                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1157                         break;
1158                 case 1:
1159                         /* XXX compute */
1160                         break;
1161                 case 2:
1162                         /* XXX compute */
1163                         break;
1164                 }
1165                 break;
1166         }
1167
1168         return 0;
1169 }
1170
1171 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1172                                              struct amdgpu_irq_src *source,
1173                                              struct amdgpu_iv_entry *entry)
1174 {
1175         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1176         schedule_work(&adev->reset_work);
1177         return 0;
1178 }
1179
1180 static int cik_sdma_set_clockgating_state(void *handle,
1181                                           enum amd_clockgating_state state)
1182 {
1183         bool gate = false;
1184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186         if (state == AMD_CG_STATE_GATE)
1187                 gate = true;
1188
1189         cik_enable_sdma_mgcg(adev, gate);
1190         cik_enable_sdma_mgls(adev, gate);
1191
1192         return 0;
1193 }
1194
1195 static int cik_sdma_set_powergating_state(void *handle,
1196                                           enum amd_powergating_state state)
1197 {
1198         return 0;
1199 }
1200
1201 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1202         .name = "cik_sdma",
1203         .early_init = cik_sdma_early_init,
1204         .late_init = NULL,
1205         .sw_init = cik_sdma_sw_init,
1206         .sw_fini = cik_sdma_sw_fini,
1207         .hw_init = cik_sdma_hw_init,
1208         .hw_fini = cik_sdma_hw_fini,
1209         .suspend = cik_sdma_suspend,
1210         .resume = cik_sdma_resume,
1211         .is_idle = cik_sdma_is_idle,
1212         .wait_for_idle = cik_sdma_wait_for_idle,
1213         .soft_reset = cik_sdma_soft_reset,
1214         .set_clockgating_state = cik_sdma_set_clockgating_state,
1215         .set_powergating_state = cik_sdma_set_powergating_state,
1216 };
1217
1218 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1219         .get_rptr = cik_sdma_ring_get_rptr,
1220         .get_wptr = cik_sdma_ring_get_wptr,
1221         .set_wptr = cik_sdma_ring_set_wptr,
1222         .parse_cs = NULL,
1223         .emit_ib = cik_sdma_ring_emit_ib,
1224         .emit_fence = cik_sdma_ring_emit_fence,
1225         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1226         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1227         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1228         .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
1229         .test_ring = cik_sdma_ring_test_ring,
1230         .test_ib = cik_sdma_ring_test_ib,
1231         .insert_nop = cik_sdma_ring_insert_nop,
1232         .pad_ib = cik_sdma_ring_pad_ib,
1233         .get_emit_ib_size = cik_sdma_ring_get_emit_ib_size,
1234         .get_dma_frame_size = cik_sdma_ring_get_dma_frame_size,
1235 };
1236
1237 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1238 {
1239         int i;
1240
1241         for (i = 0; i < adev->sdma.num_instances; i++)
1242                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1243 }
1244
1245 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1246         .set = cik_sdma_set_trap_irq_state,
1247         .process = cik_sdma_process_trap_irq,
1248 };
1249
1250 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1251         .process = cik_sdma_process_illegal_inst_irq,
1252 };
1253
1254 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1255 {
1256         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1257         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1258         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1259 }
1260
1261 /**
1262  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1263  *
1264  * @ring: amdgpu_ring structure holding ring information
1265  * @src_offset: src GPU address
1266  * @dst_offset: dst GPU address
1267  * @byte_count: number of bytes to xfer
1268  *
1269  * Copy GPU buffers using the DMA engine (CIK).
1270  * Used by the amdgpu ttm implementation to move pages if
1271  * registered as the asic copy callback.
1272  */
1273 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1274                                       uint64_t src_offset,
1275                                       uint64_t dst_offset,
1276                                       uint32_t byte_count)
1277 {
1278         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1279         ib->ptr[ib->length_dw++] = byte_count;
1280         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1281         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1282         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1283         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1284         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1285 }
1286
1287 /**
1288  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1289  *
1290  * @ring: amdgpu_ring structure holding ring information
1291  * @src_data: value to write to buffer
1292  * @dst_offset: dst GPU address
1293  * @byte_count: number of bytes to xfer
1294  *
1295  * Fill GPU buffers using the DMA engine (CIK).
1296  */
1297 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1298                                       uint32_t src_data,
1299                                       uint64_t dst_offset,
1300                                       uint32_t byte_count)
1301 {
1302         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1303         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1304         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1305         ib->ptr[ib->length_dw++] = src_data;
1306         ib->ptr[ib->length_dw++] = byte_count;
1307 }
1308
1309 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1310         .copy_max_bytes = 0x1fffff,
1311         .copy_num_dw = 7,
1312         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1313
1314         .fill_max_bytes = 0x1fffff,
1315         .fill_num_dw = 5,
1316         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1317 };
1318
1319 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1320 {
1321         if (adev->mman.buffer_funcs == NULL) {
1322                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1323                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1324         }
1325 }
1326
1327 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1328         .copy_pte = cik_sdma_vm_copy_pte,
1329         .write_pte = cik_sdma_vm_write_pte,
1330         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1331 };
1332
1333 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1334 {
1335         unsigned i;
1336
1337         if (adev->vm_manager.vm_pte_funcs == NULL) {
1338                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1339                 for (i = 0; i < adev->sdma.num_instances; i++)
1340                         adev->vm_manager.vm_pte_rings[i] =
1341                                 &adev->sdma.instance[i].ring;
1342
1343                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1344         }
1345 }