drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_8_0_d.h"
  36 #include "dce/dce_8_0_sh_mask.h"
  37
  38 #include "gca/gfx_7_2_enum.h"
  39
  40 #include "gmc/gmc_7_1_d.h"
  41 #include "gmc/gmc_7_1_sh_mask.h"
  42
  43 #include "oss/oss_2_0_d.h"
  44 #include "oss/oss_2_0_sh_mask.h"
  45
  46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
  47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  48
  49 static const u32 crtc_offsets[6] =
  50 {
  51         CRTC0_REGISTER_OFFSET,
  52         CRTC1_REGISTER_OFFSET,
  53         CRTC2_REGISTER_OFFSET,
  54         CRTC3_REGISTER_OFFSET,
  55         CRTC4_REGISTER_OFFSET,
  56         CRTC5_REGISTER_OFFSET
  57 };
  58
  59 static const uint32_t dig_offsets[] = {
  60         CRTC0_REGISTER_OFFSET,
  61         CRTC1_REGISTER_OFFSET,
  62         CRTC2_REGISTER_OFFSET,
  63         CRTC3_REGISTER_OFFSET,
  64         CRTC4_REGISTER_OFFSET,
  65         CRTC5_REGISTER_OFFSET,
  66         (0x13830 - 0x7030) >> 2,
  67 };
  68
  69 static const struct {
  70         uint32_t        reg;
  71         uint32_t        vblank;
  72         uint32_t        vline;
  73         uint32_t        hpd;
  74
  75 } interrupt_status_offsets[6] = { {
  76         .reg = mmDISP_INTERRUPT_STATUS,
  77         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  78         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  79         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  80 }, {
  81         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  82         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  83         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  84         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  85 }, {
  86         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  87         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 105 } };
 106
 107 static const uint32_t hpd_int_control_offsets[6] = {
 108         mmDC_HPD1_INT_CONTROL,
 109         mmDC_HPD2_INT_CONTROL,
 110         mmDC_HPD3_INT_CONTROL,
 111         mmDC_HPD4_INT_CONTROL,
 112         mmDC_HPD5_INT_CONTROL,
 113         mmDC_HPD6_INT_CONTROL,
 114 };
 115
 116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
 117                                      u32 block_offset, u32 reg)
 118 {
 119         unsigned long flags;
 120         u32 r;
 121
 122         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 123         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 124         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 125         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 126
 127         return r;
 128 }
 129
 130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
 131                                       u32 block_offset, u32 reg, u32 v)
 132 {
 133         unsigned long flags;
 134
 135         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 136         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 137         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 138         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 139 }
 140
 141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 142 {
 143         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 144                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 145                 return true;
 146         else
 147                 return false;
 148 }
 149
 150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 151 {
 152         u32 pos1, pos2;
 153
 154         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 155         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 156
 157         if (pos1 != pos2)
 158                 return true;
 159         else
 160                 return false;
 161 }
 162
 163 /**
 164  * dce_v8_0_vblank_wait - vblank wait asic callback.
 165  *
 166  * @adev: amdgpu_device pointer
 167  * @crtc: crtc to wait for vblank on
 168  *
 169  * Wait for vblank on the requested crtc (evergreen+).
 170  */
 171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 172 {
 173         unsigned i = 100;
 174
 175         if (crtc >= adev->mode_info.num_crtc)
 176                 return;
 177
 178         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 179                 return;
 180
 181         /* depending on when we hit vblank, we may be close to active; if so,
 182          * wait for another frame.
 183          */
 184         while (dce_v8_0_is_in_vblank(adev, crtc)) {
 185                 if (i++ == 100) {
 186                         i = 0;
 187                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 188                                 break;
 189                 }
 190         }
 191
 192         while (!dce_v8_0_is_in_vblank(adev, crtc)) {
 193                 if (i++ == 100) {
 194                         i = 0;
 195                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 196                                 break;
 197                 }
 198         }
 199 }
 200
 201 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 202 {
 203         if (crtc >= adev->mode_info.num_crtc)
 204                 return 0;
 205         else
 206                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 207 }
 208
 209 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 210 {
 211         unsigned i;
 212
 213         /* Enable pflip interrupts */
 214         for (i = 0; i < adev->mode_info.num_crtc; i++)
 215                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 216 }
 217
 218 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 219 {
 220         unsigned i;
 221
 222         /* Disable pflip interrupts */
 223         for (i = 0; i < adev->mode_info.num_crtc; i++)
 224                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 225 }
 226
 227 /**
 228  * dce_v8_0_page_flip - pageflip callback.
 229  *
 230  * @adev: amdgpu_device pointer
 231  * @crtc_id: crtc to cleanup pageflip on
 232  * @crtc_base: new address of the crtc (GPU MC address)
 233  *
 234  * Triggers the actual pageflip by updating the primary
 235  * surface base address.
 236  */
 237 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
 238                                int crtc_id, u64 crtc_base, bool async)
 239 {
 240         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 241
 242         /* flip at hsync for async, default is vsync */
 243         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 244                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 245         /* update the primary scanout addresses */
 246         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 247                upper_32_bits(crtc_base));
 248         /* writing to the low address triggers the update */
 249         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 250                lower_32_bits(crtc_base));
 251         /* post the write */
 252         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 253 }
 254
 255 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 256                                         u32 *vbl, u32 *position)
 257 {
 258         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 259                 return -EINVAL;
 260
 261         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 262         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 263
 264         return 0;
 265 }
 266
 267 /**
 268  * dce_v8_0_hpd_sense - hpd sense callback.
 269  *
 270  * @adev: amdgpu_device pointer
 271  * @hpd: hpd (hotplug detect) pin
 272  *
 273  * Checks if a digital monitor is connected (evergreen+).
 274  * Returns true if connected, false if not connected.
 275  */
 276 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
 277                                enum amdgpu_hpd_id hpd)
 278 {
 279         bool connected = false;
 280
 281         switch (hpd) {
 282         case AMDGPU_HPD_1:
 283                 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 284                         connected = true;
 285                 break;
 286         case AMDGPU_HPD_2:
 287                 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
 288                         connected = true;
 289                 break;
 290         case AMDGPU_HPD_3:
 291                 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
 292                         connected = true;
 293                 break;
 294         case AMDGPU_HPD_4:
 295                 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
 296                         connected = true;
 297                 break;
 298         case AMDGPU_HPD_5:
 299                 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
 300                         connected = true;
 301                 break;
 302         case AMDGPU_HPD_6:
 303                 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
 304                         connected = true;
 305                 break;
 306         default:
 307                 break;
 308         }
 309
 310         return connected;
 311 }
 312
 313 /**
 314  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
 315  *
 316  * @adev: amdgpu_device pointer
 317  * @hpd: hpd (hotplug detect) pin
 318  *
 319  * Set the polarity of the hpd pin (evergreen+).
 320  */
 321 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
 322                                       enum amdgpu_hpd_id hpd)
 323 {
 324         u32 tmp;
 325         bool connected = dce_v8_0_hpd_sense(adev, hpd);
 326
 327         switch (hpd) {
 328         case AMDGPU_HPD_1:
 329                 tmp = RREG32(mmDC_HPD1_INT_CONTROL);
 330                 if (connected)
 331                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 332                 else
 333                         tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 334                 WREG32(mmDC_HPD1_INT_CONTROL, tmp);
 335                 break;
 336         case AMDGPU_HPD_2:
 337                 tmp = RREG32(mmDC_HPD2_INT_CONTROL);
 338                 if (connected)
 339                         tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
 340                 else
 341                         tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
 342                 WREG32(mmDC_HPD2_INT_CONTROL, tmp);
 343                 break;
 344         case AMDGPU_HPD_3:
 345                 tmp = RREG32(mmDC_HPD3_INT_CONTROL);
 346                 if (connected)
 347                         tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
 348                 else
 349                         tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
 350                 WREG32(mmDC_HPD3_INT_CONTROL, tmp);
 351                 break;
 352         case AMDGPU_HPD_4:
 353                 tmp = RREG32(mmDC_HPD4_INT_CONTROL);
 354                 if (connected)
 355                         tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
 356                 else
 357                         tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
 358                 WREG32(mmDC_HPD4_INT_CONTROL, tmp);
 359                 break;
 360         case AMDGPU_HPD_5:
 361                 tmp = RREG32(mmDC_HPD5_INT_CONTROL);
 362                 if (connected)
 363                         tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
 364                 else
 365                         tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
 366                 WREG32(mmDC_HPD5_INT_CONTROL, tmp);
 367                         break;
 368         case AMDGPU_HPD_6:
 369                 tmp = RREG32(mmDC_HPD6_INT_CONTROL);
 370                 if (connected)
 371                         tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
 372                 else
 373                         tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
 374                 WREG32(mmDC_HPD6_INT_CONTROL, tmp);
 375                 break;
 376         default:
 377                 break;
 378         }
 379 }
 380
 381 /**
 382  * dce_v8_0_hpd_init - hpd setup callback.
 383  *
 384  * @adev: amdgpu_device pointer
 385  *
 386  * Setup the hpd pins used by the card (evergreen+).
 387  * Enable the pin, set the polarity, and enable the hpd interrupts.
 388  */
 389 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 390 {
 391         struct drm_device *dev = adev->ddev;
 392         struct drm_connector *connector;
 393         u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
 394                 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
 395                 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 396
 397         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 398                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 399
 400                 switch (amdgpu_connector->hpd.hpd) {
 401                 case AMDGPU_HPD_1:
 402                         WREG32(mmDC_HPD1_CONTROL, tmp);
 403                         break;
 404                 case AMDGPU_HPD_2:
 405                         WREG32(mmDC_HPD2_CONTROL, tmp);
 406                         break;
 407                 case AMDGPU_HPD_3:
 408                         WREG32(mmDC_HPD3_CONTROL, tmp);
 409                         break;
 410                 case AMDGPU_HPD_4:
 411                         WREG32(mmDC_HPD4_CONTROL, tmp);
 412                         break;
 413                 case AMDGPU_HPD_5:
 414                         WREG32(mmDC_HPD5_CONTROL, tmp);
 415                         break;
 416                 case AMDGPU_HPD_6:
 417                         WREG32(mmDC_HPD6_CONTROL, tmp);
 418                         break;
 419                 default:
 420                         break;
 421                 }
 422
 423                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 424                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 425                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 426                          * aux dp channel on imac and help (but not completely fix)
 427                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 428                          * also avoid interrupt storms during dpms.
 429                          */
 430                         u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
 431
 432                         switch (amdgpu_connector->hpd.hpd) {
 433                         case AMDGPU_HPD_1:
 434                                 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
 435                                 break;
 436                         case AMDGPU_HPD_2:
 437                                 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
 438                                 break;
 439                         case AMDGPU_HPD_3:
 440                                 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
 441                                 break;
 442                         case AMDGPU_HPD_4:
 443                                 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
 444                                 break;
 445                         case AMDGPU_HPD_5:
 446                                 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
 447                                 break;
 448                         case AMDGPU_HPD_6:
 449                                 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
 450                                 break;
 451                         default:
 452                                 continue;
 453                         }
 454
 455                         dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
 456                         dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 457                         WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
 458                         continue;
 459                 }
 460
 461                 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 462                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 463         }
 464 }
 465
 466 /**
 467  * dce_v8_0_hpd_fini - hpd tear down callback.
 468  *
 469  * @adev: amdgpu_device pointer
 470  *
 471  * Tear down the hpd pins used by the card (evergreen+).
 472  * Disable the hpd interrupts.
 473  */
 474 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 475 {
 476         struct drm_device *dev = adev->ddev;
 477         struct drm_connector *connector;
 478
 479         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 480                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 481
 482                 switch (amdgpu_connector->hpd.hpd) {
 483                 case AMDGPU_HPD_1:
 484                         WREG32(mmDC_HPD1_CONTROL, 0);
 485                         break;
 486                 case AMDGPU_HPD_2:
 487                         WREG32(mmDC_HPD2_CONTROL, 0);
 488                         break;
 489                 case AMDGPU_HPD_3:
 490                         WREG32(mmDC_HPD3_CONTROL, 0);
 491                         break;
 492                 case AMDGPU_HPD_4:
 493                         WREG32(mmDC_HPD4_CONTROL, 0);
 494                         break;
 495                 case AMDGPU_HPD_5:
 496                         WREG32(mmDC_HPD5_CONTROL, 0);
 497                         break;
 498                 case AMDGPU_HPD_6:
 499                         WREG32(mmDC_HPD6_CONTROL, 0);
 500                         break;
 501                 default:
 502                         break;
 503                 }
 504                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 505         }
 506 }
 507
 508 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 509 {
 510         return mmDC_GPIO_HPD_A;
 511 }
 512
 513 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
 514 {
 515         u32 crtc_hung = 0;
 516         u32 crtc_status[6];
 517         u32 i, j, tmp;
 518
 519         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 520                 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
 521                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 522                         crtc_hung |= (1 << i);
 523                 }
 524         }
 525
 526         for (j = 0; j < 10; j++) {
 527                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 528                         if (crtc_hung & (1 << i)) {
 529                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 530                                 if (tmp != crtc_status[i])
 531                                         crtc_hung &= ~(1 << i);
 532                         }
 533                 }
 534                 if (crtc_hung == 0)
 535                         return false;
 536                 udelay(100);
 537         }
 538
 539         return true;
 540 }
 541
 542 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
 543                                     struct amdgpu_mode_mc_save *save)
 544 {
 545         u32 crtc_enabled, tmp;
 546         int i;
 547
 548         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 549         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 550
 551         /* disable VGA render */
 552         tmp = RREG32(mmVGA_RENDER_CONTROL);
 553         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 554         WREG32(mmVGA_RENDER_CONTROL, tmp);
 555
 556         /* blank the display controllers */
 557         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 558                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 559                                              CRTC_CONTROL, CRTC_MASTER_EN);
 560                 if (crtc_enabled) {
 561 #if 1
 562                         save->crtc_enabled[i] = true;
 563                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 564                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 565                                 /*it is correct only for RGB ; black is 0*/
 566                                 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
 567                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 568                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 569                         }
 570                         mdelay(20);
 571 #else
 572                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 573                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 574                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 575                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 576                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 577                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 578                         save->crtc_enabled[i] = false;
 579                         /* ***** */
 580 #endif
 581                 } else {
 582                         save->crtc_enabled[i] = false;
 583                 }
 584         }
 585 }
 586
 587 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
 588                                       struct amdgpu_mode_mc_save *save)
 589 {
 590         u32 tmp;
 591         int i;
 592
 593         /* update crtc base addresses */
 594         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 595                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 596                        upper_32_bits(adev->mc.vram_start));
 597                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 598                        (u32)adev->mc.vram_start);
 599
 600                 if (save->crtc_enabled[i]) {
 601                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 602                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 603                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 604                 }
 605                 mdelay(20);
 606         }
 607
 608         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 609         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 610
 611         /* Unlock vga access */
 612         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 613         mdelay(1);
 614         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 615 }
 616
 617 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
 618                                           bool render)
 619 {
 620         u32 tmp;
 621
 622         /* Lockout access through VGA aperture*/
 623         tmp = RREG32(mmVGA_HDP_CONTROL);
 624         if (render)
 625                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 626         else
 627                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 628         WREG32(mmVGA_HDP_CONTROL, tmp);
 629
 630         /* disable VGA render */
 631         tmp = RREG32(mmVGA_RENDER_CONTROL);
 632         if (render)
 633                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 634         else
 635                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 636         WREG32(mmVGA_RENDER_CONTROL, tmp);
 637 }
 638
 639 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
 640 {
 641         int num_crtc = 0;
 642
 643         switch (adev->asic_type) {
 644         case CHIP_BONAIRE:
 645         case CHIP_HAWAII:
 646                 num_crtc = 6;
 647                 break;
 648         case CHIP_KAVERI:
 649                 num_crtc = 4;
 650                 break;
 651         case CHIP_KABINI:
 652         case CHIP_MULLINS:
 653                 num_crtc = 2;
 654                 break;
 655         default:
 656                 num_crtc = 0;
 657         }
 658         return num_crtc;
 659 }
 660
 661 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
 662 {
 663         /*Disable VGA render and enabled crtc, if has DCE engine*/
 664         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 665                 u32 tmp;
 666                 int crtc_enabled, i;
 667
 668                 dce_v8_0_set_vga_render_state(adev, false);
 669
 670                 /*Disable crtc*/
 671                 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
 672                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 673                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 674                         if (crtc_enabled) {
 675                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 676                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 677                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 678                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 679                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 680                         }
 681                 }
 682         }
 683 }
 684
 685 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
 686 {
 687         struct drm_device *dev = encoder->dev;
 688         struct amdgpu_device *adev = dev->dev_private;
 689         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 690         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 691         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 692         int bpc = 0;
 693         u32 tmp = 0;
 694         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 695
 696         if (connector) {
 697                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 698                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 699                 dither = amdgpu_connector->dither;
 700         }
 701
 702         /* LVDS/eDP FMT is set up by atom */
 703         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 704                 return;
 705
 706         /* not needed for analog */
 707         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 708             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 709                 return;
 710
 711         if (bpc == 0)
 712                 return;
 713
 714         switch (bpc) {
 715         case 6:
 716                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 717                         /* XXX sort out optimal dither settings */
 718                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 719                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 720                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 721                                 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 722                 else
 723                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 724                         (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 725                 break;
 726         case 8:
 727                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 728                         /* XXX sort out optimal dither settings */
 729                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 730                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 731                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 732                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 733                                 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 734                 else
 735                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 736                         (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 737                 break;
 738         case 10:
 739                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 740                         /* XXX sort out optimal dither settings */
 741                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 742                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 743                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 744                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 745                                 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 746                 else
 747                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 748                         (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 749                 break;
 750         default:
 751                 /* not needed */
 752                 break;
 753         }
 754
 755         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 756 }
 757
 758
 759 /* display watermark setup */
 760 /**
 761  * dce_v8_0_line_buffer_adjust - Set up the line buffer
 762  *
 763  * @adev: amdgpu_device pointer
 764  * @amdgpu_crtc: the selected display controller
 765  * @mode: the current display mode on the selected display
 766  * controller
 767  *
 768  * Setup up the line buffer allocation for
 769  * the selected display controller (CIK).
 770  * Returns the line buffer size in pixels.
 771  */
 772 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
 773                                        struct amdgpu_crtc *amdgpu_crtc,
 774                                        struct drm_display_mode *mode)
 775 {
 776         u32 tmp, buffer_alloc, i;
 777         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 778         /*
 779          * Line Buffer Setup
 780          * There are 6 line buffers, one for each display controllers.
 781          * There are 3 partitions per LB. Select the number of partitions
 782          * to enable based on the display width.  For display widths larger
 783          * than 4096, you need use to use 2 display controllers and combine
 784          * them using the stereo blender.
 785          */
 786         if (amdgpu_crtc->base.enabled && mode) {
 787                 if (mode->crtc_hdisplay < 1920) {
 788                         tmp = 1;
 789                         buffer_alloc = 2;
 790                 } else if (mode->crtc_hdisplay < 2560) {
 791                         tmp = 2;
 792                         buffer_alloc = 2;
 793                 } else if (mode->crtc_hdisplay < 4096) {
 794                         tmp = 0;
 795                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 796                 } else {
 797                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 798                         tmp = 0;
 799                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 800                 }
 801         } else {
 802                 tmp = 1;
 803                 buffer_alloc = 0;
 804         }
 805
 806         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
 807               (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
 808               (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
 809
 810         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 811                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
 812         for (i = 0; i < adev->usec_timeout; i++) {
 813                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 814                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
 815                         break;
 816                 udelay(1);
 817         }
 818
 819         if (amdgpu_crtc->base.enabled && mode) {
 820                 switch (tmp) {
 821                 case 0:
 822                 default:
 823                         return 4096 * 2;
 824                 case 1:
 825                         return 1920 * 2;
 826                 case 2:
 827                         return 2560 * 2;
 828                 }
 829         }
 830
 831         /* controller not enabled, so no lb used */
 832         return 0;
 833 }
 834
 835 /**
 836  * cik_get_number_of_dram_channels - get the number of dram channels
 837  *
 838  * @adev: amdgpu_device pointer
 839  *
 840  * Look up the number of video ram channels (CIK).
 841  * Used for display watermark bandwidth calculations
 842  * Returns the number of dram channels
 843  */
 844 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 845 {
 846         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 847
 848         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 849         case 0:
 850         default:
 851                 return 1;
 852         case 1:
 853                 return 2;
 854         case 2:
 855                 return 4;
 856         case 3:
 857                 return 8;
 858         case 4:
 859                 return 3;
 860         case 5:
 861                 return 6;
 862         case 6:
 863                 return 10;
 864         case 7:
 865                 return 12;
 866         case 8:
 867                 return 16;
 868         }
 869 }
 870
 871 struct dce8_wm_params {
 872         u32 dram_channels; /* number of dram channels */
 873         u32 yclk;          /* bandwidth per dram data pin in kHz */
 874         u32 sclk;          /* engine clock in kHz */
 875         u32 disp_clk;      /* display clock in kHz */
 876         u32 src_width;     /* viewport width */
 877         u32 active_time;   /* active display time in ns */
 878         u32 blank_time;    /* blank time in ns */
 879         bool interlaced;    /* mode is interlaced */
 880         fixed20_12 vsc;    /* vertical scale ratio */
 881         u32 num_heads;     /* number of active crtcs */
 882         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 883         u32 lb_size;       /* line buffer allocated to pipe */
 884         u32 vtaps;         /* vertical scaler taps */
 885 };
 886
 887 /**
 888  * dce_v8_0_dram_bandwidth - get the dram bandwidth
 889  *
 890  * @wm: watermark calculation data
 891  *
 892  * Calculate the raw dram bandwidth (CIK).
 893  * Used for display watermark bandwidth calculations
 894  * Returns the dram bandwidth in MBytes/s
 895  */
 896 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
 897 {
 898         /* Calculate raw DRAM Bandwidth */
 899         fixed20_12 dram_efficiency; /* 0.7 */
 900         fixed20_12 yclk, dram_channels, bandwidth;
 901         fixed20_12 a;
 902
 903         a.full = dfixed_const(1000);
 904         yclk.full = dfixed_const(wm->yclk);
 905         yclk.full = dfixed_div(yclk, a);
 906         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 907         a.full = dfixed_const(10);
 908         dram_efficiency.full = dfixed_const(7);
 909         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 910         bandwidth.full = dfixed_mul(dram_channels, yclk);
 911         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 912
 913         return dfixed_trunc(bandwidth);
 914 }
 915
 916 /**
 917  * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
 918  *
 919  * @wm: watermark calculation data
 920  *
 921  * Calculate the dram bandwidth used for display (CIK).
 922  * Used for display watermark bandwidth calculations
 923  * Returns the dram bandwidth for display in MBytes/s
 924  */
 925 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 926 {
 927         /* Calculate DRAM Bandwidth and the part allocated to display. */
 928         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 929         fixed20_12 yclk, dram_channels, bandwidth;
 930         fixed20_12 a;
 931
 932         a.full = dfixed_const(1000);
 933         yclk.full = dfixed_const(wm->yclk);
 934         yclk.full = dfixed_div(yclk, a);
 935         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 936         a.full = dfixed_const(10);
 937         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 938         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 939         bandwidth.full = dfixed_mul(dram_channels, yclk);
 940         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 941
 942         return dfixed_trunc(bandwidth);
 943 }
 944
 945 /**
 946  * dce_v8_0_data_return_bandwidth - get the data return bandwidth
 947  *
 948  * @wm: watermark calculation data
 949  *
 950  * Calculate the data return bandwidth used for display (CIK).
 951  * Used for display watermark bandwidth calculations
 952  * Returns the data return bandwidth in MBytes/s
 953  */
 954 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
 955 {
 956         /* Calculate the display Data return Bandwidth */
 957         fixed20_12 return_efficiency; /* 0.8 */
 958         fixed20_12 sclk, bandwidth;
 959         fixed20_12 a;
 960
 961         a.full = dfixed_const(1000);
 962         sclk.full = dfixed_const(wm->sclk);
 963         sclk.full = dfixed_div(sclk, a);
 964         a.full = dfixed_const(10);
 965         return_efficiency.full = dfixed_const(8);
 966         return_efficiency.full = dfixed_div(return_efficiency, a);
 967         a.full = dfixed_const(32);
 968         bandwidth.full = dfixed_mul(a, sclk);
 969         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 970
 971         return dfixed_trunc(bandwidth);
 972 }
 973
 974 /**
 975  * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
 976  *
 977  * @wm: watermark calculation data
 978  *
 979  * Calculate the dmif bandwidth used for display (CIK).
 980  * Used for display watermark bandwidth calculations
 981  * Returns the dmif bandwidth in MBytes/s
 982  */
 983 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
 984 {
 985         /* Calculate the DMIF Request Bandwidth */
 986         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 987         fixed20_12 disp_clk, bandwidth;
 988         fixed20_12 a, b;
 989
 990         a.full = dfixed_const(1000);
 991         disp_clk.full = dfixed_const(wm->disp_clk);
 992         disp_clk.full = dfixed_div(disp_clk, a);
 993         a.full = dfixed_const(32);
 994         b.full = dfixed_mul(a, disp_clk);
 995
 996         a.full = dfixed_const(10);
 997         disp_clk_request_efficiency.full = dfixed_const(8);
 998         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 999
1000         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1001
1002         return dfixed_trunc(bandwidth);
1003 }
1004
1005 /**
1006  * dce_v8_0_available_bandwidth - get the min available bandwidth
1007  *
1008  * @wm: watermark calculation data
1009  *
1010  * Calculate the min available bandwidth used for display (CIK).
1011  * Used for display watermark bandwidth calculations
1012  * Returns the min available bandwidth in MBytes/s
1013  */
1014 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
1015 {
1016         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1017         u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
1018         u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
1019         u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
1020
1021         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1022 }
1023
1024 /**
1025  * dce_v8_0_average_bandwidth - get the average available bandwidth
1026  *
1027  * @wm: watermark calculation data
1028  *
1029  * Calculate the average available bandwidth used for display (CIK).
1030  * Used for display watermark bandwidth calculations
1031  * Returns the average available bandwidth in MBytes/s
1032  */
1033 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
1034 {
1035         /* Calculate the display mode Average Bandwidth
1036          * DisplayMode should contain the source and destination dimensions,
1037          * timing, etc.
1038          */
1039         fixed20_12 bpp;
1040         fixed20_12 line_time;
1041         fixed20_12 src_width;
1042         fixed20_12 bandwidth;
1043         fixed20_12 a;
1044
1045         a.full = dfixed_const(1000);
1046         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1047         line_time.full = dfixed_div(line_time, a);
1048         bpp.full = dfixed_const(wm->bytes_per_pixel);
1049         src_width.full = dfixed_const(wm->src_width);
1050         bandwidth.full = dfixed_mul(src_width, bpp);
1051         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1052         bandwidth.full = dfixed_div(bandwidth, line_time);
1053
1054         return dfixed_trunc(bandwidth);
1055 }
1056
1057 /**
1058  * dce_v8_0_latency_watermark - get the latency watermark
1059  *
1060  * @wm: watermark calculation data
1061  *
1062  * Calculate the latency watermark (CIK).
1063  * Used for display watermark bandwidth calculations
1064  * Returns the latency watermark in ns
1065  */
1066 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
1067 {
1068         /* First calculate the latency in ns */
1069         u32 mc_latency = 2000; /* 2000 ns. */
1070         u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
1071         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1072         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1073         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1074         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1075                 (wm->num_heads * cursor_line_pair_return_time);
1076         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1077         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1078         u32 tmp, dmif_size = 12288;
1079         fixed20_12 a, b, c;
1080
1081         if (wm->num_heads == 0)
1082                 return 0;
1083
1084         a.full = dfixed_const(2);
1085         b.full = dfixed_const(1);
1086         if ((wm->vsc.full > a.full) ||
1087             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1088             (wm->vtaps >= 5) ||
1089             ((wm->vsc.full >= a.full) && wm->interlaced))
1090                 max_src_lines_per_dst_line = 4;
1091         else
1092                 max_src_lines_per_dst_line = 2;
1093
1094         a.full = dfixed_const(available_bandwidth);
1095         b.full = dfixed_const(wm->num_heads);
1096         a.full = dfixed_div(a, b);
1097         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1098         tmp = min(dfixed_trunc(a), tmp);
1099
1100         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1101
1102         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1103         b.full = dfixed_const(1000);
1104         c.full = dfixed_const(lb_fill_bw);
1105         b.full = dfixed_div(c, b);
1106         a.full = dfixed_div(a, b);
1107         line_fill_time = dfixed_trunc(a);
1108
1109         if (line_fill_time < wm->active_time)
1110                 return latency;
1111         else
1112                 return latency + (line_fill_time - wm->active_time);
1113
1114 }
1115
1116 /**
1117  * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1118  * average and available dram bandwidth
1119  *
1120  * @wm: watermark calculation data
1121  *
1122  * Check if the display average bandwidth fits in the display
1123  * dram bandwidth (CIK).
1124  * Used for display watermark bandwidth calculations
1125  * Returns true if the display fits, false if not.
1126  */
1127 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1128 {
1129         if (dce_v8_0_average_bandwidth(wm) <=
1130             (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1131                 return true;
1132         else
1133                 return false;
1134 }
1135
1136 /**
1137  * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1138  * average and available bandwidth
1139  *
1140  * @wm: watermark calculation data
1141  *
1142  * Check if the display average bandwidth fits in the display
1143  * available bandwidth (CIK).
1144  * Used for display watermark bandwidth calculations
1145  * Returns true if the display fits, false if not.
1146  */
1147 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1148 {
1149         if (dce_v8_0_average_bandwidth(wm) <=
1150             (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1151                 return true;
1152         else
1153                 return false;
1154 }
1155
1156 /**
1157  * dce_v8_0_check_latency_hiding - check latency hiding
1158  *
1159  * @wm: watermark calculation data
1160  *
1161  * Check latency hiding (CIK).
1162  * Used for display watermark bandwidth calculations
1163  * Returns true if the display fits, false if not.
1164  */
1165 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1166 {
1167         u32 lb_partitions = wm->lb_size / wm->src_width;
1168         u32 line_time = wm->active_time + wm->blank_time;
1169         u32 latency_tolerant_lines;
1170         u32 latency_hiding;
1171         fixed20_12 a;
1172
1173         a.full = dfixed_const(1);
1174         if (wm->vsc.full > a.full)
1175                 latency_tolerant_lines = 1;
1176         else {
1177                 if (lb_partitions <= (wm->vtaps + 1))
1178                         latency_tolerant_lines = 1;
1179                 else
1180                         latency_tolerant_lines = 2;
1181         }
1182
1183         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1184
1185         if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1186                 return true;
1187         else
1188                 return false;
1189 }
1190
1191 /**
1192  * dce_v8_0_program_watermarks - program display watermarks
1193  *
1194  * @adev: amdgpu_device pointer
1195  * @amdgpu_crtc: the selected display controller
1196  * @lb_size: line buffer size
1197  * @num_heads: number of display controllers in use
1198  *
1199  * Calculate and program the display watermarks for the
1200  * selected display controller (CIK).
1201  */
1202 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1203                                         struct amdgpu_crtc *amdgpu_crtc,
1204                                         u32 lb_size, u32 num_heads)
1205 {
1206         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1207         struct dce8_wm_params wm_low, wm_high;
1208         u32 active_time;
1209         u32 line_time = 0;
1210         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1211         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1212
1213         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1214                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1215                                             (u32)mode->clock);
1216                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1217                                           (u32)mode->clock);
1218                 line_time = min(line_time, (u32)65535);
1219
1220                 /* watermark for high clocks */
1221                 if (adev->pm.dpm_enabled) {
1222                         wm_high.yclk =
1223                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1224                         wm_high.sclk =
1225                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1226                 } else {
1227                         wm_high.yclk = adev->pm.current_mclk * 10;
1228                         wm_high.sclk = adev->pm.current_sclk * 10;
1229                 }
1230
1231                 wm_high.disp_clk = mode->clock;
1232                 wm_high.src_width = mode->crtc_hdisplay;
1233                 wm_high.active_time = active_time;
1234                 wm_high.blank_time = line_time - wm_high.active_time;
1235                 wm_high.interlaced = false;
1236                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1237                         wm_high.interlaced = true;
1238                 wm_high.vsc = amdgpu_crtc->vsc;
1239                 wm_high.vtaps = 1;
1240                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1241                         wm_high.vtaps = 2;
1242                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1243                 wm_high.lb_size = lb_size;
1244                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1245                 wm_high.num_heads = num_heads;
1246
1247                 /* set for high clocks */
1248                 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1249
1250                 /* possibly force display priority to high */
1251                 /* should really do this at mode validation time... */
1252                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1253                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1254                     !dce_v8_0_check_latency_hiding(&wm_high) ||
1255                     (adev->mode_info.disp_priority == 2)) {
1256                         DRM_DEBUG_KMS("force priority to high\n");
1257                 }
1258
1259                 /* watermark for low clocks */
1260                 if (adev->pm.dpm_enabled) {
1261                         wm_low.yclk =
1262                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1263                         wm_low.sclk =
1264                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1265                 } else {
1266                         wm_low.yclk = adev->pm.current_mclk * 10;
1267                         wm_low.sclk = adev->pm.current_sclk * 10;
1268                 }
1269
1270                 wm_low.disp_clk = mode->clock;
1271                 wm_low.src_width = mode->crtc_hdisplay;
1272                 wm_low.active_time = active_time;
1273                 wm_low.blank_time = line_time - wm_low.active_time;
1274                 wm_low.interlaced = false;
1275                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1276                         wm_low.interlaced = true;
1277                 wm_low.vsc = amdgpu_crtc->vsc;
1278                 wm_low.vtaps = 1;
1279                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1280                         wm_low.vtaps = 2;
1281                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1282                 wm_low.lb_size = lb_size;
1283                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1284                 wm_low.num_heads = num_heads;
1285
1286                 /* set for low clocks */
1287                 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1288
1289                 /* possibly force display priority to high */
1290                 /* should really do this at mode validation time... */
1291                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1292                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1293                     !dce_v8_0_check_latency_hiding(&wm_low) ||
1294                     (adev->mode_info.disp_priority == 2)) {
1295                         DRM_DEBUG_KMS("force priority to high\n");
1296                 }
1297                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1298         }
1299
1300         /* select wm A */
1301         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1302         tmp = wm_mask;
1303         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1304         tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1305         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1306         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1307                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1308                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1309         /* select wm B */
1310         tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1311         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1312         tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1313         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1314         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1315                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1316                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1317         /* restore original selection */
1318         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1319
1320         /* save values for DPM */
1321         amdgpu_crtc->line_time = line_time;
1322         amdgpu_crtc->wm_high = latency_watermark_a;
1323         amdgpu_crtc->wm_low = latency_watermark_b;
1324         /* Save number of lines the linebuffer leads before the scanout */
1325         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1326 }
1327
1328 /**
1329  * dce_v8_0_bandwidth_update - program display watermarks
1330  *
1331  * @adev: amdgpu_device pointer
1332  *
1333  * Calculate and program the display watermarks and line
1334  * buffer allocation (CIK).
1335  */
1336 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1337 {
1338         struct drm_display_mode *mode = NULL;
1339         u32 num_heads = 0, lb_size;
1340         int i;
1341
1342         amdgpu_update_display_priority(adev);
1343
1344         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1345                 if (adev->mode_info.crtcs[i]->base.enabled)
1346                         num_heads++;
1347         }
1348         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1349                 mode = &adev->mode_info.crtcs[i]->base.mode;
1350                 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1351                 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1352                                             lb_size, num_heads);
1353         }
1354 }
1355
1356 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1357 {
1358         int i;
1359         u32 offset, tmp;
1360
1361         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1362                 offset = adev->mode_info.audio.pin[i].offset;
1363                 tmp = RREG32_AUDIO_ENDPT(offset,
1364                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1365                 if (((tmp &
1366                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1367                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1368                         adev->mode_info.audio.pin[i].connected = false;
1369                 else
1370                         adev->mode_info.audio.pin[i].connected = true;
1371         }
1372 }
1373
1374 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1375 {
1376         int i;
1377
1378         dce_v8_0_audio_get_connected_pins(adev);
1379
1380         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1381                 if (adev->mode_info.audio.pin[i].connected)
1382                         return &adev->mode_info.audio.pin[i];
1383         }
1384         DRM_ERROR("No connected audio pins found!\n");
1385         return NULL;
1386 }
1387
1388 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1389 {
1390         struct amdgpu_device *adev = encoder->dev->dev_private;
1391         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1392         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1393         u32 offset;
1394
1395         if (!dig || !dig->afmt || !dig->afmt->pin)
1396                 return;
1397
1398         offset = dig->afmt->offset;
1399
1400         WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1401                (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1402 }
1403
1404 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1405                                                 struct drm_display_mode *mode)
1406 {
1407         struct amdgpu_device *adev = encoder->dev->dev_private;
1408         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1409         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1410         struct drm_connector *connector;
1411         struct amdgpu_connector *amdgpu_connector = NULL;
1412         u32 tmp = 0, offset;
1413
1414         if (!dig || !dig->afmt || !dig->afmt->pin)
1415                 return;
1416
1417         offset = dig->afmt->pin->offset;
1418
1419         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1420                 if (connector->encoder == encoder) {
1421                         amdgpu_connector = to_amdgpu_connector(connector);
1422                         break;
1423                 }
1424         }
1425
1426         if (!amdgpu_connector) {
1427                 DRM_ERROR("Couldn't find encoder's connector\n");
1428                 return;
1429         }
1430
1431         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1432                 if (connector->latency_present[1])
1433                         tmp =
1434                         (connector->video_latency[1] <<
1435                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1436                         (connector->audio_latency[1] <<
1437                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1438                 else
1439                         tmp =
1440                         (0 <<
1441                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1442                         (0 <<
1443                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1444         } else {
1445                 if (connector->latency_present[0])
1446                         tmp =
1447                         (connector->video_latency[0] <<
1448                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1449                         (connector->audio_latency[0] <<
1450                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1451                 else
1452                         tmp =
1453                         (0 <<
1454                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1455                         (0 <<
1456                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1457
1458         }
1459         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1460 }
1461
1462 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1463 {
1464         struct amdgpu_device *adev = encoder->dev->dev_private;
1465         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1466         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1467         struct drm_connector *connector;
1468         struct amdgpu_connector *amdgpu_connector = NULL;
1469         u32 offset, tmp;
1470         u8 *sadb = NULL;
1471         int sad_count;
1472
1473         if (!dig || !dig->afmt || !dig->afmt->pin)
1474                 return;
1475
1476         offset = dig->afmt->pin->offset;
1477
1478         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1479                 if (connector->encoder == encoder) {
1480                         amdgpu_connector = to_amdgpu_connector(connector);
1481                         break;
1482                 }
1483         }
1484
1485         if (!amdgpu_connector) {
1486                 DRM_ERROR("Couldn't find encoder's connector\n");
1487                 return;
1488         }
1489
1490         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1491         if (sad_count < 0) {
1492                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1493                 sad_count = 0;
1494         }
1495
1496         /* program the speaker allocation */
1497         tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1498         tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1499                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1500         /* set HDMI mode */
1501         tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1502         if (sad_count)
1503                 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1504         else
1505                 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1506         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1507
1508         kfree(sadb);
1509 }
1510
1511 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1512 {
1513         struct amdgpu_device *adev = encoder->dev->dev_private;
1514         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1515         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1516         u32 offset;
1517         struct drm_connector *connector;
1518         struct amdgpu_connector *amdgpu_connector = NULL;
1519         struct cea_sad *sads;
1520         int i, sad_count;
1521
1522         static const u16 eld_reg_to_type[][2] = {
1523                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1524                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1525                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1526                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1527                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1528                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1529                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1530                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1531                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1532                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1533                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1534                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1535         };
1536
1537         if (!dig || !dig->afmt || !dig->afmt->pin)
1538                 return;
1539
1540         offset = dig->afmt->pin->offset;
1541
1542         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1543                 if (connector->encoder == encoder) {
1544                         amdgpu_connector = to_amdgpu_connector(connector);
1545                         break;
1546                 }
1547         }
1548
1549         if (!amdgpu_connector) {
1550                 DRM_ERROR("Couldn't find encoder's connector\n");
1551                 return;
1552         }
1553
1554         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1555         if (sad_count <= 0) {
1556                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1557                 return;
1558         }
1559         BUG_ON(!sads);
1560
1561         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1562                 u32 value = 0;
1563                 u8 stereo_freqs = 0;
1564                 int max_channels = -1;
1565                 int j;
1566
1567                 for (j = 0; j < sad_count; j++) {
1568                         struct cea_sad *sad = &sads[j];
1569
1570                         if (sad->format == eld_reg_to_type[i][1]) {
1571                                 if (sad->channels > max_channels) {
1572                                         value = (sad->channels <<
1573                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1574                                                 (sad->byte2 <<
1575                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1576                                                 (sad->freq <<
1577                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1578                                         max_channels = sad->channels;
1579                                 }
1580
1581                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1582                                         stereo_freqs |= sad->freq;
1583                                 else
1584                                         break;
1585                         }
1586                 }
1587
1588                 value |= (stereo_freqs <<
1589                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1590
1591                 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1592         }
1593
1594         kfree(sads);
1595 }
1596
1597 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1598                                   struct amdgpu_audio_pin *pin,
1599                                   bool enable)
1600 {
1601         if (!pin)
1602                 return;
1603
1604         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1605                 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1606 }
1607
1608 static const u32 pin_offsets[7] =
1609 {
1610         (0x1780 - 0x1780),
1611         (0x1786 - 0x1780),
1612         (0x178c - 0x1780),
1613         (0x1792 - 0x1780),
1614         (0x1798 - 0x1780),
1615         (0x179d - 0x1780),
1616         (0x17a4 - 0x1780),
1617 };
1618
1619 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1620 {
1621         int i;
1622
1623         if (!amdgpu_audio)
1624                 return 0;
1625
1626         adev->mode_info.audio.enabled = true;
1627
1628         if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1629                 adev->mode_info.audio.num_pins = 7;
1630         else if ((adev->asic_type == CHIP_KABINI) ||
1631                  (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1632                 adev->mode_info.audio.num_pins = 3;
1633         else if ((adev->asic_type == CHIP_BONAIRE) ||
1634                  (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1635                 adev->mode_info.audio.num_pins = 7;
1636         else
1637                 adev->mode_info.audio.num_pins = 3;
1638
1639         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1640                 adev->mode_info.audio.pin[i].channels = -1;
1641                 adev->mode_info.audio.pin[i].rate = -1;
1642                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1643                 adev->mode_info.audio.pin[i].status_bits = 0;
1644                 adev->mode_info.audio.pin[i].category_code = 0;
1645                 adev->mode_info.audio.pin[i].connected = false;
1646                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1647                 adev->mode_info.audio.pin[i].id = i;
1648                 /* disable audio.  it will be set up later */
1649                 /* XXX remove once we switch to ip funcs */
1650                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1651         }
1652
1653         return 0;
1654 }
1655
1656 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1657 {
1658         int i;
1659
1660         if (!amdgpu_audio)
1661                 return;
1662
1663         if (!adev->mode_info.audio.enabled)
1664                 return;
1665
1666         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1667                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1668
1669         adev->mode_info.audio.enabled = false;
1670 }
1671
1672 /*
1673  * update the N and CTS parameters for a given pixel clock rate
1674  */
1675 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1676 {
1677         struct drm_device *dev = encoder->dev;
1678         struct amdgpu_device *adev = dev->dev_private;
1679         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1680         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1681         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1682         uint32_t offset = dig->afmt->offset;
1683
1684         WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1685         WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1686
1687         WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1688         WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1689
1690         WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1691         WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1692 }
1693
1694 /*
1695  * build a HDMI Video Info Frame
1696  */
1697 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1698                                                void *buffer, size_t size)
1699 {
1700         struct drm_device *dev = encoder->dev;
1701         struct amdgpu_device *adev = dev->dev_private;
1702         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1703         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1704         uint32_t offset = dig->afmt->offset;
1705         uint8_t *frame = buffer + 3;
1706         uint8_t *header = buffer;
1707
1708         WREG32(mmAFMT_AVI_INFO0 + offset,
1709                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1710         WREG32(mmAFMT_AVI_INFO1 + offset,
1711                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1712         WREG32(mmAFMT_AVI_INFO2 + offset,
1713                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1714         WREG32(mmAFMT_AVI_INFO3 + offset,
1715                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1716 }
1717
1718 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1719 {
1720         struct drm_device *dev = encoder->dev;
1721         struct amdgpu_device *adev = dev->dev_private;
1722         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1723         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1724         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1725         u32 dto_phase = 24 * 1000;
1726         u32 dto_modulo = clock;
1727
1728         if (!dig || !dig->afmt)
1729                 return;
1730
1731         /* XXX two dtos; generally use dto0 for hdmi */
1732         /* Express [24MHz / target pixel clock] as an exact rational
1733          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1734          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1735          */
1736         WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1737         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1738         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1739 }
1740
1741 /*
1742  * update the info frames with the data from the current display mode
1743  */
1744 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1745                                   struct drm_display_mode *mode)
1746 {
1747         struct drm_device *dev = encoder->dev;
1748         struct amdgpu_device *adev = dev->dev_private;
1749         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1750         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1751         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1752         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1753         struct hdmi_avi_infoframe frame;
1754         uint32_t offset, val;
1755         ssize_t err;
1756         int bpc = 8;
1757
1758         if (!dig || !dig->afmt)
1759                 return;
1760
1761         /* Silent, r600_hdmi_enable will raise WARN for us */
1762         if (!dig->afmt->enabled)
1763                 return;
1764
1765         offset = dig->afmt->offset;
1766
1767         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1768         if (encoder->crtc) {
1769                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1770                 bpc = amdgpu_crtc->bpc;
1771         }
1772
1773         /* disable audio prior to setting up hw */
1774         dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1775         dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1776
1777         dce_v8_0_audio_set_dto(encoder, mode->clock);
1778
1779         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1780                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1781
1782         WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1783
1784         val = RREG32(mmHDMI_CONTROL + offset);
1785         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1786         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1787
1788         switch (bpc) {
1789         case 0:
1790         case 6:
1791         case 8:
1792         case 16:
1793         default:
1794                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1795                           connector->name, bpc);
1796                 break;
1797         case 10:
1798                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1799                 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1800                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1801                           connector->name);
1802                 break;
1803         case 12:
1804                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1805                 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1806                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1807                           connector->name);
1808                 break;
1809         }
1810
1811         WREG32(mmHDMI_CONTROL + offset, val);
1812
1813         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1814                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1815                HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1816                HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1817
1818         WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1819                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1820                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1821
1822         WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1823                AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1824
1825         WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1826                (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1827
1828         WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1829
1830         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1831                (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1832                (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1833
1834         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1835                AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1836
1837         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1838
1839         if (bpc > 8)
1840                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1841                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1842         else
1843                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1844                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1845                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1846
1847         dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1848
1849         WREG32(mmAFMT_60958_0 + offset,
1850                (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1851
1852         WREG32(mmAFMT_60958_1 + offset,
1853                (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1854
1855         WREG32(mmAFMT_60958_2 + offset,
1856                (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1857                (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1858                (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1859                (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1860                (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1861                (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1862
1863         dce_v8_0_audio_write_speaker_allocation(encoder);
1864
1865
1866         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1867                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1868
1869         dce_v8_0_afmt_audio_select_pin(encoder);
1870         dce_v8_0_audio_write_sad_regs(encoder);
1871         dce_v8_0_audio_write_latency_fields(encoder, mode);
1872
1873         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1874         if (err < 0) {
1875                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1876                 return;
1877         }
1878
1879         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1880         if (err < 0) {
1881                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1882                 return;
1883         }
1884
1885         dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1886
1887         WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1888                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1889                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1890
1891         WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1892                  (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1893                  ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1894
1895         WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1896                   AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1897
1898         WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1899         WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1900         WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1901         WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1902
1903         /* enable audio after setting up hw */
1904         dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1905 }
1906
1907 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1908 {
1909         struct drm_device *dev = encoder->dev;
1910         struct amdgpu_device *adev = dev->dev_private;
1911         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1912         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1913
1914         if (!dig || !dig->afmt)
1915                 return;
1916
1917         /* Silent, r600_hdmi_enable will raise WARN for us */
1918         if (enable && dig->afmt->enabled)
1919                 return;
1920         if (!enable && !dig->afmt->enabled)
1921                 return;
1922
1923         if (!enable && dig->afmt->pin) {
1924                 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1925                 dig->afmt->pin = NULL;
1926         }
1927
1928         dig->afmt->enabled = enable;
1929
1930         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1931                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1932 }
1933
1934 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1935 {
1936         int i;
1937
1938         for (i = 0; i < adev->mode_info.num_dig; i++)
1939                 adev->mode_info.afmt[i] = NULL;
1940
1941         /* DCE8 has audio blocks tied to DIG encoders */
1942         for (i = 0; i < adev->mode_info.num_dig; i++) {
1943                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1944                 if (adev->mode_info.afmt[i]) {
1945                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1946                         adev->mode_info.afmt[i]->id = i;
1947                 } else {
1948                         int j;
1949                         for (j = 0; j < i; j++) {
1950                                 kfree(adev->mode_info.afmt[j]);
1951                                 adev->mode_info.afmt[j] = NULL;
1952                         }
1953                         return -ENOMEM;
1954                 }
1955         }
1956         return 0;
1957 }
1958
1959 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1960 {
1961         int i;
1962
1963         for (i = 0; i < adev->mode_info.num_dig; i++) {
1964                 kfree(adev->mode_info.afmt[i]);
1965                 adev->mode_info.afmt[i] = NULL;
1966         }
1967 }
1968
1969 static const u32 vga_control_regs[6] =
1970 {
1971         mmD1VGA_CONTROL,
1972         mmD2VGA_CONTROL,
1973         mmD3VGA_CONTROL,
1974         mmD4VGA_CONTROL,
1975         mmD5VGA_CONTROL,
1976         mmD6VGA_CONTROL,
1977 };
1978
1979 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1980 {
1981         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1982         struct drm_device *dev = crtc->dev;
1983         struct amdgpu_device *adev = dev->dev_private;
1984         u32 vga_control;
1985
1986         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1987         if (enable)
1988                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1989         else
1990                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1991 }
1992
1993 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1994 {
1995         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1996         struct drm_device *dev = crtc->dev;
1997         struct amdgpu_device *adev = dev->dev_private;
1998
1999         if (enable)
2000                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2001         else
2002                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2003 }
2004
2005 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
2006                                      struct drm_framebuffer *fb,
2007                                      int x, int y, int atomic)
2008 {
2009         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2010         struct drm_device *dev = crtc->dev;
2011         struct amdgpu_device *adev = dev->dev_private;
2012         struct amdgpu_framebuffer *amdgpu_fb;
2013         struct drm_framebuffer *target_fb;
2014         struct drm_gem_object *obj;
2015         struct amdgpu_bo *abo;
2016         uint64_t fb_location, tiling_flags;
2017         uint32_t fb_format, fb_pitch_pixels;
2018         u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2019         u32 pipe_config;
2020         u32 viewport_w, viewport_h;
2021         int r;
2022         bool bypass_lut = false;
2023         char *format_name;
2024
2025         /* no fb bound */
2026         if (!atomic && !crtc->primary->fb) {
2027                 DRM_DEBUG_KMS("No FB bound\n");
2028                 return 0;
2029         }
2030
2031         if (atomic) {
2032                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2033                 target_fb = fb;
2034         } else {
2035                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2036                 target_fb = crtc->primary->fb;
2037         }
2038
2039         /* If atomic, assume fb object is pinned & idle & fenced and
2040          * just update base pointers
2041          */
2042         obj = amdgpu_fb->obj;
2043         abo = gem_to_amdgpu_bo(obj);
2044         r = amdgpu_bo_reserve(abo, false);
2045         if (unlikely(r != 0))
2046                 return r;
2047
2048         if (atomic) {
2049                 fb_location = amdgpu_bo_gpu_offset(abo);
2050         } else {
2051                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2052                 if (unlikely(r != 0)) {
2053                         amdgpu_bo_unreserve(abo);
2054                         return -EINVAL;
2055                 }
2056         }
2057
2058         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2059         amdgpu_bo_unreserve(abo);
2060
2061         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2062
2063         switch (target_fb->pixel_format) {
2064         case DRM_FORMAT_C8:
2065                 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2066                              (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2067                 break;
2068         case DRM_FORMAT_XRGB4444:
2069         case DRM_FORMAT_ARGB4444:
2070                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2071                              (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2072 #ifdef __BIG_ENDIAN
2073                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2074 #endif
2075                 break;
2076         case DRM_FORMAT_XRGB1555:
2077         case DRM_FORMAT_ARGB1555:
2078                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2079                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2080 #ifdef __BIG_ENDIAN
2081                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2082 #endif
2083                 break;
2084         case DRM_FORMAT_BGRX5551:
2085         case DRM_FORMAT_BGRA5551:
2086                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2087                              (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2088 #ifdef __BIG_ENDIAN
2089                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2090 #endif
2091                 break;
2092         case DRM_FORMAT_RGB565:
2093                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2094                              (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2095 #ifdef __BIG_ENDIAN
2096                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2097 #endif
2098                 break;
2099         case DRM_FORMAT_XRGB8888:
2100         case DRM_FORMAT_ARGB8888:
2101                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2102                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2103 #ifdef __BIG_ENDIAN
2104                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2105 #endif
2106                 break;
2107         case DRM_FORMAT_XRGB2101010:
2108         case DRM_FORMAT_ARGB2101010:
2109                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2110                              (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2111 #ifdef __BIG_ENDIAN
2112                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2113 #endif
2114                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2115                 bypass_lut = true;
2116                 break;
2117         case DRM_FORMAT_BGRX1010102:
2118         case DRM_FORMAT_BGRA1010102:
2119                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2120                              (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2121 #ifdef __BIG_ENDIAN
2122                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2123 #endif
2124                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2125                 bypass_lut = true;
2126                 break;
2127         default:
2128                 format_name = drm_get_format_name(target_fb->pixel_format);
2129                 DRM_ERROR("Unsupported screen format %s\n", format_name);
2130                 kfree(format_name);
2131                 return -EINVAL;
2132         }
2133
2134         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2135                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2136
2137                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2138                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2139                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2140                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2141                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2142
2143                 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2144                 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2145                 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2146                 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2147                 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2148                 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2149                 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
2150         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2151                 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2152         }
2153
2154         fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2155
2156         dce_v8_0_vga_enable(crtc, false);
2157
2158         /* Make sure surface address is updated at vertical blank rather than
2159          * horizontal blank
2160          */
2161         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2162
2163         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2164                upper_32_bits(fb_location));
2165         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2166                upper_32_bits(fb_location));
2167         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2168                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2169         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2170                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2171         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2172         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2173
2174         /*
2175          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2176          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2177          * retain the full precision throughout the pipeline.
2178          */
2179         WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2180                  (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2181                  ~LUT_10BIT_BYPASS_EN);
2182
2183         if (bypass_lut)
2184                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2185
2186         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2187         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2188         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2189         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2190         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2191         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2192
2193         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2194         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2195
2196         dce_v8_0_grph_enable(crtc, true);
2197
2198         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2199                target_fb->height);
2200
2201         x &= ~3;
2202         y &= ~1;
2203         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2204                (x << 16) | y);
2205         viewport_w = crtc->mode.hdisplay;
2206         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2207         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2208                (viewport_w << 16) | viewport_h);
2209
2210         /* set pageflip to happen anywhere in vblank interval */
2211         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2212
2213         if (!atomic && fb && fb != crtc->primary->fb) {
2214                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2215                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2216                 r = amdgpu_bo_reserve(abo, false);
2217                 if (unlikely(r != 0))
2218                         return r;
2219                 amdgpu_bo_unpin(abo);
2220                 amdgpu_bo_unreserve(abo);
2221         }
2222
2223         /* Bytes per pixel may have changed */
2224         dce_v8_0_bandwidth_update(adev);
2225
2226         return 0;
2227 }
2228
2229 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2230                                     struct drm_display_mode *mode)
2231 {
2232         struct drm_device *dev = crtc->dev;
2233         struct amdgpu_device *adev = dev->dev_private;
2234         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2235
2236         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2237                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2238                        LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2239         else
2240                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2241 }
2242
2243 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2244 {
2245         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2246         struct drm_device *dev = crtc->dev;
2247         struct amdgpu_device *adev = dev->dev_private;
2248         int i;
2249
2250         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2251
2252         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2253                ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2254                 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2255         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2256                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2257         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2258                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2259         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2260                ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2261                 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2262
2263         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2264
2265         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2266         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2267         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2268
2269         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2270         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2271         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2272
2273         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2274         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2275
2276         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2277         for (i = 0; i < 256; i++) {
2278                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2279                        (amdgpu_crtc->lut_r[i] << 20) |
2280                        (amdgpu_crtc->lut_g[i] << 10) |
2281                        (amdgpu_crtc->lut_b[i] << 0));
2282         }
2283
2284         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2285                ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2286                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2287                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2288         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2289                ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2290                 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2291         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2292                ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2293                 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2294         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2295                ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2296                 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2297         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2298         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2299         /* XXX this only needs to be programmed once per crtc at startup,
2300          * not sure where the best place for it is
2301          */
2302         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2303                ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2304 }
2305
2306 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2307 {
2308         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2309         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2310
2311         switch (amdgpu_encoder->encoder_id) {
2312         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2313                 if (dig->linkb)
2314                         return 1;
2315                 else
2316                         return 0;
2317                 break;
2318         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2319                 if (dig->linkb)
2320                         return 3;
2321                 else
2322                         return 2;
2323                 break;
2324         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2325                 if (dig->linkb)
2326                         return 5;
2327                 else
2328                         return 4;
2329                 break;
2330         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2331                 return 6;
2332                 break;
2333         default:
2334                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2335                 return 0;
2336         }
2337 }
2338
2339 /**
2340  * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2341  *
2342  * @crtc: drm crtc
2343  *
2344  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2345  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2346  * monitors a dedicated PPLL must be used.  If a particular board has
2347  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2348  * as there is no need to program the PLL itself.  If we are not able to
2349  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2350  * avoid messing up an existing monitor.
2351  *
2352  * Asic specific PLL information
2353  *
2354  * DCE 8.x
2355  * KB/KV
2356  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2357  * CI
2358  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2359  *
2360  */
2361 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2362 {
2363         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2364         struct drm_device *dev = crtc->dev;
2365         struct amdgpu_device *adev = dev->dev_private;
2366         u32 pll_in_use;
2367         int pll;
2368
2369         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2370                 if (adev->clock.dp_extclk)
2371                         /* skip PPLL programming if using ext clock */
2372                         return ATOM_PPLL_INVALID;
2373                 else {
2374                         /* use the same PPLL for all DP monitors */
2375                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2376                         if (pll != ATOM_PPLL_INVALID)
2377                                 return pll;
2378                 }
2379         } else {
2380                 /* use the same PPLL for all monitors with the same clock */
2381                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2382                 if (pll != ATOM_PPLL_INVALID)
2383                         return pll;
2384         }
2385         /* otherwise, pick one of the plls */
2386         if ((adev->asic_type == CHIP_KABINI) ||
2387             (adev->asic_type == CHIP_MULLINS)) {
2388                 /* KB/ML has PPLL1 and PPLL2 */
2389                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2390                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2391                         return ATOM_PPLL2;
2392                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2393                         return ATOM_PPLL1;
2394                 DRM_ERROR("unable to allocate a PPLL\n");
2395                 return ATOM_PPLL_INVALID;
2396         } else {
2397                 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2398                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2399                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2400                         return ATOM_PPLL2;
2401                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2402                         return ATOM_PPLL1;
2403                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2404                         return ATOM_PPLL0;
2405                 DRM_ERROR("unable to allocate a PPLL\n");
2406                 return ATOM_PPLL_INVALID;
2407         }
2408         return ATOM_PPLL_INVALID;
2409 }
2410
2411 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2412 {
2413         struct amdgpu_device *adev = crtc->dev->dev_private;
2414         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2415         uint32_t cur_lock;
2416
2417         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2418         if (lock)
2419                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2420         else
2421                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2422         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2423 }
2424
2425 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2426 {
2427         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2428         struct amdgpu_device *adev = crtc->dev->dev_private;
2429
2430         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2431                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2432                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2433 }
2434
2435 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2436 {
2437         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2438         struct amdgpu_device *adev = crtc->dev->dev_private;
2439
2440         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2441                upper_32_bits(amdgpu_crtc->cursor_addr));
2442         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2443                lower_32_bits(amdgpu_crtc->cursor_addr));
2444
2445         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2446                    CUR_CONTROL__CURSOR_EN_MASK |
2447                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2448                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2449 }
2450
2451 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2452                                        int x, int y)
2453 {
2454         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2455         struct amdgpu_device *adev = crtc->dev->dev_private;
2456         int xorigin = 0, yorigin = 0;
2457
2458         amdgpu_crtc->cursor_x = x;
2459         amdgpu_crtc->cursor_y = y;
2460
2461         /* avivo cursor are offset into the total surface */
2462         x += crtc->x;
2463         y += crtc->y;
2464         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2465
2466         if (x < 0) {
2467                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2468                 x = 0;
2469         }
2470         if (y < 0) {
2471                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2472                 y = 0;
2473         }
2474
2475         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2476         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2477         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2478                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2479
2480         return 0;
2481 }
2482
2483 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2484                                      int x, int y)
2485 {
2486         int ret;
2487
2488         dce_v8_0_lock_cursor(crtc, true);
2489         ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2490         dce_v8_0_lock_cursor(crtc, false);
2491
2492         return ret;
2493 }
2494
2495 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2496                                      struct drm_file *file_priv,
2497                                      uint32_t handle,
2498                                      uint32_t width,
2499                                      uint32_t height,
2500                                      int32_t hot_x,
2501                                      int32_t hot_y)
2502 {
2503         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2504         struct drm_gem_object *obj;
2505         struct amdgpu_bo *aobj;
2506         int ret;
2507
2508         if (!handle) {
2509                 /* turn off cursor */
2510                 dce_v8_0_hide_cursor(crtc);
2511                 obj = NULL;
2512                 goto unpin;
2513         }
2514
2515         if ((width > amdgpu_crtc->max_cursor_width) ||
2516             (height > amdgpu_crtc->max_cursor_height)) {
2517                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2518                 return -EINVAL;
2519         }
2520
2521         obj = drm_gem_object_lookup(file_priv, handle);
2522         if (!obj) {
2523                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2524                 return -ENOENT;
2525         }
2526
2527         aobj = gem_to_amdgpu_bo(obj);
2528         ret = amdgpu_bo_reserve(aobj, false);
2529         if (ret != 0) {
2530                 drm_gem_object_unreference_unlocked(obj);
2531                 return ret;
2532         }
2533
2534         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2535         amdgpu_bo_unreserve(aobj);
2536         if (ret) {
2537                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2538                 drm_gem_object_unreference_unlocked(obj);
2539                 return ret;
2540         }
2541
2542         dce_v8_0_lock_cursor(crtc, true);
2543
2544         if (width != amdgpu_crtc->cursor_width ||
2545             height != amdgpu_crtc->cursor_height ||
2546             hot_x != amdgpu_crtc->cursor_hot_x ||
2547             hot_y != amdgpu_crtc->cursor_hot_y) {
2548                 int x, y;
2549
2550                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2551                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2552
2553                 dce_v8_0_cursor_move_locked(crtc, x, y);
2554
2555                 amdgpu_crtc->cursor_width = width;
2556                 amdgpu_crtc->cursor_height = height;
2557                 amdgpu_crtc->cursor_hot_x = hot_x;
2558                 amdgpu_crtc->cursor_hot_y = hot_y;
2559         }
2560
2561         dce_v8_0_show_cursor(crtc);
2562         dce_v8_0_lock_cursor(crtc, false);
2563
2564 unpin:
2565         if (amdgpu_crtc->cursor_bo) {
2566                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2567                 ret = amdgpu_bo_reserve(aobj, false);
2568                 if (likely(ret == 0)) {
2569                         amdgpu_bo_unpin(aobj);
2570                         amdgpu_bo_unreserve(aobj);
2571                 }
2572                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2573         }
2574
2575         amdgpu_crtc->cursor_bo = obj;
2576         return 0;
2577 }
2578
2579 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2580 {
2581         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2582
2583         if (amdgpu_crtc->cursor_bo) {
2584                 dce_v8_0_lock_cursor(crtc, true);
2585
2586                 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2587                                             amdgpu_crtc->cursor_y);
2588
2589                 dce_v8_0_show_cursor(crtc);
2590
2591                 dce_v8_0_lock_cursor(crtc, false);
2592         }
2593 }
2594
2595 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2596                                    u16 *blue, uint32_t size)
2597 {
2598         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2599         int i;
2600
2601         /* userspace palettes are always correct as is */
2602         for (i = 0; i < size; i++) {
2603                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2604                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2605                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2606         }
2607         dce_v8_0_crtc_load_lut(crtc);
2608
2609         return 0;
2610 }
2611
2612 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2613 {
2614         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2615
2616         drm_crtc_cleanup(crtc);
2617         kfree(amdgpu_crtc);
2618 }
2619
2620 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2621         .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2622         .cursor_move = dce_v8_0_crtc_cursor_move,
2623         .gamma_set = dce_v8_0_crtc_gamma_set,
2624         .set_config = amdgpu_crtc_set_config,
2625         .destroy = dce_v8_0_crtc_destroy,
2626         .page_flip_target = amdgpu_crtc_page_flip_target,
2627 };
2628
2629 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2630 {
2631         struct drm_device *dev = crtc->dev;
2632         struct amdgpu_device *adev = dev->dev_private;
2633         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2634         unsigned type;
2635
2636         switch (mode) {
2637         case DRM_MODE_DPMS_ON:
2638                 amdgpu_crtc->enabled = true;
2639                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2640                 dce_v8_0_vga_enable(crtc, true);
2641                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2642                 dce_v8_0_vga_enable(crtc, false);
2643                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2644                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2645                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2646                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2647                 drm_crtc_vblank_on(crtc);
2648                 dce_v8_0_crtc_load_lut(crtc);
2649                 break;
2650         case DRM_MODE_DPMS_STANDBY:
2651         case DRM_MODE_DPMS_SUSPEND:
2652         case DRM_MODE_DPMS_OFF:
2653                 drm_crtc_vblank_off(crtc);
2654                 if (amdgpu_crtc->enabled) {
2655                         dce_v8_0_vga_enable(crtc, true);
2656                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2657                         dce_v8_0_vga_enable(crtc, false);
2658                 }
2659                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2660                 amdgpu_crtc->enabled = false;
2661                 break;
2662         }
2663         /* adjust pm to dpms */
2664         amdgpu_pm_compute_clocks(adev);
2665 }
2666
2667 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2668 {
2669         /* disable crtc pair power gating before programming */
2670         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2671         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2672         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2673 }
2674
2675 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2676 {
2677         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2678         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2679 }
2680
2681 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2682 {
2683         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2684         struct drm_device *dev = crtc->dev;
2685         struct amdgpu_device *adev = dev->dev_private;
2686         struct amdgpu_atom_ss ss;
2687         int i;
2688
2689         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2690         if (crtc->primary->fb) {
2691                 int r;
2692                 struct amdgpu_framebuffer *amdgpu_fb;
2693                 struct amdgpu_bo *abo;
2694
2695                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2696                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2697                 r = amdgpu_bo_reserve(abo, false);
2698                 if (unlikely(r))
2699                         DRM_ERROR("failed to reserve abo before unpin\n");
2700                 else {
2701                         amdgpu_bo_unpin(abo);
2702                         amdgpu_bo_unreserve(abo);
2703                 }
2704         }
2705         /* disable the GRPH */
2706         dce_v8_0_grph_enable(crtc, false);
2707
2708         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2709
2710         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2711                 if (adev->mode_info.crtcs[i] &&
2712                     adev->mode_info.crtcs[i]->enabled &&
2713                     i != amdgpu_crtc->crtc_id &&
2714                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2715                         /* one other crtc is using this pll don't turn
2716                          * off the pll
2717                          */
2718                         goto done;
2719                 }
2720         }
2721
2722         switch (amdgpu_crtc->pll_id) {
2723         case ATOM_PPLL1:
2724         case ATOM_PPLL2:
2725                 /* disable the ppll */
2726                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2727                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2728                 break;
2729         case ATOM_PPLL0:
2730                 /* disable the ppll */
2731                 if ((adev->asic_type == CHIP_KAVERI) ||
2732                     (adev->asic_type == CHIP_BONAIRE) ||
2733                     (adev->asic_type == CHIP_HAWAII))
2734                         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2735                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2736                 break;
2737         default:
2738                 break;
2739         }
2740 done:
2741         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2742         amdgpu_crtc->adjusted_clock = 0;
2743         amdgpu_crtc->encoder = NULL;
2744         amdgpu_crtc->connector = NULL;
2745 }
2746
2747 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2748                                   struct drm_display_mode *mode,
2749                                   struct drm_display_mode *adjusted_mode,
2750                                   int x, int y, struct drm_framebuffer *old_fb)
2751 {
2752         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2753
2754         if (!amdgpu_crtc->adjusted_clock)
2755                 return -EINVAL;
2756
2757         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2758         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2759         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2760         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2761         amdgpu_atombios_crtc_scaler_setup(crtc);
2762         dce_v8_0_cursor_reset(crtc);
2763         /* update the hw version fpr dpm */
2764         amdgpu_crtc->hw_mode = *adjusted_mode;
2765
2766         return 0;
2767 }
2768
2769 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2770                                      const struct drm_display_mode *mode,
2771                                      struct drm_display_mode *adjusted_mode)
2772 {
2773         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2774         struct drm_device *dev = crtc->dev;
2775         struct drm_encoder *encoder;
2776
2777         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2778         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2779                 if (encoder->crtc == crtc) {
2780                         amdgpu_crtc->encoder = encoder;
2781                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2782                         break;
2783                 }
2784         }
2785         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2786                 amdgpu_crtc->encoder = NULL;
2787                 amdgpu_crtc->connector = NULL;
2788                 return false;
2789         }
2790         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2791                 return false;
2792         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2793                 return false;
2794         /* pick pll */
2795         amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2796         /* if we can't get a PPLL for a non-DP encoder, fail */
2797         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2798             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2799                 return false;
2800
2801         return true;
2802 }
2803
2804 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2805                                   struct drm_framebuffer *old_fb)
2806 {
2807         return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2808 }
2809
2810 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2811                                          struct drm_framebuffer *fb,
2812                                          int x, int y, enum mode_set_atomic state)
2813 {
2814        return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2815 }
2816
2817 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2818         .dpms = dce_v8_0_crtc_dpms,
2819         .mode_fixup = dce_v8_0_crtc_mode_fixup,
2820         .mode_set = dce_v8_0_crtc_mode_set,
2821         .mode_set_base = dce_v8_0_crtc_set_base,
2822         .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2823         .prepare = dce_v8_0_crtc_prepare,
2824         .commit = dce_v8_0_crtc_commit,
2825         .load_lut = dce_v8_0_crtc_load_lut,
2826         .disable = dce_v8_0_crtc_disable,
2827 };
2828
2829 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2830 {
2831         struct amdgpu_crtc *amdgpu_crtc;
2832         int i;
2833
2834         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2835                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2836         if (amdgpu_crtc == NULL)
2837                 return -ENOMEM;
2838
2839         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2840
2841         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2842         amdgpu_crtc->crtc_id = index;
2843         adev->mode_info.crtcs[index] = amdgpu_crtc;
2844
2845         amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2846         amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2847         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2848         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2849
2850         for (i = 0; i < 256; i++) {
2851                 amdgpu_crtc->lut_r[i] = i << 2;
2852                 amdgpu_crtc->lut_g[i] = i << 2;
2853                 amdgpu_crtc->lut_b[i] = i << 2;
2854         }
2855
2856         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2857
2858         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2859         amdgpu_crtc->adjusted_clock = 0;
2860         amdgpu_crtc->encoder = NULL;
2861         amdgpu_crtc->connector = NULL;
2862         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2863
2864         return 0;
2865 }
2866
2867 static int dce_v8_0_early_init(void *handle)
2868 {
2869         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2870
2871         adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2872         adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2873
2874         dce_v8_0_set_display_funcs(adev);
2875         dce_v8_0_set_irq_funcs(adev);
2876
2877         adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2878
2879         switch (adev->asic_type) {
2880         case CHIP_BONAIRE:
2881         case CHIP_HAWAII:
2882                 adev->mode_info.num_hpd = 6;
2883                 adev->mode_info.num_dig = 6;
2884                 break;
2885         case CHIP_KAVERI:
2886                 adev->mode_info.num_hpd = 6;
2887                 adev->mode_info.num_dig = 7;
2888                 break;
2889         case CHIP_KABINI:
2890         case CHIP_MULLINS:
2891                 adev->mode_info.num_hpd = 6;
2892                 adev->mode_info.num_dig = 6; /* ? */
2893                 break;
2894         default:
2895                 /* FIXME: not supported yet */
2896                 return -EINVAL;
2897         }
2898
2899         return 0;
2900 }
2901
2902 static int dce_v8_0_sw_init(void *handle)
2903 {
2904         int r, i;
2905         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2906
2907         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2908                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2909                 if (r)
2910                         return r;
2911         }
2912
2913         for (i = 8; i < 20; i += 2) {
2914                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2915                 if (r)
2916                         return r;
2917         }
2918
2919         /* HPD hotplug */
2920         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2921         if (r)
2922                 return r;
2923
2924         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2925
2926         adev->ddev->mode_config.async_page_flip = true;
2927
2928         adev->ddev->mode_config.max_width = 16384;
2929         adev->ddev->mode_config.max_height = 16384;
2930
2931         adev->ddev->mode_config.preferred_depth = 24;
2932         adev->ddev->mode_config.prefer_shadow = 1;
2933
2934         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2935
2936         r = amdgpu_modeset_create_props(adev);
2937         if (r)
2938                 return r;
2939
2940         adev->ddev->mode_config.max_width = 16384;
2941         adev->ddev->mode_config.max_height = 16384;
2942
2943         /* allocate crtcs */
2944         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2945                 r = dce_v8_0_crtc_init(adev, i);
2946                 if (r)
2947                         return r;
2948         }
2949
2950         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2951                 amdgpu_print_display_setup(adev->ddev);
2952         else
2953                 return -EINVAL;
2954
2955         /* setup afmt */
2956         r = dce_v8_0_afmt_init(adev);
2957         if (r)
2958                 return r;
2959
2960         r = dce_v8_0_audio_init(adev);
2961         if (r)
2962                 return r;
2963
2964         drm_kms_helper_poll_init(adev->ddev);
2965
2966         adev->mode_info.mode_config_initialized = true;
2967         return 0;
2968 }
2969
2970 static int dce_v8_0_sw_fini(void *handle)
2971 {
2972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2973
2974         kfree(adev->mode_info.bios_hardcoded_edid);
2975
2976         drm_kms_helper_poll_fini(adev->ddev);
2977
2978         dce_v8_0_audio_fini(adev);
2979
2980         dce_v8_0_afmt_fini(adev);
2981
2982         drm_mode_config_cleanup(adev->ddev);
2983         adev->mode_info.mode_config_initialized = false;
2984
2985         return 0;
2986 }
2987
2988 static int dce_v8_0_hw_init(void *handle)
2989 {
2990         int i;
2991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2992
2993         /* init dig PHYs, disp eng pll */
2994         amdgpu_atombios_encoder_init_dig(adev);
2995         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2996
2997         /* initialize hpd */
2998         dce_v8_0_hpd_init(adev);
2999
3000         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3001                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3002         }
3003
3004         dce_v8_0_pageflip_interrupt_init(adev);
3005
3006         return 0;
3007 }
3008
3009 static int dce_v8_0_hw_fini(void *handle)
3010 {
3011         int i;
3012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3013
3014         dce_v8_0_hpd_fini(adev);
3015
3016         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3017                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3018         }
3019
3020         dce_v8_0_pageflip_interrupt_fini(adev);
3021
3022         return 0;
3023 }
3024
3025 static int dce_v8_0_suspend(void *handle)
3026 {
3027         return dce_v8_0_hw_fini(handle);
3028 }
3029
3030 static int dce_v8_0_resume(void *handle)
3031 {
3032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3033         int ret;
3034
3035         ret = dce_v8_0_hw_init(handle);
3036
3037         /* turn on the BL */
3038         if (adev->mode_info.bl_encoder) {
3039                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3040                                                                   adev->mode_info.bl_encoder);
3041                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3042                                                     bl_level);
3043         }
3044
3045         return ret;
3046 }
3047
3048 static bool dce_v8_0_is_idle(void *handle)
3049 {
3050         return true;
3051 }
3052
3053 static int dce_v8_0_wait_for_idle(void *handle)
3054 {
3055         return 0;
3056 }
3057
3058 static int dce_v8_0_soft_reset(void *handle)
3059 {
3060         u32 srbm_soft_reset = 0, tmp;
3061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3062
3063         if (dce_v8_0_is_display_hung(adev))
3064                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3065
3066         if (srbm_soft_reset) {
3067                 tmp = RREG32(mmSRBM_SOFT_RESET);
3068                 tmp |= srbm_soft_reset;
3069                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3070                 WREG32(mmSRBM_SOFT_RESET, tmp);
3071                 tmp = RREG32(mmSRBM_SOFT_RESET);
3072
3073                 udelay(50);
3074
3075                 tmp &= ~srbm_soft_reset;
3076                 WREG32(mmSRBM_SOFT_RESET, tmp);
3077                 tmp = RREG32(mmSRBM_SOFT_RESET);
3078
3079                 /* Wait a little for things to settle down */
3080                 udelay(50);
3081         }
3082         return 0;
3083 }
3084
3085 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3086                                                      int crtc,
3087                                                      enum amdgpu_interrupt_state state)
3088 {
3089         u32 reg_block, lb_interrupt_mask;
3090
3091         if (crtc >= adev->mode_info.num_crtc) {
3092                 DRM_DEBUG("invalid crtc %d\n", crtc);
3093                 return;
3094         }
3095
3096         switch (crtc) {
3097         case 0:
3098                 reg_block = CRTC0_REGISTER_OFFSET;
3099                 break;
3100         case 1:
3101                 reg_block = CRTC1_REGISTER_OFFSET;
3102                 break;
3103         case 2:
3104                 reg_block = CRTC2_REGISTER_OFFSET;
3105                 break;
3106         case 3:
3107                 reg_block = CRTC3_REGISTER_OFFSET;
3108                 break;
3109         case 4:
3110                 reg_block = CRTC4_REGISTER_OFFSET;
3111                 break;
3112         case 5:
3113                 reg_block = CRTC5_REGISTER_OFFSET;
3114                 break;
3115         default:
3116                 DRM_DEBUG("invalid crtc %d\n", crtc);
3117                 return;
3118         }
3119
3120         switch (state) {
3121         case AMDGPU_IRQ_STATE_DISABLE:
3122                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3123                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3124                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3125                 break;
3126         case AMDGPU_IRQ_STATE_ENABLE:
3127                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3128                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3129                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3130                 break;
3131         default:
3132                 break;
3133         }
3134 }
3135
3136 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3137                                                     int crtc,
3138                                                     enum amdgpu_interrupt_state state)
3139 {
3140         u32 reg_block, lb_interrupt_mask;
3141
3142         if (crtc >= adev->mode_info.num_crtc) {
3143                 DRM_DEBUG("invalid crtc %d\n", crtc);
3144                 return;
3145         }
3146
3147         switch (crtc) {
3148         case 0:
3149                 reg_block = CRTC0_REGISTER_OFFSET;
3150                 break;
3151         case 1:
3152                 reg_block = CRTC1_REGISTER_OFFSET;
3153                 break;
3154         case 2:
3155                 reg_block = CRTC2_REGISTER_OFFSET;
3156                 break;
3157         case 3:
3158                 reg_block = CRTC3_REGISTER_OFFSET;
3159                 break;
3160         case 4:
3161                 reg_block = CRTC4_REGISTER_OFFSET;
3162                 break;
3163         case 5:
3164                 reg_block = CRTC5_REGISTER_OFFSET;
3165                 break;
3166         default:
3167                 DRM_DEBUG("invalid crtc %d\n", crtc);
3168                 return;
3169         }
3170
3171         switch (state) {
3172         case AMDGPU_IRQ_STATE_DISABLE:
3173                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3174                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3175                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3176                 break;
3177         case AMDGPU_IRQ_STATE_ENABLE:
3178                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3179                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3180                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3181                 break;
3182         default:
3183                 break;
3184         }
3185 }
3186
3187 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3188                                             struct amdgpu_irq_src *src,
3189                                             unsigned type,
3190                                             enum amdgpu_interrupt_state state)
3191 {
3192         u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
3193
3194         switch (type) {
3195         case AMDGPU_HPD_1:
3196                 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
3197                 break;
3198         case AMDGPU_HPD_2:
3199                 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
3200                 break;
3201         case AMDGPU_HPD_3:
3202                 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
3203                 break;
3204         case AMDGPU_HPD_4:
3205                 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
3206                 break;
3207         case AMDGPU_HPD_5:
3208                 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
3209                 break;
3210         case AMDGPU_HPD_6:
3211                 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
3212                 break;
3213         default:
3214                 DRM_DEBUG("invalid hdp %d\n", type);
3215                 return 0;
3216         }
3217
3218         switch (state) {
3219         case AMDGPU_IRQ_STATE_DISABLE:
3220                 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3221                 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3222                 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3223                 break;
3224         case AMDGPU_IRQ_STATE_ENABLE:
3225                 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3226                 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3227                 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3228                 break;
3229         default:
3230                 break;
3231         }
3232
3233         return 0;
3234 }
3235
3236 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3237                                              struct amdgpu_irq_src *src,
3238                                              unsigned type,
3239                                              enum amdgpu_interrupt_state state)
3240 {
3241         switch (type) {
3242         case AMDGPU_CRTC_IRQ_VBLANK1:
3243                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3244                 break;
3245         case AMDGPU_CRTC_IRQ_VBLANK2:
3246                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3247                 break;
3248         case AMDGPU_CRTC_IRQ_VBLANK3:
3249                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3250                 break;
3251         case AMDGPU_CRTC_IRQ_VBLANK4:
3252                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3253                 break;
3254         case AMDGPU_CRTC_IRQ_VBLANK5:
3255                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3256                 break;
3257         case AMDGPU_CRTC_IRQ_VBLANK6:
3258                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3259                 break;
3260         case AMDGPU_CRTC_IRQ_VLINE1:
3261                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3262                 break;
3263         case AMDGPU_CRTC_IRQ_VLINE2:
3264                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3265                 break;
3266         case AMDGPU_CRTC_IRQ_VLINE3:
3267                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3268                 break;
3269         case AMDGPU_CRTC_IRQ_VLINE4:
3270                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3271                 break;
3272         case AMDGPU_CRTC_IRQ_VLINE5:
3273                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3274                 break;
3275         case AMDGPU_CRTC_IRQ_VLINE6:
3276                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3277                 break;
3278         default:
3279                 break;
3280         }
3281         return 0;
3282 }
3283
3284 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3285                              struct amdgpu_irq_src *source,
3286                              struct amdgpu_iv_entry *entry)
3287 {
3288         unsigned crtc = entry->src_id - 1;
3289         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3290         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3291
3292         switch (entry->src_data) {
3293         case 0: /* vblank */
3294                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3295                         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3296                 else
3297                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3298
3299                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3300                         drm_handle_vblank(adev->ddev, crtc);
3301                 }
3302                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3303                 break;
3304         case 1: /* vline */
3305                 if (disp_int & interrupt_status_offsets[crtc].vline)
3306                         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3307                 else
3308                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3309
3310                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3311                 break;
3312         default:
3313                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3314                 break;
3315         }
3316
3317         return 0;
3318 }
3319
3320 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3321                                                  struct amdgpu_irq_src *src,
3322                                                  unsigned type,
3323                                                  enum amdgpu_interrupt_state state)
3324 {
3325         u32 reg;
3326
3327         if (type >= adev->mode_info.num_crtc) {
3328                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3329                 return -EINVAL;
3330         }
3331
3332         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3333         if (state == AMDGPU_IRQ_STATE_DISABLE)
3334                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3335                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3336         else
3337                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3338                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3339
3340         return 0;
3341 }
3342
3343 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3344                                 struct amdgpu_irq_src *source,
3345                                 struct amdgpu_iv_entry *entry)
3346 {
3347         unsigned long flags;
3348         unsigned crtc_id;
3349         struct amdgpu_crtc *amdgpu_crtc;
3350         struct amdgpu_flip_work *works;
3351
3352         crtc_id = (entry->src_id - 8) >> 1;
3353         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3354
3355         if (crtc_id >= adev->mode_info.num_crtc) {
3356                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3357                 return -EINVAL;
3358         }
3359
3360         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3361             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3362                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3363                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3364
3365         /* IRQ could occur when in initial stage */
3366         if (amdgpu_crtc == NULL)
3367                 return 0;
3368
3369         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3370         works = amdgpu_crtc->pflip_works;
3371         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3372                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3373                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3374                                                 amdgpu_crtc->pflip_status,
3375                                                 AMDGPU_FLIP_SUBMITTED);
3376                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3377                 return 0;
3378         }
3379
3380         /* page flip completed. clean up */
3381         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3382         amdgpu_crtc->pflip_works = NULL;
3383
3384         /* wakeup usersapce */
3385         if (works->event)
3386                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3387
3388         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3389
3390         drm_crtc_vblank_put(&amdgpu_crtc->base);
3391         schedule_work(&works->unpin_work);
3392
3393         return 0;
3394 }
3395
3396 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3397                             struct amdgpu_irq_src *source,
3398                             struct amdgpu_iv_entry *entry)
3399 {
3400         uint32_t disp_int, mask, int_control, tmp;
3401         unsigned hpd;
3402
3403         if (entry->src_data >= adev->mode_info.num_hpd) {
3404                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3405                 return 0;
3406         }
3407
3408         hpd = entry->src_data;
3409         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3410         mask = interrupt_status_offsets[hpd].hpd;
3411         int_control = hpd_int_control_offsets[hpd];
3412
3413         if (disp_int & mask) {
3414                 tmp = RREG32(int_control);
3415                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3416                 WREG32(int_control, tmp);
3417                 schedule_work(&adev->hotplug_work);
3418                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3419         }
3420
3421         return 0;
3422
3423 }
3424
3425 static int dce_v8_0_set_clockgating_state(void *handle,
3426                                           enum amd_clockgating_state state)
3427 {
3428         return 0;
3429 }
3430
3431 static int dce_v8_0_set_powergating_state(void *handle,
3432                                           enum amd_powergating_state state)
3433 {
3434         return 0;
3435 }
3436
3437 const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3438         .name = "dce_v8_0",
3439         .early_init = dce_v8_0_early_init,
3440         .late_init = NULL,
3441         .sw_init = dce_v8_0_sw_init,
3442         .sw_fini = dce_v8_0_sw_fini,
3443         .hw_init = dce_v8_0_hw_init,
3444         .hw_fini = dce_v8_0_hw_fini,
3445         .suspend = dce_v8_0_suspend,
3446         .resume = dce_v8_0_resume,
3447         .is_idle = dce_v8_0_is_idle,
3448         .wait_for_idle = dce_v8_0_wait_for_idle,
3449         .soft_reset = dce_v8_0_soft_reset,
3450         .set_clockgating_state = dce_v8_0_set_clockgating_state,
3451         .set_powergating_state = dce_v8_0_set_powergating_state,
3452 };
3453
3454 static void
3455 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3456                           struct drm_display_mode *mode,
3457                           struct drm_display_mode *adjusted_mode)
3458 {
3459         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3460
3461         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3462
3463         /* need to call this here rather than in prepare() since we need some crtc info */
3464         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3465
3466         /* set scaler clears this on some chips */
3467         dce_v8_0_set_interleave(encoder->crtc, mode);
3468
3469         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3470                 dce_v8_0_afmt_enable(encoder, true);
3471                 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3472         }
3473 }
3474
3475 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3476 {
3477         struct amdgpu_device *adev = encoder->dev->dev_private;
3478         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3479         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3480
3481         if ((amdgpu_encoder->active_device &
3482              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3483             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3484              ENCODER_OBJECT_ID_NONE)) {
3485                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3486                 if (dig) {
3487                         dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3488                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3489                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3490                 }
3491         }
3492
3493         amdgpu_atombios_scratch_regs_lock(adev, true);
3494
3495         if (connector) {
3496                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3497
3498                 /* select the clock/data port if it uses a router */
3499                 if (amdgpu_connector->router.cd_valid)
3500                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3501
3502                 /* turn eDP panel on for mode set */
3503                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3504                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3505                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3506         }
3507
3508         /* this is needed for the pll/ss setup to work correctly in some cases */
3509         amdgpu_atombios_encoder_set_crtc_source(encoder);
3510         /* set up the FMT blocks */
3511         dce_v8_0_program_fmt(encoder);
3512 }
3513
3514 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3515 {
3516         struct drm_device *dev = encoder->dev;
3517         struct amdgpu_device *adev = dev->dev_private;
3518
3519         /* need to call this here as we need the crtc set up */
3520         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3521         amdgpu_atombios_scratch_regs_lock(adev, false);
3522 }
3523
3524 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3525 {
3526         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3527         struct amdgpu_encoder_atom_dig *dig;
3528
3529         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3530
3531         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3532                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3533                         dce_v8_0_afmt_enable(encoder, false);
3534                 dig = amdgpu_encoder->enc_priv;
3535                 dig->dig_encoder = -1;
3536         }
3537         amdgpu_encoder->active_device = 0;
3538 }
3539
3540 /* these are handled by the primary encoders */
3541 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3542 {
3543
3544 }
3545
3546 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3547 {
3548
3549 }
3550
3551 static void
3552 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3553                       struct drm_display_mode *mode,
3554                       struct drm_display_mode *adjusted_mode)
3555 {
3556
3557 }
3558
3559 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3560 {
3561
3562 }
3563
3564 static void
3565 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3566 {
3567
3568 }
3569
3570 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3571         .dpms = dce_v8_0_ext_dpms,
3572         .prepare = dce_v8_0_ext_prepare,
3573         .mode_set = dce_v8_0_ext_mode_set,
3574         .commit = dce_v8_0_ext_commit,
3575         .disable = dce_v8_0_ext_disable,
3576         /* no detect for TMDS/LVDS yet */
3577 };
3578
3579 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3580         .dpms = amdgpu_atombios_encoder_dpms,
3581         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3582         .prepare = dce_v8_0_encoder_prepare,
3583         .mode_set = dce_v8_0_encoder_mode_set,
3584         .commit = dce_v8_0_encoder_commit,
3585         .disable = dce_v8_0_encoder_disable,
3586         .detect = amdgpu_atombios_encoder_dig_detect,
3587 };
3588
3589 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3590         .dpms = amdgpu_atombios_encoder_dpms,
3591         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3592         .prepare = dce_v8_0_encoder_prepare,
3593         .mode_set = dce_v8_0_encoder_mode_set,
3594         .commit = dce_v8_0_encoder_commit,
3595         .detect = amdgpu_atombios_encoder_dac_detect,
3596 };
3597
3598 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3599 {
3600         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3601         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3602                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3603         kfree(amdgpu_encoder->enc_priv);
3604         drm_encoder_cleanup(encoder);
3605         kfree(amdgpu_encoder);
3606 }
3607
3608 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3609         .destroy = dce_v8_0_encoder_destroy,
3610 };
3611
3612 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3613                                  uint32_t encoder_enum,
3614                                  uint32_t supported_device,
3615                                  u16 caps)
3616 {
3617         struct drm_device *dev = adev->ddev;
3618         struct drm_encoder *encoder;
3619         struct amdgpu_encoder *amdgpu_encoder;
3620
3621         /* see if we already added it */
3622         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3623                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3624                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3625                         amdgpu_encoder->devices |= supported_device;
3626                         return;
3627                 }
3628
3629         }
3630
3631         /* add a new one */
3632         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3633         if (!amdgpu_encoder)
3634                 return;
3635
3636         encoder = &amdgpu_encoder->base;
3637         switch (adev->mode_info.num_crtc) {
3638         case 1:
3639                 encoder->possible_crtcs = 0x1;
3640                 break;
3641         case 2:
3642         default:
3643                 encoder->possible_crtcs = 0x3;
3644                 break;
3645         case 4:
3646                 encoder->possible_crtcs = 0xf;
3647                 break;
3648         case 6:
3649                 encoder->possible_crtcs = 0x3f;
3650                 break;
3651         }
3652
3653         amdgpu_encoder->enc_priv = NULL;
3654
3655         amdgpu_encoder->encoder_enum = encoder_enum;
3656         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3657         amdgpu_encoder->devices = supported_device;
3658         amdgpu_encoder->rmx_type = RMX_OFF;
3659         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3660         amdgpu_encoder->is_ext_encoder = false;
3661         amdgpu_encoder->caps = caps;
3662
3663         switch (amdgpu_encoder->encoder_id) {
3664         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3665         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3666                 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3667                                  DRM_MODE_ENCODER_DAC, NULL);
3668                 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3669                 break;
3670         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3671         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3672         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3673         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3674         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3675                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3676                         amdgpu_encoder->rmx_type = RMX_FULL;
3677                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3678                                          DRM_MODE_ENCODER_LVDS, NULL);
3679                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3680                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3681                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3682                                          DRM_MODE_ENCODER_DAC, NULL);
3683                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3684                 } else {
3685                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3686                                          DRM_MODE_ENCODER_TMDS, NULL);
3687                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3688                 }
3689                 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3690                 break;
3691         case ENCODER_OBJECT_ID_SI170B:
3692         case ENCODER_OBJECT_ID_CH7303:
3693         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3694         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3695         case ENCODER_OBJECT_ID_TITFP513:
3696         case ENCODER_OBJECT_ID_VT1623:
3697         case ENCODER_OBJECT_ID_HDMI_SI1930:
3698         case ENCODER_OBJECT_ID_TRAVIS:
3699         case ENCODER_OBJECT_ID_NUTMEG:
3700                 /* these are handled by the primary encoders */
3701                 amdgpu_encoder->is_ext_encoder = true;
3702                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3703                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3704                                          DRM_MODE_ENCODER_LVDS, NULL);
3705                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3706                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3707                                          DRM_MODE_ENCODER_DAC, NULL);
3708                 else
3709                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3710                                          DRM_MODE_ENCODER_TMDS, NULL);
3711                 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3712                 break;
3713         }
3714 }
3715
3716 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3717         .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3718         .bandwidth_update = &dce_v8_0_bandwidth_update,
3719         .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3720         .vblank_wait = &dce_v8_0_vblank_wait,
3721         .is_display_hung = &dce_v8_0_is_display_hung,
3722         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3723         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3724         .hpd_sense = &dce_v8_0_hpd_sense,
3725         .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3726         .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3727         .page_flip = &dce_v8_0_page_flip,
3728         .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3729         .add_encoder = &dce_v8_0_encoder_add,
3730         .add_connector = &amdgpu_connector_add,
3731         .stop_mc_access = &dce_v8_0_stop_mc_access,
3732         .resume_mc_access = &dce_v8_0_resume_mc_access,
3733 };
3734
3735 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3736 {
3737         if (adev->mode_info.funcs == NULL)
3738                 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3739 }
3740
3741 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3742         .set = dce_v8_0_set_crtc_interrupt_state,
3743         .process = dce_v8_0_crtc_irq,
3744 };
3745
3746 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3747         .set = dce_v8_0_set_pageflip_interrupt_state,
3748         .process = dce_v8_0_pageflip_irq,
3749 };
3750
3751 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3752         .set = dce_v8_0_set_hpd_interrupt_state,
3753         .process = dce_v8_0_hpd_irq,
3754 };
3755
3756 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3757 {
3758         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3759         adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3760
3761         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3762         adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3763
3764         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3765         adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3766 }