2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_ih.h"
26 #include "amdgpu_gfx.h"
27 #include "amdgpu_ucode.h"
28 #include "clearstate_si.h"
29 #include "bif/bif_3_0_d.h"
30 #include "bif/bif_3_0_sh_mask.h"
31 #include "oss/oss_1_0_d.h"
32 #include "oss/oss_1_0_sh_mask.h"
33 #include "gca/gfx_6_0_d.h"
34 #include "gca/gfx_6_0_sh_mask.h"
35 #include "gmc/gmc_6_0_d.h"
36 #include "gmc/gmc_6_0_sh_mask.h"
37 #include "dce/dce_6_0_d.h"
38 #include "dce/dce_6_0_sh_mask.h"
39 #include "gca/gfx_7_2_enum.h"
43 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
44 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
45 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
49 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
50 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
51 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
52 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
54 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
55 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
56 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
57 #define MICRO_TILE_MODE(x) ((x) << 0)
58 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
59 #define BANK_WIDTH(x) ((x) << 14)
60 #define BANK_HEIGHT(x) ((x) << 16)
61 #define MACRO_TILE_ASPECT(x) ((x) << 18)
62 #define NUM_BANKS(x) ((x) << 20)
64 static const u32 verde_rlc_save_restore_register_list[] =
66 (0x8000 << 16) | (0x98f4 >> 2),
68 (0x8040 << 16) | (0x98f4 >> 2),
70 (0x8000 << 16) | (0xe80 >> 2),
72 (0x8040 << 16) | (0xe80 >> 2),
74 (0x8000 << 16) | (0x89bc >> 2),
76 (0x8040 << 16) | (0x89bc >> 2),
78 (0x8000 << 16) | (0x8c1c >> 2),
80 (0x8040 << 16) | (0x8c1c >> 2),
82 (0x9c00 << 16) | (0x98f0 >> 2),
84 (0x9c00 << 16) | (0xe7c >> 2),
86 (0x8000 << 16) | (0x9148 >> 2),
88 (0x8040 << 16) | (0x9148 >> 2),
90 (0x9c00 << 16) | (0x9150 >> 2),
92 (0x9c00 << 16) | (0x897c >> 2),
94 (0x9c00 << 16) | (0x8d8c >> 2),
96 (0x9c00 << 16) | (0xac54 >> 2),
99 (0x9c00 << 16) | (0x98f8 >> 2),
101 (0x9c00 << 16) | (0x9910 >> 2),
103 (0x9c00 << 16) | (0x9914 >> 2),
105 (0x9c00 << 16) | (0x9918 >> 2),
107 (0x9c00 << 16) | (0x991c >> 2),
109 (0x9c00 << 16) | (0x9920 >> 2),
111 (0x9c00 << 16) | (0x9924 >> 2),
113 (0x9c00 << 16) | (0x9928 >> 2),
115 (0x9c00 << 16) | (0x992c >> 2),
117 (0x9c00 << 16) | (0x9930 >> 2),
119 (0x9c00 << 16) | (0x9934 >> 2),
121 (0x9c00 << 16) | (0x9938 >> 2),
123 (0x9c00 << 16) | (0x993c >> 2),
125 (0x9c00 << 16) | (0x9940 >> 2),
127 (0x9c00 << 16) | (0x9944 >> 2),
129 (0x9c00 << 16) | (0x9948 >> 2),
131 (0x9c00 << 16) | (0x994c >> 2),
133 (0x9c00 << 16) | (0x9950 >> 2),
135 (0x9c00 << 16) | (0x9954 >> 2),
137 (0x9c00 << 16) | (0x9958 >> 2),
139 (0x9c00 << 16) | (0x995c >> 2),
141 (0x9c00 << 16) | (0x9960 >> 2),
143 (0x9c00 << 16) | (0x9964 >> 2),
145 (0x9c00 << 16) | (0x9968 >> 2),
147 (0x9c00 << 16) | (0x996c >> 2),
149 (0x9c00 << 16) | (0x9970 >> 2),
151 (0x9c00 << 16) | (0x9974 >> 2),
153 (0x9c00 << 16) | (0x9978 >> 2),
155 (0x9c00 << 16) | (0x997c >> 2),
157 (0x9c00 << 16) | (0x9980 >> 2),
159 (0x9c00 << 16) | (0x9984 >> 2),
161 (0x9c00 << 16) | (0x9988 >> 2),
163 (0x9c00 << 16) | (0x998c >> 2),
165 (0x9c00 << 16) | (0x8c00 >> 2),
167 (0x9c00 << 16) | (0x8c14 >> 2),
169 (0x9c00 << 16) | (0x8c04 >> 2),
171 (0x9c00 << 16) | (0x8c08 >> 2),
173 (0x8000 << 16) | (0x9b7c >> 2),
175 (0x8040 << 16) | (0x9b7c >> 2),
177 (0x8000 << 16) | (0xe84 >> 2),
179 (0x8040 << 16) | (0xe84 >> 2),
181 (0x8000 << 16) | (0x89c0 >> 2),
183 (0x8040 << 16) | (0x89c0 >> 2),
185 (0x8000 << 16) | (0x914c >> 2),
187 (0x8040 << 16) | (0x914c >> 2),
189 (0x8000 << 16) | (0x8c20 >> 2),
191 (0x8040 << 16) | (0x8c20 >> 2),
193 (0x8000 << 16) | (0x9354 >> 2),
195 (0x8040 << 16) | (0x9354 >> 2),
197 (0x9c00 << 16) | (0x9060 >> 2),
199 (0x9c00 << 16) | (0x9364 >> 2),
201 (0x9c00 << 16) | (0x9100 >> 2),
203 (0x9c00 << 16) | (0x913c >> 2),
205 (0x8000 << 16) | (0x90e0 >> 2),
207 (0x8000 << 16) | (0x90e4 >> 2),
209 (0x8000 << 16) | (0x90e8 >> 2),
211 (0x8040 << 16) | (0x90e0 >> 2),
213 (0x8040 << 16) | (0x90e4 >> 2),
215 (0x8040 << 16) | (0x90e8 >> 2),
217 (0x9c00 << 16) | (0x8bcc >> 2),
219 (0x9c00 << 16) | (0x8b24 >> 2),
221 (0x9c00 << 16) | (0x88c4 >> 2),
223 (0x9c00 << 16) | (0x8e50 >> 2),
225 (0x9c00 << 16) | (0x8c0c >> 2),
227 (0x9c00 << 16) | (0x8e58 >> 2),
229 (0x9c00 << 16) | (0x8e5c >> 2),
231 (0x9c00 << 16) | (0x9508 >> 2),
233 (0x9c00 << 16) | (0x950c >> 2),
235 (0x9c00 << 16) | (0x9494 >> 2),
237 (0x9c00 << 16) | (0xac0c >> 2),
239 (0x9c00 << 16) | (0xac10 >> 2),
241 (0x9c00 << 16) | (0xac14 >> 2),
243 (0x9c00 << 16) | (0xae00 >> 2),
245 (0x9c00 << 16) | (0xac08 >> 2),
247 (0x9c00 << 16) | (0x88d4 >> 2),
249 (0x9c00 << 16) | (0x88c8 >> 2),
251 (0x9c00 << 16) | (0x88cc >> 2),
253 (0x9c00 << 16) | (0x89b0 >> 2),
255 (0x9c00 << 16) | (0x8b10 >> 2),
257 (0x9c00 << 16) | (0x8a14 >> 2),
259 (0x9c00 << 16) | (0x9830 >> 2),
261 (0x9c00 << 16) | (0x9834 >> 2),
263 (0x9c00 << 16) | (0x9838 >> 2),
265 (0x9c00 << 16) | (0x9a10 >> 2),
267 (0x8000 << 16) | (0x9870 >> 2),
269 (0x8000 << 16) | (0x9874 >> 2),
271 (0x8001 << 16) | (0x9870 >> 2),
273 (0x8001 << 16) | (0x9874 >> 2),
275 (0x8040 << 16) | (0x9870 >> 2),
277 (0x8040 << 16) | (0x9874 >> 2),
279 (0x8041 << 16) | (0x9870 >> 2),
281 (0x8041 << 16) | (0x9874 >> 2),
286 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
288 const char *chip_name;
291 const struct gfx_firmware_header_v1_0 *cp_hdr;
292 const struct rlc_firmware_header_v1_0 *rlc_hdr;
296 switch (adev->asic_type) {
298 chip_name = "tahiti";
301 chip_name = "pitcairn";
310 chip_name = "hainan";
315 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
316 err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
319 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
322 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
323 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
324 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
326 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
327 err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
330 err = amdgpu_ucode_validate(adev->gfx.me_fw);
333 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
334 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
335 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
337 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
338 err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
341 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
345 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
348 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
349 err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
352 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
353 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
354 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
355 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
359 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
360 release_firmware(adev->gfx.pfp_fw);
361 adev->gfx.pfp_fw = NULL;
362 release_firmware(adev->gfx.me_fw);
363 adev->gfx.me_fw = NULL;
364 release_firmware(adev->gfx.ce_fw);
365 adev->gfx.ce_fw = NULL;
366 release_firmware(adev->gfx.rlc_fw);
367 adev->gfx.rlc_fw = NULL;
372 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
374 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
375 u32 reg_offset, split_equal_to_row_size, *tilemode;
377 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
378 tilemode = adev->gfx.config.tile_mode_array;
380 switch (adev->gfx.config.mem_row_size_in_kb) {
382 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
386 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
389 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
393 if (adev->asic_type == CHIP_VERDE) {
394 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
395 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
396 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
397 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
398 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
399 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
400 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
401 NUM_BANKS(ADDR_SURF_16_BANK);
402 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
403 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
404 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
405 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
406 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
407 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
408 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
409 NUM_BANKS(ADDR_SURF_16_BANK);
410 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
411 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
412 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
413 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
414 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
415 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
416 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
417 NUM_BANKS(ADDR_SURF_16_BANK);
418 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
419 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
424 NUM_BANKS(ADDR_SURF_8_BANK) |
425 TILE_SPLIT(split_equal_to_row_size);
426 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
427 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
428 PIPE_CONFIG(ADDR_SURF_P4_8x16);
429 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
430 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
431 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
432 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
433 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
436 NUM_BANKS(ADDR_SURF_4_BANK);
437 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
438 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
439 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
440 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
441 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
444 NUM_BANKS(ADDR_SURF_4_BANK);
445 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
446 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
447 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
448 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
449 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
452 NUM_BANKS(ADDR_SURF_2_BANK);
453 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
454 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
455 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
456 PIPE_CONFIG(ADDR_SURF_P4_8x16);
457 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
458 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
459 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
460 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
461 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
464 NUM_BANKS(ADDR_SURF_16_BANK);
465 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
466 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
467 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
468 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
469 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
472 NUM_BANKS(ADDR_SURF_16_BANK);
473 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
474 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
475 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
476 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
477 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
480 NUM_BANKS(ADDR_SURF_16_BANK);
481 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
482 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
483 PIPE_CONFIG(ADDR_SURF_P4_8x16);
484 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
485 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
486 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
487 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
488 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
489 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
490 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
491 NUM_BANKS(ADDR_SURF_16_BANK);
492 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
493 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
494 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
495 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
496 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
497 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
498 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
499 NUM_BANKS(ADDR_SURF_16_BANK);
500 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
501 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
502 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
503 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
504 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
505 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
506 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
507 NUM_BANKS(ADDR_SURF_16_BANK);
508 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
509 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
510 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
514 NUM_BANKS(ADDR_SURF_16_BANK) |
515 TILE_SPLIT(split_equal_to_row_size);
516 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
517 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
518 PIPE_CONFIG(ADDR_SURF_P4_8x16);
519 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
520 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
521 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
522 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
525 NUM_BANKS(ADDR_SURF_16_BANK) |
526 TILE_SPLIT(split_equal_to_row_size);
527 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
528 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
529 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
530 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
533 NUM_BANKS(ADDR_SURF_16_BANK) |
534 TILE_SPLIT(split_equal_to_row_size);
535 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
536 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
537 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
538 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
539 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
540 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
541 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
542 NUM_BANKS(ADDR_SURF_8_BANK);
543 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
544 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
545 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
546 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
550 NUM_BANKS(ADDR_SURF_8_BANK);
551 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
552 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
553 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
554 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
555 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
558 NUM_BANKS(ADDR_SURF_4_BANK);
559 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
560 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
561 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
562 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
563 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
566 NUM_BANKS(ADDR_SURF_4_BANK);
567 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
568 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
569 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
570 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
571 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
572 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
573 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
574 NUM_BANKS(ADDR_SURF_2_BANK);
575 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
576 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
577 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
578 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
579 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
580 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
581 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
582 NUM_BANKS(ADDR_SURF_2_BANK);
583 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
584 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
585 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
586 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
587 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
588 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
589 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
590 NUM_BANKS(ADDR_SURF_2_BANK);
591 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
592 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
593 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
594 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
595 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
598 NUM_BANKS(ADDR_SURF_2_BANK);
599 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
600 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
601 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
602 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
603 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
606 NUM_BANKS(ADDR_SURF_2_BANK);
607 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
608 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
609 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
610 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
611 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
612 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
613 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
614 NUM_BANKS(ADDR_SURF_2_BANK);
615 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
616 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
617 } else if (adev->asic_type == CHIP_OLAND) {
618 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
619 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
620 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
621 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
622 NUM_BANKS(ADDR_SURF_16_BANK) |
623 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
626 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
627 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
628 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
629 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
630 NUM_BANKS(ADDR_SURF_16_BANK) |
631 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
632 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
633 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
634 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
635 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
636 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
637 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
638 NUM_BANKS(ADDR_SURF_16_BANK) |
639 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
640 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
641 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
642 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
643 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
644 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
645 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
646 NUM_BANKS(ADDR_SURF_16_BANK) |
647 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
648 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
649 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
650 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
651 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
652 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
653 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
654 NUM_BANKS(ADDR_SURF_16_BANK) |
655 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
656 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
657 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
658 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
659 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
660 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
661 TILE_SPLIT(split_equal_to_row_size) |
662 NUM_BANKS(ADDR_SURF_16_BANK) |
663 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
664 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
665 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
666 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
667 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
668 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
669 TILE_SPLIT(split_equal_to_row_size) |
670 NUM_BANKS(ADDR_SURF_16_BANK) |
671 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
672 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
673 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
674 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
675 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
676 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
677 TILE_SPLIT(split_equal_to_row_size) |
678 NUM_BANKS(ADDR_SURF_16_BANK) |
679 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
680 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
681 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
682 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
683 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
684 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
685 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
686 NUM_BANKS(ADDR_SURF_16_BANK) |
687 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
688 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
689 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
690 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
691 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
692 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
693 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
694 NUM_BANKS(ADDR_SURF_16_BANK) |
695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
698 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
699 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
700 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
701 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
702 NUM_BANKS(ADDR_SURF_16_BANK) |
703 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
704 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
705 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
706 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
707 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
708 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
709 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
710 NUM_BANKS(ADDR_SURF_16_BANK) |
711 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
712 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
713 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
714 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
715 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
716 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
717 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
718 NUM_BANKS(ADDR_SURF_16_BANK) |
719 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
720 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
721 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
722 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
723 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
724 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
725 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
726 NUM_BANKS(ADDR_SURF_16_BANK) |
727 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
728 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
729 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
730 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
731 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
732 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
733 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
734 NUM_BANKS(ADDR_SURF_16_BANK) |
735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
737 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
738 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
739 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
740 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
741 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
742 NUM_BANKS(ADDR_SURF_16_BANK) |
743 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
744 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
745 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
746 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
747 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
748 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
749 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
750 NUM_BANKS(ADDR_SURF_16_BANK) |
751 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
752 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
753 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
754 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
755 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
756 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
757 TILE_SPLIT(split_equal_to_row_size) |
758 NUM_BANKS(ADDR_SURF_16_BANK) |
759 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
760 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
761 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
762 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
763 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
764 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
765 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
766 NUM_BANKS(ADDR_SURF_16_BANK) |
767 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
768 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
769 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
770 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
771 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
772 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
773 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
774 NUM_BANKS(ADDR_SURF_16_BANK) |
775 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
776 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
777 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
778 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
779 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
780 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
781 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
782 NUM_BANKS(ADDR_SURF_16_BANK) |
783 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
784 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
785 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
786 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
787 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
788 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
789 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
790 NUM_BANKS(ADDR_SURF_16_BANK) |
791 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
792 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
793 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
794 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
795 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
796 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
797 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
798 NUM_BANKS(ADDR_SURF_8_BANK) |
799 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
800 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
801 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
802 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
803 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
804 } else if (adev->asic_type == CHIP_HAINAN) {
805 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
806 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
807 PIPE_CONFIG(ADDR_SURF_P2) |
808 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
809 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
812 NUM_BANKS(ADDR_SURF_16_BANK);
813 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
814 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
815 PIPE_CONFIG(ADDR_SURF_P2) |
816 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
817 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
820 NUM_BANKS(ADDR_SURF_16_BANK);
821 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
822 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
823 PIPE_CONFIG(ADDR_SURF_P2) |
824 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
825 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
828 NUM_BANKS(ADDR_SURF_16_BANK);
829 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
830 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
831 PIPE_CONFIG(ADDR_SURF_P2) |
832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
835 NUM_BANKS(ADDR_SURF_8_BANK) |
836 TILE_SPLIT(split_equal_to_row_size);
837 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
838 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
839 PIPE_CONFIG(ADDR_SURF_P2);
840 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
841 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
842 PIPE_CONFIG(ADDR_SURF_P2) |
843 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
844 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
845 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
846 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
847 NUM_BANKS(ADDR_SURF_8_BANK);
848 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
849 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
850 PIPE_CONFIG(ADDR_SURF_P2) |
851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
852 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
853 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
854 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
855 NUM_BANKS(ADDR_SURF_8_BANK);
856 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
857 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
858 PIPE_CONFIG(ADDR_SURF_P2) |
859 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
860 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
861 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
862 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
863 NUM_BANKS(ADDR_SURF_4_BANK);
864 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
865 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
866 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
867 PIPE_CONFIG(ADDR_SURF_P2);
868 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
869 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
870 PIPE_CONFIG(ADDR_SURF_P2) |
871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
872 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
873 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
874 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
875 NUM_BANKS(ADDR_SURF_16_BANK);
876 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
877 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
878 PIPE_CONFIG(ADDR_SURF_P2) |
879 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
880 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
881 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
882 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
883 NUM_BANKS(ADDR_SURF_16_BANK);
884 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
885 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
886 PIPE_CONFIG(ADDR_SURF_P2) |
887 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
888 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
889 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
890 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
891 NUM_BANKS(ADDR_SURF_16_BANK);
892 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
893 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
894 PIPE_CONFIG(ADDR_SURF_P2);
895 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
896 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
897 PIPE_CONFIG(ADDR_SURF_P2) |
898 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
899 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
900 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
901 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
902 NUM_BANKS(ADDR_SURF_16_BANK);
903 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
904 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
905 PIPE_CONFIG(ADDR_SURF_P2) |
906 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
907 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
908 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
909 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
910 NUM_BANKS(ADDR_SURF_16_BANK);
911 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
912 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
913 PIPE_CONFIG(ADDR_SURF_P2) |
914 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
915 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
916 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
917 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
918 NUM_BANKS(ADDR_SURF_16_BANK);
919 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
920 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
921 PIPE_CONFIG(ADDR_SURF_P2) |
922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
925 NUM_BANKS(ADDR_SURF_16_BANK) |
926 TILE_SPLIT(split_equal_to_row_size);
927 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
928 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
929 PIPE_CONFIG(ADDR_SURF_P2);
930 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
931 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
932 PIPE_CONFIG(ADDR_SURF_P2) |
933 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
934 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
935 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
936 NUM_BANKS(ADDR_SURF_16_BANK) |
937 TILE_SPLIT(split_equal_to_row_size);
938 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
939 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
940 PIPE_CONFIG(ADDR_SURF_P2) |
941 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
942 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
943 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
944 NUM_BANKS(ADDR_SURF_16_BANK) |
945 TILE_SPLIT(split_equal_to_row_size);
946 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
947 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
948 PIPE_CONFIG(ADDR_SURF_P2) |
949 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
950 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
951 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
952 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
953 NUM_BANKS(ADDR_SURF_8_BANK);
954 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
955 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 PIPE_CONFIG(ADDR_SURF_P2) |
957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
961 NUM_BANKS(ADDR_SURF_8_BANK);
962 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
963 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
964 PIPE_CONFIG(ADDR_SURF_P2) |
965 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
966 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
967 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
968 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
969 NUM_BANKS(ADDR_SURF_8_BANK);
970 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
971 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
972 PIPE_CONFIG(ADDR_SURF_P2) |
973 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
974 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
975 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
976 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
977 NUM_BANKS(ADDR_SURF_8_BANK);
978 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
979 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
980 PIPE_CONFIG(ADDR_SURF_P2) |
981 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
982 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
983 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
984 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
985 NUM_BANKS(ADDR_SURF_4_BANK);
986 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
987 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
988 PIPE_CONFIG(ADDR_SURF_P2) |
989 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
990 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
991 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
992 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
993 NUM_BANKS(ADDR_SURF_4_BANK);
994 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
995 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
996 PIPE_CONFIG(ADDR_SURF_P2) |
997 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
998 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
999 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1000 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1001 NUM_BANKS(ADDR_SURF_4_BANK);
1002 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1003 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1004 PIPE_CONFIG(ADDR_SURF_P2) |
1005 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1006 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1007 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1008 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1009 NUM_BANKS(ADDR_SURF_4_BANK);
1010 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1011 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1012 PIPE_CONFIG(ADDR_SURF_P2) |
1013 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1014 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1015 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1016 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1017 NUM_BANKS(ADDR_SURF_4_BANK);
1018 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1019 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1020 PIPE_CONFIG(ADDR_SURF_P2) |
1021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1022 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1023 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1024 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1025 NUM_BANKS(ADDR_SURF_4_BANK);
1026 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1027 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1028 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1029 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1030 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1031 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1032 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1033 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1034 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1035 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1036 NUM_BANKS(ADDR_SURF_16_BANK);
1037 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1038 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1039 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1040 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1041 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1042 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1043 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1044 NUM_BANKS(ADDR_SURF_16_BANK);
1045 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1046 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1047 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1049 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1050 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1051 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1052 NUM_BANKS(ADDR_SURF_16_BANK);
1053 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1054 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1055 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1059 NUM_BANKS(ADDR_SURF_4_BANK) |
1060 TILE_SPLIT(split_equal_to_row_size);
1061 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1062 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1063 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1064 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1065 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1068 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1069 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1070 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1071 NUM_BANKS(ADDR_SURF_2_BANK);
1072 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1073 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1074 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1075 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1076 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1077 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1078 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1079 NUM_BANKS(ADDR_SURF_2_BANK);
1080 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1081 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1082 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1083 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1084 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1085 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1086 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1087 NUM_BANKS(ADDR_SURF_2_BANK);
1088 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1089 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1090 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1092 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1094 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1095 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1096 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1097 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1098 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1099 NUM_BANKS(ADDR_SURF_16_BANK);
1100 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1101 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1102 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1103 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1104 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1105 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1106 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1107 NUM_BANKS(ADDR_SURF_16_BANK);
1108 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1109 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1110 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1111 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1112 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1113 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1114 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1115 NUM_BANKS(ADDR_SURF_16_BANK);
1116 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1117 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1118 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1119 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1120 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1121 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1122 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1123 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1124 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1125 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1126 NUM_BANKS(ADDR_SURF_16_BANK);
1127 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1128 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1129 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1130 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1131 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1132 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1133 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1134 NUM_BANKS(ADDR_SURF_16_BANK);
1135 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1136 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1137 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1138 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1139 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1140 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1141 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1142 NUM_BANKS(ADDR_SURF_16_BANK);
1143 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1144 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1145 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1149 NUM_BANKS(ADDR_SURF_16_BANK) |
1150 TILE_SPLIT(split_equal_to_row_size);
1151 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1152 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1153 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1154 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1155 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1156 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1157 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1160 NUM_BANKS(ADDR_SURF_16_BANK) |
1161 TILE_SPLIT(split_equal_to_row_size);
1162 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1163 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1164 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1165 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1166 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1167 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1168 NUM_BANKS(ADDR_SURF_16_BANK) |
1169 TILE_SPLIT(split_equal_to_row_size);
1170 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1171 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1172 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1173 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1174 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1176 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1177 NUM_BANKS(ADDR_SURF_4_BANK);
1178 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1179 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1180 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1181 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1182 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1185 NUM_BANKS(ADDR_SURF_4_BANK);
1186 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1187 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1188 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1189 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1190 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1193 NUM_BANKS(ADDR_SURF_2_BANK);
1194 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1195 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1196 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1197 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1198 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1201 NUM_BANKS(ADDR_SURF_2_BANK);
1202 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1203 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1204 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1205 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1206 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1209 NUM_BANKS(ADDR_SURF_2_BANK);
1210 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1211 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1212 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1213 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1214 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1215 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1216 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1217 NUM_BANKS(ADDR_SURF_2_BANK);
1218 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1219 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1220 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1221 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1222 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1223 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1224 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1225 NUM_BANKS(ADDR_SURF_2_BANK);
1226 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1227 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1230 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1231 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1232 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1233 NUM_BANKS(ADDR_SURF_2_BANK);
1234 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1235 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1236 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1238 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1241 NUM_BANKS(ADDR_SURF_2_BANK);
1242 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1243 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1244 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1246 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1249 NUM_BANKS(ADDR_SURF_2_BANK);
1250 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1251 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1253 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1257 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1258 u32 sh_num, u32 instance)
1262 if (instance == 0xffffffff)
1263 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1265 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1267 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1268 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1269 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1270 else if (se_num == 0xffffffff)
1271 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1272 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1273 else if (sh_num == 0xffffffff)
1274 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1275 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1277 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1278 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1279 WREG32(mmGRBM_GFX_INDEX, data);
1282 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1286 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1287 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1289 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1291 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1292 adev->gfx.config.max_sh_per_se);
1294 return ~data & mask;
1297 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1299 switch (adev->asic_type) {
1303 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1304 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1305 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1306 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1307 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1308 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1309 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1313 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1314 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1315 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1318 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1324 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1329 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1330 u32 raster_config, unsigned rb_mask,
1333 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1334 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1335 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1336 unsigned rb_per_se = num_rb / num_se;
1337 unsigned se_mask[4];
1340 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1341 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1342 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1343 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1345 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1346 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1347 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1349 for (se = 0; se < num_se; se++) {
1350 unsigned raster_config_se = raster_config;
1351 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1352 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1353 int idx = (se / 2) * 2;
1355 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1356 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1359 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1361 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1364 pkr0_mask &= rb_mask;
1365 pkr1_mask &= rb_mask;
1366 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1367 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1370 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1372 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1375 if (rb_per_se >= 2) {
1376 unsigned rb0_mask = 1 << (se * rb_per_se);
1377 unsigned rb1_mask = rb0_mask << 1;
1379 rb0_mask &= rb_mask;
1380 rb1_mask &= rb_mask;
1381 if (!rb0_mask || !rb1_mask) {
1382 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1386 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1389 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1392 if (rb_per_se > 2) {
1393 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1394 rb1_mask = rb0_mask << 1;
1395 rb0_mask &= rb_mask;
1396 rb1_mask &= rb_mask;
1397 if (!rb0_mask || !rb1_mask) {
1398 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1402 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1405 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1410 /* GRBM_GFX_INDEX has a different offset on SI */
1411 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1412 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1415 /* GRBM_GFX_INDEX has a different offset on SI */
1416 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1419 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1423 u32 raster_config = 0;
1425 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1426 adev->gfx.config.max_sh_per_se;
1427 unsigned num_rb_pipes;
1429 mutex_lock(&adev->grbm_idx_mutex);
1430 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1431 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1432 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1433 data = gfx_v6_0_get_rb_active_bitmap(adev);
1434 active_rbs |= data <<
1435 ((i * adev->gfx.config.max_sh_per_se + j) *
1436 rb_bitmap_width_per_sh);
1439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1441 adev->gfx.config.backend_enable_mask = active_rbs;
1442 adev->gfx.config.num_rbs = hweight32(active_rbs);
1444 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1445 adev->gfx.config.max_shader_engines, 16);
1447 gfx_v6_0_raster_config(adev, &raster_config);
1449 if (!adev->gfx.config.backend_enable_mask ||
1450 adev->gfx.config.num_rbs >= num_rb_pipes)
1451 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1453 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1454 adev->gfx.config.backend_enable_mask,
1457 /* cache the values for userspace */
1458 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1459 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1460 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1461 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1462 RREG32(mmCC_RB_BACKEND_DISABLE);
1463 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1464 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1465 adev->gfx.config.rb_config[i][j].raster_config =
1466 RREG32(mmPA_SC_RASTER_CONFIG);
1469 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1470 mutex_unlock(&adev->grbm_idx_mutex);
1473 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1481 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1482 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1484 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1487 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1491 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1492 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1494 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1495 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1499 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1505 mutex_lock(&adev->grbm_idx_mutex);
1506 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1507 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1508 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1509 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1510 active_cu = gfx_v6_0_get_cu_enabled(adev);
1513 for (k = 0; k < 16; k++) {
1515 if (active_cu & mask) {
1517 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1523 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1524 mutex_unlock(&adev->grbm_idx_mutex);
1527 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1529 adev->gfx.config.double_offchip_lds_buf = 0;
1532 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1534 u32 gb_addr_config = 0;
1535 u32 mc_shared_chmap, mc_arb_ramcfg;
1537 u32 hdp_host_path_cntl;
1540 switch (adev->asic_type) {
1542 adev->gfx.config.max_shader_engines = 2;
1543 adev->gfx.config.max_tile_pipes = 12;
1544 adev->gfx.config.max_cu_per_sh = 8;
1545 adev->gfx.config.max_sh_per_se = 2;
1546 adev->gfx.config.max_backends_per_se = 4;
1547 adev->gfx.config.max_texture_channel_caches = 12;
1548 adev->gfx.config.max_gprs = 256;
1549 adev->gfx.config.max_gs_threads = 32;
1550 adev->gfx.config.max_hw_contexts = 8;
1552 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1553 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1554 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1555 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1556 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1559 adev->gfx.config.max_shader_engines = 2;
1560 adev->gfx.config.max_tile_pipes = 8;
1561 adev->gfx.config.max_cu_per_sh = 5;
1562 adev->gfx.config.max_sh_per_se = 2;
1563 adev->gfx.config.max_backends_per_se = 4;
1564 adev->gfx.config.max_texture_channel_caches = 8;
1565 adev->gfx.config.max_gprs = 256;
1566 adev->gfx.config.max_gs_threads = 32;
1567 adev->gfx.config.max_hw_contexts = 8;
1569 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1570 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1571 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1572 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1573 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1576 adev->gfx.config.max_shader_engines = 1;
1577 adev->gfx.config.max_tile_pipes = 4;
1578 adev->gfx.config.max_cu_per_sh = 5;
1579 adev->gfx.config.max_sh_per_se = 2;
1580 adev->gfx.config.max_backends_per_se = 4;
1581 adev->gfx.config.max_texture_channel_caches = 4;
1582 adev->gfx.config.max_gprs = 256;
1583 adev->gfx.config.max_gs_threads = 32;
1584 adev->gfx.config.max_hw_contexts = 8;
1586 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1587 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1588 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1589 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1590 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1593 adev->gfx.config.max_shader_engines = 1;
1594 adev->gfx.config.max_tile_pipes = 4;
1595 adev->gfx.config.max_cu_per_sh = 6;
1596 adev->gfx.config.max_sh_per_se = 1;
1597 adev->gfx.config.max_backends_per_se = 2;
1598 adev->gfx.config.max_texture_channel_caches = 4;
1599 adev->gfx.config.max_gprs = 256;
1600 adev->gfx.config.max_gs_threads = 16;
1601 adev->gfx.config.max_hw_contexts = 8;
1603 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1604 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1605 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1606 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1607 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1610 adev->gfx.config.max_shader_engines = 1;
1611 adev->gfx.config.max_tile_pipes = 4;
1612 adev->gfx.config.max_cu_per_sh = 5;
1613 adev->gfx.config.max_sh_per_se = 1;
1614 adev->gfx.config.max_backends_per_se = 1;
1615 adev->gfx.config.max_texture_channel_caches = 2;
1616 adev->gfx.config.max_gprs = 256;
1617 adev->gfx.config.max_gs_threads = 16;
1618 adev->gfx.config.max_hw_contexts = 8;
1620 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1621 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1622 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1623 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1624 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1631 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1632 WREG32(mmSRBM_INT_CNTL, 1);
1633 WREG32(mmSRBM_INT_ACK, 1);
1635 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1637 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1638 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1639 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1641 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1642 adev->gfx.config.mem_max_burst_length_bytes = 256;
1643 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1644 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1645 if (adev->gfx.config.mem_row_size_in_kb > 4)
1646 adev->gfx.config.mem_row_size_in_kb = 4;
1647 adev->gfx.config.shader_engine_tile_size = 32;
1648 adev->gfx.config.num_gpus = 1;
1649 adev->gfx.config.multi_gpu_tile_size = 64;
1651 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1652 switch (adev->gfx.config.mem_row_size_in_kb) {
1655 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1658 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1661 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1664 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1665 if (adev->gfx.config.max_shader_engines == 2)
1666 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1667 adev->gfx.config.gb_addr_config = gb_addr_config;
1669 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1670 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1671 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1672 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1673 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1674 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1677 if (adev->has_uvd) {
1678 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1679 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1680 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1683 gfx_v6_0_tiling_mode_table_init(adev);
1685 gfx_v6_0_setup_rb(adev);
1687 gfx_v6_0_setup_spi(adev);
1689 gfx_v6_0_get_cu_info(adev);
1690 gfx_v6_0_config_init(adev);
1692 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1693 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1694 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1695 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1697 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1698 WREG32(mmSX_DEBUG_1, sx_debug_1);
1700 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1702 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1703 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1704 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1705 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1707 WREG32(mmVGT_NUM_INSTANCES, 1);
1708 WREG32(mmCP_PERFMON_CNTL, 0);
1709 WREG32(mmSQ_CONFIG, 0);
1710 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1711 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1713 WREG32(mmVGT_CACHE_INVALIDATION,
1714 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1715 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1717 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1718 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1720 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1721 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1722 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1723 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1724 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1725 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1726 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1727 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1729 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1730 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1732 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1733 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1739 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1741 adev->gfx.scratch.num_reg = 8;
1742 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1743 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1746 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1748 struct amdgpu_device *adev = ring->adev;
1754 r = amdgpu_gfx_scratch_get(adev, &scratch);
1756 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1759 WREG32(scratch, 0xCAFEDEAD);
1761 r = amdgpu_ring_alloc(ring, 3);
1763 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1764 amdgpu_gfx_scratch_free(adev, scratch);
1767 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1768 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1769 amdgpu_ring_write(ring, 0xDEADBEEF);
1770 amdgpu_ring_commit(ring);
1772 for (i = 0; i < adev->usec_timeout; i++) {
1773 tmp = RREG32(scratch);
1774 if (tmp == 0xDEADBEEF)
1778 if (i < adev->usec_timeout) {
1779 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1781 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1782 ring->idx, scratch, tmp);
1785 amdgpu_gfx_scratch_free(adev, scratch);
1789 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1791 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1792 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1796 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1797 u64 seq, unsigned flags)
1799 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1800 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1801 /* flush read cache over gart */
1802 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1803 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1804 amdgpu_ring_write(ring, 0);
1805 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1806 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1807 PACKET3_TC_ACTION_ENA |
1808 PACKET3_SH_KCACHE_ACTION_ENA |
1809 PACKET3_SH_ICACHE_ACTION_ENA);
1810 amdgpu_ring_write(ring, 0xFFFFFFFF);
1811 amdgpu_ring_write(ring, 0);
1812 amdgpu_ring_write(ring, 10); /* poll interval */
1813 /* EVENT_WRITE_EOP - flush caches, send int */
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1815 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1816 amdgpu_ring_write(ring, addr & 0xfffffffc);
1817 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1818 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1819 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1820 amdgpu_ring_write(ring, lower_32_bits(seq));
1821 amdgpu_ring_write(ring, upper_32_bits(seq));
1824 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1825 struct amdgpu_ib *ib,
1826 unsigned vmid, bool ctx_switch)
1828 u32 header, control = 0;
1830 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1832 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1833 amdgpu_ring_write(ring, 0);
1836 if (ib->flags & AMDGPU_IB_FLAG_CE)
1837 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1839 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1841 control |= ib->length_dw | (vmid << 24);
1843 amdgpu_ring_write(ring, header);
1844 amdgpu_ring_write(ring,
1848 (ib->gpu_addr & 0xFFFFFFFC));
1849 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1850 amdgpu_ring_write(ring, control);
1854 * gfx_v6_0_ring_test_ib - basic ring IB test
1856 * @ring: amdgpu_ring structure holding ring information
1858 * Allocate an IB and execute it on the gfx ring (SI).
1859 * Provides a basic gfx ring test to verify that IBs are working.
1860 * Returns 0 on success, error on failure.
1862 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1864 struct amdgpu_device *adev = ring->adev;
1865 struct amdgpu_ib ib;
1866 struct dma_fence *f = NULL;
1871 r = amdgpu_gfx_scratch_get(adev, &scratch);
1873 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1876 WREG32(scratch, 0xCAFEDEAD);
1877 memset(&ib, 0, sizeof(ib));
1878 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1880 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1883 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1884 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1885 ib.ptr[2] = 0xDEADBEEF;
1888 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1892 r = dma_fence_wait_timeout(f, false, timeout);
1894 DRM_ERROR("amdgpu: IB test timed out\n");
1898 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1901 tmp = RREG32(scratch);
1902 if (tmp == 0xDEADBEEF) {
1903 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1906 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1912 amdgpu_ib_free(adev, &ib, NULL);
1915 amdgpu_gfx_scratch_free(adev, scratch);
1919 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1923 WREG32(mmCP_ME_CNTL, 0);
1925 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1926 CP_ME_CNTL__PFP_HALT_MASK |
1927 CP_ME_CNTL__CE_HALT_MASK));
1928 WREG32(mmSCRATCH_UMSK, 0);
1929 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1930 adev->gfx.gfx_ring[i].ready = false;
1931 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1932 adev->gfx.compute_ring[i].ready = false;
1937 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1940 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1941 const struct gfx_firmware_header_v1_0 *ce_hdr;
1942 const struct gfx_firmware_header_v1_0 *me_hdr;
1943 const __le32 *fw_data;
1946 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1949 gfx_v6_0_cp_gfx_enable(adev, false);
1950 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1951 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1952 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1954 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1955 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1956 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1959 fw_data = (const __le32 *)
1960 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1961 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1962 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1963 for (i = 0; i < fw_size; i++)
1964 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1965 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1968 fw_data = (const __le32 *)
1969 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1970 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1971 WREG32(mmCP_CE_UCODE_ADDR, 0);
1972 for (i = 0; i < fw_size; i++)
1973 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1974 WREG32(mmCP_CE_UCODE_ADDR, 0);
1977 fw_data = (const __be32 *)
1978 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1979 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1980 WREG32(mmCP_ME_RAM_WADDR, 0);
1981 for (i = 0; i < fw_size; i++)
1982 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1983 WREG32(mmCP_ME_RAM_WADDR, 0);
1985 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1986 WREG32(mmCP_CE_UCODE_ADDR, 0);
1987 WREG32(mmCP_ME_RAM_WADDR, 0);
1988 WREG32(mmCP_ME_RAM_RADDR, 0);
1992 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1994 const struct cs_section_def *sect = NULL;
1995 const struct cs_extent_def *ext = NULL;
1996 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1999 r = amdgpu_ring_alloc(ring, 7 + 4);
2001 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2004 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2005 amdgpu_ring_write(ring, 0x1);
2006 amdgpu_ring_write(ring, 0x0);
2007 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2008 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2009 amdgpu_ring_write(ring, 0);
2010 amdgpu_ring_write(ring, 0);
2012 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2013 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2014 amdgpu_ring_write(ring, 0xc000);
2015 amdgpu_ring_write(ring, 0xe000);
2016 amdgpu_ring_commit(ring);
2018 gfx_v6_0_cp_gfx_enable(adev, true);
2020 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2022 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2026 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2027 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2029 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2030 for (ext = sect->section; ext->extent != NULL; ++ext) {
2031 if (sect->id == SECT_CONTEXT) {
2032 amdgpu_ring_write(ring,
2033 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2034 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2035 for (i = 0; i < ext->reg_count; i++)
2036 amdgpu_ring_write(ring, ext->extent[i]);
2041 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2042 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2044 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2045 amdgpu_ring_write(ring, 0);
2047 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2048 amdgpu_ring_write(ring, 0x00000316);
2049 amdgpu_ring_write(ring, 0x0000000e);
2050 amdgpu_ring_write(ring, 0x00000010);
2052 amdgpu_ring_commit(ring);
2057 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2059 struct amdgpu_ring *ring;
2065 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2066 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2068 /* Set the write pointer delay */
2069 WREG32(mmCP_RB_WPTR_DELAY, 0);
2071 WREG32(mmCP_DEBUG, 0);
2072 WREG32(mmSCRATCH_ADDR, 0);
2074 /* ring 0 - compute and gfx */
2075 /* Set ring buffer size */
2076 ring = &adev->gfx.gfx_ring[0];
2077 rb_bufsz = order_base_2(ring->ring_size / 8);
2078 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2081 tmp |= BUF_SWAP_32BIT;
2083 WREG32(mmCP_RB0_CNTL, tmp);
2085 /* Initialize the ring buffer's read and write pointers */
2086 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2088 WREG32(mmCP_RB0_WPTR, ring->wptr);
2090 /* set the wb address whether it's enabled or not */
2091 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2092 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2093 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2095 WREG32(mmSCRATCH_UMSK, 0);
2098 WREG32(mmCP_RB0_CNTL, tmp);
2100 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2102 /* start the rings */
2103 gfx_v6_0_cp_gfx_start(adev);
2105 r = amdgpu_ring_test_ring(ring);
2107 ring->ready = false;
2114 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2116 return ring->adev->wb.wb[ring->rptr_offs];
2119 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2121 struct amdgpu_device *adev = ring->adev;
2123 if (ring == &adev->gfx.gfx_ring[0])
2124 return RREG32(mmCP_RB0_WPTR);
2125 else if (ring == &adev->gfx.compute_ring[0])
2126 return RREG32(mmCP_RB1_WPTR);
2127 else if (ring == &adev->gfx.compute_ring[1])
2128 return RREG32(mmCP_RB2_WPTR);
2133 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2135 struct amdgpu_device *adev = ring->adev;
2137 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2138 (void)RREG32(mmCP_RB0_WPTR);
2141 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2143 struct amdgpu_device *adev = ring->adev;
2145 if (ring == &adev->gfx.compute_ring[0]) {
2146 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2147 (void)RREG32(mmCP_RB1_WPTR);
2148 } else if (ring == &adev->gfx.compute_ring[1]) {
2149 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2150 (void)RREG32(mmCP_RB2_WPTR);
2157 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2159 struct amdgpu_ring *ring;
2165 /* ring1 - compute only */
2166 /* Set ring buffer size */
2168 ring = &adev->gfx.compute_ring[0];
2169 rb_bufsz = order_base_2(ring->ring_size / 8);
2170 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2172 tmp |= BUF_SWAP_32BIT;
2174 WREG32(mmCP_RB1_CNTL, tmp);
2176 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2178 WREG32(mmCP_RB1_WPTR, ring->wptr);
2180 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2181 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2182 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2185 WREG32(mmCP_RB1_CNTL, tmp);
2186 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2188 ring = &adev->gfx.compute_ring[1];
2189 rb_bufsz = order_base_2(ring->ring_size / 8);
2190 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2192 tmp |= BUF_SWAP_32BIT;
2194 WREG32(mmCP_RB2_CNTL, tmp);
2196 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2198 WREG32(mmCP_RB2_WPTR, ring->wptr);
2199 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2200 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2201 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2204 WREG32(mmCP_RB2_CNTL, tmp);
2205 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2207 adev->gfx.compute_ring[0].ready = false;
2208 adev->gfx.compute_ring[1].ready = false;
2210 for (i = 0; i < 2; i++) {
2211 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2214 adev->gfx.compute_ring[i].ready = true;
2220 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2222 gfx_v6_0_cp_gfx_enable(adev, enable);
2225 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2227 return gfx_v6_0_cp_gfx_load_microcode(adev);
2230 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2233 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2238 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2239 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2241 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2242 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2243 WREG32(mmCP_INT_CNTL_RING0, tmp);
2246 /* read a gfx register */
2247 tmp = RREG32(mmDB_DEPTH_INFO);
2249 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2250 for (i = 0; i < adev->usec_timeout; i++) {
2251 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2258 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2262 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2264 r = gfx_v6_0_cp_load_microcode(adev);
2268 r = gfx_v6_0_cp_gfx_resume(adev);
2271 r = gfx_v6_0_cp_compute_resume(adev);
2275 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2280 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2282 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2283 uint32_t seq = ring->fence_drv.sync_seq;
2284 uint64_t addr = ring->fence_drv.gpu_addr;
2286 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2287 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2288 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2289 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2290 amdgpu_ring_write(ring, addr & 0xfffffffc);
2291 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2292 amdgpu_ring_write(ring, seq);
2293 amdgpu_ring_write(ring, 0xffffffff);
2294 amdgpu_ring_write(ring, 4); /* poll interval */
2297 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2298 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2299 amdgpu_ring_write(ring, 0);
2300 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2301 amdgpu_ring_write(ring, 0);
2305 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2306 unsigned vmid, uint64_t pd_addr)
2308 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2310 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2312 /* wait for the invalidate to complete */
2313 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2314 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2315 WAIT_REG_MEM_ENGINE(0))); /* me */
2316 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2317 amdgpu_ring_write(ring, 0);
2318 amdgpu_ring_write(ring, 0); /* ref */
2319 amdgpu_ring_write(ring, 0); /* mask */
2320 amdgpu_ring_write(ring, 0x20); /* poll interval */
2323 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2324 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2325 amdgpu_ring_write(ring, 0x0);
2327 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2328 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2329 amdgpu_ring_write(ring, 0);
2330 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2331 amdgpu_ring_write(ring, 0);
2335 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2336 uint32_t reg, uint32_t val)
2338 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2340 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2341 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2342 WRITE_DATA_DST_SEL(0)));
2343 amdgpu_ring_write(ring, reg);
2344 amdgpu_ring_write(ring, 0);
2345 amdgpu_ring_write(ring, val);
2348 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2350 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2351 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2352 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2355 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2358 volatile u32 *dst_ptr;
2360 u64 reg_list_mc_addr;
2361 const struct cs_section_def *cs_data;
2364 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2365 adev->gfx.rlc.reg_list_size =
2366 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2368 adev->gfx.rlc.cs_data = si_cs_data;
2369 src_ptr = adev->gfx.rlc.reg_list;
2370 dws = adev->gfx.rlc.reg_list_size;
2371 cs_data = adev->gfx.rlc.cs_data;
2374 /* save restore block */
2375 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2376 AMDGPU_GEM_DOMAIN_VRAM,
2377 &adev->gfx.rlc.save_restore_obj,
2378 &adev->gfx.rlc.save_restore_gpu_addr,
2379 (void **)&adev->gfx.rlc.sr_ptr);
2381 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2383 gfx_v6_0_rlc_fini(adev);
2387 /* write the sr buffer */
2388 dst_ptr = adev->gfx.rlc.sr_ptr;
2389 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2390 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2392 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2393 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2397 /* clear state block */
2398 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2399 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2401 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2402 AMDGPU_GEM_DOMAIN_VRAM,
2403 &adev->gfx.rlc.clear_state_obj,
2404 &adev->gfx.rlc.clear_state_gpu_addr,
2405 (void **)&adev->gfx.rlc.cs_ptr);
2407 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2408 gfx_v6_0_rlc_fini(adev);
2412 /* set up the cs buffer */
2413 dst_ptr = adev->gfx.rlc.cs_ptr;
2414 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2415 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2416 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2417 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2418 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2419 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2420 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2426 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2428 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2431 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2432 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2436 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2440 for (i = 0; i < adev->usec_timeout; i++) {
2441 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2446 for (i = 0; i < adev->usec_timeout; i++) {
2447 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2453 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2457 tmp = RREG32(mmRLC_CNTL);
2459 WREG32(mmRLC_CNTL, rlc);
2462 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2466 orig = data = RREG32(mmRLC_CNTL);
2468 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2469 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2470 WREG32(mmRLC_CNTL, data);
2472 gfx_v6_0_wait_for_rlc_serdes(adev);
2478 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2480 WREG32(mmRLC_CNTL, 0);
2482 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2483 gfx_v6_0_wait_for_rlc_serdes(adev);
2486 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2488 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2490 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2495 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2497 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2499 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2503 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2507 /* Enable LBPW only for DDR3 */
2508 tmp = RREG32(mmMC_SEQ_MISC0);
2509 if ((tmp & 0xF0000000) == 0xB0000000)
2514 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2518 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2521 const struct rlc_firmware_header_v1_0 *hdr;
2522 const __le32 *fw_data;
2526 if (!adev->gfx.rlc_fw)
2529 gfx_v6_0_rlc_stop(adev);
2530 gfx_v6_0_rlc_reset(adev);
2531 gfx_v6_0_init_pg(adev);
2532 gfx_v6_0_init_cg(adev);
2534 WREG32(mmRLC_RL_BASE, 0);
2535 WREG32(mmRLC_RL_SIZE, 0);
2536 WREG32(mmRLC_LB_CNTL, 0);
2537 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2538 WREG32(mmRLC_LB_CNTR_INIT, 0);
2539 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2541 WREG32(mmRLC_MC_CNTL, 0);
2542 WREG32(mmRLC_UCODE_CNTL, 0);
2544 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2545 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2546 fw_data = (const __le32 *)
2547 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2549 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2551 for (i = 0; i < fw_size; i++) {
2552 WREG32(mmRLC_UCODE_ADDR, i);
2553 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2555 WREG32(mmRLC_UCODE_ADDR, 0);
2557 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2558 gfx_v6_0_rlc_start(adev);
2563 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2565 u32 data, orig, tmp;
2567 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2569 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2570 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2572 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2574 tmp = gfx_v6_0_halt_rlc(adev);
2576 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2577 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2578 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2580 gfx_v6_0_wait_for_rlc_serdes(adev);
2581 gfx_v6_0_update_rlc(adev, tmp);
2583 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2585 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2587 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2589 RREG32(mmCB_CGTT_SCLK_CTRL);
2590 RREG32(mmCB_CGTT_SCLK_CTRL);
2591 RREG32(mmCB_CGTT_SCLK_CTRL);
2592 RREG32(mmCB_CGTT_SCLK_CTRL);
2594 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2598 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2602 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2605 u32 data, orig, tmp = 0;
2607 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2608 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2611 WREG32(mmCGTS_SM_CTRL_REG, data);
2613 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2614 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2615 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2617 WREG32(mmCP_MEM_SLP_CNTL, data);
2620 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2623 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2625 tmp = gfx_v6_0_halt_rlc(adev);
2627 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2628 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2629 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2631 gfx_v6_0_update_rlc(adev, tmp);
2633 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2636 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2638 data = RREG32(mmCP_MEM_SLP_CNTL);
2639 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2640 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2641 WREG32(mmCP_MEM_SLP_CNTL, data);
2643 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2644 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2646 WREG32(mmCGTS_SM_CTRL_REG, data);
2648 tmp = gfx_v6_0_halt_rlc(adev);
2650 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2651 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2652 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2654 gfx_v6_0_update_rlc(adev, tmp);
2658 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2661 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2663 gfx_v6_0_enable_mgcg(adev, true);
2664 gfx_v6_0_enable_cgcg(adev, true);
2666 gfx_v6_0_enable_cgcg(adev, false);
2667 gfx_v6_0_enable_mgcg(adev, false);
2669 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2673 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2678 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2683 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2687 orig = data = RREG32(mmRLC_PG_CNTL);
2688 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2693 WREG32(mmRLC_PG_CNTL, data);
2696 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2700 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2702 const __le32 *fw_data;
2703 volatile u32 *dst_ptr;
2704 int me, i, max_me = 4;
2706 u32 table_offset, table_size;
2708 if (adev->asic_type == CHIP_KAVERI)
2711 if (adev->gfx.rlc.cp_table_ptr == NULL)
2714 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2715 for (me = 0; me < max_me; me++) {
2717 const struct gfx_firmware_header_v1_0 *hdr =
2718 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2719 fw_data = (const __le32 *)
2720 (adev->gfx.ce_fw->data +
2721 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2722 table_offset = le32_to_cpu(hdr->jt_offset);
2723 table_size = le32_to_cpu(hdr->jt_size);
2724 } else if (me == 1) {
2725 const struct gfx_firmware_header_v1_0 *hdr =
2726 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2727 fw_data = (const __le32 *)
2728 (adev->gfx.pfp_fw->data +
2729 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2730 table_offset = le32_to_cpu(hdr->jt_offset);
2731 table_size = le32_to_cpu(hdr->jt_size);
2732 } else if (me == 2) {
2733 const struct gfx_firmware_header_v1_0 *hdr =
2734 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2735 fw_data = (const __le32 *)
2736 (adev->gfx.me_fw->data +
2737 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2738 table_offset = le32_to_cpu(hdr->jt_offset);
2739 table_size = le32_to_cpu(hdr->jt_size);
2740 } else if (me == 3) {
2741 const struct gfx_firmware_header_v1_0 *hdr =
2742 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2743 fw_data = (const __le32 *)
2744 (adev->gfx.mec_fw->data +
2745 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2746 table_offset = le32_to_cpu(hdr->jt_offset);
2747 table_size = le32_to_cpu(hdr->jt_size);
2749 const struct gfx_firmware_header_v1_0 *hdr =
2750 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2751 fw_data = (const __le32 *)
2752 (adev->gfx.mec2_fw->data +
2753 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2754 table_offset = le32_to_cpu(hdr->jt_offset);
2755 table_size = le32_to_cpu(hdr->jt_size);
2758 for (i = 0; i < table_size; i ++) {
2759 dst_ptr[bo_offset + i] =
2760 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2763 bo_offset += table_size;
2767 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2770 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2771 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2772 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2773 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2775 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2776 (void)RREG32(mmDB_RENDER_CONTROL);
2780 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2784 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2786 tmp = RREG32(mmRLC_MAX_PG_CU);
2787 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2788 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2789 WREG32(mmRLC_MAX_PG_CU, tmp);
2792 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2797 orig = data = RREG32(mmRLC_PG_CNTL);
2798 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2799 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2801 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2803 WREG32(mmRLC_PG_CNTL, data);
2806 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2811 orig = data = RREG32(mmRLC_PG_CNTL);
2812 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2813 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2815 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2817 WREG32(mmRLC_PG_CNTL, data);
2820 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2824 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2825 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2826 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2828 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2829 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2830 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2831 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2832 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2835 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2837 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2838 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2839 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2842 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2845 const struct cs_section_def *sect = NULL;
2846 const struct cs_extent_def *ext = NULL;
2848 if (adev->gfx.rlc.cs_data == NULL)
2851 /* begin clear state */
2853 /* context control state */
2856 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2857 for (ext = sect->section; ext->extent != NULL; ++ext) {
2858 if (sect->id == SECT_CONTEXT)
2859 count += 2 + ext->reg_count;
2864 /* pa_sc_raster_config */
2866 /* end clear state */
2874 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2875 volatile u32 *buffer)
2878 const struct cs_section_def *sect = NULL;
2879 const struct cs_extent_def *ext = NULL;
2881 if (adev->gfx.rlc.cs_data == NULL)
2886 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2887 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2888 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2889 buffer[count++] = cpu_to_le32(0x80000000);
2890 buffer[count++] = cpu_to_le32(0x80000000);
2892 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2893 for (ext = sect->section; ext->extent != NULL; ++ext) {
2894 if (sect->id == SECT_CONTEXT) {
2896 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2897 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2898 for (i = 0; i < ext->reg_count; i++)
2899 buffer[count++] = cpu_to_le32(ext->extent[i]);
2906 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2907 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2908 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2910 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2911 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2913 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2914 buffer[count++] = cpu_to_le32(0);
2917 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2919 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2920 AMD_PG_SUPPORT_GFX_SMG |
2921 AMD_PG_SUPPORT_GFX_DMG |
2923 AMD_PG_SUPPORT_GDS |
2924 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2925 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2926 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2927 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2928 gfx_v6_0_init_gfx_cgpg(adev);
2929 gfx_v6_0_enable_cp_pg(adev, true);
2930 gfx_v6_0_enable_gds_pg(adev, true);
2932 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2933 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2936 gfx_v6_0_init_ao_cu_mask(adev);
2937 gfx_v6_0_update_gfx_pg(adev, true);
2940 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2941 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2945 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2947 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2948 AMD_PG_SUPPORT_GFX_SMG |
2949 AMD_PG_SUPPORT_GFX_DMG |
2951 AMD_PG_SUPPORT_GDS |
2952 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2953 gfx_v6_0_update_gfx_pg(adev, false);
2954 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2955 gfx_v6_0_enable_cp_pg(adev, false);
2956 gfx_v6_0_enable_gds_pg(adev, false);
2961 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2965 mutex_lock(&adev->gfx.gpu_clock_mutex);
2966 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2967 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2968 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2969 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2973 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2975 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2976 gfx_v6_0_ring_emit_vgt_flush(ring);
2977 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2978 amdgpu_ring_write(ring, 0x80000000);
2979 amdgpu_ring_write(ring, 0);
2983 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2985 WREG32(mmSQ_IND_INDEX,
2986 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2987 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2988 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2989 (SQ_IND_INDEX__FORCE_READ_MASK));
2990 return RREG32(mmSQ_IND_DATA);
2993 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2994 uint32_t wave, uint32_t thread,
2995 uint32_t regno, uint32_t num, uint32_t *out)
2997 WREG32(mmSQ_IND_INDEX,
2998 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2999 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3000 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3001 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3002 (SQ_IND_INDEX__FORCE_READ_MASK) |
3003 (SQ_IND_INDEX__AUTO_INCR_MASK));
3005 *(out++) = RREG32(mmSQ_IND_DATA);
3008 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3010 /* type 0 wave data */
3011 dst[(*no_fields)++] = 0;
3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3016 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3018 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3019 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3025 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3026 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3027 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3028 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3032 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3033 uint32_t wave, uint32_t start,
3034 uint32_t size, uint32_t *dst)
3037 adev, simd, wave, 0,
3038 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3041 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3042 u32 me, u32 pipe, u32 q)
3044 DRM_INFO("Not implemented\n");
3047 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3048 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3049 .select_se_sh = &gfx_v6_0_select_se_sh,
3050 .read_wave_data = &gfx_v6_0_read_wave_data,
3051 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3052 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3055 static int gfx_v6_0_early_init(void *handle)
3057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3059 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3060 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3061 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3062 gfx_v6_0_set_ring_funcs(adev);
3063 gfx_v6_0_set_irq_funcs(adev);
3068 static int gfx_v6_0_sw_init(void *handle)
3070 struct amdgpu_ring *ring;
3071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3074 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3078 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3082 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3086 gfx_v6_0_scratch_init(adev);
3088 r = gfx_v6_0_init_microcode(adev);
3090 DRM_ERROR("Failed to load gfx firmware!\n");
3094 r = gfx_v6_0_rlc_init(adev);
3096 DRM_ERROR("Failed to init rlc BOs!\n");
3100 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3101 ring = &adev->gfx.gfx_ring[i];
3102 ring->ring_obj = NULL;
3103 sprintf(ring->name, "gfx");
3104 r = amdgpu_ring_init(adev, ring, 1024,
3105 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3110 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3113 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3114 DRM_ERROR("Too many (%d) compute rings!\n", i);
3117 ring = &adev->gfx.compute_ring[i];
3118 ring->ring_obj = NULL;
3119 ring->use_doorbell = false;
3120 ring->doorbell_index = 0;
3124 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3125 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3126 r = amdgpu_ring_init(adev, ring, 1024,
3127 &adev->gfx.eop_irq, irq_type);
3135 static int gfx_v6_0_sw_fini(void *handle)
3138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3140 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3141 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3142 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3143 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3145 gfx_v6_0_rlc_fini(adev);
3150 static int gfx_v6_0_hw_init(void *handle)
3153 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3155 gfx_v6_0_gpu_init(adev);
3157 r = gfx_v6_0_rlc_resume(adev);
3161 r = gfx_v6_0_cp_resume(adev);
3165 adev->gfx.ce_ram_size = 0x8000;
3170 static int gfx_v6_0_hw_fini(void *handle)
3172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3174 gfx_v6_0_cp_enable(adev, false);
3175 gfx_v6_0_rlc_stop(adev);
3176 gfx_v6_0_fini_pg(adev);
3181 static int gfx_v6_0_suspend(void *handle)
3183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3185 return gfx_v6_0_hw_fini(adev);
3188 static int gfx_v6_0_resume(void *handle)
3190 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3192 return gfx_v6_0_hw_init(adev);
3195 static bool gfx_v6_0_is_idle(void *handle)
3197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3199 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3205 static int gfx_v6_0_wait_for_idle(void *handle)
3208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3210 for (i = 0; i < adev->usec_timeout; i++) {
3211 if (gfx_v6_0_is_idle(handle))
3218 static int gfx_v6_0_soft_reset(void *handle)
3223 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3224 enum amdgpu_interrupt_state state)
3229 case AMDGPU_IRQ_STATE_DISABLE:
3230 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3231 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3232 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3234 case AMDGPU_IRQ_STATE_ENABLE:
3235 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3236 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3237 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3244 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3246 enum amdgpu_interrupt_state state)
3250 case AMDGPU_IRQ_STATE_DISABLE:
3252 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3253 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3254 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3257 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3258 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3259 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3263 case AMDGPU_IRQ_STATE_ENABLE:
3265 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3266 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3267 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3270 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3271 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3272 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3284 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3285 struct amdgpu_irq_src *src,
3287 enum amdgpu_interrupt_state state)
3292 case AMDGPU_IRQ_STATE_DISABLE:
3293 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3294 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3295 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3297 case AMDGPU_IRQ_STATE_ENABLE:
3298 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3299 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3300 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3309 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3310 struct amdgpu_irq_src *src,
3312 enum amdgpu_interrupt_state state)
3317 case AMDGPU_IRQ_STATE_DISABLE:
3318 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3319 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3320 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3322 case AMDGPU_IRQ_STATE_ENABLE:
3323 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3324 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3325 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3334 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3335 struct amdgpu_irq_src *src,
3337 enum amdgpu_interrupt_state state)
3340 case AMDGPU_CP_IRQ_GFX_EOP:
3341 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3343 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3344 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3346 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3347 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3355 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3356 struct amdgpu_irq_src *source,
3357 struct amdgpu_iv_entry *entry)
3359 switch (entry->ring_id) {
3361 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3365 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3373 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3374 struct amdgpu_irq_src *source,
3375 struct amdgpu_iv_entry *entry)
3377 DRM_ERROR("Illegal register access in command stream\n");
3378 schedule_work(&adev->reset_work);
3382 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3383 struct amdgpu_irq_src *source,
3384 struct amdgpu_iv_entry *entry)
3386 DRM_ERROR("Illegal instruction in command stream\n");
3387 schedule_work(&adev->reset_work);
3391 static int gfx_v6_0_set_clockgating_state(void *handle,
3392 enum amd_clockgating_state state)
3395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3397 if (state == AMD_CG_STATE_GATE)
3400 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3402 gfx_v6_0_enable_mgcg(adev, true);
3403 gfx_v6_0_enable_cgcg(adev, true);
3405 gfx_v6_0_enable_cgcg(adev, false);
3406 gfx_v6_0_enable_mgcg(adev, false);
3408 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3413 static int gfx_v6_0_set_powergating_state(void *handle,
3414 enum amd_powergating_state state)
3417 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3419 if (state == AMD_PG_STATE_GATE)
3422 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3423 AMD_PG_SUPPORT_GFX_SMG |
3424 AMD_PG_SUPPORT_GFX_DMG |
3426 AMD_PG_SUPPORT_GDS |
3427 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3428 gfx_v6_0_update_gfx_pg(adev, gate);
3429 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3430 gfx_v6_0_enable_cp_pg(adev, gate);
3431 gfx_v6_0_enable_gds_pg(adev, gate);
3438 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3440 .early_init = gfx_v6_0_early_init,
3442 .sw_init = gfx_v6_0_sw_init,
3443 .sw_fini = gfx_v6_0_sw_fini,
3444 .hw_init = gfx_v6_0_hw_init,
3445 .hw_fini = gfx_v6_0_hw_fini,
3446 .suspend = gfx_v6_0_suspend,
3447 .resume = gfx_v6_0_resume,
3448 .is_idle = gfx_v6_0_is_idle,
3449 .wait_for_idle = gfx_v6_0_wait_for_idle,
3450 .soft_reset = gfx_v6_0_soft_reset,
3451 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3452 .set_powergating_state = gfx_v6_0_set_powergating_state,
3455 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3456 .type = AMDGPU_RING_TYPE_GFX,
3459 .support_64bit_ptrs = false,
3460 .get_rptr = gfx_v6_0_ring_get_rptr,
3461 .get_wptr = gfx_v6_0_ring_get_wptr,
3462 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3464 5 + 5 + /* hdp flush / invalidate */
3465 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3466 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3467 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3468 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3469 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3470 .emit_ib = gfx_v6_0_ring_emit_ib,
3471 .emit_fence = gfx_v6_0_ring_emit_fence,
3472 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3473 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3474 .test_ring = gfx_v6_0_ring_test_ring,
3475 .test_ib = gfx_v6_0_ring_test_ib,
3476 .insert_nop = amdgpu_ring_insert_nop,
3477 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3478 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3481 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3482 .type = AMDGPU_RING_TYPE_COMPUTE,
3485 .get_rptr = gfx_v6_0_ring_get_rptr,
3486 .get_wptr = gfx_v6_0_ring_get_wptr,
3487 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3489 5 + 5 + /* hdp flush / invalidate */
3490 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3491 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3492 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3493 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3494 .emit_ib = gfx_v6_0_ring_emit_ib,
3495 .emit_fence = gfx_v6_0_ring_emit_fence,
3496 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3497 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3498 .test_ring = gfx_v6_0_ring_test_ring,
3499 .test_ib = gfx_v6_0_ring_test_ib,
3500 .insert_nop = amdgpu_ring_insert_nop,
3501 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3504 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3508 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3509 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3510 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3511 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3514 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3515 .set = gfx_v6_0_set_eop_interrupt_state,
3516 .process = gfx_v6_0_eop_irq,
3519 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3520 .set = gfx_v6_0_set_priv_reg_fault_state,
3521 .process = gfx_v6_0_priv_reg_irq,
3524 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3525 .set = gfx_v6_0_set_priv_inst_fault_state,
3526 .process = gfx_v6_0_priv_inst_irq,
3529 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3531 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3532 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3534 adev->gfx.priv_reg_irq.num_types = 1;
3535 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3537 adev->gfx.priv_inst_irq.num_types = 1;
3538 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3541 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3543 int i, j, k, counter, active_cu_number = 0;
3544 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3545 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3546 unsigned disable_masks[4 * 2];
3549 if (adev->flags & AMD_IS_APU)
3552 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3554 memset(cu_info, 0, sizeof(*cu_info));
3556 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3558 mutex_lock(&adev->grbm_idx_mutex);
3559 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3560 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3564 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3566 gfx_v6_0_set_user_cu_inactive_bitmap(
3567 adev, disable_masks[i * 2 + j]);
3568 bitmap = gfx_v6_0_get_cu_enabled(adev);
3569 cu_info->bitmap[i][j] = bitmap;
3571 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3572 if (bitmap & mask) {
3573 if (counter < ao_cu_num)
3579 active_cu_number += counter;
3581 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3582 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3586 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3587 mutex_unlock(&adev->grbm_idx_mutex);
3589 cu_info->number = active_cu_number;
3590 cu_info->ao_cu_mask = ao_cu_mask;
3593 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3595 .type = AMD_IP_BLOCK_TYPE_GFX,
3599 .funcs = &gfx_v6_0_ip_funcs,
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