drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_ih.h"
  27 #include "amdgpu_gfx.h"
  28 #include "cikd.h"
  29 #include "cik.h"
  30 #include "cik_structs.h"
  31 #include "atom.h"
  32 #include "amdgpu_ucode.h"
  33 #include "clearstate_ci.h"
  34
  35 #include "dce/dce_8_0_d.h"
  36 #include "dce/dce_8_0_sh_mask.h"
  37
  38 #include "bif/bif_4_1_d.h"
  39 #include "bif/bif_4_1_sh_mask.h"
  40
  41 #include "gca/gfx_7_0_d.h"
  42 #include "gca/gfx_7_2_enum.h"
  43 #include "gca/gfx_7_2_sh_mask.h"
  44
  45 #include "gmc/gmc_7_0_d.h"
  46 #include "gmc/gmc_7_0_sh_mask.h"
  47
  48 #include "oss/oss_2_0_d.h"
  49 #include "oss/oss_2_0_sh_mask.h"
  50
  51 #define GFX7_NUM_GFX_RINGS     1
  52 #define GFX7_MEC_HPD_SIZE      2048
  53
  54 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  55 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  56 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  57
  58 /*(DEBLOBBED)*/
  59
  60 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  61 {
  62         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  63         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  64         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  65         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  66         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  67         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  68         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  69         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
  70         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
  71         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
  72         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
  73         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
  74         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
  75         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
  76         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
  77         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
  78 };
  79
  80 static const u32 spectre_rlc_save_restore_register_list[] =
  81 {
  82         (0x0e00 << 16) | (0xc12c >> 2),
  83         0x00000000,
  84         (0x0e00 << 16) | (0xc140 >> 2),
  85         0x00000000,
  86         (0x0e00 << 16) | (0xc150 >> 2),
  87         0x00000000,
  88         (0x0e00 << 16) | (0xc15c >> 2),
  89         0x00000000,
  90         (0x0e00 << 16) | (0xc168 >> 2),
  91         0x00000000,
  92         (0x0e00 << 16) | (0xc170 >> 2),
  93         0x00000000,
  94         (0x0e00 << 16) | (0xc178 >> 2),
  95         0x00000000,
  96         (0x0e00 << 16) | (0xc204 >> 2),
  97         0x00000000,
  98         (0x0e00 << 16) | (0xc2b4 >> 2),
  99         0x00000000,
 100         (0x0e00 << 16) | (0xc2b8 >> 2),
 101         0x00000000,
 102         (0x0e00 << 16) | (0xc2bc >> 2),
 103         0x00000000,
 104         (0x0e00 << 16) | (0xc2c0 >> 2),
 105         0x00000000,
 106         (0x0e00 << 16) | (0x8228 >> 2),
 107         0x00000000,
 108         (0x0e00 << 16) | (0x829c >> 2),
 109         0x00000000,
 110         (0x0e00 << 16) | (0x869c >> 2),
 111         0x00000000,
 112         (0x0600 << 16) | (0x98f4 >> 2),
 113         0x00000000,
 114         (0x0e00 << 16) | (0x98f8 >> 2),
 115         0x00000000,
 116         (0x0e00 << 16) | (0x9900 >> 2),
 117         0x00000000,
 118         (0x0e00 << 16) | (0xc260 >> 2),
 119         0x00000000,
 120         (0x0e00 << 16) | (0x90e8 >> 2),
 121         0x00000000,
 122         (0x0e00 << 16) | (0x3c000 >> 2),
 123         0x00000000,
 124         (0x0e00 << 16) | (0x3c00c >> 2),
 125         0x00000000,
 126         (0x0e00 << 16) | (0x8c1c >> 2),
 127         0x00000000,
 128         (0x0e00 << 16) | (0x9700 >> 2),
 129         0x00000000,
 130         (0x0e00 << 16) | (0xcd20 >> 2),
 131         0x00000000,
 132         (0x4e00 << 16) | (0xcd20 >> 2),
 133         0x00000000,
 134         (0x5e00 << 16) | (0xcd20 >> 2),
 135         0x00000000,
 136         (0x6e00 << 16) | (0xcd20 >> 2),
 137         0x00000000,
 138         (0x7e00 << 16) | (0xcd20 >> 2),
 139         0x00000000,
 140         (0x8e00 << 16) | (0xcd20 >> 2),
 141         0x00000000,
 142         (0x9e00 << 16) | (0xcd20 >> 2),
 143         0x00000000,
 144         (0xae00 << 16) | (0xcd20 >> 2),
 145         0x00000000,
 146         (0xbe00 << 16) | (0xcd20 >> 2),
 147         0x00000000,
 148         (0x0e00 << 16) | (0x89bc >> 2),
 149         0x00000000,
 150         (0x0e00 << 16) | (0x8900 >> 2),
 151         0x00000000,
 152         0x3,
 153         (0x0e00 << 16) | (0xc130 >> 2),
 154         0x00000000,
 155         (0x0e00 << 16) | (0xc134 >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0xc1fc >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0xc208 >> 2),
 160         0x00000000,
 161         (0x0e00 << 16) | (0xc264 >> 2),
 162         0x00000000,
 163         (0x0e00 << 16) | (0xc268 >> 2),
 164         0x00000000,
 165         (0x0e00 << 16) | (0xc26c >> 2),
 166         0x00000000,
 167         (0x0e00 << 16) | (0xc270 >> 2),
 168         0x00000000,
 169         (0x0e00 << 16) | (0xc274 >> 2),
 170         0x00000000,
 171         (0x0e00 << 16) | (0xc278 >> 2),
 172         0x00000000,
 173         (0x0e00 << 16) | (0xc27c >> 2),
 174         0x00000000,
 175         (0x0e00 << 16) | (0xc280 >> 2),
 176         0x00000000,
 177         (0x0e00 << 16) | (0xc284 >> 2),
 178         0x00000000,
 179         (0x0e00 << 16) | (0xc288 >> 2),
 180         0x00000000,
 181         (0x0e00 << 16) | (0xc28c >> 2),
 182         0x00000000,
 183         (0x0e00 << 16) | (0xc290 >> 2),
 184         0x00000000,
 185         (0x0e00 << 16) | (0xc294 >> 2),
 186         0x00000000,
 187         (0x0e00 << 16) | (0xc298 >> 2),
 188         0x00000000,
 189         (0x0e00 << 16) | (0xc29c >> 2),
 190         0x00000000,
 191         (0x0e00 << 16) | (0xc2a0 >> 2),
 192         0x00000000,
 193         (0x0e00 << 16) | (0xc2a4 >> 2),
 194         0x00000000,
 195         (0x0e00 << 16) | (0xc2a8 >> 2),
 196         0x00000000,
 197         (0x0e00 << 16) | (0xc2ac  >> 2),
 198         0x00000000,
 199         (0x0e00 << 16) | (0xc2b0 >> 2),
 200         0x00000000,
 201         (0x0e00 << 16) | (0x301d0 >> 2),
 202         0x00000000,
 203         (0x0e00 << 16) | (0x30238 >> 2),
 204         0x00000000,
 205         (0x0e00 << 16) | (0x30250 >> 2),
 206         0x00000000,
 207         (0x0e00 << 16) | (0x30254 >> 2),
 208         0x00000000,
 209         (0x0e00 << 16) | (0x30258 >> 2),
 210         0x00000000,
 211         (0x0e00 << 16) | (0x3025c >> 2),
 212         0x00000000,
 213         (0x4e00 << 16) | (0xc900 >> 2),
 214         0x00000000,
 215         (0x5e00 << 16) | (0xc900 >> 2),
 216         0x00000000,
 217         (0x6e00 << 16) | (0xc900 >> 2),
 218         0x00000000,
 219         (0x7e00 << 16) | (0xc900 >> 2),
 220         0x00000000,
 221         (0x8e00 << 16) | (0xc900 >> 2),
 222         0x00000000,
 223         (0x9e00 << 16) | (0xc900 >> 2),
 224         0x00000000,
 225         (0xae00 << 16) | (0xc900 >> 2),
 226         0x00000000,
 227         (0xbe00 << 16) | (0xc900 >> 2),
 228         0x00000000,
 229         (0x4e00 << 16) | (0xc904 >> 2),
 230         0x00000000,
 231         (0x5e00 << 16) | (0xc904 >> 2),
 232         0x00000000,
 233         (0x6e00 << 16) | (0xc904 >> 2),
 234         0x00000000,
 235         (0x7e00 << 16) | (0xc904 >> 2),
 236         0x00000000,
 237         (0x8e00 << 16) | (0xc904 >> 2),
 238         0x00000000,
 239         (0x9e00 << 16) | (0xc904 >> 2),
 240         0x00000000,
 241         (0xae00 << 16) | (0xc904 >> 2),
 242         0x00000000,
 243         (0xbe00 << 16) | (0xc904 >> 2),
 244         0x00000000,
 245         (0x4e00 << 16) | (0xc908 >> 2),
 246         0x00000000,
 247         (0x5e00 << 16) | (0xc908 >> 2),
 248         0x00000000,
 249         (0x6e00 << 16) | (0xc908 >> 2),
 250         0x00000000,
 251         (0x7e00 << 16) | (0xc908 >> 2),
 252         0x00000000,
 253         (0x8e00 << 16) | (0xc908 >> 2),
 254         0x00000000,
 255         (0x9e00 << 16) | (0xc908 >> 2),
 256         0x00000000,
 257         (0xae00 << 16) | (0xc908 >> 2),
 258         0x00000000,
 259         (0xbe00 << 16) | (0xc908 >> 2),
 260         0x00000000,
 261         (0x4e00 << 16) | (0xc90c >> 2),
 262         0x00000000,
 263         (0x5e00 << 16) | (0xc90c >> 2),
 264         0x00000000,
 265         (0x6e00 << 16) | (0xc90c >> 2),
 266         0x00000000,
 267         (0x7e00 << 16) | (0xc90c >> 2),
 268         0x00000000,
 269         (0x8e00 << 16) | (0xc90c >> 2),
 270         0x00000000,
 271         (0x9e00 << 16) | (0xc90c >> 2),
 272         0x00000000,
 273         (0xae00 << 16) | (0xc90c >> 2),
 274         0x00000000,
 275         (0xbe00 << 16) | (0xc90c >> 2),
 276         0x00000000,
 277         (0x4e00 << 16) | (0xc910 >> 2),
 278         0x00000000,
 279         (0x5e00 << 16) | (0xc910 >> 2),
 280         0x00000000,
 281         (0x6e00 << 16) | (0xc910 >> 2),
 282         0x00000000,
 283         (0x7e00 << 16) | (0xc910 >> 2),
 284         0x00000000,
 285         (0x8e00 << 16) | (0xc910 >> 2),
 286         0x00000000,
 287         (0x9e00 << 16) | (0xc910 >> 2),
 288         0x00000000,
 289         (0xae00 << 16) | (0xc910 >> 2),
 290         0x00000000,
 291         (0xbe00 << 16) | (0xc910 >> 2),
 292         0x00000000,
 293         (0x0e00 << 16) | (0xc99c >> 2),
 294         0x00000000,
 295         (0x0e00 << 16) | (0x9834 >> 2),
 296         0x00000000,
 297         (0x0000 << 16) | (0x30f00 >> 2),
 298         0x00000000,
 299         (0x0001 << 16) | (0x30f00 >> 2),
 300         0x00000000,
 301         (0x0000 << 16) | (0x30f04 >> 2),
 302         0x00000000,
 303         (0x0001 << 16) | (0x30f04 >> 2),
 304         0x00000000,
 305         (0x0000 << 16) | (0x30f08 >> 2),
 306         0x00000000,
 307         (0x0001 << 16) | (0x30f08 >> 2),
 308         0x00000000,
 309         (0x0000 << 16) | (0x30f0c >> 2),
 310         0x00000000,
 311         (0x0001 << 16) | (0x30f0c >> 2),
 312         0x00000000,
 313         (0x0600 << 16) | (0x9b7c >> 2),
 314         0x00000000,
 315         (0x0e00 << 16) | (0x8a14 >> 2),
 316         0x00000000,
 317         (0x0e00 << 16) | (0x8a18 >> 2),
 318         0x00000000,
 319         (0x0600 << 16) | (0x30a00 >> 2),
 320         0x00000000,
 321         (0x0e00 << 16) | (0x8bf0 >> 2),
 322         0x00000000,
 323         (0x0e00 << 16) | (0x8bcc >> 2),
 324         0x00000000,
 325         (0x0e00 << 16) | (0x8b24 >> 2),
 326         0x00000000,
 327         (0x0e00 << 16) | (0x30a04 >> 2),
 328         0x00000000,
 329         (0x0600 << 16) | (0x30a10 >> 2),
 330         0x00000000,
 331         (0x0600 << 16) | (0x30a14 >> 2),
 332         0x00000000,
 333         (0x0600 << 16) | (0x30a18 >> 2),
 334         0x00000000,
 335         (0x0600 << 16) | (0x30a2c >> 2),
 336         0x00000000,
 337         (0x0e00 << 16) | (0xc700 >> 2),
 338         0x00000000,
 339         (0x0e00 << 16) | (0xc704 >> 2),
 340         0x00000000,
 341         (0x0e00 << 16) | (0xc708 >> 2),
 342         0x00000000,
 343         (0x0e00 << 16) | (0xc768 >> 2),
 344         0x00000000,
 345         (0x0400 << 16) | (0xc770 >> 2),
 346         0x00000000,
 347         (0x0400 << 16) | (0xc774 >> 2),
 348         0x00000000,
 349         (0x0400 << 16) | (0xc778 >> 2),
 350         0x00000000,
 351         (0x0400 << 16) | (0xc77c >> 2),
 352         0x00000000,
 353         (0x0400 << 16) | (0xc780 >> 2),
 354         0x00000000,
 355         (0x0400 << 16) | (0xc784 >> 2),
 356         0x00000000,
 357         (0x0400 << 16) | (0xc788 >> 2),
 358         0x00000000,
 359         (0x0400 << 16) | (0xc78c >> 2),
 360         0x00000000,
 361         (0x0400 << 16) | (0xc798 >> 2),
 362         0x00000000,
 363         (0x0400 << 16) | (0xc79c >> 2),
 364         0x00000000,
 365         (0x0400 << 16) | (0xc7a0 >> 2),
 366         0x00000000,
 367         (0x0400 << 16) | (0xc7a4 >> 2),
 368         0x00000000,
 369         (0x0400 << 16) | (0xc7a8 >> 2),
 370         0x00000000,
 371         (0x0400 << 16) | (0xc7ac >> 2),
 372         0x00000000,
 373         (0x0400 << 16) | (0xc7b0 >> 2),
 374         0x00000000,
 375         (0x0400 << 16) | (0xc7b4 >> 2),
 376         0x00000000,
 377         (0x0e00 << 16) | (0x9100 >> 2),
 378         0x00000000,
 379         (0x0e00 << 16) | (0x3c010 >> 2),
 380         0x00000000,
 381         (0x0e00 << 16) | (0x92a8 >> 2),
 382         0x00000000,
 383         (0x0e00 << 16) | (0x92ac >> 2),
 384         0x00000000,
 385         (0x0e00 << 16) | (0x92b4 >> 2),
 386         0x00000000,
 387         (0x0e00 << 16) | (0x92b8 >> 2),
 388         0x00000000,
 389         (0x0e00 << 16) | (0x92bc >> 2),
 390         0x00000000,
 391         (0x0e00 << 16) | (0x92c0 >> 2),
 392         0x00000000,
 393         (0x0e00 << 16) | (0x92c4 >> 2),
 394         0x00000000,
 395         (0x0e00 << 16) | (0x92c8 >> 2),
 396         0x00000000,
 397         (0x0e00 << 16) | (0x92cc >> 2),
 398         0x00000000,
 399         (0x0e00 << 16) | (0x92d0 >> 2),
 400         0x00000000,
 401         (0x0e00 << 16) | (0x8c00 >> 2),
 402         0x00000000,
 403         (0x0e00 << 16) | (0x8c04 >> 2),
 404         0x00000000,
 405         (0x0e00 << 16) | (0x8c20 >> 2),
 406         0x00000000,
 407         (0x0e00 << 16) | (0x8c38 >> 2),
 408         0x00000000,
 409         (0x0e00 << 16) | (0x8c3c >> 2),
 410         0x00000000,
 411         (0x0e00 << 16) | (0xae00 >> 2),
 412         0x00000000,
 413         (0x0e00 << 16) | (0x9604 >> 2),
 414         0x00000000,
 415         (0x0e00 << 16) | (0xac08 >> 2),
 416         0x00000000,
 417         (0x0e00 << 16) | (0xac0c >> 2),
 418         0x00000000,
 419         (0x0e00 << 16) | (0xac10 >> 2),
 420         0x00000000,
 421         (0x0e00 << 16) | (0xac14 >> 2),
 422         0x00000000,
 423         (0x0e00 << 16) | (0xac58 >> 2),
 424         0x00000000,
 425         (0x0e00 << 16) | (0xac68 >> 2),
 426         0x00000000,
 427         (0x0e00 << 16) | (0xac6c >> 2),
 428         0x00000000,
 429         (0x0e00 << 16) | (0xac70 >> 2),
 430         0x00000000,
 431         (0x0e00 << 16) | (0xac74 >> 2),
 432         0x00000000,
 433         (0x0e00 << 16) | (0xac78 >> 2),
 434         0x00000000,
 435         (0x0e00 << 16) | (0xac7c >> 2),
 436         0x00000000,
 437         (0x0e00 << 16) | (0xac80 >> 2),
 438         0x00000000,
 439         (0x0e00 << 16) | (0xac84 >> 2),
 440         0x00000000,
 441         (0x0e00 << 16) | (0xac88 >> 2),
 442         0x00000000,
 443         (0x0e00 << 16) | (0xac8c >> 2),
 444         0x00000000,
 445         (0x0e00 << 16) | (0x970c >> 2),
 446         0x00000000,
 447         (0x0e00 << 16) | (0x9714 >> 2),
 448         0x00000000,
 449         (0x0e00 << 16) | (0x9718 >> 2),
 450         0x00000000,
 451         (0x0e00 << 16) | (0x971c >> 2),
 452         0x00000000,
 453         (0x0e00 << 16) | (0x31068 >> 2),
 454         0x00000000,
 455         (0x4e00 << 16) | (0x31068 >> 2),
 456         0x00000000,
 457         (0x5e00 << 16) | (0x31068 >> 2),
 458         0x00000000,
 459         (0x6e00 << 16) | (0x31068 >> 2),
 460         0x00000000,
 461         (0x7e00 << 16) | (0x31068 >> 2),
 462         0x00000000,
 463         (0x8e00 << 16) | (0x31068 >> 2),
 464         0x00000000,
 465         (0x9e00 << 16) | (0x31068 >> 2),
 466         0x00000000,
 467         (0xae00 << 16) | (0x31068 >> 2),
 468         0x00000000,
 469         (0xbe00 << 16) | (0x31068 >> 2),
 470         0x00000000,
 471         (0x0e00 << 16) | (0xcd10 >> 2),
 472         0x00000000,
 473         (0x0e00 << 16) | (0xcd14 >> 2),
 474         0x00000000,
 475         (0x0e00 << 16) | (0x88b0 >> 2),
 476         0x00000000,
 477         (0x0e00 << 16) | (0x88b4 >> 2),
 478         0x00000000,
 479         (0x0e00 << 16) | (0x88b8 >> 2),
 480         0x00000000,
 481         (0x0e00 << 16) | (0x88bc >> 2),
 482         0x00000000,
 483         (0x0400 << 16) | (0x89c0 >> 2),
 484         0x00000000,
 485         (0x0e00 << 16) | (0x88c4 >> 2),
 486         0x00000000,
 487         (0x0e00 << 16) | (0x88c8 >> 2),
 488         0x00000000,
 489         (0x0e00 << 16) | (0x88d0 >> 2),
 490         0x00000000,
 491         (0x0e00 << 16) | (0x88d4 >> 2),
 492         0x00000000,
 493         (0x0e00 << 16) | (0x88d8 >> 2),
 494         0x00000000,
 495         (0x0e00 << 16) | (0x8980 >> 2),
 496         0x00000000,
 497         (0x0e00 << 16) | (0x30938 >> 2),
 498         0x00000000,
 499         (0x0e00 << 16) | (0x3093c >> 2),
 500         0x00000000,
 501         (0x0e00 << 16) | (0x30940 >> 2),
 502         0x00000000,
 503         (0x0e00 << 16) | (0x89a0 >> 2),
 504         0x00000000,
 505         (0x0e00 << 16) | (0x30900 >> 2),
 506         0x00000000,
 507         (0x0e00 << 16) | (0x30904 >> 2),
 508         0x00000000,
 509         (0x0e00 << 16) | (0x89b4 >> 2),
 510         0x00000000,
 511         (0x0e00 << 16) | (0x3c210 >> 2),
 512         0x00000000,
 513         (0x0e00 << 16) | (0x3c214 >> 2),
 514         0x00000000,
 515         (0x0e00 << 16) | (0x3c218 >> 2),
 516         0x00000000,
 517         (0x0e00 << 16) | (0x8904 >> 2),
 518         0x00000000,
 519         0x5,
 520         (0x0e00 << 16) | (0x8c28 >> 2),
 521         (0x0e00 << 16) | (0x8c2c >> 2),
 522         (0x0e00 << 16) | (0x8c30 >> 2),
 523         (0x0e00 << 16) | (0x8c34 >> 2),
 524         (0x0e00 << 16) | (0x9600 >> 2),
 525 };
 526
 527 static const u32 kalindi_rlc_save_restore_register_list[] =
 528 {
 529         (0x0e00 << 16) | (0xc12c >> 2),
 530         0x00000000,
 531         (0x0e00 << 16) | (0xc140 >> 2),
 532         0x00000000,
 533         (0x0e00 << 16) | (0xc150 >> 2),
 534         0x00000000,
 535         (0x0e00 << 16) | (0xc15c >> 2),
 536         0x00000000,
 537         (0x0e00 << 16) | (0xc168 >> 2),
 538         0x00000000,
 539         (0x0e00 << 16) | (0xc170 >> 2),
 540         0x00000000,
 541         (0x0e00 << 16) | (0xc204 >> 2),
 542         0x00000000,
 543         (0x0e00 << 16) | (0xc2b4 >> 2),
 544         0x00000000,
 545         (0x0e00 << 16) | (0xc2b8 >> 2),
 546         0x00000000,
 547         (0x0e00 << 16) | (0xc2bc >> 2),
 548         0x00000000,
 549         (0x0e00 << 16) | (0xc2c0 >> 2),
 550         0x00000000,
 551         (0x0e00 << 16) | (0x8228 >> 2),
 552         0x00000000,
 553         (0x0e00 << 16) | (0x829c >> 2),
 554         0x00000000,
 555         (0x0e00 << 16) | (0x869c >> 2),
 556         0x00000000,
 557         (0x0600 << 16) | (0x98f4 >> 2),
 558         0x00000000,
 559         (0x0e00 << 16) | (0x98f8 >> 2),
 560         0x00000000,
 561         (0x0e00 << 16) | (0x9900 >> 2),
 562         0x00000000,
 563         (0x0e00 << 16) | (0xc260 >> 2),
 564         0x00000000,
 565         (0x0e00 << 16) | (0x90e8 >> 2),
 566         0x00000000,
 567         (0x0e00 << 16) | (0x3c000 >> 2),
 568         0x00000000,
 569         (0x0e00 << 16) | (0x3c00c >> 2),
 570         0x00000000,
 571         (0x0e00 << 16) | (0x8c1c >> 2),
 572         0x00000000,
 573         (0x0e00 << 16) | (0x9700 >> 2),
 574         0x00000000,
 575         (0x0e00 << 16) | (0xcd20 >> 2),
 576         0x00000000,
 577         (0x4e00 << 16) | (0xcd20 >> 2),
 578         0x00000000,
 579         (0x5e00 << 16) | (0xcd20 >> 2),
 580         0x00000000,
 581         (0x6e00 << 16) | (0xcd20 >> 2),
 582         0x00000000,
 583         (0x7e00 << 16) | (0xcd20 >> 2),
 584         0x00000000,
 585         (0x0e00 << 16) | (0x89bc >> 2),
 586         0x00000000,
 587         (0x0e00 << 16) | (0x8900 >> 2),
 588         0x00000000,
 589         0x3,
 590         (0x0e00 << 16) | (0xc130 >> 2),
 591         0x00000000,
 592         (0x0e00 << 16) | (0xc134 >> 2),
 593         0x00000000,
 594         (0x0e00 << 16) | (0xc1fc >> 2),
 595         0x00000000,
 596         (0x0e00 << 16) | (0xc208 >> 2),
 597         0x00000000,
 598         (0x0e00 << 16) | (0xc264 >> 2),
 599         0x00000000,
 600         (0x0e00 << 16) | (0xc268 >> 2),
 601         0x00000000,
 602         (0x0e00 << 16) | (0xc26c >> 2),
 603         0x00000000,
 604         (0x0e00 << 16) | (0xc270 >> 2),
 605         0x00000000,
 606         (0x0e00 << 16) | (0xc274 >> 2),
 607         0x00000000,
 608         (0x0e00 << 16) | (0xc28c >> 2),
 609         0x00000000,
 610         (0x0e00 << 16) | (0xc290 >> 2),
 611         0x00000000,
 612         (0x0e00 << 16) | (0xc294 >> 2),
 613         0x00000000,
 614         (0x0e00 << 16) | (0xc298 >> 2),
 615         0x00000000,
 616         (0x0e00 << 16) | (0xc2a0 >> 2),
 617         0x00000000,
 618         (0x0e00 << 16) | (0xc2a4 >> 2),
 619         0x00000000,
 620         (0x0e00 << 16) | (0xc2a8 >> 2),
 621         0x00000000,
 622         (0x0e00 << 16) | (0xc2ac >> 2),
 623         0x00000000,
 624         (0x0e00 << 16) | (0x301d0 >> 2),
 625         0x00000000,
 626         (0x0e00 << 16) | (0x30238 >> 2),
 627         0x00000000,
 628         (0x0e00 << 16) | (0x30250 >> 2),
 629         0x00000000,
 630         (0x0e00 << 16) | (0x30254 >> 2),
 631         0x00000000,
 632         (0x0e00 << 16) | (0x30258 >> 2),
 633         0x00000000,
 634         (0x0e00 << 16) | (0x3025c >> 2),
 635         0x00000000,
 636         (0x4e00 << 16) | (0xc900 >> 2),
 637         0x00000000,
 638         (0x5e00 << 16) | (0xc900 >> 2),
 639         0x00000000,
 640         (0x6e00 << 16) | (0xc900 >> 2),
 641         0x00000000,
 642         (0x7e00 << 16) | (0xc900 >> 2),
 643         0x00000000,
 644         (0x4e00 << 16) | (0xc904 >> 2),
 645         0x00000000,
 646         (0x5e00 << 16) | (0xc904 >> 2),
 647         0x00000000,
 648         (0x6e00 << 16) | (0xc904 >> 2),
 649         0x00000000,
 650         (0x7e00 << 16) | (0xc904 >> 2),
 651         0x00000000,
 652         (0x4e00 << 16) | (0xc908 >> 2),
 653         0x00000000,
 654         (0x5e00 << 16) | (0xc908 >> 2),
 655         0x00000000,
 656         (0x6e00 << 16) | (0xc908 >> 2),
 657         0x00000000,
 658         (0x7e00 << 16) | (0xc908 >> 2),
 659         0x00000000,
 660         (0x4e00 << 16) | (0xc90c >> 2),
 661         0x00000000,
 662         (0x5e00 << 16) | (0xc90c >> 2),
 663         0x00000000,
 664         (0x6e00 << 16) | (0xc90c >> 2),
 665         0x00000000,
 666         (0x7e00 << 16) | (0xc90c >> 2),
 667         0x00000000,
 668         (0x4e00 << 16) | (0xc910 >> 2),
 669         0x00000000,
 670         (0x5e00 << 16) | (0xc910 >> 2),
 671         0x00000000,
 672         (0x6e00 << 16) | (0xc910 >> 2),
 673         0x00000000,
 674         (0x7e00 << 16) | (0xc910 >> 2),
 675         0x00000000,
 676         (0x0e00 << 16) | (0xc99c >> 2),
 677         0x00000000,
 678         (0x0e00 << 16) | (0x9834 >> 2),
 679         0x00000000,
 680         (0x0000 << 16) | (0x30f00 >> 2),
 681         0x00000000,
 682         (0x0000 << 16) | (0x30f04 >> 2),
 683         0x00000000,
 684         (0x0000 << 16) | (0x30f08 >> 2),
 685         0x00000000,
 686         (0x0000 << 16) | (0x30f0c >> 2),
 687         0x00000000,
 688         (0x0600 << 16) | (0x9b7c >> 2),
 689         0x00000000,
 690         (0x0e00 << 16) | (0x8a14 >> 2),
 691         0x00000000,
 692         (0x0e00 << 16) | (0x8a18 >> 2),
 693         0x00000000,
 694         (0x0600 << 16) | (0x30a00 >> 2),
 695         0x00000000,
 696         (0x0e00 << 16) | (0x8bf0 >> 2),
 697         0x00000000,
 698         (0x0e00 << 16) | (0x8bcc >> 2),
 699         0x00000000,
 700         (0x0e00 << 16) | (0x8b24 >> 2),
 701         0x00000000,
 702         (0x0e00 << 16) | (0x30a04 >> 2),
 703         0x00000000,
 704         (0x0600 << 16) | (0x30a10 >> 2),
 705         0x00000000,
 706         (0x0600 << 16) | (0x30a14 >> 2),
 707         0x00000000,
 708         (0x0600 << 16) | (0x30a18 >> 2),
 709         0x00000000,
 710         (0x0600 << 16) | (0x30a2c >> 2),
 711         0x00000000,
 712         (0x0e00 << 16) | (0xc700 >> 2),
 713         0x00000000,
 714         (0x0e00 << 16) | (0xc704 >> 2),
 715         0x00000000,
 716         (0x0e00 << 16) | (0xc708 >> 2),
 717         0x00000000,
 718         (0x0e00 << 16) | (0xc768 >> 2),
 719         0x00000000,
 720         (0x0400 << 16) | (0xc770 >> 2),
 721         0x00000000,
 722         (0x0400 << 16) | (0xc774 >> 2),
 723         0x00000000,
 724         (0x0400 << 16) | (0xc798 >> 2),
 725         0x00000000,
 726         (0x0400 << 16) | (0xc79c >> 2),
 727         0x00000000,
 728         (0x0e00 << 16) | (0x9100 >> 2),
 729         0x00000000,
 730         (0x0e00 << 16) | (0x3c010 >> 2),
 731         0x00000000,
 732         (0x0e00 << 16) | (0x8c00 >> 2),
 733         0x00000000,
 734         (0x0e00 << 16) | (0x8c04 >> 2),
 735         0x00000000,
 736         (0x0e00 << 16) | (0x8c20 >> 2),
 737         0x00000000,
 738         (0x0e00 << 16) | (0x8c38 >> 2),
 739         0x00000000,
 740         (0x0e00 << 16) | (0x8c3c >> 2),
 741         0x00000000,
 742         (0x0e00 << 16) | (0xae00 >> 2),
 743         0x00000000,
 744         (0x0e00 << 16) | (0x9604 >> 2),
 745         0x00000000,
 746         (0x0e00 << 16) | (0xac08 >> 2),
 747         0x00000000,
 748         (0x0e00 << 16) | (0xac0c >> 2),
 749         0x00000000,
 750         (0x0e00 << 16) | (0xac10 >> 2),
 751         0x00000000,
 752         (0x0e00 << 16) | (0xac14 >> 2),
 753         0x00000000,
 754         (0x0e00 << 16) | (0xac58 >> 2),
 755         0x00000000,
 756         (0x0e00 << 16) | (0xac68 >> 2),
 757         0x00000000,
 758         (0x0e00 << 16) | (0xac6c >> 2),
 759         0x00000000,
 760         (0x0e00 << 16) | (0xac70 >> 2),
 761         0x00000000,
 762         (0x0e00 << 16) | (0xac74 >> 2),
 763         0x00000000,
 764         (0x0e00 << 16) | (0xac78 >> 2),
 765         0x00000000,
 766         (0x0e00 << 16) | (0xac7c >> 2),
 767         0x00000000,
 768         (0x0e00 << 16) | (0xac80 >> 2),
 769         0x00000000,
 770         (0x0e00 << 16) | (0xac84 >> 2),
 771         0x00000000,
 772         (0x0e00 << 16) | (0xac88 >> 2),
 773         0x00000000,
 774         (0x0e00 << 16) | (0xac8c >> 2),
 775         0x00000000,
 776         (0x0e00 << 16) | (0x970c >> 2),
 777         0x00000000,
 778         (0x0e00 << 16) | (0x9714 >> 2),
 779         0x00000000,
 780         (0x0e00 << 16) | (0x9718 >> 2),
 781         0x00000000,
 782         (0x0e00 << 16) | (0x971c >> 2),
 783         0x00000000,
 784         (0x0e00 << 16) | (0x31068 >> 2),
 785         0x00000000,
 786         (0x4e00 << 16) | (0x31068 >> 2),
 787         0x00000000,
 788         (0x5e00 << 16) | (0x31068 >> 2),
 789         0x00000000,
 790         (0x6e00 << 16) | (0x31068 >> 2),
 791         0x00000000,
 792         (0x7e00 << 16) | (0x31068 >> 2),
 793         0x00000000,
 794         (0x0e00 << 16) | (0xcd10 >> 2),
 795         0x00000000,
 796         (0x0e00 << 16) | (0xcd14 >> 2),
 797         0x00000000,
 798         (0x0e00 << 16) | (0x88b0 >> 2),
 799         0x00000000,
 800         (0x0e00 << 16) | (0x88b4 >> 2),
 801         0x00000000,
 802         (0x0e00 << 16) | (0x88b8 >> 2),
 803         0x00000000,
 804         (0x0e00 << 16) | (0x88bc >> 2),
 805         0x00000000,
 806         (0x0400 << 16) | (0x89c0 >> 2),
 807         0x00000000,
 808         (0x0e00 << 16) | (0x88c4 >> 2),
 809         0x00000000,
 810         (0x0e00 << 16) | (0x88c8 >> 2),
 811         0x00000000,
 812         (0x0e00 << 16) | (0x88d0 >> 2),
 813         0x00000000,
 814         (0x0e00 << 16) | (0x88d4 >> 2),
 815         0x00000000,
 816         (0x0e00 << 16) | (0x88d8 >> 2),
 817         0x00000000,
 818         (0x0e00 << 16) | (0x8980 >> 2),
 819         0x00000000,
 820         (0x0e00 << 16) | (0x30938 >> 2),
 821         0x00000000,
 822         (0x0e00 << 16) | (0x3093c >> 2),
 823         0x00000000,
 824         (0x0e00 << 16) | (0x30940 >> 2),
 825         0x00000000,
 826         (0x0e00 << 16) | (0x89a0 >> 2),
 827         0x00000000,
 828         (0x0e00 << 16) | (0x30900 >> 2),
 829         0x00000000,
 830         (0x0e00 << 16) | (0x30904 >> 2),
 831         0x00000000,
 832         (0x0e00 << 16) | (0x89b4 >> 2),
 833         0x00000000,
 834         (0x0e00 << 16) | (0x3e1fc >> 2),
 835         0x00000000,
 836         (0x0e00 << 16) | (0x3c210 >> 2),
 837         0x00000000,
 838         (0x0e00 << 16) | (0x3c214 >> 2),
 839         0x00000000,
 840         (0x0e00 << 16) | (0x3c218 >> 2),
 841         0x00000000,
 842         (0x0e00 << 16) | (0x8904 >> 2),
 843         0x00000000,
 844         0x5,
 845         (0x0e00 << 16) | (0x8c28 >> 2),
 846         (0x0e00 << 16) | (0x8c2c >> 2),
 847         (0x0e00 << 16) | (0x8c30 >> 2),
 848         (0x0e00 << 16) | (0x8c34 >> 2),
 849         (0x0e00 << 16) | (0x9600 >> 2),
 850 };
 851
 852 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 853 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 854 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 855 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 856 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 857
 858 /*
 859  * Core functions
 860  */
 861 /**
 862  * gfx_v7_0_init_microcode - load ucode images from disk
 863  *
 864  * @adev: amdgpu_device pointer
 865  *
 866  * Use the firmware interface to load the ucode images into
 867  * the driver (not loaded into hw).
 868  * Returns 0 on success, error on failure.
 869  */
 870 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 871 {
 872         const char *chip_name;
 873         char fw_name[30];
 874         int err;
 875
 876         DRM_DEBUG("\n");
 877
 878         switch (adev->asic_type) {
 879         case CHIP_BONAIRE:
 880                 chip_name = "bonaire";
 881                 break;
 882         case CHIP_HAWAII:
 883                 chip_name = "hawaii";
 884                 break;
 885         case CHIP_KAVERI:
 886                 chip_name = "kaveri";
 887                 break;
 888         case CHIP_KABINI:
 889                 chip_name = "kabini";
 890                 break;
 891         case CHIP_MULLINS:
 892                 chip_name = "mullins";
 893                 break;
 894         default: BUG();
 895         }
 896
 897         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 898         err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 899         if (err)
 900                 goto out;
 901         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 902         if (err)
 903                 goto out;
 904
 905         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 906         err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 907         if (err)
 908                 goto out;
 909         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 910         if (err)
 911                 goto out;
 912
 913         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 914         err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 915         if (err)
 916                 goto out;
 917         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 918         if (err)
 919                 goto out;
 920
 921         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 922         err = reject_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 923         if (err)
 924                 goto out;
 925         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 926         if (err)
 927                 goto out;
 928
 929         if (adev->asic_type == CHIP_KAVERI) {
 930                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 931                 err = reject_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 932                 if (err)
 933                         goto out;
 934                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 935                 if (err)
 936                         goto out;
 937         }
 938
 939         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 940         err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 941         if (err)
 942                 goto out;
 943         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 944
 945 out:
 946         if (err) {
 947                 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
 948                 release_firmware(adev->gfx.pfp_fw);
 949                 adev->gfx.pfp_fw = NULL;
 950                 release_firmware(adev->gfx.me_fw);
 951                 adev->gfx.me_fw = NULL;
 952                 release_firmware(adev->gfx.ce_fw);
 953                 adev->gfx.ce_fw = NULL;
 954                 release_firmware(adev->gfx.mec_fw);
 955                 adev->gfx.mec_fw = NULL;
 956                 release_firmware(adev->gfx.mec2_fw);
 957                 adev->gfx.mec2_fw = NULL;
 958                 release_firmware(adev->gfx.rlc_fw);
 959                 adev->gfx.rlc_fw = NULL;
 960         }
 961         return err;
 962 }
 963
 964 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 965 {
 966         release_firmware(adev->gfx.pfp_fw);
 967         adev->gfx.pfp_fw = NULL;
 968         release_firmware(adev->gfx.me_fw);
 969         adev->gfx.me_fw = NULL;
 970         release_firmware(adev->gfx.ce_fw);
 971         adev->gfx.ce_fw = NULL;
 972         release_firmware(adev->gfx.mec_fw);
 973         adev->gfx.mec_fw = NULL;
 974         release_firmware(adev->gfx.mec2_fw);
 975         adev->gfx.mec2_fw = NULL;
 976         release_firmware(adev->gfx.rlc_fw);
 977         adev->gfx.rlc_fw = NULL;
 978 }
 979
 980 /**
 981  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
 982  *
 983  * @adev: amdgpu_device pointer
 984  *
 985  * Starting with SI, the tiling setup is done globally in a
 986  * set of 32 tiling modes.  Rather than selecting each set of
 987  * parameters per surface as on older asics, we just select
 988  * which index in the tiling table we want to use, and the
 989  * surface uses those parameters (CIK).
 990  */
 991 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
 992 {
 993         const u32 num_tile_mode_states =
 994                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 995         const u32 num_secondary_tile_mode_states =
 996                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 997         u32 reg_offset, split_equal_to_row_size;
 998         uint32_t *tile, *macrotile;
 999
1000         tile = adev->gfx.config.tile_mode_array;
1001         macrotile = adev->gfx.config.macrotile_mode_array;
1002
1003         switch (adev->gfx.config.mem_row_size_in_kb) {
1004         case 1:
1005                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1006                 break;
1007         case 2:
1008         default:
1009                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1010                 break;
1011         case 4:
1012                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1013                 break;
1014         }
1015
1016         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1017                 tile[reg_offset] = 0;
1018         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1019                 macrotile[reg_offset] = 0;
1020
1021         switch (adev->asic_type) {
1022         case CHIP_BONAIRE:
1023                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1024                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1025                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1026                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1027                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1028                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1029                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1030                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1031                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1033                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1034                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1035                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1036                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1037                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1038                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1039                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1040                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1041                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1042                            TILE_SPLIT(split_equal_to_row_size));
1043                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1044                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1045                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1046                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1047                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1048                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1049                            TILE_SPLIT(split_equal_to_row_size));
1050                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1051                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1052                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
1053                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1054                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1056                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1057                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1058                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1059                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1060                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1061                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1063                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1064                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1065                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1066                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1067                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1068                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1070                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1071                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1072                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1073                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1074                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1075                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1076                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1077                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1078                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1079                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1080                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1081                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1082                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1083                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1084                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1085                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1086                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1088                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1089                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1090                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1091                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1092                 tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1093                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1094                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1095                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1096                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1097                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1098                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1099                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1100                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1101                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1102                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1103                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1104                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1105                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1106                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1107                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1108                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1109                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1110                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1111                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1112                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1113                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1114                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1115                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1116                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1117                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1118                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1119                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1120                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1121                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1122                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1123                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1124                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1125
1126                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1128                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1129                                 NUM_BANKS(ADDR_SURF_16_BANK));
1130                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1131                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1132                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1133                                 NUM_BANKS(ADDR_SURF_16_BANK));
1134                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1135                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1136                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1137                                 NUM_BANKS(ADDR_SURF_16_BANK));
1138                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1139                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1140                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1141                                 NUM_BANKS(ADDR_SURF_16_BANK));
1142                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1143                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1144                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1145                                 NUM_BANKS(ADDR_SURF_16_BANK));
1146                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1148                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1149                                 NUM_BANKS(ADDR_SURF_8_BANK));
1150                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1151                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1152                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1153                                 NUM_BANKS(ADDR_SURF_4_BANK));
1154                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1155                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1156                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1157                                 NUM_BANKS(ADDR_SURF_16_BANK));
1158                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1159                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1160                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1161                                 NUM_BANKS(ADDR_SURF_16_BANK));
1162                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1164                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1165                                 NUM_BANKS(ADDR_SURF_16_BANK));
1166                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1167                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1168                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1169                                 NUM_BANKS(ADDR_SURF_16_BANK));
1170                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1171                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1172                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1173                                 NUM_BANKS(ADDR_SURF_16_BANK));
1174                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1175                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1176                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1177                                 NUM_BANKS(ADDR_SURF_8_BANK));
1178                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1179                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1180                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1181                                 NUM_BANKS(ADDR_SURF_4_BANK));
1182
1183                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1184                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1185                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1186                         if (reg_offset != 7)
1187                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1188                 break;
1189         case CHIP_HAWAII:
1190                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1191                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1192                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1193                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1194                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1196                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1197                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1198                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1199                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1200                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1201                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1202                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1204                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1205                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1206                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1207                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1208                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1209                            TILE_SPLIT(split_equal_to_row_size));
1210                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1211                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1212                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1213                            TILE_SPLIT(split_equal_to_row_size));
1214                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1215                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1216                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1217                            TILE_SPLIT(split_equal_to_row_size));
1218                 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1219                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1220                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1221                            TILE_SPLIT(split_equal_to_row_size));
1222                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1223                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1224                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1227                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1229                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1230                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1231                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1232                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1233                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1234                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1235                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1236                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1237                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1238                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1239                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1240                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1241                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1242                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1244                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1245                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1246                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1247                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1248                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1249                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1250                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1251                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1252                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1253                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1254                 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1255                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1256                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1257                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1258                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1259                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1260                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1261                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1262                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1263                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1264                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1265                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1266                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1267                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1268                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1269                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1270                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1271                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1272                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1273                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1274                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1275                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1276                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1277                 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1278                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1279                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1280                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1281                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1282                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1283                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1284                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1285                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1286                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1287                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1288                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1289                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1290                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1291                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1292                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1293                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1294                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1295                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1296                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1297                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1298                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1299                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1300                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1301                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1302                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1303                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1304                 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1305                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1306                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1307                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1308
1309                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1310                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1311                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1312                                 NUM_BANKS(ADDR_SURF_16_BANK));
1313                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1314                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1315                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1316                                 NUM_BANKS(ADDR_SURF_16_BANK));
1317                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1318                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1319                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1320                                 NUM_BANKS(ADDR_SURF_16_BANK));
1321                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1322                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1323                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1324                                 NUM_BANKS(ADDR_SURF_16_BANK));
1325                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1326                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1327                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1328                                 NUM_BANKS(ADDR_SURF_8_BANK));
1329                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1330                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1331                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1332                                 NUM_BANKS(ADDR_SURF_4_BANK));
1333                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1334                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1335                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1336                                 NUM_BANKS(ADDR_SURF_4_BANK));
1337                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1338                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1339                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1340                                 NUM_BANKS(ADDR_SURF_16_BANK));
1341                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1342                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1343                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1344                                 NUM_BANKS(ADDR_SURF_16_BANK));
1345                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1346                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1347                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1348                                 NUM_BANKS(ADDR_SURF_16_BANK));
1349                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1351                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1352                                 NUM_BANKS(ADDR_SURF_8_BANK));
1353                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1354                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1355                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1356                                 NUM_BANKS(ADDR_SURF_16_BANK));
1357                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1358                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1359                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1360                                 NUM_BANKS(ADDR_SURF_8_BANK));
1361                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1362                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1363                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1364                                 NUM_BANKS(ADDR_SURF_4_BANK));
1365
1366                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1367                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1368                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1369                         if (reg_offset != 7)
1370                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1371                 break;
1372         case CHIP_KABINI:
1373         case CHIP_KAVERI:
1374         case CHIP_MULLINS:
1375         default:
1376                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1377                            PIPE_CONFIG(ADDR_SURF_P2) |
1378                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1379                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1380                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1381                            PIPE_CONFIG(ADDR_SURF_P2) |
1382                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1383                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1384                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1385                            PIPE_CONFIG(ADDR_SURF_P2) |
1386                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1387                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1388                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1389                            PIPE_CONFIG(ADDR_SURF_P2) |
1390                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1391                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1392                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1393                            PIPE_CONFIG(ADDR_SURF_P2) |
1394                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1395                            TILE_SPLIT(split_equal_to_row_size));
1396                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1397                            PIPE_CONFIG(ADDR_SURF_P2) |
1398                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1399                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1400                            PIPE_CONFIG(ADDR_SURF_P2) |
1401                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1402                            TILE_SPLIT(split_equal_to_row_size));
1403                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1404                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1405                            PIPE_CONFIG(ADDR_SURF_P2));
1406                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1407                            PIPE_CONFIG(ADDR_SURF_P2) |
1408                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1409                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1410                             PIPE_CONFIG(ADDR_SURF_P2) |
1411                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1412                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1413                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1414                             PIPE_CONFIG(ADDR_SURF_P2) |
1415                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1416                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1417                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1418                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1419                             PIPE_CONFIG(ADDR_SURF_P2) |
1420                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1421                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1422                             PIPE_CONFIG(ADDR_SURF_P2) |
1423                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1424                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1425                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1426                             PIPE_CONFIG(ADDR_SURF_P2) |
1427                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1428                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1429                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1430                             PIPE_CONFIG(ADDR_SURF_P2) |
1431                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1432                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1433                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1434                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1435                             PIPE_CONFIG(ADDR_SURF_P2) |
1436                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1437                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1438                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1439                             PIPE_CONFIG(ADDR_SURF_P2) |
1440                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1441                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1442                             PIPE_CONFIG(ADDR_SURF_P2) |
1443                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1444                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1445                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1446                             PIPE_CONFIG(ADDR_SURF_P2) |
1447                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1448                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1449                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1450                             PIPE_CONFIG(ADDR_SURF_P2) |
1451                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1452                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1453                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1454                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1455                             PIPE_CONFIG(ADDR_SURF_P2) |
1456                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1457                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1458                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1459                             PIPE_CONFIG(ADDR_SURF_P2) |
1460                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1461                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1462                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1463                             PIPE_CONFIG(ADDR_SURF_P2) |
1464                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1465                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1466                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1467                             PIPE_CONFIG(ADDR_SURF_P2) |
1468                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1469                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1470                             PIPE_CONFIG(ADDR_SURF_P2) |
1471                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1472                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1473                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1474                             PIPE_CONFIG(ADDR_SURF_P2) |
1475                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1476                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1477                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1478
1479                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1480                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1481                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1482                                 NUM_BANKS(ADDR_SURF_8_BANK));
1483                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1484                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1485                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1486                                 NUM_BANKS(ADDR_SURF_8_BANK));
1487                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1488                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1489                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1490                                 NUM_BANKS(ADDR_SURF_8_BANK));
1491                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1492                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1493                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1494                                 NUM_BANKS(ADDR_SURF_8_BANK));
1495                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1496                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1497                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1498                                 NUM_BANKS(ADDR_SURF_8_BANK));
1499                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1500                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1501                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1502                                 NUM_BANKS(ADDR_SURF_8_BANK));
1503                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1504                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1505                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1506                                 NUM_BANKS(ADDR_SURF_8_BANK));
1507                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1508                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1509                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1510                                 NUM_BANKS(ADDR_SURF_16_BANK));
1511                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1512                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1513                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1514                                 NUM_BANKS(ADDR_SURF_16_BANK));
1515                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1516                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1517                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1518                                 NUM_BANKS(ADDR_SURF_16_BANK));
1519                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1520                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1521                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1522                                 NUM_BANKS(ADDR_SURF_16_BANK));
1523                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1524                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1525                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1526                                 NUM_BANKS(ADDR_SURF_16_BANK));
1527                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1528                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1529                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1530                                 NUM_BANKS(ADDR_SURF_16_BANK));
1531                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1532                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1533                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1534                                 NUM_BANKS(ADDR_SURF_8_BANK));
1535
1536                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1537                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1538                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1539                         if (reg_offset != 7)
1540                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1541                 break;
1542         }
1543 }
1544
1545 /**
1546  * gfx_v7_0_select_se_sh - select which SE, SH to address
1547  *
1548  * @adev: amdgpu_device pointer
1549  * @se_num: shader engine to address
1550  * @sh_num: sh block to address
1551  *
1552  * Select which SE, SH combinations to address. Certain
1553  * registers are instanced per SE or SH.  0xffffffff means
1554  * broadcast to all SEs or SHs (CIK).
1555  */
1556 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1557                                   u32 se_num, u32 sh_num, u32 instance)
1558 {
1559         u32 data;
1560
1561         if (instance == 0xffffffff)
1562                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1563         else
1564                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1565
1566         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1567                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1568                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1569         else if (se_num == 0xffffffff)
1570                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1571                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1572         else if (sh_num == 0xffffffff)
1573                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1574                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1575         else
1576                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1577                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1578         WREG32(mmGRBM_GFX_INDEX, data);
1579 }
1580
1581 /**
1582  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1583  *
1584  * @adev: amdgpu_device pointer
1585  *
1586  * Calculates the bitmask of enabled RBs (CIK).
1587  * Returns the enabled RB bitmask.
1588  */
1589 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1590 {
1591         u32 data, mask;
1592
1593         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1594         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1595
1596         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1597         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1598
1599         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1600                                          adev->gfx.config.max_sh_per_se);
1601
1602         return (~data) & mask;
1603 }
1604
1605 static void
1606 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1607 {
1608         switch (adev->asic_type) {
1609         case CHIP_BONAIRE:
1610                 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1611                           SE_XSEL(1) | SE_YSEL(1);
1612                 *rconf1 |= 0x0;
1613                 break;
1614         case CHIP_HAWAII:
1615                 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1616                           RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1617                           PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1618                           SE_YSEL(3);
1619                 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1620                            SE_PAIR_YSEL(2);
1621                 break;
1622         case CHIP_KAVERI:
1623                 *rconf |= RB_MAP_PKR0(2);
1624                 *rconf1 |= 0x0;
1625                 break;
1626         case CHIP_KABINI:
1627         case CHIP_MULLINS:
1628                 *rconf |= 0x0;
1629                 *rconf1 |= 0x0;
1630                 break;
1631         default:
1632                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1633                 break;
1634         }
1635 }
1636
1637 static void
1638 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1639                                         u32 raster_config, u32 raster_config_1,
1640                                         unsigned rb_mask, unsigned num_rb)
1641 {
1642         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1643         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1644         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1645         unsigned rb_per_se = num_rb / num_se;
1646         unsigned se_mask[4];
1647         unsigned se;
1648
1649         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1650         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1651         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1652         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1653
1654         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1655         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1656         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1657
1658         if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1659                              (!se_mask[2] && !se_mask[3]))) {
1660                 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1661
1662                 if (!se_mask[0] && !se_mask[1]) {
1663                         raster_config_1 |=
1664                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1665                 } else {
1666                         raster_config_1 |=
1667                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1668                 }
1669         }
1670
1671         for (se = 0; se < num_se; se++) {
1672                 unsigned raster_config_se = raster_config;
1673                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1674                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1675                 int idx = (se / 2) * 2;
1676
1677                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1678                         raster_config_se &= ~SE_MAP_MASK;
1679
1680                         if (!se_mask[idx]) {
1681                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1682                         } else {
1683                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1684                         }
1685                 }
1686
1687                 pkr0_mask &= rb_mask;
1688                 pkr1_mask &= rb_mask;
1689                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1690                         raster_config_se &= ~PKR_MAP_MASK;
1691
1692                         if (!pkr0_mask) {
1693                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1694                         } else {
1695                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1696                         }
1697                 }
1698
1699                 if (rb_per_se >= 2) {
1700                         unsigned rb0_mask = 1 << (se * rb_per_se);
1701                         unsigned rb1_mask = rb0_mask << 1;
1702
1703                         rb0_mask &= rb_mask;
1704                         rb1_mask &= rb_mask;
1705                         if (!rb0_mask || !rb1_mask) {
1706                                 raster_config_se &= ~RB_MAP_PKR0_MASK;
1707
1708                                 if (!rb0_mask) {
1709                                         raster_config_se |=
1710                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1711                                 } else {
1712                                         raster_config_se |=
1713                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1714                                 }
1715                         }
1716
1717                         if (rb_per_se > 2) {
1718                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1719                                 rb1_mask = rb0_mask << 1;
1720                                 rb0_mask &= rb_mask;
1721                                 rb1_mask &= rb_mask;
1722                                 if (!rb0_mask || !rb1_mask) {
1723                                         raster_config_se &= ~RB_MAP_PKR1_MASK;
1724
1725                                         if (!rb0_mask) {
1726                                                 raster_config_se |=
1727                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1728                                         } else {
1729                                                 raster_config_se |=
1730                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1731                                         }
1732                                 }
1733                         }
1734                 }
1735
1736                 /* GRBM_GFX_INDEX has a different offset on CI+ */
1737                 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1738                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1739                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1740         }
1741
1742         /* GRBM_GFX_INDEX has a different offset on CI+ */
1743         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1744 }
1745
1746 /**
1747  * gfx_v7_0_setup_rb - setup the RBs on the asic
1748  *
1749  * @adev: amdgpu_device pointer
1750  * @se_num: number of SEs (shader engines) for the asic
1751  * @sh_per_se: number of SH blocks per SE for the asic
1752  *
1753  * Configures per-SE/SH RB registers (CIK).
1754  */
1755 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1756 {
1757         int i, j;
1758         u32 data;
1759         u32 raster_config = 0, raster_config_1 = 0;
1760         u32 active_rbs = 0;
1761         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1762                                         adev->gfx.config.max_sh_per_se;
1763         unsigned num_rb_pipes;
1764
1765         mutex_lock(&adev->grbm_idx_mutex);
1766         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1767                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1768                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1769                         data = gfx_v7_0_get_rb_active_bitmap(adev);
1770                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1771                                                rb_bitmap_width_per_sh);
1772                 }
1773         }
1774         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1775
1776         adev->gfx.config.backend_enable_mask = active_rbs;
1777         adev->gfx.config.num_rbs = hweight32(active_rbs);
1778
1779         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1780                              adev->gfx.config.max_shader_engines, 16);
1781
1782         gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1783
1784         if (!adev->gfx.config.backend_enable_mask ||
1785                         adev->gfx.config.num_rbs >= num_rb_pipes) {
1786                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1787                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1788         } else {
1789                 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1790                                                         adev->gfx.config.backend_enable_mask,
1791                                                         num_rb_pipes);
1792         }
1793         mutex_unlock(&adev->grbm_idx_mutex);
1794 }
1795
1796 /**
1797  * gfx_v7_0_init_compute_vmid - gart enable
1798  *
1799  * @adev: amdgpu_device pointer
1800  *
1801  * Initialize compute vmid sh_mem registers
1802  *
1803  */
1804 #define DEFAULT_SH_MEM_BASES    (0x6000)
1805 #define FIRST_COMPUTE_VMID      (8)
1806 #define LAST_COMPUTE_VMID       (16)
1807 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1808 {
1809         int i;
1810         uint32_t sh_mem_config;
1811         uint32_t sh_mem_bases;
1812
1813         /*
1814          * Configure apertures:
1815          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1816          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1817          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1818         */
1819         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1820         sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1821                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1822         sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1823         mutex_lock(&adev->srbm_mutex);
1824         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1825                 cik_srbm_select(adev, 0, 0, 0, i);
1826                 /* CP and shaders */
1827                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1828                 WREG32(mmSH_MEM_APE1_BASE, 1);
1829                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1830                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1831         }
1832         cik_srbm_select(adev, 0, 0, 0, 0);
1833         mutex_unlock(&adev->srbm_mutex);
1834 }
1835
1836 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1837 {
1838         adev->gfx.config.double_offchip_lds_buf = 1;
1839 }
1840
1841 /**
1842  * gfx_v7_0_gpu_init - setup the 3D engine
1843  *
1844  * @adev: amdgpu_device pointer
1845  *
1846  * Configures the 3D engine and tiling configuration
1847  * registers so that the 3D engine is usable.
1848  */
1849 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1850 {
1851         u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1852         u32 tmp;
1853         int i;
1854
1855         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1856
1857         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1858         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1859         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1860
1861         gfx_v7_0_tiling_mode_table_init(adev);
1862
1863         gfx_v7_0_setup_rb(adev);
1864         gfx_v7_0_get_cu_info(adev);
1865         gfx_v7_0_config_init(adev);
1866
1867         /* set HW defaults for 3D engine */
1868         WREG32(mmCP_MEQ_THRESHOLDS,
1869                (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1870                (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1871
1872         mutex_lock(&adev->grbm_idx_mutex);
1873         /*
1874          * making sure that the following register writes will be broadcasted
1875          * to all the shaders
1876          */
1877         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1878
1879         /* XXX SH_MEM regs */
1880         /* where to put LDS, scratch, GPUVM in FSA64 space */
1881         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1882                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1883         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1884                                    MTYPE_NC);
1885         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1886                                    MTYPE_UC);
1887         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1888
1889         sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1890                                    SWIZZLE_ENABLE, 1);
1891         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1892                                    ELEMENT_SIZE, 1);
1893         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1894                                    INDEX_STRIDE, 3);
1895         WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1896
1897         mutex_lock(&adev->srbm_mutex);
1898         for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1899                 if (i == 0)
1900                         sh_mem_base = 0;
1901                 else
1902                         sh_mem_base = adev->mc.shared_aperture_start >> 48;
1903                 cik_srbm_select(adev, 0, 0, 0, i);
1904                 /* CP and shaders */
1905                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1906                 WREG32(mmSH_MEM_APE1_BASE, 1);
1907                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1908                 WREG32(mmSH_MEM_BASES, sh_mem_base);
1909         }
1910         cik_srbm_select(adev, 0, 0, 0, 0);
1911         mutex_unlock(&adev->srbm_mutex);
1912
1913         gfx_v7_0_init_compute_vmid(adev);
1914
1915         WREG32(mmSX_DEBUG_1, 0x20);
1916
1917         WREG32(mmTA_CNTL_AUX, 0x00010000);
1918
1919         tmp = RREG32(mmSPI_CONFIG_CNTL);
1920         tmp |= 0x03000000;
1921         WREG32(mmSPI_CONFIG_CNTL, tmp);
1922
1923         WREG32(mmSQ_CONFIG, 1);
1924
1925         WREG32(mmDB_DEBUG, 0);
1926
1927         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1928         tmp |= 0x00000400;
1929         WREG32(mmDB_DEBUG2, tmp);
1930
1931         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1932         tmp |= 0x00020200;
1933         WREG32(mmDB_DEBUG3, tmp);
1934
1935         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1936         tmp |= 0x00018208;
1937         WREG32(mmCB_HW_CONTROL, tmp);
1938
1939         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1940
1941         WREG32(mmPA_SC_FIFO_SIZE,
1942                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1943                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1944                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1945                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1946
1947         WREG32(mmVGT_NUM_INSTANCES, 1);
1948
1949         WREG32(mmCP_PERFMON_CNTL, 0);
1950
1951         WREG32(mmSQ_CONFIG, 0);
1952
1953         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1954                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1955                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1956
1957         WREG32(mmVGT_CACHE_INVALIDATION,
1958                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1959                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1960
1961         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1962         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1963
1964         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1965                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1966         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1967
1968         tmp = RREG32(mmSPI_ARB_PRIORITY);
1969         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
1970         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
1971         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
1972         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
1973         WREG32(mmSPI_ARB_PRIORITY, tmp);
1974
1975         mutex_unlock(&adev->grbm_idx_mutex);
1976
1977         udelay(50);
1978 }
1979
1980 /*
1981  * GPU scratch registers helpers function.
1982  */
1983 /**
1984  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1985  *
1986  * @adev: amdgpu_device pointer
1987  *
1988  * Set up the number and offset of the CP scratch registers.
1989  * NOTE: use of CP scratch registers is a legacy inferface and
1990  * is not used by default on newer asics (r6xx+).  On newer asics,
1991  * memory buffers are used for fences rather than scratch regs.
1992  */
1993 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1994 {
1995         adev->gfx.scratch.num_reg = 8;
1996         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1997         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1998 }
1999
2000 /**
2001  * gfx_v7_0_ring_test_ring - basic gfx ring test
2002  *
2003  * @adev: amdgpu_device pointer
2004  * @ring: amdgpu_ring structure holding ring information
2005  *
2006  * Allocate a scratch register and write to it using the gfx ring (CIK).
2007  * Provides a basic gfx ring test to verify that the ring is working.
2008  * Used by gfx_v7_0_cp_gfx_resume();
2009  * Returns 0 on success, error on failure.
2010  */
2011 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2012 {
2013         struct amdgpu_device *adev = ring->adev;
2014         uint32_t scratch;
2015         uint32_t tmp = 0;
2016         unsigned i;
2017         int r;
2018
2019         r = amdgpu_gfx_scratch_get(adev, &scratch);
2020         if (r) {
2021                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2022                 return r;
2023         }
2024         WREG32(scratch, 0xCAFEDEAD);
2025         r = amdgpu_ring_alloc(ring, 3);
2026         if (r) {
2027                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2028                 amdgpu_gfx_scratch_free(adev, scratch);
2029                 return r;
2030         }
2031         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2032         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2033         amdgpu_ring_write(ring, 0xDEADBEEF);
2034         amdgpu_ring_commit(ring);
2035
2036         for (i = 0; i < adev->usec_timeout; i++) {
2037                 tmp = RREG32(scratch);
2038                 if (tmp == 0xDEADBEEF)
2039                         break;
2040                 DRM_UDELAY(1);
2041         }
2042         if (i < adev->usec_timeout) {
2043                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2044         } else {
2045                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2046                           ring->idx, scratch, tmp);
2047                 r = -EINVAL;
2048         }
2049         amdgpu_gfx_scratch_free(adev, scratch);
2050         return r;
2051 }
2052
2053 /**
2054  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2055  *
2056  * @adev: amdgpu_device pointer
2057  * @ridx: amdgpu ring index
2058  *
2059  * Emits an hdp flush on the cp.
2060  */
2061 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2062 {
2063         u32 ref_and_mask;
2064         int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2065
2066         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2067                 switch (ring->me) {
2068                 case 1:
2069                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2070                         break;
2071                 case 2:
2072                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2073                         break;
2074                 default:
2075                         return;
2076                 }
2077         } else {
2078                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2079         }
2080
2081         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2082         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2083                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
2084                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2085         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2086         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2087         amdgpu_ring_write(ring, ref_and_mask);
2088         amdgpu_ring_write(ring, ref_and_mask);
2089         amdgpu_ring_write(ring, 0x20); /* poll interval */
2090 }
2091
2092 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2093 {
2094         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2095         amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2096                 EVENT_INDEX(4));
2097
2098         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2099         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2100                 EVENT_INDEX(0));
2101 }
2102
2103
2104 /**
2105  * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2106  *
2107  * @adev: amdgpu_device pointer
2108  * @ridx: amdgpu ring index
2109  *
2110  * Emits an hdp invalidate on the cp.
2111  */
2112 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2113 {
2114         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2115         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2116                                  WRITE_DATA_DST_SEL(0) |
2117                                  WR_CONFIRM));
2118         amdgpu_ring_write(ring, mmHDP_DEBUG0);
2119         amdgpu_ring_write(ring, 0);
2120         amdgpu_ring_write(ring, 1);
2121 }
2122
2123 /**
2124  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2125  *
2126  * @adev: amdgpu_device pointer
2127  * @fence: amdgpu fence object
2128  *
2129  * Emits a fence sequnce number on the gfx ring and flushes
2130  * GPU caches.
2131  */
2132 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2133                                          u64 seq, unsigned flags)
2134 {
2135         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2136         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2137         /* Workaround for cache flush problems. First send a dummy EOP
2138          * event down the pipe with seq one below.
2139          */
2140         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2141         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2142                                  EOP_TC_ACTION_EN |
2143                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2144                                  EVENT_INDEX(5)));
2145         amdgpu_ring_write(ring, addr & 0xfffffffc);
2146         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2147                                 DATA_SEL(1) | INT_SEL(0));
2148         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2149         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2150
2151         /* Then send the real EOP event down the pipe. */
2152         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2153         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2154                                  EOP_TC_ACTION_EN |
2155                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2156                                  EVENT_INDEX(5)));
2157         amdgpu_ring_write(ring, addr & 0xfffffffc);
2158         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2159                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2160         amdgpu_ring_write(ring, lower_32_bits(seq));
2161         amdgpu_ring_write(ring, upper_32_bits(seq));
2162 }
2163
2164 /**
2165  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2166  *
2167  * @adev: amdgpu_device pointer
2168  * @fence: amdgpu fence object
2169  *
2170  * Emits a fence sequnce number on the compute ring and flushes
2171  * GPU caches.
2172  */
2173 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2174                                              u64 addr, u64 seq,
2175                                              unsigned flags)
2176 {
2177         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2178         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2179
2180         /* RELEASE_MEM - flush caches, send int */
2181         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2182         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2183                                  EOP_TC_ACTION_EN |
2184                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2185                                  EVENT_INDEX(5)));
2186         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2187         amdgpu_ring_write(ring, addr & 0xfffffffc);
2188         amdgpu_ring_write(ring, upper_32_bits(addr));
2189         amdgpu_ring_write(ring, lower_32_bits(seq));
2190         amdgpu_ring_write(ring, upper_32_bits(seq));
2191 }
2192
2193 /*
2194  * IB stuff
2195  */
2196 /**
2197  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2198  *
2199  * @ring: amdgpu_ring structure holding ring information
2200  * @ib: amdgpu indirect buffer object
2201  *
2202  * Emits an DE (drawing engine) or CE (constant engine) IB
2203  * on the gfx ring.  IBs are usually generated by userspace
2204  * acceleration drivers and submitted to the kernel for
2205  * sheduling on the ring.  This function schedules the IB
2206  * on the gfx ring for execution by the GPU.
2207  */
2208 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2209                                       struct amdgpu_ib *ib,
2210                                       unsigned vm_id, bool ctx_switch)
2211 {
2212         u32 header, control = 0;
2213
2214         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2215         if (ctx_switch) {
2216                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2217                 amdgpu_ring_write(ring, 0);
2218         }
2219
2220         if (ib->flags & AMDGPU_IB_FLAG_CE)
2221                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2222         else
2223                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2224
2225         control |= ib->length_dw | (vm_id << 24);
2226
2227         amdgpu_ring_write(ring, header);
2228         amdgpu_ring_write(ring,
2229 #ifdef __BIG_ENDIAN
2230                           (2 << 0) |
2231 #endif
2232                           (ib->gpu_addr & 0xFFFFFFFC));
2233         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2234         amdgpu_ring_write(ring, control);
2235 }
2236
2237 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2238                                           struct amdgpu_ib *ib,
2239                                           unsigned vm_id, bool ctx_switch)
2240 {
2241         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2242
2243         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2244         amdgpu_ring_write(ring,
2245 #ifdef __BIG_ENDIAN
2246                                           (2 << 0) |
2247 #endif
2248                                           (ib->gpu_addr & 0xFFFFFFFC));
2249         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2250         amdgpu_ring_write(ring, control);
2251 }
2252
2253 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2254 {
2255         uint32_t dw2 = 0;
2256
2257         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2258         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2259                 gfx_v7_0_ring_emit_vgt_flush(ring);
2260                 /* set load_global_config & load_global_uconfig */
2261                 dw2 |= 0x8001;
2262                 /* set load_cs_sh_regs */
2263                 dw2 |= 0x01000000;
2264                 /* set load_per_context_state & load_gfx_sh_regs */
2265                 dw2 |= 0x10002;
2266         }
2267
2268         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2269         amdgpu_ring_write(ring, dw2);
2270         amdgpu_ring_write(ring, 0);
2271 }
2272
2273 /**
2274  * gfx_v7_0_ring_test_ib - basic ring IB test
2275  *
2276  * @ring: amdgpu_ring structure holding ring information
2277  *
2278  * Allocate an IB and execute it on the gfx ring (CIK).
2279  * Provides a basic gfx ring test to verify that IBs are working.
2280  * Returns 0 on success, error on failure.
2281  */
2282 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2283 {
2284         struct amdgpu_device *adev = ring->adev;
2285         struct amdgpu_ib ib;
2286         struct dma_fence *f = NULL;
2287         uint32_t scratch;
2288         uint32_t tmp = 0;
2289         long r;
2290
2291         r = amdgpu_gfx_scratch_get(adev, &scratch);
2292         if (r) {
2293                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
2294                 return r;
2295         }
2296         WREG32(scratch, 0xCAFEDEAD);
2297         memset(&ib, 0, sizeof(ib));
2298         r = amdgpu_ib_get(adev, NULL, 256, &ib);
2299         if (r) {
2300                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
2301                 goto err1;
2302         }
2303         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2304         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2305         ib.ptr[2] = 0xDEADBEEF;
2306         ib.length_dw = 3;
2307
2308         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2309         if (r)
2310                 goto err2;
2311
2312         r = dma_fence_wait_timeout(f, false, timeout);
2313         if (r == 0) {
2314                 DRM_ERROR("amdgpu: IB test timed out\n");
2315                 r = -ETIMEDOUT;
2316                 goto err2;
2317         } else if (r < 0) {
2318                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
2319                 goto err2;
2320         }
2321         tmp = RREG32(scratch);
2322         if (tmp == 0xDEADBEEF) {
2323                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
2324                 r = 0;
2325         } else {
2326                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2327                           scratch, tmp);
2328                 r = -EINVAL;
2329         }
2330
2331 err2:
2332         amdgpu_ib_free(adev, &ib, NULL);
2333         dma_fence_put(f);
2334 err1:
2335         amdgpu_gfx_scratch_free(adev, scratch);
2336         return r;
2337 }
2338
2339 /*
2340  * CP.
2341  * On CIK, gfx and compute now have independant command processors.
2342  *
2343  * GFX
2344  * Gfx consists of a single ring and can process both gfx jobs and
2345  * compute jobs.  The gfx CP consists of three microengines (ME):
2346  * PFP - Pre-Fetch Parser
2347  * ME - Micro Engine
2348  * CE - Constant Engine
2349  * The PFP and ME make up what is considered the Drawing Engine (DE).
2350  * The CE is an asynchronous engine used for updating buffer desciptors
2351  * used by the DE so that they can be loaded into cache in parallel
2352  * while the DE is processing state update packets.
2353  *
2354  * Compute
2355  * The compute CP consists of two microengines (ME):
2356  * MEC1 - Compute MicroEngine 1
2357  * MEC2 - Compute MicroEngine 2
2358  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2359  * The queues are exposed to userspace and are programmed directly
2360  * by the compute runtime.
2361  */
2362 /**
2363  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2364  *
2365  * @adev: amdgpu_device pointer
2366  * @enable: enable or disable the MEs
2367  *
2368  * Halts or unhalts the gfx MEs.
2369  */
2370 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2371 {
2372         int i;
2373
2374         if (enable) {
2375                 WREG32(mmCP_ME_CNTL, 0);
2376         } else {
2377                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2378                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2379                         adev->gfx.gfx_ring[i].ready = false;
2380         }
2381         udelay(50);
2382 }
2383
2384 /**
2385  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2386  *
2387  * @adev: amdgpu_device pointer
2388  *
2389  * Loads the gfx PFP, ME, and CE ucode.
2390  * Returns 0 for success, -EINVAL if the ucode is not available.
2391  */
2392 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2393 {
2394         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2395         const struct gfx_firmware_header_v1_0 *ce_hdr;
2396         const struct gfx_firmware_header_v1_0 *me_hdr;
2397         const __le32 *fw_data;
2398         unsigned i, fw_size;
2399
2400         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2401                 return -EINVAL;
2402
2403         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2404         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2405         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2406
2407         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2408         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2409         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2410         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2411         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2412         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2413         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2414         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2415         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2416
2417         gfx_v7_0_cp_gfx_enable(adev, false);
2418
2419         /* PFP */
2420         fw_data = (const __le32 *)
2421                 (adev->gfx.pfp_fw->data +
2422                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2423         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2424         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2425         for (i = 0; i < fw_size; i++)
2426                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2427         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2428
2429         /* CE */
2430         fw_data = (const __le32 *)
2431                 (adev->gfx.ce_fw->data +
2432                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2433         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2434         WREG32(mmCP_CE_UCODE_ADDR, 0);
2435         for (i = 0; i < fw_size; i++)
2436                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2437         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2438
2439         /* ME */
2440         fw_data = (const __le32 *)
2441                 (adev->gfx.me_fw->data +
2442                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2443         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2444         WREG32(mmCP_ME_RAM_WADDR, 0);
2445         for (i = 0; i < fw_size; i++)
2446                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2447         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2448
2449         return 0;
2450 }
2451
2452 /**
2453  * gfx_v7_0_cp_gfx_start - start the gfx ring
2454  *
2455  * @adev: amdgpu_device pointer
2456  *
2457  * Enables the ring and loads the clear state context and other
2458  * packets required to init the ring.
2459  * Returns 0 for success, error for failure.
2460  */
2461 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2462 {
2463         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2464         const struct cs_section_def *sect = NULL;
2465         const struct cs_extent_def *ext = NULL;
2466         int r, i;
2467
2468         /* init the CP */
2469         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2470         WREG32(mmCP_ENDIAN_SWAP, 0);
2471         WREG32(mmCP_DEVICE_ID, 1);
2472
2473         gfx_v7_0_cp_gfx_enable(adev, true);
2474
2475         r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2476         if (r) {
2477                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2478                 return r;
2479         }
2480
2481         /* init the CE partitions.  CE only used for gfx on CIK */
2482         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2483         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2484         amdgpu_ring_write(ring, 0x8000);
2485         amdgpu_ring_write(ring, 0x8000);
2486
2487         /* clear state buffer */
2488         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2489         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2490
2491         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2492         amdgpu_ring_write(ring, 0x80000000);
2493         amdgpu_ring_write(ring, 0x80000000);
2494
2495         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2496                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2497                         if (sect->id == SECT_CONTEXT) {
2498                                 amdgpu_ring_write(ring,
2499                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2500                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2501                                 for (i = 0; i < ext->reg_count; i++)
2502                                         amdgpu_ring_write(ring, ext->extent[i]);
2503                         }
2504                 }
2505         }
2506
2507         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2508         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2509         switch (adev->asic_type) {
2510         case CHIP_BONAIRE:
2511                 amdgpu_ring_write(ring, 0x16000012);
2512                 amdgpu_ring_write(ring, 0x00000000);
2513                 break;
2514         case CHIP_KAVERI:
2515                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2516                 amdgpu_ring_write(ring, 0x00000000);
2517                 break;
2518         case CHIP_KABINI:
2519         case CHIP_MULLINS:
2520                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2521                 amdgpu_ring_write(ring, 0x00000000);
2522                 break;
2523         case CHIP_HAWAII:
2524                 amdgpu_ring_write(ring, 0x3a00161a);
2525                 amdgpu_ring_write(ring, 0x0000002e);
2526                 break;
2527         default:
2528                 amdgpu_ring_write(ring, 0x00000000);
2529                 amdgpu_ring_write(ring, 0x00000000);
2530                 break;
2531         }
2532
2533         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2534         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2535
2536         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2537         amdgpu_ring_write(ring, 0);
2538
2539         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2540         amdgpu_ring_write(ring, 0x00000316);
2541         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2542         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2543
2544         amdgpu_ring_commit(ring);
2545
2546         return 0;
2547 }
2548
2549 /**
2550  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2551  *
2552  * @adev: amdgpu_device pointer
2553  *
2554  * Program the location and size of the gfx ring buffer
2555  * and test it to make sure it's working.
2556  * Returns 0 for success, error for failure.
2557  */
2558 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2559 {
2560         struct amdgpu_ring *ring;
2561         u32 tmp;
2562         u32 rb_bufsz;
2563         u64 rb_addr, rptr_addr;
2564         int r;
2565
2566         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2567         if (adev->asic_type != CHIP_HAWAII)
2568                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2569
2570         /* Set the write pointer delay */
2571         WREG32(mmCP_RB_WPTR_DELAY, 0);
2572
2573         /* set the RB to use vmid 0 */
2574         WREG32(mmCP_RB_VMID, 0);
2575
2576         WREG32(mmSCRATCH_ADDR, 0);
2577
2578         /* ring 0 - compute and gfx */
2579         /* Set ring buffer size */
2580         ring = &adev->gfx.gfx_ring[0];
2581         rb_bufsz = order_base_2(ring->ring_size / 8);
2582         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2583 #ifdef __BIG_ENDIAN
2584         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2585 #endif
2586         WREG32(mmCP_RB0_CNTL, tmp);
2587
2588         /* Initialize the ring buffer's read and write pointers */
2589         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2590         ring->wptr = 0;
2591         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2592
2593         /* set the wb address wether it's enabled or not */
2594         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2595         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2596         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2597
2598         /* scratch register shadowing is no longer supported */
2599         WREG32(mmSCRATCH_UMSK, 0);
2600
2601         mdelay(1);
2602         WREG32(mmCP_RB0_CNTL, tmp);
2603
2604         rb_addr = ring->gpu_addr >> 8;
2605         WREG32(mmCP_RB0_BASE, rb_addr);
2606         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2607
2608         /* start the ring */
2609         gfx_v7_0_cp_gfx_start(adev);
2610         ring->ready = true;
2611         r = amdgpu_ring_test_ring(ring);
2612         if (r) {
2613                 ring->ready = false;
2614                 return r;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2621 {
2622         return ring->adev->wb.wb[ring->rptr_offs];
2623 }
2624
2625 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2626 {
2627         struct amdgpu_device *adev = ring->adev;
2628
2629         return RREG32(mmCP_RB0_WPTR);
2630 }
2631
2632 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2633 {
2634         struct amdgpu_device *adev = ring->adev;
2635
2636         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2637         (void)RREG32(mmCP_RB0_WPTR);
2638 }
2639
2640 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2641 {
2642         /* XXX check if swapping is necessary on BE */
2643         return ring->adev->wb.wb[ring->wptr_offs];
2644 }
2645
2646 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2647 {
2648         struct amdgpu_device *adev = ring->adev;
2649
2650         /* XXX check if swapping is necessary on BE */
2651         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2652         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2653 }
2654
2655 /**
2656  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2657  *
2658  * @adev: amdgpu_device pointer
2659  * @enable: enable or disable the MEs
2660  *
2661  * Halts or unhalts the compute MEs.
2662  */
2663 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2664 {
2665         int i;
2666
2667         if (enable) {
2668                 WREG32(mmCP_MEC_CNTL, 0);
2669         } else {
2670                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2671                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2672                         adev->gfx.compute_ring[i].ready = false;
2673         }
2674         udelay(50);
2675 }
2676
2677 /**
2678  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2679  *
2680  * @adev: amdgpu_device pointer
2681  *
2682  * Loads the compute MEC1&2 ucode.
2683  * Returns 0 for success, -EINVAL if the ucode is not available.
2684  */
2685 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2686 {
2687         const struct gfx_firmware_header_v1_0 *mec_hdr;
2688         const __le32 *fw_data;
2689         unsigned i, fw_size;
2690
2691         if (!adev->gfx.mec_fw)
2692                 return -EINVAL;
2693
2694         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2695         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2696         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2697         adev->gfx.mec_feature_version = le32_to_cpu(
2698                                         mec_hdr->ucode_feature_version);
2699
2700         gfx_v7_0_cp_compute_enable(adev, false);
2701
2702         /* MEC1 */
2703         fw_data = (const __le32 *)
2704                 (adev->gfx.mec_fw->data +
2705                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2706         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2707         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2708         for (i = 0; i < fw_size; i++)
2709                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2710         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2711
2712         if (adev->asic_type == CHIP_KAVERI) {
2713                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2714
2715                 if (!adev->gfx.mec2_fw)
2716                         return -EINVAL;
2717
2718                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2719                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2720                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2721                 adev->gfx.mec2_feature_version = le32_to_cpu(
2722                                 mec2_hdr->ucode_feature_version);
2723
2724                 /* MEC2 */
2725                 fw_data = (const __le32 *)
2726                         (adev->gfx.mec2_fw->data +
2727                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2728                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2729                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2730                 for (i = 0; i < fw_size; i++)
2731                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2732                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2733         }
2734
2735         return 0;
2736 }
2737
2738 /**
2739  * gfx_v7_0_cp_compute_fini - stop the compute queues
2740  *
2741  * @adev: amdgpu_device pointer
2742  *
2743  * Stop the compute queues and tear down the driver queue
2744  * info.
2745  */
2746 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2747 {
2748         int i;
2749
2750         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2751                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2752
2753                 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2754         }
2755 }
2756
2757 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2758 {
2759         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2760 }
2761
2762 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2763 {
2764         int r;
2765         u32 *hpd;
2766         size_t mec_hpd_size;
2767
2768         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2769
2770         /* take ownership of the relevant compute queues */
2771         amdgpu_gfx_compute_queue_acquire(adev);
2772
2773         /* allocate space for ALL pipes (even the ones we don't own) */
2774         mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2775                 * GFX7_MEC_HPD_SIZE * 2;
2776
2777         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2778                                       AMDGPU_GEM_DOMAIN_GTT,
2779                                       &adev->gfx.mec.hpd_eop_obj,
2780                                       &adev->gfx.mec.hpd_eop_gpu_addr,
2781                                       (void **)&hpd);
2782         if (r) {
2783                 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2784                 gfx_v7_0_mec_fini(adev);
2785                 return r;
2786         }
2787
2788         /* clear memory.  Not sure if this is required or not */
2789         memset(hpd, 0, mec_hpd_size);
2790
2791         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2792         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2793
2794         return 0;
2795 }
2796
2797 struct hqd_registers
2798 {
2799         u32 cp_mqd_base_addr;
2800         u32 cp_mqd_base_addr_hi;
2801         u32 cp_hqd_active;
2802         u32 cp_hqd_vmid;
2803         u32 cp_hqd_persistent_state;
2804         u32 cp_hqd_pipe_priority;
2805         u32 cp_hqd_queue_priority;
2806         u32 cp_hqd_quantum;
2807         u32 cp_hqd_pq_base;
2808         u32 cp_hqd_pq_base_hi;
2809         u32 cp_hqd_pq_rptr;
2810         u32 cp_hqd_pq_rptr_report_addr;
2811         u32 cp_hqd_pq_rptr_report_addr_hi;
2812         u32 cp_hqd_pq_wptr_poll_addr;
2813         u32 cp_hqd_pq_wptr_poll_addr_hi;
2814         u32 cp_hqd_pq_doorbell_control;
2815         u32 cp_hqd_pq_wptr;
2816         u32 cp_hqd_pq_control;
2817         u32 cp_hqd_ib_base_addr;
2818         u32 cp_hqd_ib_base_addr_hi;
2819         u32 cp_hqd_ib_rptr;
2820         u32 cp_hqd_ib_control;
2821         u32 cp_hqd_iq_timer;
2822         u32 cp_hqd_iq_rptr;
2823         u32 cp_hqd_dequeue_request;
2824         u32 cp_hqd_dma_offload;
2825         u32 cp_hqd_sema_cmd;
2826         u32 cp_hqd_msg_type;
2827         u32 cp_hqd_atomic0_preop_lo;
2828         u32 cp_hqd_atomic0_preop_hi;
2829         u32 cp_hqd_atomic1_preop_lo;
2830         u32 cp_hqd_atomic1_preop_hi;
2831         u32 cp_hqd_hq_scheduler0;
2832         u32 cp_hqd_hq_scheduler1;
2833         u32 cp_mqd_control;
2834 };
2835
2836 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2837                                        int mec, int pipe)
2838 {
2839         u64 eop_gpu_addr;
2840         u32 tmp;
2841         size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2842                             * GFX7_MEC_HPD_SIZE * 2;
2843
2844         mutex_lock(&adev->srbm_mutex);
2845         eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2846
2847         cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2848
2849         /* write the EOP addr */
2850         WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2851         WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2852
2853         /* set the VMID assigned */
2854         WREG32(mmCP_HPD_EOP_VMID, 0);
2855
2856         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2857         tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2858         tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2859         tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2860         WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2861
2862         cik_srbm_select(adev, 0, 0, 0, 0);
2863         mutex_unlock(&adev->srbm_mutex);
2864 }
2865
2866 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2867 {
2868         int i;
2869
2870         /* disable the queue if it's active */
2871         if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2872                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2873                 for (i = 0; i < adev->usec_timeout; i++) {
2874                         if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2875                                 break;
2876                         udelay(1);
2877                 }
2878
2879                 if (i == adev->usec_timeout)
2880                         return -ETIMEDOUT;
2881
2882                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2883                 WREG32(mmCP_HQD_PQ_RPTR, 0);
2884                 WREG32(mmCP_HQD_PQ_WPTR, 0);
2885         }
2886
2887         return 0;
2888 }
2889
2890 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2891                              struct cik_mqd *mqd,
2892                              uint64_t mqd_gpu_addr,
2893                              struct amdgpu_ring *ring)
2894 {
2895         u64 hqd_gpu_addr;
2896         u64 wb_gpu_addr;
2897
2898         /* init the mqd struct */
2899         memset(mqd, 0, sizeof(struct cik_mqd));
2900
2901         mqd->header = 0xC0310800;
2902         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2903         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2904         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2905         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2906
2907         /* enable doorbell? */
2908         mqd->cp_hqd_pq_doorbell_control =
2909                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2910         if (ring->use_doorbell)
2911                 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2912         else
2913                 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2914
2915         /* set the pointer to the MQD */
2916         mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2917         mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2918
2919         /* set MQD vmid to 0 */
2920         mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2921         mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2922
2923         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2924         hqd_gpu_addr = ring->gpu_addr >> 8;
2925         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2926         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2927
2928         /* set up the HQD, this is similar to CP_RB0_CNTL */
2929         mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2930         mqd->cp_hqd_pq_control &=
2931                 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2932                                 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2933
2934         mqd->cp_hqd_pq_control |=
2935                 order_base_2(ring->ring_size / 8);
2936         mqd->cp_hqd_pq_control |=
2937                 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2938 #ifdef __BIG_ENDIAN
2939         mqd->cp_hqd_pq_control |=
2940                 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2941 #endif
2942         mqd->cp_hqd_pq_control &=
2943                 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2944                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2945                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2946         mqd->cp_hqd_pq_control |=
2947                 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2948                 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2949
2950         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2951         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2952         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2953         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2954
2955         /* set the wb address wether it's enabled or not */
2956         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2957         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2958         mqd->cp_hqd_pq_rptr_report_addr_hi =
2959                 upper_32_bits(wb_gpu_addr) & 0xffff;
2960
2961         /* enable the doorbell if requested */
2962         if (ring->use_doorbell) {
2963                 mqd->cp_hqd_pq_doorbell_control =
2964                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2965                 mqd->cp_hqd_pq_doorbell_control &=
2966                         ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2967                 mqd->cp_hqd_pq_doorbell_control |=
2968                         (ring->doorbell_index <<
2969                          CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2970                 mqd->cp_hqd_pq_doorbell_control |=
2971                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2972                 mqd->cp_hqd_pq_doorbell_control &=
2973                         ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2974                                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2975
2976         } else {
2977                 mqd->cp_hqd_pq_doorbell_control = 0;
2978         }
2979
2980         /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2981         ring->wptr = 0;
2982         mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
2983         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2984
2985         /* set the vmid for the queue */
2986         mqd->cp_hqd_vmid = 0;
2987
2988         /* defaults */
2989         mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
2990         mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
2991         mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
2992         mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
2993         mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
2994         mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
2995         mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
2996         mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
2997         mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
2998         mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
2999         mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
3000         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3001         mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
3002         mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
3003         mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
3004         mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
3005
3006         /* activate the queue */
3007         mqd->cp_hqd_active = 1;
3008 }
3009
3010 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
3011 {
3012         uint32_t tmp;
3013         uint32_t mqd_reg;
3014         uint32_t *mqd_data;
3015
3016         /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3017         mqd_data = &mqd->cp_mqd_base_addr_lo;
3018
3019         /* disable wptr polling */
3020         tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3021         tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3022         WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3023
3024         /* program all HQD registers */
3025         for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
3026                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3027
3028         /* activate the HQD */
3029         for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3030                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3031
3032         return 0;
3033 }
3034
3035 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
3036 {
3037         int r;
3038         u64 mqd_gpu_addr;
3039         struct cik_mqd *mqd;
3040         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3041
3042         r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
3043                                       AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
3044                                       &mqd_gpu_addr, (void **)&mqd);
3045         if (r) {
3046                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3047                 return r;
3048         }
3049
3050         mutex_lock(&adev->srbm_mutex);
3051         cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3052
3053         gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
3054         gfx_v7_0_mqd_deactivate(adev);
3055         gfx_v7_0_mqd_commit(adev, mqd);
3056
3057         cik_srbm_select(adev, 0, 0, 0, 0);
3058         mutex_unlock(&adev->srbm_mutex);
3059
3060         amdgpu_bo_kunmap(ring->mqd_obj);
3061         amdgpu_bo_unreserve(ring->mqd_obj);
3062         return 0;
3063 }
3064
3065 /**
3066  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3067  *
3068  * @adev: amdgpu_device pointer
3069  *
3070  * Program the compute queues and test them to make sure they
3071  * are working.
3072  * Returns 0 for success, error for failure.
3073  */
3074 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3075 {
3076         int r, i, j;
3077         u32 tmp;
3078         struct amdgpu_ring *ring;
3079
3080         /* fix up chicken bits */
3081         tmp = RREG32(mmCP_CPF_DEBUG);
3082         tmp |= (1 << 23);
3083         WREG32(mmCP_CPF_DEBUG, tmp);
3084
3085         /* init all pipes (even the ones we don't own) */
3086         for (i = 0; i < adev->gfx.mec.num_mec; i++)
3087                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3088                         gfx_v7_0_compute_pipe_init(adev, i, j);
3089
3090         /* init the queues */
3091         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3092                 r = gfx_v7_0_compute_queue_init(adev, i);
3093                 if (r) {
3094                         gfx_v7_0_cp_compute_fini(adev);
3095                         return r;
3096                 }
3097         }
3098
3099         gfx_v7_0_cp_compute_enable(adev, true);
3100
3101         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3102                 ring = &adev->gfx.compute_ring[i];
3103                 ring->ready = true;
3104                 r = amdgpu_ring_test_ring(ring);
3105                 if (r)
3106                         ring->ready = false;
3107         }
3108
3109         return 0;
3110 }
3111
3112 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3113 {
3114         gfx_v7_0_cp_gfx_enable(adev, enable);
3115         gfx_v7_0_cp_compute_enable(adev, enable);
3116 }
3117
3118 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3119 {
3120         int r;
3121
3122         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3123         if (r)
3124                 return r;
3125         r = gfx_v7_0_cp_compute_load_microcode(adev);
3126         if (r)
3127                 return r;
3128
3129         return 0;
3130 }
3131
3132 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3133                                                bool enable)
3134 {
3135         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3136
3137         if (enable)
3138                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3139                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3140         else
3141                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3142                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3143         WREG32(mmCP_INT_CNTL_RING0, tmp);
3144 }
3145
3146 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3147 {
3148         int r;
3149
3150         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3151
3152         r = gfx_v7_0_cp_load_microcode(adev);
3153         if (r)
3154                 return r;
3155
3156         r = gfx_v7_0_cp_gfx_resume(adev);
3157         if (r)
3158                 return r;
3159         r = gfx_v7_0_cp_compute_resume(adev);
3160         if (r)
3161                 return r;
3162
3163         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3164
3165         return 0;
3166 }
3167
3168 /**
3169  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3170  *
3171  * @ring: the ring to emmit the commands to
3172  *
3173  * Sync the command pipeline with the PFP. E.g. wait for everything
3174  * to be completed.
3175  */
3176 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3177 {
3178         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3179         uint32_t seq = ring->fence_drv.sync_seq;
3180         uint64_t addr = ring->fence_drv.gpu_addr;
3181
3182         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3183         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3184                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
3185                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3186         amdgpu_ring_write(ring, addr & 0xfffffffc);
3187         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3188         amdgpu_ring_write(ring, seq);
3189         amdgpu_ring_write(ring, 0xffffffff);
3190         amdgpu_ring_write(ring, 4); /* poll interval */
3191
3192         if (usepfp) {
3193                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3194                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3195                 amdgpu_ring_write(ring, 0);
3196                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3197                 amdgpu_ring_write(ring, 0);
3198         }
3199 }
3200
3201 /*
3202  * vm
3203  * VMID 0 is the physical GPU addresses as used by the kernel.
3204  * VMIDs 1-15 are used for userspace clients and are handled
3205  * by the amdgpu vm/hsa code.
3206  */
3207 /**
3208  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3209  *
3210  * @adev: amdgpu_device pointer
3211  *
3212  * Update the page table base and flush the VM TLB
3213  * using the CP (CIK).
3214  */
3215 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3216                                         unsigned vm_id, uint64_t pd_addr)
3217 {
3218         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3219
3220         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3221         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3222                                  WRITE_DATA_DST_SEL(0)));
3223         if (vm_id < 8) {
3224                 amdgpu_ring_write(ring,
3225                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3226         } else {
3227                 amdgpu_ring_write(ring,
3228                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3229         }
3230         amdgpu_ring_write(ring, 0);
3231         amdgpu_ring_write(ring, pd_addr >> 12);
3232
3233         /* bits 0-15 are the VM contexts0-15 */
3234         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3235         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3236                                  WRITE_DATA_DST_SEL(0)));
3237         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3238         amdgpu_ring_write(ring, 0);
3239         amdgpu_ring_write(ring, 1 << vm_id);
3240
3241         /* wait for the invalidate to complete */
3242         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3243         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3244                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3245                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3246         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3247         amdgpu_ring_write(ring, 0);
3248         amdgpu_ring_write(ring, 0); /* ref */
3249         amdgpu_ring_write(ring, 0); /* mask */
3250         amdgpu_ring_write(ring, 0x20); /* poll interval */
3251
3252         /* compute doesn't have PFP */
3253         if (usepfp) {
3254                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3255                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3256                 amdgpu_ring_write(ring, 0x0);
3257
3258                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3259                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3260                 amdgpu_ring_write(ring, 0);
3261                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3262                 amdgpu_ring_write(ring, 0);
3263         }
3264 }
3265
3266 /*
3267  * RLC
3268  * The RLC is a multi-purpose microengine that handles a
3269  * variety of functions.
3270  */
3271 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3272 {
3273         amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
3274         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
3275         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
3276 }
3277
3278 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3279 {
3280         const u32 *src_ptr;
3281         volatile u32 *dst_ptr;
3282         u32 dws, i;
3283         const struct cs_section_def *cs_data;
3284         int r;
3285
3286         /* allocate rlc buffers */
3287         if (adev->flags & AMD_IS_APU) {
3288                 if (adev->asic_type == CHIP_KAVERI) {
3289                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3290                         adev->gfx.rlc.reg_list_size =
3291                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3292                 } else {
3293                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3294                         adev->gfx.rlc.reg_list_size =
3295                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3296                 }
3297         }
3298         adev->gfx.rlc.cs_data = ci_cs_data;
3299         adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3300         adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3301
3302         src_ptr = adev->gfx.rlc.reg_list;
3303         dws = adev->gfx.rlc.reg_list_size;
3304         dws += (5 * 16) + 48 + 48 + 64;
3305
3306         cs_data = adev->gfx.rlc.cs_data;
3307
3308         if (src_ptr) {
3309                 /* save restore block */
3310                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3311                                               AMDGPU_GEM_DOMAIN_VRAM,
3312                                               &adev->gfx.rlc.save_restore_obj,
3313                                               &adev->gfx.rlc.save_restore_gpu_addr,
3314                                               (void **)&adev->gfx.rlc.sr_ptr);
3315                 if (r) {
3316                         dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r);
3317                         gfx_v7_0_rlc_fini(adev);
3318                         return r;
3319                 }
3320
3321                 /* write the sr buffer */
3322                 dst_ptr = adev->gfx.rlc.sr_ptr;
3323                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3324                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3325                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3326                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3327         }
3328
3329         if (cs_data) {
3330                 /* clear state block */
3331                 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3332
3333                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3334                                               AMDGPU_GEM_DOMAIN_VRAM,
3335                                               &adev->gfx.rlc.clear_state_obj,
3336                                               &adev->gfx.rlc.clear_state_gpu_addr,
3337                                               (void **)&adev->gfx.rlc.cs_ptr);
3338                 if (r) {
3339                         dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3340                         gfx_v7_0_rlc_fini(adev);
3341                         return r;
3342                 }
3343
3344                 /* set up the cs buffer */
3345                 dst_ptr = adev->gfx.rlc.cs_ptr;
3346                 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3347                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3348                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3349         }
3350
3351         if (adev->gfx.rlc.cp_table_size) {
3352
3353                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
3354                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
3355                                               &adev->gfx.rlc.cp_table_obj,
3356                                               &adev->gfx.rlc.cp_table_gpu_addr,
3357                                               (void **)&adev->gfx.rlc.cp_table_ptr);
3358                 if (r) {
3359                         dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3360                         gfx_v7_0_rlc_fini(adev);
3361                         return r;
3362                 }
3363
3364                 gfx_v7_0_init_cp_pg_table(adev);
3365
3366                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3367                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3368
3369         }
3370
3371         return 0;
3372 }
3373
3374 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3375 {
3376         u32 tmp;
3377
3378         tmp = RREG32(mmRLC_LB_CNTL);
3379         if (enable)
3380                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3381         else
3382                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3383         WREG32(mmRLC_LB_CNTL, tmp);
3384 }
3385
3386 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3387 {
3388         u32 i, j, k;
3389         u32 mask;
3390
3391         mutex_lock(&adev->grbm_idx_mutex);
3392         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3393                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3394                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3395                         for (k = 0; k < adev->usec_timeout; k++) {
3396                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3397                                         break;
3398                                 udelay(1);
3399                         }
3400                 }
3401         }
3402         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3403         mutex_unlock(&adev->grbm_idx_mutex);
3404
3405         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3406                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3407                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3408                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3409         for (k = 0; k < adev->usec_timeout; k++) {
3410                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3411                         break;
3412                 udelay(1);
3413         }
3414 }
3415
3416 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3417 {
3418         u32 tmp;
3419
3420         tmp = RREG32(mmRLC_CNTL);
3421         if (tmp != rlc)
3422                 WREG32(mmRLC_CNTL, rlc);
3423 }
3424
3425 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3426 {
3427         u32 data, orig;
3428
3429         orig = data = RREG32(mmRLC_CNTL);
3430
3431         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3432                 u32 i;
3433
3434                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3435                 WREG32(mmRLC_CNTL, data);
3436
3437                 for (i = 0; i < adev->usec_timeout; i++) {
3438                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3439                                 break;
3440                         udelay(1);
3441                 }
3442
3443                 gfx_v7_0_wait_for_rlc_serdes(adev);
3444         }
3445
3446         return orig;
3447 }
3448
3449 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3450 {
3451         u32 tmp, i, mask;
3452
3453         tmp = 0x1 | (1 << 1);
3454         WREG32(mmRLC_GPR_REG2, tmp);
3455
3456         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3457                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3458         for (i = 0; i < adev->usec_timeout; i++) {
3459                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3460                         break;
3461                 udelay(1);
3462         }
3463
3464         for (i = 0; i < adev->usec_timeout; i++) {
3465                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3466                         break;
3467                 udelay(1);
3468         }
3469 }
3470
3471 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3472 {
3473         u32 tmp;
3474
3475         tmp = 0x1 | (0 << 1);
3476         WREG32(mmRLC_GPR_REG2, tmp);
3477 }
3478
3479 /**
3480  * gfx_v7_0_rlc_stop - stop the RLC ME
3481  *
3482  * @adev: amdgpu_device pointer
3483  *
3484  * Halt the RLC ME (MicroEngine) (CIK).
3485  */
3486 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3487 {
3488         WREG32(mmRLC_CNTL, 0);
3489
3490         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3491
3492         gfx_v7_0_wait_for_rlc_serdes(adev);
3493 }
3494
3495 /**
3496  * gfx_v7_0_rlc_start - start the RLC ME
3497  *
3498  * @adev: amdgpu_device pointer
3499  *
3500  * Unhalt the RLC ME (MicroEngine) (CIK).
3501  */
3502 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3503 {
3504         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3505
3506         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3507
3508         udelay(50);
3509 }
3510
3511 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3512 {
3513         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3514
3515         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3516         WREG32(mmGRBM_SOFT_RESET, tmp);
3517         udelay(50);
3518         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3519         WREG32(mmGRBM_SOFT_RESET, tmp);
3520         udelay(50);
3521 }
3522
3523 /**
3524  * gfx_v7_0_rlc_resume - setup the RLC hw
3525  *
3526  * @adev: amdgpu_device pointer
3527  *
3528  * Initialize the RLC registers, load the ucode,
3529  * and start the RLC (CIK).
3530  * Returns 0 for success, -EINVAL if the ucode is not available.
3531  */
3532 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3533 {
3534         const struct rlc_firmware_header_v1_0 *hdr;
3535         const __le32 *fw_data;
3536         unsigned i, fw_size;
3537         u32 tmp;
3538
3539         if (!adev->gfx.rlc_fw)
3540                 return -EINVAL;
3541
3542         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3543         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3544         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3545         adev->gfx.rlc_feature_version = le32_to_cpu(
3546                                         hdr->ucode_feature_version);
3547
3548         gfx_v7_0_rlc_stop(adev);
3549
3550         /* disable CG */
3551         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3552         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3553
3554         gfx_v7_0_rlc_reset(adev);
3555
3556         gfx_v7_0_init_pg(adev);
3557
3558         WREG32(mmRLC_LB_CNTR_INIT, 0);
3559         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3560
3561         mutex_lock(&adev->grbm_idx_mutex);
3562         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3563         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3564         WREG32(mmRLC_LB_PARAMS, 0x00600408);
3565         WREG32(mmRLC_LB_CNTL, 0x80000004);
3566         mutex_unlock(&adev->grbm_idx_mutex);
3567
3568         WREG32(mmRLC_MC_CNTL, 0);
3569         WREG32(mmRLC_UCODE_CNTL, 0);
3570
3571         fw_data = (const __le32 *)
3572                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3573         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3574         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3575         for (i = 0; i < fw_size; i++)
3576                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3577         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3578
3579         /* XXX - find out what chips support lbpw */
3580         gfx_v7_0_enable_lbpw(adev, false);
3581
3582         if (adev->asic_type == CHIP_BONAIRE)
3583                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3584
3585         gfx_v7_0_rlc_start(adev);
3586
3587         return 0;
3588 }
3589
3590 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3591 {
3592         u32 data, orig, tmp, tmp2;
3593
3594         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3595
3596         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3597                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3598
3599                 tmp = gfx_v7_0_halt_rlc(adev);
3600
3601                 mutex_lock(&adev->grbm_idx_mutex);
3602                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3603                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3604                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3605                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3606                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3607                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3608                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3609                 mutex_unlock(&adev->grbm_idx_mutex);
3610
3611                 gfx_v7_0_update_rlc(adev, tmp);
3612
3613                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3614                 if (orig != data)
3615                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3616
3617         } else {
3618                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3619
3620                 RREG32(mmCB_CGTT_SCLK_CTRL);
3621                 RREG32(mmCB_CGTT_SCLK_CTRL);
3622                 RREG32(mmCB_CGTT_SCLK_CTRL);
3623                 RREG32(mmCB_CGTT_SCLK_CTRL);
3624
3625                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3626                 if (orig != data)
3627                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3628
3629                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3630         }
3631 }
3632
3633 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3634 {
3635         u32 data, orig, tmp = 0;
3636
3637         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3638                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3639                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3640                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3641                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3642                                 if (orig != data)
3643                                         WREG32(mmCP_MEM_SLP_CNTL, data);
3644                         }
3645                 }
3646
3647                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3648                 data |= 0x00000001;
3649                 data &= 0xfffffffd;
3650                 if (orig != data)
3651                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3652
3653                 tmp = gfx_v7_0_halt_rlc(adev);
3654
3655                 mutex_lock(&adev->grbm_idx_mutex);
3656                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3657                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3658                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3659                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3660                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3661                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3662                 mutex_unlock(&adev->grbm_idx_mutex);
3663
3664                 gfx_v7_0_update_rlc(adev, tmp);
3665
3666                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3667                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3668                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3669                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3670                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3671                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3672                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3673                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3674                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3675                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3676                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3677                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3678                         if (orig != data)
3679                                 WREG32(mmCGTS_SM_CTRL_REG, data);
3680                 }
3681         } else {
3682                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3683                 data |= 0x00000003;
3684                 if (orig != data)
3685                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3686
3687                 data = RREG32(mmRLC_MEM_SLP_CNTL);
3688                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3689                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3690                         WREG32(mmRLC_MEM_SLP_CNTL, data);
3691                 }
3692
3693                 data = RREG32(mmCP_MEM_SLP_CNTL);
3694                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3695                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3696                         WREG32(mmCP_MEM_SLP_CNTL, data);
3697                 }
3698
3699                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3700                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3701                 if (orig != data)
3702                         WREG32(mmCGTS_SM_CTRL_REG, data);
3703
3704                 tmp = gfx_v7_0_halt_rlc(adev);
3705
3706                 mutex_lock(&adev->grbm_idx_mutex);
3707                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3708                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3709                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3710                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3711                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3712                 mutex_unlock(&adev->grbm_idx_mutex);
3713
3714                 gfx_v7_0_update_rlc(adev, tmp);
3715         }
3716 }
3717
3718 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3719                                bool enable)
3720 {
3721         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3722         /* order matters! */
3723         if (enable) {
3724                 gfx_v7_0_enable_mgcg(adev, true);
3725                 gfx_v7_0_enable_cgcg(adev, true);
3726         } else {
3727                 gfx_v7_0_enable_cgcg(adev, false);
3728                 gfx_v7_0_enable_mgcg(adev, false);
3729         }
3730         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3731 }
3732
3733 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3734                                                 bool enable)
3735 {
3736         u32 data, orig;
3737
3738         orig = data = RREG32(mmRLC_PG_CNTL);
3739         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3740                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3741         else
3742                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3743         if (orig != data)
3744                 WREG32(mmRLC_PG_CNTL, data);
3745 }
3746
3747 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3748                                                 bool enable)
3749 {
3750         u32 data, orig;
3751
3752         orig = data = RREG32(mmRLC_PG_CNTL);
3753         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3754                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3755         else
3756                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3757         if (orig != data)
3758                 WREG32(mmRLC_PG_CNTL, data);
3759 }
3760
3761 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3762 {
3763         u32 data, orig;
3764
3765         orig = data = RREG32(mmRLC_PG_CNTL);
3766         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3767                 data &= ~0x8000;
3768         else
3769                 data |= 0x8000;
3770         if (orig != data)
3771                 WREG32(mmRLC_PG_CNTL, data);
3772 }
3773
3774 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3775 {
3776         u32 data, orig;
3777
3778         orig = data = RREG32(mmRLC_PG_CNTL);
3779         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3780                 data &= ~0x2000;
3781         else
3782                 data |= 0x2000;
3783         if (orig != data)
3784                 WREG32(mmRLC_PG_CNTL, data);
3785 }
3786
3787 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3788 {
3789         const __le32 *fw_data;
3790         volatile u32 *dst_ptr;
3791         int me, i, max_me = 4;
3792         u32 bo_offset = 0;
3793         u32 table_offset, table_size;
3794
3795         if (adev->asic_type == CHIP_KAVERI)
3796                 max_me = 5;
3797
3798         if (adev->gfx.rlc.cp_table_ptr == NULL)
3799                 return;
3800
3801         /* write the cp table buffer */
3802         dst_ptr = adev->gfx.rlc.cp_table_ptr;
3803         for (me = 0; me < max_me; me++) {
3804                 if (me == 0) {
3805                         const struct gfx_firmware_header_v1_0 *hdr =
3806                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3807                         fw_data = (const __le32 *)
3808                                 (adev->gfx.ce_fw->data +
3809                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3810                         table_offset = le32_to_cpu(hdr->jt_offset);
3811                         table_size = le32_to_cpu(hdr->jt_size);
3812                 } else if (me == 1) {
3813                         const struct gfx_firmware_header_v1_0 *hdr =
3814                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3815                         fw_data = (const __le32 *)
3816                                 (adev->gfx.pfp_fw->data +
3817                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3818                         table_offset = le32_to_cpu(hdr->jt_offset);
3819                         table_size = le32_to_cpu(hdr->jt_size);
3820                 } else if (me == 2) {
3821                         const struct gfx_firmware_header_v1_0 *hdr =
3822                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3823                         fw_data = (const __le32 *)
3824                                 (adev->gfx.me_fw->data +
3825                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3826                         table_offset = le32_to_cpu(hdr->jt_offset);
3827                         table_size = le32_to_cpu(hdr->jt_size);
3828                 } else if (me == 3) {
3829                         const struct gfx_firmware_header_v1_0 *hdr =
3830                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3831                         fw_data = (const __le32 *)
3832                                 (adev->gfx.mec_fw->data +
3833                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3834                         table_offset = le32_to_cpu(hdr->jt_offset);
3835                         table_size = le32_to_cpu(hdr->jt_size);
3836                 } else {
3837                         const struct gfx_firmware_header_v1_0 *hdr =
3838                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3839                         fw_data = (const __le32 *)
3840                                 (adev->gfx.mec2_fw->data +
3841                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3842                         table_offset = le32_to_cpu(hdr->jt_offset);
3843                         table_size = le32_to_cpu(hdr->jt_size);
3844                 }
3845
3846                 for (i = 0; i < table_size; i ++) {
3847                         dst_ptr[bo_offset + i] =
3848                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3849                 }
3850
3851                 bo_offset += table_size;
3852         }
3853 }
3854
3855 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3856                                      bool enable)
3857 {
3858         u32 data, orig;
3859
3860         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3861                 orig = data = RREG32(mmRLC_PG_CNTL);
3862                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3863                 if (orig != data)
3864                         WREG32(mmRLC_PG_CNTL, data);
3865
3866                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3867                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3868                 if (orig != data)
3869                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3870         } else {
3871                 orig = data = RREG32(mmRLC_PG_CNTL);
3872                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3873                 if (orig != data)
3874                         WREG32(mmRLC_PG_CNTL, data);
3875
3876                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3877                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3878                 if (orig != data)
3879                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3880
3881                 data = RREG32(mmDB_RENDER_CONTROL);
3882         }
3883 }
3884
3885 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3886                                                  u32 bitmap)
3887 {
3888         u32 data;
3889
3890         if (!bitmap)
3891                 return;
3892
3893         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3894         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3895
3896         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3897 }
3898
3899 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3900 {
3901         u32 data, mask;
3902
3903         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3904         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3905
3906         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3907         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3908
3909         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3910
3911         return (~data) & mask;
3912 }
3913
3914 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3915 {
3916         u32 tmp;
3917
3918         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3919
3920         tmp = RREG32(mmRLC_MAX_PG_CU);
3921         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3922         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3923         WREG32(mmRLC_MAX_PG_CU, tmp);
3924 }
3925
3926 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3927                                             bool enable)
3928 {
3929         u32 data, orig;
3930
3931         orig = data = RREG32(mmRLC_PG_CNTL);
3932         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3933                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3934         else
3935                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3936         if (orig != data)
3937                 WREG32(mmRLC_PG_CNTL, data);
3938 }
3939
3940 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3941                                              bool enable)
3942 {
3943         u32 data, orig;
3944
3945         orig = data = RREG32(mmRLC_PG_CNTL);
3946         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3947                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3948         else
3949                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3950         if (orig != data)
3951                 WREG32(mmRLC_PG_CNTL, data);
3952 }
3953
3954 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3955 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
3956
3957 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3958 {
3959         u32 data, orig;
3960         u32 i;
3961
3962         if (adev->gfx.rlc.cs_data) {
3963                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3964                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3965                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3966                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3967         } else {
3968                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3969                 for (i = 0; i < 3; i++)
3970                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3971         }
3972         if (adev->gfx.rlc.reg_list) {
3973                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3974                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3975                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3976         }
3977
3978         orig = data = RREG32(mmRLC_PG_CNTL);
3979         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3980         if (orig != data)
3981                 WREG32(mmRLC_PG_CNTL, data);
3982
3983         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3984         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3985
3986         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3987         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3988         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3989         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3990
3991         data = 0x10101010;
3992         WREG32(mmRLC_PG_DELAY, data);
3993
3994         data = RREG32(mmRLC_PG_DELAY_2);
3995         data &= ~0xff;
3996         data |= 0x3;
3997         WREG32(mmRLC_PG_DELAY_2, data);
3998
3999         data = RREG32(mmRLC_AUTO_PG_CTRL);
4000         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4001         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4002         WREG32(mmRLC_AUTO_PG_CTRL, data);
4003
4004 }
4005
4006 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4007 {
4008         gfx_v7_0_enable_gfx_cgpg(adev, enable);
4009         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4010         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4011 }
4012
4013 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4014 {
4015         u32 count = 0;
4016         const struct cs_section_def *sect = NULL;
4017         const struct cs_extent_def *ext = NULL;
4018
4019         if (adev->gfx.rlc.cs_data == NULL)
4020                 return 0;
4021
4022         /* begin clear state */
4023         count += 2;
4024         /* context control state */
4025         count += 3;
4026
4027         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4028                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4029                         if (sect->id == SECT_CONTEXT)
4030                                 count += 2 + ext->reg_count;
4031                         else
4032                                 return 0;
4033                 }
4034         }
4035         /* pa_sc_raster_config/pa_sc_raster_config1 */
4036         count += 4;
4037         /* end clear state */
4038         count += 2;
4039         /* clear state */
4040         count += 2;
4041
4042         return count;
4043 }
4044
4045 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4046                                     volatile u32 *buffer)
4047 {
4048         u32 count = 0, i;
4049         const struct cs_section_def *sect = NULL;
4050         const struct cs_extent_def *ext = NULL;
4051
4052         if (adev->gfx.rlc.cs_data == NULL)
4053                 return;
4054         if (buffer == NULL)
4055                 return;
4056
4057         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4058         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4059
4060         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4061         buffer[count++] = cpu_to_le32(0x80000000);
4062         buffer[count++] = cpu_to_le32(0x80000000);
4063
4064         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4065                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4066                         if (sect->id == SECT_CONTEXT) {
4067                                 buffer[count++] =
4068                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4069                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4070                                 for (i = 0; i < ext->reg_count; i++)
4071                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4072                         } else {
4073                                 return;
4074                         }
4075                 }
4076         }
4077
4078         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4079         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4080         switch (adev->asic_type) {
4081         case CHIP_BONAIRE:
4082                 buffer[count++] = cpu_to_le32(0x16000012);
4083                 buffer[count++] = cpu_to_le32(0x00000000);
4084                 break;
4085         case CHIP_KAVERI:
4086                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4087                 buffer[count++] = cpu_to_le32(0x00000000);
4088                 break;
4089         case CHIP_KABINI:
4090         case CHIP_MULLINS:
4091                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4092                 buffer[count++] = cpu_to_le32(0x00000000);
4093                 break;
4094         case CHIP_HAWAII:
4095                 buffer[count++] = cpu_to_le32(0x3a00161a);
4096                 buffer[count++] = cpu_to_le32(0x0000002e);
4097                 break;
4098         default:
4099                 buffer[count++] = cpu_to_le32(0x00000000);
4100                 buffer[count++] = cpu_to_le32(0x00000000);
4101                 break;
4102         }
4103
4104         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4105         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4106
4107         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4108         buffer[count++] = cpu_to_le32(0);
4109 }
4110
4111 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4112 {
4113         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4114                               AMD_PG_SUPPORT_GFX_SMG |
4115                               AMD_PG_SUPPORT_GFX_DMG |
4116                               AMD_PG_SUPPORT_CP |
4117                               AMD_PG_SUPPORT_GDS |
4118                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4119                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4120                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4121                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4122                         gfx_v7_0_init_gfx_cgpg(adev);
4123                         gfx_v7_0_enable_cp_pg(adev, true);
4124                         gfx_v7_0_enable_gds_pg(adev, true);
4125                 }
4126                 gfx_v7_0_init_ao_cu_mask(adev);
4127                 gfx_v7_0_update_gfx_pg(adev, true);
4128         }
4129 }
4130
4131 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4132 {
4133         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4134                               AMD_PG_SUPPORT_GFX_SMG |
4135                               AMD_PG_SUPPORT_GFX_DMG |
4136                               AMD_PG_SUPPORT_CP |
4137                               AMD_PG_SUPPORT_GDS |
4138                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4139                 gfx_v7_0_update_gfx_pg(adev, false);
4140                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4141                         gfx_v7_0_enable_cp_pg(adev, false);
4142                         gfx_v7_0_enable_gds_pg(adev, false);
4143                 }
4144         }
4145 }
4146
4147 /**
4148  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4149  *
4150  * @adev: amdgpu_device pointer
4151  *
4152  * Fetches a GPU clock counter snapshot (SI).
4153  * Returns the 64 bit clock counter snapshot.
4154  */
4155 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4156 {
4157         uint64_t clock;
4158
4159         mutex_lock(&adev->gfx.gpu_clock_mutex);
4160         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4161         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4162                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4163         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4164         return clock;
4165 }
4166
4167 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4168                                           uint32_t vmid,
4169                                           uint32_t gds_base, uint32_t gds_size,
4170                                           uint32_t gws_base, uint32_t gws_size,
4171                                           uint32_t oa_base, uint32_t oa_size)
4172 {
4173         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4174         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4175
4176         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4177         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4178
4179         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4180         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4181
4182         /* GDS Base */
4183         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4184         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4185                                 WRITE_DATA_DST_SEL(0)));
4186         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4187         amdgpu_ring_write(ring, 0);
4188         amdgpu_ring_write(ring, gds_base);
4189
4190         /* GDS Size */
4191         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4192         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4193                                 WRITE_DATA_DST_SEL(0)));
4194         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4195         amdgpu_ring_write(ring, 0);
4196         amdgpu_ring_write(ring, gds_size);
4197
4198         /* GWS */
4199         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4200         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4201                                 WRITE_DATA_DST_SEL(0)));
4202         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4203         amdgpu_ring_write(ring, 0);
4204         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4205
4206         /* OA */
4207         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4208         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4209                                 WRITE_DATA_DST_SEL(0)));
4210         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4211         amdgpu_ring_write(ring, 0);
4212         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4213 }
4214
4215 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4216 {
4217         WREG32(mmSQ_IND_INDEX,
4218                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4219                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4220                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4221                 (SQ_IND_INDEX__FORCE_READ_MASK));
4222         return RREG32(mmSQ_IND_DATA);
4223 }
4224
4225 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4226                            uint32_t wave, uint32_t thread,
4227                            uint32_t regno, uint32_t num, uint32_t *out)
4228 {
4229         WREG32(mmSQ_IND_INDEX,
4230                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4231                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4232                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4233                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4234                 (SQ_IND_INDEX__FORCE_READ_MASK) |
4235                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4236         while (num--)
4237                 *(out++) = RREG32(mmSQ_IND_DATA);
4238 }
4239
4240 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4241 {
4242         /* type 0 wave data */
4243         dst[(*no_fields)++] = 0;
4244         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4245         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4246         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4247         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4248         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4249         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4250         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4251         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4252         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4253         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4254         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4255         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4256         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4257         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4258         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4259         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4260         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4261         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4262 }
4263
4264 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4265                                      uint32_t wave, uint32_t start,
4266                                      uint32_t size, uint32_t *dst)
4267 {
4268         wave_read_regs(
4269                 adev, simd, wave, 0,
4270                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4271 }
4272
4273 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4274         .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4275         .select_se_sh = &gfx_v7_0_select_se_sh,
4276         .read_wave_data = &gfx_v7_0_read_wave_data,
4277         .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4278 };
4279
4280 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4281         .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4282         .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4283 };
4284
4285 static int gfx_v7_0_early_init(void *handle)
4286 {
4287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4288
4289         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4290         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
4291         adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4292         adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4293         gfx_v7_0_set_ring_funcs(adev);
4294         gfx_v7_0_set_irq_funcs(adev);
4295         gfx_v7_0_set_gds_init(adev);
4296
4297         return 0;
4298 }
4299
4300 static int gfx_v7_0_late_init(void *handle)
4301 {
4302         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4303         int r;
4304
4305         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4306         if (r)
4307                 return r;
4308
4309         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4310         if (r)
4311                 return r;
4312
4313         return 0;
4314 }
4315
4316 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4317 {
4318         u32 gb_addr_config;
4319         u32 mc_shared_chmap, mc_arb_ramcfg;
4320         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4321         u32 tmp;
4322
4323         switch (adev->asic_type) {
4324         case CHIP_BONAIRE:
4325                 adev->gfx.config.max_shader_engines = 2;
4326                 adev->gfx.config.max_tile_pipes = 4;
4327                 adev->gfx.config.max_cu_per_sh = 7;
4328                 adev->gfx.config.max_sh_per_se = 1;
4329                 adev->gfx.config.max_backends_per_se = 2;
4330                 adev->gfx.config.max_texture_channel_caches = 4;
4331                 adev->gfx.config.max_gprs = 256;
4332                 adev->gfx.config.max_gs_threads = 32;
4333                 adev->gfx.config.max_hw_contexts = 8;
4334
4335                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4336                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4337                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4338                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4339                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4340                 break;
4341         case CHIP_HAWAII:
4342                 adev->gfx.config.max_shader_engines = 4;
4343                 adev->gfx.config.max_tile_pipes = 16;
4344                 adev->gfx.config.max_cu_per_sh = 11;
4345                 adev->gfx.config.max_sh_per_se = 1;
4346                 adev->gfx.config.max_backends_per_se = 4;
4347                 adev->gfx.config.max_texture_channel_caches = 16;
4348                 adev->gfx.config.max_gprs = 256;
4349                 adev->gfx.config.max_gs_threads = 32;
4350                 adev->gfx.config.max_hw_contexts = 8;
4351
4352                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4353                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4354                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4355                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4356                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4357                 break;
4358         case CHIP_KAVERI:
4359                 adev->gfx.config.max_shader_engines = 1;
4360                 adev->gfx.config.max_tile_pipes = 4;
4361                 adev->gfx.config.max_cu_per_sh = 8;
4362                 adev->gfx.config.max_backends_per_se = 2;
4363                 adev->gfx.config.max_sh_per_se = 1;
4364                 adev->gfx.config.max_texture_channel_caches = 4;
4365                 adev->gfx.config.max_gprs = 256;
4366                 adev->gfx.config.max_gs_threads = 16;
4367                 adev->gfx.config.max_hw_contexts = 8;
4368
4369                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4370                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4371                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4372                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4373                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4374                 break;
4375         case CHIP_KABINI:
4376         case CHIP_MULLINS:
4377         default:
4378                 adev->gfx.config.max_shader_engines = 1;
4379                 adev->gfx.config.max_tile_pipes = 2;
4380                 adev->gfx.config.max_cu_per_sh = 2;
4381                 adev->gfx.config.max_sh_per_se = 1;
4382                 adev->gfx.config.max_backends_per_se = 1;
4383                 adev->gfx.config.max_texture_channel_caches = 2;
4384                 adev->gfx.config.max_gprs = 256;
4385                 adev->gfx.config.max_gs_threads = 16;
4386                 adev->gfx.config.max_hw_contexts = 8;
4387
4388                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4389                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4390                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4391                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4392                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4393                 break;
4394         }
4395
4396         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4397         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4398         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4399
4400         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4401         adev->gfx.config.mem_max_burst_length_bytes = 256;
4402         if (adev->flags & AMD_IS_APU) {
4403                 /* Get memory bank mapping mode. */
4404                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4405                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4406                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4407
4408                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4409                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4410                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4411
4412                 /* Validate settings in case only one DIMM installed. */
4413                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4414                         dimm00_addr_map = 0;
4415                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4416                         dimm01_addr_map = 0;
4417                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4418                         dimm10_addr_map = 0;
4419                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4420                         dimm11_addr_map = 0;
4421
4422                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4423                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4424                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4425                         adev->gfx.config.mem_row_size_in_kb = 2;
4426                 else
4427                         adev->gfx.config.mem_row_size_in_kb = 1;
4428         } else {
4429                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4430                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4431                 if (adev->gfx.config.mem_row_size_in_kb > 4)
4432                         adev->gfx.config.mem_row_size_in_kb = 4;
4433         }
4434         /* XXX use MC settings? */
4435         adev->gfx.config.shader_engine_tile_size = 32;
4436         adev->gfx.config.num_gpus = 1;
4437         adev->gfx.config.multi_gpu_tile_size = 64;
4438
4439         /* fix up row size */
4440         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4441         switch (adev->gfx.config.mem_row_size_in_kb) {
4442         case 1:
4443         default:
4444                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4445                 break;
4446         case 2:
4447                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4448                 break;
4449         case 4:
4450                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4451                 break;
4452         }
4453         adev->gfx.config.gb_addr_config = gb_addr_config;
4454 }
4455
4456 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4457                                         int mec, int pipe, int queue)
4458 {
4459         int r;
4460         unsigned irq_type;
4461         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4462
4463         /* mec0 is me1 */
4464         ring->me = mec + 1;
4465         ring->pipe = pipe;
4466         ring->queue = queue;
4467
4468         ring->ring_obj = NULL;
4469         ring->use_doorbell = true;
4470         ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
4471         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4472
4473         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4474                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4475                 + ring->pipe;
4476
4477         /* type-2 packets are deprecated on MEC, use type-3 instead */
4478         r = amdgpu_ring_init(adev, ring, 1024,
4479                         &adev->gfx.eop_irq, irq_type);
4480         if (r)
4481                 return r;
4482
4483
4484         return 0;
4485 }
4486
4487 static int gfx_v7_0_sw_init(void *handle)
4488 {
4489         struct amdgpu_ring *ring;
4490         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4491         int i, j, k, r, ring_id;
4492
4493         switch (adev->asic_type) {
4494         case CHIP_KAVERI:
4495                 adev->gfx.mec.num_mec = 2;
4496                 break;
4497         case CHIP_BONAIRE:
4498         case CHIP_HAWAII:
4499         case CHIP_KABINI:
4500         case CHIP_MULLINS:
4501         default:
4502                 adev->gfx.mec.num_mec = 1;
4503                 break;
4504         }
4505         adev->gfx.mec.num_pipe_per_mec = 4;
4506         adev->gfx.mec.num_queue_per_pipe = 8;
4507
4508         /* EOP Event */
4509         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4510         if (r)
4511                 return r;
4512
4513         /* Privileged reg */
4514         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
4515                               &adev->gfx.priv_reg_irq);
4516         if (r)
4517                 return r;
4518
4519         /* Privileged inst */
4520         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
4521                               &adev->gfx.priv_inst_irq);
4522         if (r)
4523                 return r;
4524
4525         gfx_v7_0_scratch_init(adev);
4526
4527         r = gfx_v7_0_init_microcode(adev);
4528         if (r) {
4529                 DRM_ERROR("Failed to load gfx firmware!\n");
4530                 return r;
4531         }
4532
4533         r = gfx_v7_0_rlc_init(adev);
4534         if (r) {
4535                 DRM_ERROR("Failed to init rlc BOs!\n");
4536                 return r;
4537         }
4538
4539         /* allocate mec buffers */
4540         r = gfx_v7_0_mec_init(adev);
4541         if (r) {
4542                 DRM_ERROR("Failed to init MEC BOs!\n");
4543                 return r;
4544         }
4545
4546         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4547                 ring = &adev->gfx.gfx_ring[i];
4548                 ring->ring_obj = NULL;
4549                 sprintf(ring->name, "gfx");
4550                 r = amdgpu_ring_init(adev, ring, 1024,
4551                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
4552                 if (r)
4553                         return r;
4554         }
4555
4556         /* set up the compute queues - allocate horizontally across pipes */
4557         ring_id = 0;
4558         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4559                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4560                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4561                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
4562                                         continue;
4563
4564                                 r = gfx_v7_0_compute_ring_init(adev,
4565                                                                 ring_id,
4566                                                                 i, k, j);
4567                                 if (r)
4568                                         return r;
4569
4570                                 ring_id++;
4571                         }
4572                 }
4573         }
4574
4575         /* reserve GDS, GWS and OA resource for gfx */
4576         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4577                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4578                                     &adev->gds.gds_gfx_bo, NULL, NULL);
4579         if (r)
4580                 return r;
4581
4582         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4583                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4584                                     &adev->gds.gws_gfx_bo, NULL, NULL);
4585         if (r)
4586                 return r;
4587
4588         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4589                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4590                                     &adev->gds.oa_gfx_bo, NULL, NULL);
4591         if (r)
4592                 return r;
4593
4594         adev->gfx.ce_ram_size = 0x8000;
4595
4596         gfx_v7_0_gpu_early_init(adev);
4597
4598         return r;
4599 }
4600
4601 static int gfx_v7_0_sw_fini(void *handle)
4602 {
4603         int i;
4604         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4605
4606         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4607         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4608         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4609
4610         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4611                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4612         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4613                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4614
4615         gfx_v7_0_cp_compute_fini(adev);
4616         gfx_v7_0_rlc_fini(adev);
4617         gfx_v7_0_mec_fini(adev);
4618         gfx_v7_0_free_microcode(adev);
4619
4620         return 0;
4621 }
4622
4623 static int gfx_v7_0_hw_init(void *handle)
4624 {
4625         int r;
4626         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4627
4628         gfx_v7_0_gpu_init(adev);
4629
4630         /* init rlc */
4631         r = gfx_v7_0_rlc_resume(adev);
4632         if (r)
4633                 return r;
4634
4635         r = gfx_v7_0_cp_resume(adev);
4636         if (r)
4637                 return r;
4638
4639         return r;
4640 }
4641
4642 static int gfx_v7_0_hw_fini(void *handle)
4643 {
4644         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4645
4646         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4647         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4648         gfx_v7_0_cp_enable(adev, false);
4649         gfx_v7_0_rlc_stop(adev);
4650         gfx_v7_0_fini_pg(adev);
4651
4652         return 0;
4653 }
4654
4655 static int gfx_v7_0_suspend(void *handle)
4656 {
4657         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4658
4659         return gfx_v7_0_hw_fini(adev);
4660 }
4661
4662 static int gfx_v7_0_resume(void *handle)
4663 {
4664         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4665
4666         return gfx_v7_0_hw_init(adev);
4667 }
4668
4669 static bool gfx_v7_0_is_idle(void *handle)
4670 {
4671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4672
4673         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4674                 return false;
4675         else
4676                 return true;
4677 }
4678
4679 static int gfx_v7_0_wait_for_idle(void *handle)
4680 {
4681         unsigned i;
4682         u32 tmp;
4683         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4684
4685         for (i = 0; i < adev->usec_timeout; i++) {
4686                 /* read MC_STATUS */
4687                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4688
4689                 if (!tmp)
4690                         return 0;
4691                 udelay(1);
4692         }
4693         return -ETIMEDOUT;
4694 }
4695
4696 static int gfx_v7_0_soft_reset(void *handle)
4697 {
4698         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4699         u32 tmp;
4700         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4701
4702         /* GRBM_STATUS */
4703         tmp = RREG32(mmGRBM_STATUS);
4704         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4705                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4706                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4707                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4708                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4709                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4710                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4711                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4712
4713         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4714                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4715                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4716         }
4717
4718         /* GRBM_STATUS2 */
4719         tmp = RREG32(mmGRBM_STATUS2);
4720         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4721                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4722
4723         /* SRBM_STATUS */
4724         tmp = RREG32(mmSRBM_STATUS);
4725         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4726                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4727
4728         if (grbm_soft_reset || srbm_soft_reset) {
4729                 /* disable CG/PG */
4730                 gfx_v7_0_fini_pg(adev);
4731                 gfx_v7_0_update_cg(adev, false);
4732
4733                 /* stop the rlc */
4734                 gfx_v7_0_rlc_stop(adev);
4735
4736                 /* Disable GFX parsing/prefetching */
4737                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4738
4739                 /* Disable MEC parsing/prefetching */
4740                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4741
4742                 if (grbm_soft_reset) {
4743                         tmp = RREG32(mmGRBM_SOFT_RESET);
4744                         tmp |= grbm_soft_reset;
4745                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4746                         WREG32(mmGRBM_SOFT_RESET, tmp);
4747                         tmp = RREG32(mmGRBM_SOFT_RESET);
4748
4749                         udelay(50);
4750
4751                         tmp &= ~grbm_soft_reset;
4752                         WREG32(mmGRBM_SOFT_RESET, tmp);
4753                         tmp = RREG32(mmGRBM_SOFT_RESET);
4754                 }
4755
4756                 if (srbm_soft_reset) {
4757                         tmp = RREG32(mmSRBM_SOFT_RESET);
4758                         tmp |= srbm_soft_reset;
4759                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4760                         WREG32(mmSRBM_SOFT_RESET, tmp);
4761                         tmp = RREG32(mmSRBM_SOFT_RESET);
4762
4763                         udelay(50);
4764
4765                         tmp &= ~srbm_soft_reset;
4766                         WREG32(mmSRBM_SOFT_RESET, tmp);
4767                         tmp = RREG32(mmSRBM_SOFT_RESET);
4768                 }
4769                 /* Wait a little for things to settle down */
4770                 udelay(50);
4771         }
4772         return 0;
4773 }
4774
4775 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4776                                                  enum amdgpu_interrupt_state state)
4777 {
4778         u32 cp_int_cntl;
4779
4780         switch (state) {
4781         case AMDGPU_IRQ_STATE_DISABLE:
4782                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4783                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4784                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4785                 break;
4786         case AMDGPU_IRQ_STATE_ENABLE:
4787                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4788                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4789                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4790                 break;
4791         default:
4792                 break;
4793         }
4794 }
4795
4796 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4797                                                      int me, int pipe,
4798                                                      enum amdgpu_interrupt_state state)
4799 {
4800         u32 mec_int_cntl, mec_int_cntl_reg;
4801
4802         /*
4803          * amdgpu controls only the first MEC. That's why this function only
4804          * handles the setting of interrupts for this specific MEC. All other
4805          * pipes' interrupts are set by amdkfd.
4806          */
4807
4808         if (me == 1) {
4809                 switch (pipe) {
4810                 case 0:
4811                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4812                         break;
4813                 case 1:
4814                         mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4815                         break;
4816                 case 2:
4817                         mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4818                         break;
4819                 case 3:
4820                         mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4821                         break;
4822                 default:
4823                         DRM_DEBUG("invalid pipe %d\n", pipe);
4824                         return;
4825                 }
4826         } else {
4827                 DRM_DEBUG("invalid me %d\n", me);
4828                 return;
4829         }
4830
4831         switch (state) {
4832         case AMDGPU_IRQ_STATE_DISABLE:
4833                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4834                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4835                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4836                 break;
4837         case AMDGPU_IRQ_STATE_ENABLE:
4838                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4839                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4840                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4841                 break;
4842         default:
4843                 break;
4844         }
4845 }
4846
4847 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4848                                              struct amdgpu_irq_src *src,
4849                                              unsigned type,
4850                                              enum amdgpu_interrupt_state state)
4851 {
4852         u32 cp_int_cntl;
4853
4854         switch (state) {
4855         case AMDGPU_IRQ_STATE_DISABLE:
4856                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4857                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4858                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4859                 break;
4860         case AMDGPU_IRQ_STATE_ENABLE:
4861                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4862                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4863                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4864                 break;
4865         default:
4866                 break;
4867         }
4868
4869         return 0;
4870 }
4871
4872 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4873                                               struct amdgpu_irq_src *src,
4874                                               unsigned type,
4875                                               enum amdgpu_interrupt_state state)
4876 {
4877         u32 cp_int_cntl;
4878
4879         switch (state) {
4880         case AMDGPU_IRQ_STATE_DISABLE:
4881                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4882                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4883                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4884                 break;
4885         case AMDGPU_IRQ_STATE_ENABLE:
4886                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4887                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4888                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4889                 break;
4890         default:
4891                 break;
4892         }
4893
4894         return 0;
4895 }
4896
4897 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4898                                             struct amdgpu_irq_src *src,
4899                                             unsigned type,
4900                                             enum amdgpu_interrupt_state state)
4901 {
4902         switch (type) {
4903         case AMDGPU_CP_IRQ_GFX_EOP:
4904                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4905                 break;
4906         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4907                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4908                 break;
4909         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4910                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4911                 break;
4912         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4913                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4914                 break;
4915         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4916                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4917                 break;
4918         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4919                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4920                 break;
4921         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4922                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4923                 break;
4924         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4925                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4926                 break;
4927         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4928                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4929                 break;
4930         default:
4931                 break;
4932         }
4933         return 0;
4934 }
4935
4936 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4937                             struct amdgpu_irq_src *source,
4938                             struct amdgpu_iv_entry *entry)
4939 {
4940         u8 me_id, pipe_id;
4941         struct amdgpu_ring *ring;
4942         int i;
4943
4944         DRM_DEBUG("IH: CP EOP\n");
4945         me_id = (entry->ring_id & 0x0c) >> 2;
4946         pipe_id = (entry->ring_id & 0x03) >> 0;
4947         switch (me_id) {
4948         case 0:
4949                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4950                 break;
4951         case 1:
4952         case 2:
4953                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4954                         ring = &adev->gfx.compute_ring[i];
4955                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
4956                                 amdgpu_fence_process(ring);
4957                 }
4958                 break;
4959         }
4960         return 0;
4961 }
4962
4963 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4964                                  struct amdgpu_irq_src *source,
4965                                  struct amdgpu_iv_entry *entry)
4966 {
4967         DRM_ERROR("Illegal register access in command stream\n");
4968         schedule_work(&adev->reset_work);
4969         return 0;
4970 }
4971
4972 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4973                                   struct amdgpu_irq_src *source,
4974                                   struct amdgpu_iv_entry *entry)
4975 {
4976         DRM_ERROR("Illegal instruction in command stream\n");
4977         // XXX soft reset the gfx block only
4978         schedule_work(&adev->reset_work);
4979         return 0;
4980 }
4981
4982 static int gfx_v7_0_set_clockgating_state(void *handle,
4983                                           enum amd_clockgating_state state)
4984 {
4985         bool gate = false;
4986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4987
4988         if (state == AMD_CG_STATE_GATE)
4989                 gate = true;
4990
4991         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4992         /* order matters! */
4993         if (gate) {
4994                 gfx_v7_0_enable_mgcg(adev, true);
4995                 gfx_v7_0_enable_cgcg(adev, true);
4996         } else {
4997                 gfx_v7_0_enable_cgcg(adev, false);
4998                 gfx_v7_0_enable_mgcg(adev, false);
4999         }
5000         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5001
5002         return 0;
5003 }
5004
5005 static int gfx_v7_0_set_powergating_state(void *handle,
5006                                           enum amd_powergating_state state)
5007 {
5008         bool gate = false;
5009         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5010
5011         if (state == AMD_PG_STATE_GATE)
5012                 gate = true;
5013
5014         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5015                               AMD_PG_SUPPORT_GFX_SMG |
5016                               AMD_PG_SUPPORT_GFX_DMG |
5017                               AMD_PG_SUPPORT_CP |
5018                               AMD_PG_SUPPORT_GDS |
5019                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
5020                 gfx_v7_0_update_gfx_pg(adev, gate);
5021                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5022                         gfx_v7_0_enable_cp_pg(adev, gate);
5023                         gfx_v7_0_enable_gds_pg(adev, gate);
5024                 }
5025         }
5026
5027         return 0;
5028 }
5029
5030 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5031         .name = "gfx_v7_0",
5032         .early_init = gfx_v7_0_early_init,
5033         .late_init = gfx_v7_0_late_init,
5034         .sw_init = gfx_v7_0_sw_init,
5035         .sw_fini = gfx_v7_0_sw_fini,
5036         .hw_init = gfx_v7_0_hw_init,
5037         .hw_fini = gfx_v7_0_hw_fini,
5038         .suspend = gfx_v7_0_suspend,
5039         .resume = gfx_v7_0_resume,
5040         .is_idle = gfx_v7_0_is_idle,
5041         .wait_for_idle = gfx_v7_0_wait_for_idle,
5042         .soft_reset = gfx_v7_0_soft_reset,
5043         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5044         .set_powergating_state = gfx_v7_0_set_powergating_state,
5045 };
5046
5047 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5048         .type = AMDGPU_RING_TYPE_GFX,
5049         .align_mask = 0xff,
5050         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5051         .support_64bit_ptrs = false,
5052         .get_rptr = gfx_v7_0_ring_get_rptr,
5053         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5054         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5055         .emit_frame_size =
5056                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5057                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5058                 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5059                 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5060                 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5061                 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5062                 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5063         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5064         .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5065         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5066         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5067         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5068         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5069         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5070         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5071         .test_ring = gfx_v7_0_ring_test_ring,
5072         .test_ib = gfx_v7_0_ring_test_ib,
5073         .insert_nop = amdgpu_ring_insert_nop,
5074         .pad_ib = amdgpu_ring_generic_pad_ib,
5075         .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5076 };
5077
5078 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5079         .type = AMDGPU_RING_TYPE_COMPUTE,
5080         .align_mask = 0xff,
5081         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5082         .support_64bit_ptrs = false,
5083         .get_rptr = gfx_v7_0_ring_get_rptr,
5084         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5085         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5086         .emit_frame_size =
5087                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5088                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5089                 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5090                 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5091                 17 + /* gfx_v7_0_ring_emit_vm_flush */
5092                 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5093         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5094         .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5095         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5096         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5097         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5098         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5099         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5100         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5101         .test_ring = gfx_v7_0_ring_test_ring,
5102         .test_ib = gfx_v7_0_ring_test_ib,
5103         .insert_nop = amdgpu_ring_insert_nop,
5104         .pad_ib = amdgpu_ring_generic_pad_ib,
5105 };
5106
5107 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5108 {
5109         int i;
5110
5111         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5112                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5113         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5114                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5115 }
5116
5117 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5118         .set = gfx_v7_0_set_eop_interrupt_state,
5119         .process = gfx_v7_0_eop_irq,
5120 };
5121
5122 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5123         .set = gfx_v7_0_set_priv_reg_fault_state,
5124         .process = gfx_v7_0_priv_reg_irq,
5125 };
5126
5127 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5128         .set = gfx_v7_0_set_priv_inst_fault_state,
5129         .process = gfx_v7_0_priv_inst_irq,
5130 };
5131
5132 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5133 {
5134         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5135         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5136
5137         adev->gfx.priv_reg_irq.num_types = 1;
5138         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5139
5140         adev->gfx.priv_inst_irq.num_types = 1;
5141         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5142 }
5143
5144 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5145 {
5146         /* init asci gds info */
5147         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5148         adev->gds.gws.total_size = 64;
5149         adev->gds.oa.total_size = 16;
5150
5151         if (adev->gds.mem.total_size == 64 * 1024) {
5152                 adev->gds.mem.gfx_partition_size = 4096;
5153                 adev->gds.mem.cs_partition_size = 4096;
5154
5155                 adev->gds.gws.gfx_partition_size = 4;
5156                 adev->gds.gws.cs_partition_size = 4;
5157
5158                 adev->gds.oa.gfx_partition_size = 4;
5159                 adev->gds.oa.cs_partition_size = 1;
5160         } else {
5161                 adev->gds.mem.gfx_partition_size = 1024;
5162                 adev->gds.mem.cs_partition_size = 1024;
5163
5164                 adev->gds.gws.gfx_partition_size = 16;
5165                 adev->gds.gws.cs_partition_size = 16;
5166
5167                 adev->gds.oa.gfx_partition_size = 4;
5168                 adev->gds.oa.cs_partition_size = 4;
5169         }
5170 }
5171
5172
5173 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5174 {
5175         int i, j, k, counter, active_cu_number = 0;
5176         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5177         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5178         unsigned disable_masks[4 * 2];
5179         u32 ao_cu_num;
5180
5181         if (adev->flags & AMD_IS_APU)
5182                 ao_cu_num = 2;
5183         else
5184                 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5185
5186         memset(cu_info, 0, sizeof(*cu_info));
5187
5188         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5189
5190         mutex_lock(&adev->grbm_idx_mutex);
5191         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5192                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5193                         mask = 1;
5194                         ao_bitmap = 0;
5195                         counter = 0;
5196                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5197                         if (i < 4 && j < 2)
5198                                 gfx_v7_0_set_user_cu_inactive_bitmap(
5199                                         adev, disable_masks[i * 2 + j]);
5200                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5201                         cu_info->bitmap[i][j] = bitmap;
5202
5203                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5204                                 if (bitmap & mask) {
5205                                         if (counter < ao_cu_num)
5206                                                 ao_bitmap |= mask;
5207                                         counter ++;
5208                                 }
5209                                 mask <<= 1;
5210                         }
5211                         active_cu_number += counter;
5212                         if (i < 2 && j < 2)
5213                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5214                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5215                 }
5216         }
5217         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5218         mutex_unlock(&adev->grbm_idx_mutex);
5219
5220         cu_info->number = active_cu_number;
5221         cu_info->ao_cu_mask = ao_cu_mask;
5222 }
5223
5224 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5225 {
5226         .type = AMD_IP_BLOCK_TYPE_GFX,
5227         .major = 7,
5228         .minor = 0,
5229         .rev = 0,
5230         .funcs = &gfx_v7_0_ip_funcs,
5231 };
5232
5233 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5234 {
5235         .type = AMD_IP_BLOCK_TYPE_GFX,
5236         .major = 7,
5237         .minor = 1,
5238         .rev = 0,
5239         .funcs = &gfx_v7_0_ip_funcs,
5240 };
5241
5242 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5243 {
5244         .type = AMD_IP_BLOCK_TYPE_GFX,
5245         .major = 7,
5246         .minor = 2,
5247         .rev = 0,
5248         .funcs = &gfx_v7_0_ip_funcs,
5249 };
5250
5251 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5252 {
5253         .type = AMD_IP_BLOCK_TYPE_GFX,
5254         .major = 7,
5255         .minor = 3,
5256         .rev = 0,
5257         .funcs = &gfx_v7_0_ip_funcs,
5258 };