drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 /*(DEBLOBBED)*/
  70
  71 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  72 {
  73         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  74         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  75         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  76         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  77         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  78         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  79         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  80         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
  81         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
  82         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
  83         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
  84         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
  85         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
  86         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
  87         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
  88         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
  89 };
  90
  91 static const u32 golden_settings_tonga_a11[] =
  92 {
  93         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
  94         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
  95         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  96         mmGB_GPU_ID, 0x0000000f, 0x00000000,
  97         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
  98         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
  99         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 100         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 101         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 102         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 103         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 104         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 105         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 106         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 107         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 108 };
 109
 110 static const u32 tonga_golden_common_all[] =
 111 {
 112         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 113         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 114         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 115         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 116         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 117         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 118         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 119         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 120 };
 121
 122 static const u32 tonga_mgcg_cgcg_init[] =
 123 {
 124         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 125         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 126         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 127         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 128         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 129         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 130         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 131         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 132         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 133         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 134         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 135         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 136         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 137         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 138         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 139         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 140         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 141         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 142         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 143         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 144         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 145         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 146         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 147         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 148         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 149         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 150         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 151         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 152         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 153         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 154         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 155         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 156         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 157         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 158         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 159         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 160         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 161         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 162         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 163         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 164         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 165         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 166         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 167         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 168         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 169         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 170         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 171         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 172         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 173         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 174         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 175         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 176         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 177         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 178         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 179         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 180         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 181         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 182         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 183         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 184         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 185         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 186         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 187         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 188         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 189         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 190         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 191         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 192         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 193         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 194         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 195         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 196         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 197         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 198         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 199 };
 200
 201 static const u32 fiji_golden_common_all[] =
 202 {
 203         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 204         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 205         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 206         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 207         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 208         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 209         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 210         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
 211         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 212         mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
 213 };
 214
 215 static const u32 golden_settings_fiji_a10[] =
 216 {
 217         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 218         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 219         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 220         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 221         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 222         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 223         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 224         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 225         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 226         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 227         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 228 };
 229
 230 static const u32 fiji_mgcg_cgcg_init[] =
 231 {
 232         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 233         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 234         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 235         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 236         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 237         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 238         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 239         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 240         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 241         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 242         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 243         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 244         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 245         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 246         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 247         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 248         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 249         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 250         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 251         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 252         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 253         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 254         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 255         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 256         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 257         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 258         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 259         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 260         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 261         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 262         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 263         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 264         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 265         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 266         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 267 };
 268
 269 static const u32 golden_settings_iceland_a11[] =
 270 {
 271         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 272         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 273         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 274         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 275         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 276         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 277         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 278         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 279         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 280         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 281         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 282         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 283         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 284         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 285         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 286 };
 287
 288 static const u32 iceland_golden_common_all[] =
 289 {
 290         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 291         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 292         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 293         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 294         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 295         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 296         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 297         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 298 };
 299
 300 static const u32 iceland_mgcg_cgcg_init[] =
 301 {
 302         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 303         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 304         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 305         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 306         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 307         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 308         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 309         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 310         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 311         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 312         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 313         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 314         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 315         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 316         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 317         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 318         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 319         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 320         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 321         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 322         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 323         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 324         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 325         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 326         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 327         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 328         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 329         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 330         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 331         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 332         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 333         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 334         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 335         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 336         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 337         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 338         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 339         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 340         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 341         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 342         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 343         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 344         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 345         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 346         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 347         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 348         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 349         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 350         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 351         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 352         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 353         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 354         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 355         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 356         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 357         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 358         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 359         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 360         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 361         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 362         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 363         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 364         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 365         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 366 };
 367
 368 static const u32 cz_golden_settings_a11[] =
 369 {
 370         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 371         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 372         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 373         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 374         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 375         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 376         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 377         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 378         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 379         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 380 };
 381
 382 static const u32 cz_golden_common_all[] =
 383 {
 384         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 385         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 386         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 387         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 388         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 389         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 390         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 391         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 392 };
 393
 394 static const u32 cz_mgcg_cgcg_init[] =
 395 {
 396         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 397         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 398         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 399         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 400         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 401         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 402         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 403         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 404         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 405         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 406         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 407         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 408         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 409         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 410         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 411         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 412         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 413         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 414         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 415         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 416         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 417         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 418         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 419         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 420         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 421         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 422         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 423         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 424         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 425         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 426         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 427         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 428         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 429         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 430         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 431         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 432         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 433         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 434         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 435         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 436         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 437         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 438         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 439         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 440         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 441         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 442         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 443         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 444         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 445         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 446         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 447         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 448         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 449         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 450         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 451         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 452         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 453         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 454         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 455         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 456         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 457         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 458         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 459         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 460         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 461         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 462         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 463         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 464         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 465         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 466         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 467         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 468         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 469         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 470         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 471 };
 472
 473 static const u32 stoney_golden_settings_a11[] =
 474 {
 475         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 476         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 477         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 478         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 479         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 480         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 481         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 482         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 483         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
 484         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
 485 };
 486
 487 static const u32 stoney_golden_common_all[] =
 488 {
 489         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 490         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
 491         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 492         mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
 493         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 494         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 495         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 496         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
 497 };
 498
 499 static const u32 stoney_mgcg_cgcg_init[] =
 500 {
 501         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 502         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 503         mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 504         mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 505         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 506         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 507 };
 508
 509 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 510 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 511 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 512
 513 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 514 {
 515         switch (adev->asic_type) {
 516         case CHIP_TOPAZ:
 517                 amdgpu_program_register_sequence(adev,
 518                                                  iceland_mgcg_cgcg_init,
 519                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 520                 amdgpu_program_register_sequence(adev,
 521                                                  golden_settings_iceland_a11,
 522                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 523                 amdgpu_program_register_sequence(adev,
 524                                                  iceland_golden_common_all,
 525                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 526                 break;
 527         case CHIP_FIJI:
 528                 amdgpu_program_register_sequence(adev,
 529                                                  fiji_mgcg_cgcg_init,
 530                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 531                 amdgpu_program_register_sequence(adev,
 532                                                  golden_settings_fiji_a10,
 533                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 534                 amdgpu_program_register_sequence(adev,
 535                                                  fiji_golden_common_all,
 536                                                  (const u32)ARRAY_SIZE(fiji_golden_common_all));
 537                 break;
 538
 539         case CHIP_TONGA:
 540                 amdgpu_program_register_sequence(adev,
 541                                                  tonga_mgcg_cgcg_init,
 542                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 543                 amdgpu_program_register_sequence(adev,
 544                                                  golden_settings_tonga_a11,
 545                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 546                 amdgpu_program_register_sequence(adev,
 547                                                  tonga_golden_common_all,
 548                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 549                 break;
 550         case CHIP_CARRIZO:
 551                 amdgpu_program_register_sequence(adev,
 552                                                  cz_mgcg_cgcg_init,
 553                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 554                 amdgpu_program_register_sequence(adev,
 555                                                  cz_golden_settings_a11,
 556                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 557                 amdgpu_program_register_sequence(adev,
 558                                                  cz_golden_common_all,
 559                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 560                 break;
 561         case CHIP_STONEY:
 562                 amdgpu_program_register_sequence(adev,
 563                                                  stoney_mgcg_cgcg_init,
 564                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 565                 amdgpu_program_register_sequence(adev,
 566                                                  stoney_golden_settings_a11,
 567                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 568                 amdgpu_program_register_sequence(adev,
 569                                                  stoney_golden_common_all,
 570                                                  (const u32)ARRAY_SIZE(stoney_golden_common_all));
 571                 break;
 572         default:
 573                 break;
 574         }
 575 }
 576
 577 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 578 {
 579         int i;
 580
 581         adev->gfx.scratch.num_reg = 7;
 582         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 583         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 584                 adev->gfx.scratch.free[i] = true;
 585                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 586         }
 587 }
 588
 589 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 590 {
 591         struct amdgpu_device *adev = ring->adev;
 592         uint32_t scratch;
 593         uint32_t tmp = 0;
 594         unsigned i;
 595         int r;
 596
 597         r = amdgpu_gfx_scratch_get(adev, &scratch);
 598         if (r) {
 599                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 600                 return r;
 601         }
 602         WREG32(scratch, 0xCAFEDEAD);
 603         r = amdgpu_ring_lock(ring, 3);
 604         if (r) {
 605                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 606                           ring->idx, r);
 607                 amdgpu_gfx_scratch_free(adev, scratch);
 608                 return r;
 609         }
 610         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 611         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 612         amdgpu_ring_write(ring, 0xDEADBEEF);
 613         amdgpu_ring_unlock_commit(ring);
 614
 615         for (i = 0; i < adev->usec_timeout; i++) {
 616                 tmp = RREG32(scratch);
 617                 if (tmp == 0xDEADBEEF)
 618                         break;
 619                 DRM_UDELAY(1);
 620         }
 621         if (i < adev->usec_timeout) {
 622                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 623                          ring->idx, i);
 624         } else {
 625                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 626                           ring->idx, scratch, tmp);
 627                 r = -EINVAL;
 628         }
 629         amdgpu_gfx_scratch_free(adev, scratch);
 630         return r;
 631 }
 632
 633 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 634 {
 635         struct amdgpu_device *adev = ring->adev;
 636         struct amdgpu_ib ib;
 637         struct fence *f = NULL;
 638         uint32_t scratch;
 639         uint32_t tmp = 0;
 640         unsigned i;
 641         int r;
 642
 643         r = amdgpu_gfx_scratch_get(adev, &scratch);
 644         if (r) {
 645                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 646                 return r;
 647         }
 648         WREG32(scratch, 0xCAFEDEAD);
 649         memset(&ib, 0, sizeof(ib));
 650         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 651         if (r) {
 652                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 653                 goto err1;
 654         }
 655         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 656         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 657         ib.ptr[2] = 0xDEADBEEF;
 658         ib.length_dw = 3;
 659
 660         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 661                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 662                                                  &f);
 663         if (r)
 664                 goto err2;
 665
 666         r = fence_wait(f, false);
 667         if (r) {
 668                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 669                 goto err2;
 670         }
 671         for (i = 0; i < adev->usec_timeout; i++) {
 672                 tmp = RREG32(scratch);
 673                 if (tmp == 0xDEADBEEF)
 674                         break;
 675                 DRM_UDELAY(1);
 676         }
 677         if (i < adev->usec_timeout) {
 678                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 679                          ring->idx, i);
 680                 goto err2;
 681         } else {
 682                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 683                           scratch, tmp);
 684                 r = -EINVAL;
 685         }
 686 err2:
 687         fence_put(f);
 688         amdgpu_ib_free(adev, &ib);
 689 err1:
 690         amdgpu_gfx_scratch_free(adev, scratch);
 691         return r;
 692 }
 693
 694 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 695 {
 696         const char *chip_name;
 697         char fw_name[30];
 698         int err;
 699         struct amdgpu_firmware_info *info = NULL;
 700         const struct common_firmware_header *header = NULL;
 701         const struct gfx_firmware_header_v1_0 *cp_hdr;
 702
 703         DRM_DEBUG("\n");
 704
 705         switch (adev->asic_type) {
 706         case CHIP_TOPAZ:
 707                 chip_name = "topaz";
 708                 break;
 709         case CHIP_TONGA:
 710                 chip_name = "tonga";
 711                 break;
 712         case CHIP_CARRIZO:
 713                 chip_name = "carrizo";
 714                 break;
 715         case CHIP_FIJI:
 716                 chip_name = "fiji";
 717                 break;
 718         case CHIP_STONEY:
 719                 chip_name = "stoney";
 720                 break;
 721         default:
 722                 BUG();
 723         }
 724
 725         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 726         err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 727         if (err)
 728                 goto out;
 729         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 730         if (err)
 731                 goto out;
 732         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 733         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 734         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 735
 736         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 737         err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 738         if (err)
 739                 goto out;
 740         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 741         if (err)
 742                 goto out;
 743         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 744         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 745         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 746
 747         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 748         err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 749         if (err)
 750                 goto out;
 751         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 752         if (err)
 753                 goto out;
 754         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 755         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 756         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 757
 758         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 759         err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 760         if (err)
 761                 goto out;
 762         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 763         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 764         adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 765         adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 766
 767         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 768         err = reject_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 769         if (err)
 770                 goto out;
 771         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 772         if (err)
 773                 goto out;
 774         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 775         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 776         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 777
 778         if ((adev->asic_type != CHIP_STONEY) &&
 779             (adev->asic_type != CHIP_TOPAZ)) {
 780                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 781                 err = reject_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 782                 if (!err) {
 783                         err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 784                         if (err)
 785                                 goto out;
 786                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 787                                 adev->gfx.mec2_fw->data;
 788                         adev->gfx.mec2_fw_version =
 789                                 le32_to_cpu(cp_hdr->header.ucode_version);
 790                         adev->gfx.mec2_feature_version =
 791                                 le32_to_cpu(cp_hdr->ucode_feature_version);
 792                 } else {
 793                         err = 0;
 794                         adev->gfx.mec2_fw = NULL;
 795                 }
 796         }
 797
 798         if (adev->firmware.smu_load) {
 799                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 800                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 801                 info->fw = adev->gfx.pfp_fw;
 802                 header = (const struct common_firmware_header *)info->fw->data;
 803                 adev->firmware.fw_size +=
 804                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 805
 806                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 807                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 808                 info->fw = adev->gfx.me_fw;
 809                 header = (const struct common_firmware_header *)info->fw->data;
 810                 adev->firmware.fw_size +=
 811                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 812
 813                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 814                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 815                 info->fw = adev->gfx.ce_fw;
 816                 header = (const struct common_firmware_header *)info->fw->data;
 817                 adev->firmware.fw_size +=
 818                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 819
 820                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 821                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 822                 info->fw = adev->gfx.rlc_fw;
 823                 header = (const struct common_firmware_header *)info->fw->data;
 824                 adev->firmware.fw_size +=
 825                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 826
 827                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 828                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 829                 info->fw = adev->gfx.mec_fw;
 830                 header = (const struct common_firmware_header *)info->fw->data;
 831                 adev->firmware.fw_size +=
 832                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 833
 834                 if (adev->gfx.mec2_fw) {
 835                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 836                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 837                         info->fw = adev->gfx.mec2_fw;
 838                         header = (const struct common_firmware_header *)info->fw->data;
 839                         adev->firmware.fw_size +=
 840                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 841                 }
 842
 843         }
 844
 845 out:
 846         if (err) {
 847                 dev_err(adev->dev,
 848                         "gfx8: Failed to load firmware \"%s\"\n",
 849                         fw_name);
 850                 release_firmware(adev->gfx.pfp_fw);
 851                 adev->gfx.pfp_fw = NULL;
 852                 release_firmware(adev->gfx.me_fw);
 853                 adev->gfx.me_fw = NULL;
 854                 release_firmware(adev->gfx.ce_fw);
 855                 adev->gfx.ce_fw = NULL;
 856                 release_firmware(adev->gfx.rlc_fw);
 857                 adev->gfx.rlc_fw = NULL;
 858                 release_firmware(adev->gfx.mec_fw);
 859                 adev->gfx.mec_fw = NULL;
 860                 release_firmware(adev->gfx.mec2_fw);
 861                 adev->gfx.mec2_fw = NULL;
 862         }
 863         return err;
 864 }
 865
 866 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 867 {
 868         int r;
 869
 870         if (adev->gfx.mec.hpd_eop_obj) {
 871                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 872                 if (unlikely(r != 0))
 873                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 874                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 875                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 876
 877                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 878                 adev->gfx.mec.hpd_eop_obj = NULL;
 879         }
 880 }
 881
 882 #define MEC_HPD_SIZE 2048
 883
 884 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 885 {
 886         int r;
 887         u32 *hpd;
 888
 889         /*
 890          * we assign only 1 pipe because all other pipes will
 891          * be handled by KFD
 892          */
 893         adev->gfx.mec.num_mec = 1;
 894         adev->gfx.mec.num_pipe = 1;
 895         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 896
 897         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 898                 r = amdgpu_bo_create(adev,
 899                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 900                                      PAGE_SIZE, true,
 901                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 902                                      &adev->gfx.mec.hpd_eop_obj);
 903                 if (r) {
 904                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 905                         return r;
 906                 }
 907         }
 908
 909         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 910         if (unlikely(r != 0)) {
 911                 gfx_v8_0_mec_fini(adev);
 912                 return r;
 913         }
 914         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 915                           &adev->gfx.mec.hpd_eop_gpu_addr);
 916         if (r) {
 917                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 918                 gfx_v8_0_mec_fini(adev);
 919                 return r;
 920         }
 921         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 922         if (r) {
 923                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 924                 gfx_v8_0_mec_fini(adev);
 925                 return r;
 926         }
 927
 928         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 929
 930         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 931         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 932
 933         return 0;
 934 }
 935
 936 static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
 937 {
 938         u32 gb_addr_config;
 939         u32 mc_shared_chmap, mc_arb_ramcfg;
 940         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
 941         u32 tmp;
 942
 943         switch (adev->asic_type) {
 944         case CHIP_TOPAZ:
 945                 adev->gfx.config.max_shader_engines = 1;
 946                 adev->gfx.config.max_tile_pipes = 2;
 947                 adev->gfx.config.max_cu_per_sh = 6;
 948                 adev->gfx.config.max_sh_per_se = 1;
 949                 adev->gfx.config.max_backends_per_se = 2;
 950                 adev->gfx.config.max_texture_channel_caches = 2;
 951                 adev->gfx.config.max_gprs = 256;
 952                 adev->gfx.config.max_gs_threads = 32;
 953                 adev->gfx.config.max_hw_contexts = 8;
 954
 955                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 956                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 957                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 958                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 959                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
 960                 break;
 961         case CHIP_FIJI:
 962                 adev->gfx.config.max_shader_engines = 4;
 963                 adev->gfx.config.max_tile_pipes = 16;
 964                 adev->gfx.config.max_cu_per_sh = 16;
 965                 adev->gfx.config.max_sh_per_se = 1;
 966                 adev->gfx.config.max_backends_per_se = 4;
 967                 adev->gfx.config.max_texture_channel_caches = 16;
 968                 adev->gfx.config.max_gprs = 256;
 969                 adev->gfx.config.max_gs_threads = 32;
 970                 adev->gfx.config.max_hw_contexts = 8;
 971
 972                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 973                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 974                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 975                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 976                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
 977                 break;
 978         case CHIP_TONGA:
 979                 adev->gfx.config.max_shader_engines = 4;
 980                 adev->gfx.config.max_tile_pipes = 8;
 981                 adev->gfx.config.max_cu_per_sh = 8;
 982                 adev->gfx.config.max_sh_per_se = 1;
 983                 adev->gfx.config.max_backends_per_se = 2;
 984                 adev->gfx.config.max_texture_channel_caches = 8;
 985                 adev->gfx.config.max_gprs = 256;
 986                 adev->gfx.config.max_gs_threads = 32;
 987                 adev->gfx.config.max_hw_contexts = 8;
 988
 989                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 990                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 991                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 992                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 993                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
 994                 break;
 995         case CHIP_CARRIZO:
 996                 adev->gfx.config.max_shader_engines = 1;
 997                 adev->gfx.config.max_tile_pipes = 2;
 998                 adev->gfx.config.max_sh_per_se = 1;
 999                 adev->gfx.config.max_backends_per_se = 2;
1000
1001                 switch (adev->pdev->revision) {
1002                 case 0xc4:
1003                 case 0x84:
1004                 case 0xc8:
1005                 case 0xcc:
1006                 case 0xe1:
1007                 case 0xe3:
1008                         /* B10 */
1009                         adev->gfx.config.max_cu_per_sh = 8;
1010                         break;
1011                 case 0xc5:
1012                 case 0x81:
1013                 case 0x85:
1014                 case 0xc9:
1015                 case 0xcd:
1016                 case 0xe2:
1017                 case 0xe4:
1018                         /* B8 */
1019                         adev->gfx.config.max_cu_per_sh = 6;
1020                         break;
1021                 case 0xc6:
1022                 case 0xca:
1023                 case 0xce:
1024                 case 0x88:
1025                         /* B6 */
1026                         adev->gfx.config.max_cu_per_sh = 6;
1027                         break;
1028                 case 0xc7:
1029                 case 0x87:
1030                 case 0xcb:
1031                 case 0xe5:
1032                 case 0x89:
1033                 default:
1034                         /* B4 */
1035                         adev->gfx.config.max_cu_per_sh = 4;
1036                         break;
1037                 }
1038
1039                 adev->gfx.config.max_texture_channel_caches = 2;
1040                 adev->gfx.config.max_gprs = 256;
1041                 adev->gfx.config.max_gs_threads = 32;
1042                 adev->gfx.config.max_hw_contexts = 8;
1043
1044                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1045                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1046                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1047                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1048                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1049                 break;
1050         case CHIP_STONEY:
1051                 adev->gfx.config.max_shader_engines = 1;
1052                 adev->gfx.config.max_tile_pipes = 2;
1053                 adev->gfx.config.max_sh_per_se = 1;
1054                 adev->gfx.config.max_backends_per_se = 1;
1055
1056                 switch (adev->pdev->revision) {
1057                 case 0xc0:
1058                 case 0xc1:
1059                 case 0xc2:
1060                 case 0xc4:
1061                 case 0xc8:
1062                 case 0xc9:
1063                         adev->gfx.config.max_cu_per_sh = 3;
1064                         break;
1065                 case 0xd0:
1066                 case 0xd1:
1067                 case 0xd2:
1068                 default:
1069                         adev->gfx.config.max_cu_per_sh = 2;
1070                         break;
1071                 }
1072
1073                 adev->gfx.config.max_texture_channel_caches = 2;
1074                 adev->gfx.config.max_gprs = 256;
1075                 adev->gfx.config.max_gs_threads = 16;
1076                 adev->gfx.config.max_hw_contexts = 8;
1077
1078                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1079                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1080                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1081                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1082                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1083                 break;
1084         default:
1085                 adev->gfx.config.max_shader_engines = 2;
1086                 adev->gfx.config.max_tile_pipes = 4;
1087                 adev->gfx.config.max_cu_per_sh = 2;
1088                 adev->gfx.config.max_sh_per_se = 1;
1089                 adev->gfx.config.max_backends_per_se = 2;
1090                 adev->gfx.config.max_texture_channel_caches = 4;
1091                 adev->gfx.config.max_gprs = 256;
1092                 adev->gfx.config.max_gs_threads = 32;
1093                 adev->gfx.config.max_hw_contexts = 8;
1094
1095                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1096                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1097                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1098                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1099                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1100                 break;
1101         }
1102
1103         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1104         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1105         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1106
1107         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1108         adev->gfx.config.mem_max_burst_length_bytes = 256;
1109         if (adev->flags & AMD_IS_APU) {
1110                 /* Get memory bank mapping mode. */
1111                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1112                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1113                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1114
1115                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1116                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1117                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1118
1119                 /* Validate settings in case only one DIMM installed. */
1120                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1121                         dimm00_addr_map = 0;
1122                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1123                         dimm01_addr_map = 0;
1124                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1125                         dimm10_addr_map = 0;
1126                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1127                         dimm11_addr_map = 0;
1128
1129                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1130                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1131                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1132                         adev->gfx.config.mem_row_size_in_kb = 2;
1133                 else
1134                         adev->gfx.config.mem_row_size_in_kb = 1;
1135         } else {
1136                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1137                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1138                 if (adev->gfx.config.mem_row_size_in_kb > 4)
1139                         adev->gfx.config.mem_row_size_in_kb = 4;
1140         }
1141
1142         adev->gfx.config.shader_engine_tile_size = 32;
1143         adev->gfx.config.num_gpus = 1;
1144         adev->gfx.config.multi_gpu_tile_size = 64;
1145
1146         /* fix up row size */
1147         switch (adev->gfx.config.mem_row_size_in_kb) {
1148         case 1:
1149         default:
1150                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1151                 break;
1152         case 2:
1153                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1154                 break;
1155         case 4:
1156                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1157                 break;
1158         }
1159         adev->gfx.config.gb_addr_config = gb_addr_config;
1160 }
1161
1162 static int gfx_v8_0_sw_init(void *handle)
1163 {
1164         int i, r;
1165         struct amdgpu_ring *ring;
1166         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167
1168         /* EOP Event */
1169         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1170         if (r)
1171                 return r;
1172
1173         /* Privileged reg */
1174         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1175         if (r)
1176                 return r;
1177
1178         /* Privileged inst */
1179         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1180         if (r)
1181                 return r;
1182
1183         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1184
1185         gfx_v8_0_scratch_init(adev);
1186
1187         r = gfx_v8_0_init_microcode(adev);
1188         if (r) {
1189                 DRM_ERROR("Failed to load gfx firmware!\n");
1190                 return r;
1191         }
1192
1193         r = gfx_v8_0_mec_init(adev);
1194         if (r) {
1195                 DRM_ERROR("Failed to init MEC BOs!\n");
1196                 return r;
1197         }
1198
1199         /* set up the gfx ring */
1200         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1201                 ring = &adev->gfx.gfx_ring[i];
1202                 ring->ring_obj = NULL;
1203                 sprintf(ring->name, "gfx");
1204                 /* no gfx doorbells on iceland */
1205                 if (adev->asic_type != CHIP_TOPAZ) {
1206                         ring->use_doorbell = true;
1207                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1208                 }
1209
1210                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1211                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1212                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1213                                      AMDGPU_RING_TYPE_GFX);
1214                 if (r)
1215                         return r;
1216         }
1217
1218         /* set up the compute queues */
1219         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1220                 unsigned irq_type;
1221
1222                 /* max 32 queues per MEC */
1223                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1224                         DRM_ERROR("Too many (%d) compute rings!\n", i);
1225                         break;
1226                 }
1227                 ring = &adev->gfx.compute_ring[i];
1228                 ring->ring_obj = NULL;
1229                 ring->use_doorbell = true;
1230                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1231                 ring->me = 1; /* first MEC */
1232                 ring->pipe = i / 8;
1233                 ring->queue = i % 8;
1234                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1235                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1236                 /* type-2 packets are deprecated on MEC, use type-3 instead */
1237                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1238                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1239                                      &adev->gfx.eop_irq, irq_type,
1240                                      AMDGPU_RING_TYPE_COMPUTE);
1241                 if (r)
1242                         return r;
1243         }
1244
1245         /* reserve GDS, GWS and OA resource for gfx */
1246         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1247                         PAGE_SIZE, true,
1248                         AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
1249                         NULL, &adev->gds.gds_gfx_bo);
1250         if (r)
1251                 return r;
1252
1253         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1254                 PAGE_SIZE, true,
1255                 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
1256                 NULL, &adev->gds.gws_gfx_bo);
1257         if (r)
1258                 return r;
1259
1260         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1261                         PAGE_SIZE, true,
1262                         AMDGPU_GEM_DOMAIN_OA, 0, NULL,
1263                         NULL, &adev->gds.oa_gfx_bo);
1264         if (r)
1265                 return r;
1266
1267         adev->gfx.ce_ram_size = 0x8000;
1268
1269         gfx_v8_0_gpu_early_init(adev);
1270
1271         return 0;
1272 }
1273
1274 static int gfx_v8_0_sw_fini(void *handle)
1275 {
1276         int i;
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278
1279         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1280         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1281         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1282
1283         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1284                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1285         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1286                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1287
1288         gfx_v8_0_mec_fini(adev);
1289
1290         return 0;
1291 }
1292
1293 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1294 {
1295         const u32 num_tile_mode_states = 32;
1296         const u32 num_secondary_tile_mode_states = 16;
1297         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1298
1299         switch (adev->gfx.config.mem_row_size_in_kb) {
1300         case 1:
1301                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1302                 break;
1303         case 2:
1304         default:
1305                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1306                 break;
1307         case 4:
1308                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1309                 break;
1310         }
1311
1312         switch (adev->asic_type) {
1313         case CHIP_TOPAZ:
1314                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1315                         switch (reg_offset) {
1316                         case 0:
1317                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1318                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1319                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1320                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1321                                 break;
1322                         case 1:
1323                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1324                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1325                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1326                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1327                                 break;
1328                         case 2:
1329                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1330                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1331                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1332                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1333                                 break;
1334                         case 3:
1335                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1336                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1337                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1338                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1339                                 break;
1340                         case 4:
1341                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1342                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1343                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1344                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1345                                 break;
1346                         case 5:
1347                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1348                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1349                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1350                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1351                                 break;
1352                         case 6:
1353                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1354                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1355                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1356                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1357                                 break;
1358                         case 8:
1359                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1360                                                 PIPE_CONFIG(ADDR_SURF_P2));
1361                                 break;
1362                         case 9:
1363                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1364                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1365                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1366                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1367                                 break;
1368                         case 10:
1369                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1370                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1371                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1372                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1373                                 break;
1374                         case 11:
1375                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1376                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1377                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1378                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1379                                 break;
1380                         case 13:
1381                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1382                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1383                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1384                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1385                                 break;
1386                         case 14:
1387                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1388                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1389                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1390                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1391                                 break;
1392                         case 15:
1393                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1394                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1395                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1396                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1397                                 break;
1398                         case 16:
1399                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1400                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1401                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1402                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1403                                 break;
1404                         case 18:
1405                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1406                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1407                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1408                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1409                                 break;
1410                         case 19:
1411                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1412                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1413                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1414                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1415                                 break;
1416                         case 20:
1417                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1418                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1419                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1420                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1421                                 break;
1422                         case 21:
1423                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1424                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1425                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1426                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1427                                 break;
1428                         case 22:
1429                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1430                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1431                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1432                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1433                                 break;
1434                         case 24:
1435                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1436                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1437                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1439                                 break;
1440                         case 25:
1441                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1442                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1443                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1444                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1445                                 break;
1446                         case 26:
1447                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1448                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1449                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1450                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1451                                 break;
1452                         case 27:
1453                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1454                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1455                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1456                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1457                                 break;
1458                         case 28:
1459                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1460                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1461                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1462                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1463                                 break;
1464                         case 29:
1465                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1466                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1467                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1468                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1469                                 break;
1470                         case 7:
1471                         case 12:
1472                         case 17:
1473                         case 23:
1474                                 /* unused idx */
1475                                 continue;
1476                         default:
1477                                 gb_tile_moden = 0;
1478                                 break;
1479                         };
1480                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1481                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1482                 }
1483                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1484                         switch (reg_offset) {
1485                         case 0:
1486                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1487                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1488                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1489                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1490                                 break;
1491                         case 1:
1492                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1493                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1494                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1495                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1496                                 break;
1497                         case 2:
1498                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1499                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1500                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1501                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1502                                 break;
1503                         case 3:
1504                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1505                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1506                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1507                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1508                                 break;
1509                         case 4:
1510                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1511                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1512                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1513                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1514                                 break;
1515                         case 5:
1516                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1517                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1518                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1519                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1520                                 break;
1521                         case 6:
1522                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1523                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1524                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1525                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1526                                 break;
1527                         case 8:
1528                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1529                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1530                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1531                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1532                                 break;
1533                         case 9:
1534                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1535                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1536                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1537                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1538                                 break;
1539                         case 10:
1540                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1541                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1542                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1543                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1544                                 break;
1545                         case 11:
1546                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1547                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1548                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1549                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1550                                 break;
1551                         case 12:
1552                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1553                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1554                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1555                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1556                                 break;
1557                         case 13:
1558                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1559                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1560                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1561                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1562                                 break;
1563                         case 14:
1564                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1565                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1566                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1567                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1568                                 break;
1569                         case 7:
1570                                 /* unused idx */
1571                                 continue;
1572                         default:
1573                                 gb_tile_moden = 0;
1574                                 break;
1575                         };
1576                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1577                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1578                 }
1579         case CHIP_FIJI:
1580                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1581                         switch (reg_offset) {
1582                         case 0:
1583                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1584                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1585                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1586                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1587                                 break;
1588                         case 1:
1589                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1590                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1591                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1592                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1593                                 break;
1594                         case 2:
1595                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1596                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1597                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1598                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1599                                 break;
1600                         case 3:
1601                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1602                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1603                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1604                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1605                                 break;
1606                         case 4:
1607                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1608                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1609                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1610                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1611                                 break;
1612                         case 5:
1613                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1614                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1615                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1616                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1617                                 break;
1618                         case 6:
1619                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1620                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1621                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1622                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1623                                 break;
1624                         case 7:
1625                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1626                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1627                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1628                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1629                                 break;
1630                         case 8:
1631                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1632                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1633                                 break;
1634                         case 9:
1635                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1636                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1637                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1638                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1639                                 break;
1640                         case 10:
1641                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1642                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1643                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1644                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1645                                 break;
1646                         case 11:
1647                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1648                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1649                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1650                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1651                                 break;
1652                         case 12:
1653                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1654                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1655                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1656                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1657                                 break;
1658                         case 13:
1659                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1660                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1661                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1662                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1663                                 break;
1664                         case 14:
1665                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1666                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1667                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1668                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1669                                 break;
1670                         case 15:
1671                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1672                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1673                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1674                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1675                                 break;
1676                         case 16:
1677                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1678                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1679                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1680                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1681                                 break;
1682                         case 17:
1683                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1684                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1685                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1686                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1687                                 break;
1688                         case 18:
1689                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1690                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1691                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1692                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1693                                 break;
1694                         case 19:
1695                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1696                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1697                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1698                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1699                                 break;
1700                         case 20:
1701                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1702                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1703                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1704                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1705                                 break;
1706                         case 21:
1707                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1708                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1709                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1710                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1711                                 break;
1712                         case 22:
1713                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1714                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1715                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1716                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1717                                 break;
1718                         case 23:
1719                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1720                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1721                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1722                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1723                                 break;
1724                         case 24:
1725                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1726                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1727                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1728                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1729                                 break;
1730                         case 25:
1731                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1732                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1733                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1734                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1735                                 break;
1736                         case 26:
1737                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1738                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1739                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1740                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1741                                 break;
1742                         case 27:
1743                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1744                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1745                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1746                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1747                                 break;
1748                         case 28:
1749                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1750                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1751                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1752                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1753                                 break;
1754                         case 29:
1755                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1756                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1757                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1758                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1759                                 break;
1760                         case 30:
1761                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1762                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1763                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1764                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1765                                 break;
1766                         default:
1767                                 gb_tile_moden = 0;
1768                                 break;
1769                         }
1770                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1771                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1772                 }
1773                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1774                         switch (reg_offset) {
1775                         case 0:
1776                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1777                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1778                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1779                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1780                                 break;
1781                         case 1:
1782                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1783                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1784                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1785                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1786                                 break;
1787                         case 2:
1788                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1789                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1790                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1791                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1792                                 break;
1793                         case 3:
1794                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1795                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1796                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1797                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1798                                 break;
1799                         case 4:
1800                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1801                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1802                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1803                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1804                                 break;
1805                         case 5:
1806                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1807                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1808                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1809                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1810                                 break;
1811                         case 6:
1812                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1813                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1814                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1815                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1816                                 break;
1817                         case 8:
1818                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1819                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1820                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1821                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1822                                 break;
1823                         case 9:
1824                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1825                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1826                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1827                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1828                                 break;
1829                         case 10:
1830                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1831                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1832                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1833                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1834                                 break;
1835                         case 11:
1836                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1837                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1838                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1839                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1840                                 break;
1841                         case 12:
1842                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1843                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1844                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1845                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1846                                 break;
1847                         case 13:
1848                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1849                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1850                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1851                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1852                                 break;
1853                         case 14:
1854                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1855                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1856                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1857                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1858                                 break;
1859                         case 7:
1860                                 /* unused idx */
1861                                 continue;
1862                         default:
1863                                 gb_tile_moden = 0;
1864                                 break;
1865                         }
1866                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1867                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1868                 }
1869                 break;
1870         case CHIP_TONGA:
1871                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1872                         switch (reg_offset) {
1873                         case 0:
1874                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1875                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1876                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1877                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1878                                 break;
1879                         case 1:
1880                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1881                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1882                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1883                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1884                                 break;
1885                         case 2:
1886                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1887                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1888                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1889                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1890                                 break;
1891                         case 3:
1892                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1893                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1894                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1895                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1896                                 break;
1897                         case 4:
1898                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1899                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1900                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1901                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1902                                 break;
1903                         case 5:
1904                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1905                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1906                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1907                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1908                                 break;
1909                         case 6:
1910                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1911                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1912                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1913                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1914                                 break;
1915                         case 7:
1916                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1917                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1918                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1919                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1920                                 break;
1921                         case 8:
1922                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1923                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1924                                 break;
1925                         case 9:
1926                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1927                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1928                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1929                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1930                                 break;
1931                         case 10:
1932                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1933                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1934                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1935                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1936                                 break;
1937                         case 11:
1938                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1939                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1940                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1941                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1942                                 break;
1943                         case 12:
1944                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1945                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1946                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1947                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1948                                 break;
1949                         case 13:
1950                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1951                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1952                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1953                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1954                                 break;
1955                         case 14:
1956                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1957                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1958                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1959                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1960                                 break;
1961                         case 15:
1962                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1963                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1964                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1965                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1966                                 break;
1967                         case 16:
1968                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1969                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1970                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1971                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1972                                 break;
1973                         case 17:
1974                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1975                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1976                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1977                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1978                                 break;
1979                         case 18:
1980                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1981                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1982                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1983                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1984                                 break;
1985                         case 19:
1986                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1987                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1988                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1989                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1990                                 break;
1991                         case 20:
1992                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1993                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1994                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1995                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1996                                 break;
1997                         case 21:
1998                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1999                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2000                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2001                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2002                                 break;
2003                         case 22:
2004                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2005                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2006                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2007                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2008                                 break;
2009                         case 23:
2010                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2011                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2012                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2013                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2014                                 break;
2015                         case 24:
2016                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2017                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2018                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2019                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2020                                 break;
2021                         case 25:
2022                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2023                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2024                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2025                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2026                                 break;
2027                         case 26:
2028                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2029                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2030                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2031                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2032                                 break;
2033                         case 27:
2034                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2035                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2036                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2037                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2038                                 break;
2039                         case 28:
2040                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2041                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2042                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2043                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2044                                 break;
2045                         case 29:
2046                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2047                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2048                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2049                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2050                                 break;
2051                         case 30:
2052                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2053                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2054                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2055                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2056                                 break;
2057                         default:
2058                                 gb_tile_moden = 0;
2059                                 break;
2060                         };
2061                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2062                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2063                 }
2064                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2065                         switch (reg_offset) {
2066                         case 0:
2067                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2068                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2069                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2070                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2071                                 break;
2072                         case 1:
2073                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2074                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2075                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2076                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2077                                 break;
2078                         case 2:
2079                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2080                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2081                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2082                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2083                                 break;
2084                         case 3:
2085                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2086                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2087                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2088                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2089                                 break;
2090                         case 4:
2091                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2092                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2093                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2094                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2095                                 break;
2096                         case 5:
2097                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2098                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2099                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2100                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2101                                 break;
2102                         case 6:
2103                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2104                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2105                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2106                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2107                                 break;
2108                         case 8:
2109                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2110                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2111                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2112                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2113                                 break;
2114                         case 9:
2115                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2116                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2117                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2118                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2119                                 break;
2120                         case 10:
2121                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2122                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2123                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2124                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2125                                 break;
2126                         case 11:
2127                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2128                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2129                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2130                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2131                                 break;
2132                         case 12:
2133                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2134                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2135                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2136                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2137                                 break;
2138                         case 13:
2139                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2140                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2141                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2142                                                 NUM_BANKS(ADDR_SURF_4_BANK));
2143                                 break;
2144                         case 14:
2145                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2146                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2147                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2148                                                 NUM_BANKS(ADDR_SURF_4_BANK));
2149                                 break;
2150                         case 7:
2151                                 /* unused idx */
2152                                 continue;
2153                         default:
2154                                 gb_tile_moden = 0;
2155                                 break;
2156                         };
2157                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2158                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2159                 }
2160                 break;
2161         case CHIP_STONEY:
2162                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2163                         switch (reg_offset) {
2164                         case 0:
2165                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2166                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2167                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2168                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2169                                 break;
2170                         case 1:
2171                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2172                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2173                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2174                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2175                                 break;
2176                         case 2:
2177                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2178                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2179                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2180                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2181                                 break;
2182                         case 3:
2183                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2184                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2185                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2186                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2187                                 break;
2188                         case 4:
2189                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2190                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2191                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2192                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2193                                 break;
2194                         case 5:
2195                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2196                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2197                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2198                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2199                                 break;
2200                         case 6:
2201                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2202                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2203                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2204                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2205                                 break;
2206                         case 8:
2207                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2208                                                 PIPE_CONFIG(ADDR_SURF_P2));
2209                                 break;
2210                         case 9:
2211                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2212                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2213                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2214                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2215                                 break;
2216                         case 10:
2217                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2218                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2219                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2220                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2221                                 break;
2222                         case 11:
2223                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2224                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2225                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2226                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2227                                 break;
2228                         case 13:
2229                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2230                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2231                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2232                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2233                                 break;
2234                         case 14:
2235                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2236                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2237                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2238                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2239                                 break;
2240                         case 15:
2241                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2242                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2243                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2244                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2245                                 break;
2246                         case 16:
2247                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2248                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2249                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2250                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2251                                 break;
2252                         case 18:
2253                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2254                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2255                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2256                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2257                                 break;
2258                         case 19:
2259                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2260                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2261                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2262                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2263                                 break;
2264                         case 20:
2265                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2266                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2267                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2268                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2269                                 break;
2270                         case 21:
2271                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2272                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2273                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2274                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2275                                 break;
2276                         case 22:
2277                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2278                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2279                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2280                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2281                                 break;
2282                         case 24:
2283                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2284                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2285                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2286                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2287                                 break;
2288                         case 25:
2289                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2290                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2291                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2292                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2293                                 break;
2294                         case 26:
2295                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2296                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2297                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2298                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2299                                 break;
2300                         case 27:
2301                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2302                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2303                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2304                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2305                                 break;
2306                         case 28:
2307                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2308                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2309                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2310                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2311                                 break;
2312                         case 29:
2313                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2314                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2315                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2316                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2317                                 break;
2318                         case 7:
2319                         case 12:
2320                         case 17:
2321                         case 23:
2322                                 /* unused idx */
2323                                 continue;
2324                         default:
2325                                 gb_tile_moden = 0;
2326                                 break;
2327                         };
2328                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2329                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2330                 }
2331                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2332                         switch (reg_offset) {
2333                         case 0:
2334                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2335                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2336                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2337                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2338                                 break;
2339                         case 1:
2340                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2341                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2342                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2343                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2344                                 break;
2345                         case 2:
2346                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2347                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2348                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2349                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2350                                 break;
2351                         case 3:
2352                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2353                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2354                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2355                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2356                                 break;
2357                         case 4:
2358                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2359                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2360                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2361                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2362                                 break;
2363                         case 5:
2364                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2365                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2366                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2367                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2368                                 break;
2369                         case 6:
2370                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2371                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2372                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2373                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2374                                 break;
2375                         case 8:
2376                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2377                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2378                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2379                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2380                                 break;
2381                         case 9:
2382                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2383                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2384                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2385                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2386                                 break;
2387                         case 10:
2388                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2389                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2390                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2391                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2392                                 break;
2393                         case 11:
2394                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2395                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2396                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2397                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2398                                 break;
2399                         case 12:
2400                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2401                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2402                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2403                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2404                                 break;
2405                         case 13:
2406                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2407                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2408                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2409                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2410                                 break;
2411                         case 14:
2412                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2413                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2414                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2415                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2416                                 break;
2417                         case 7:
2418                                 /* unused idx */
2419                                 continue;
2420                         default:
2421                                 gb_tile_moden = 0;
2422                                 break;
2423                         };
2424                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2425                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2426                 }
2427                 break;
2428         case CHIP_CARRIZO:
2429         default:
2430                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2431                         switch (reg_offset) {
2432                         case 0:
2433                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2434                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2435                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2436                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2437                                 break;
2438                         case 1:
2439                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2440                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2441                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2442                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2443                                 break;
2444                         case 2:
2445                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2446                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2447                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2448                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2449                                 break;
2450                         case 3:
2451                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2452                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2453                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2454                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2455                                 break;
2456                         case 4:
2457                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2458                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2459                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2460                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2461                                 break;
2462                         case 5:
2463                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2464                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2465                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2466                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2467                                 break;
2468                         case 6:
2469                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2470                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2471                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2472                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2473                                 break;
2474                         case 8:
2475                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2476                                                 PIPE_CONFIG(ADDR_SURF_P2));
2477                                 break;
2478                         case 9:
2479                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2480                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2481                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2482                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2483                                 break;
2484                         case 10:
2485                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2486                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2487                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2488                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2489                                 break;
2490                         case 11:
2491                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2492                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2493                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2494                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2495                                 break;
2496                         case 13:
2497                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2498                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2499                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2500                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2501                                 break;
2502                         case 14:
2503                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2504                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2505                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2506                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2507                                 break;
2508                         case 15:
2509                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2510                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2511                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2512                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2513                                 break;
2514                         case 16:
2515                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2516                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2517                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2518                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2519                                 break;
2520                         case 18:
2521                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2522                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2523                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2524                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2525                                 break;
2526                         case 19:
2527                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2528                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2529                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2530                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2531                                 break;
2532                         case 20:
2533                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2534                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2535                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2536                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2537                                 break;
2538                         case 21:
2539                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2540                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2541                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2542                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2543                                 break;
2544                         case 22:
2545                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2546                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2547                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2548                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2549                                 break;
2550                         case 24:
2551                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2552                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2553                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2554                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2555                                 break;
2556                         case 25:
2557                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2558                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2559                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2560                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2561                                 break;
2562                         case 26:
2563                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2564                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2565                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2566                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2567                                 break;
2568                         case 27:
2569                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2570                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2571                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2572                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2573                                 break;
2574                         case 28:
2575                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2576                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2577                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2578                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2579                                 break;
2580                         case 29:
2581                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2582                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2583                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2584                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2585                                 break;
2586                         case 7:
2587                         case 12:
2588                         case 17:
2589                         case 23:
2590                                 /* unused idx */
2591                                 continue;
2592                         default:
2593                                 gb_tile_moden = 0;
2594                                 break;
2595                         };
2596                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2597                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2598                 }
2599                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2600                         switch (reg_offset) {
2601                         case 0:
2602                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2603                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2604                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2605                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2606                                 break;
2607                         case 1:
2608                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2610                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2611                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2612                                 break;
2613                         case 2:
2614                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2615                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2616                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2617                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2618                                 break;
2619                         case 3:
2620                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2621                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2622                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2623                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2624                                 break;
2625                         case 4:
2626                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2628                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2629                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2630                                 break;
2631                         case 5:
2632                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2633                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2634                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2635                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2636                                 break;
2637                         case 6:
2638                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2640                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2641                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2642                                 break;
2643                         case 8:
2644                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2645                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2646                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2647                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2648                                 break;
2649                         case 9:
2650                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2651                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2652                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2653                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2654                                 break;
2655                         case 10:
2656                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2657                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2658                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2659                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2660                                 break;
2661                         case 11:
2662                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2663                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2664                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2665                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2666                                 break;
2667                         case 12:
2668                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2669                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2670                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2671                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2672                                 break;
2673                         case 13:
2674                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2675                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2676                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2677                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2678                                 break;
2679                         case 14:
2680                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2681                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2682                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2683                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2684                                 break;
2685                         case 7:
2686                                 /* unused idx */
2687                                 continue;
2688                         default:
2689                                 gb_tile_moden = 0;
2690                                 break;
2691                         };
2692                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2693                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2694                 }
2695         }
2696 }
2697
2698 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
2699 {
2700         u32 i, mask = 0;
2701
2702         for (i = 0; i < bit_width; i++) {
2703                 mask <<= 1;
2704                 mask |= 1;
2705         }
2706         return mask;
2707 }
2708
2709 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
2710 {
2711         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2712
2713         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
2714                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2715                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2716         } else if (se_num == 0xffffffff) {
2717                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2718                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2719         } else if (sh_num == 0xffffffff) {
2720                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2721                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2722         } else {
2723                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2724                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2725         }
2726         WREG32(mmGRBM_GFX_INDEX, data);
2727 }
2728
2729 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
2730                                     u32 max_rb_num_per_se,
2731                                     u32 sh_per_se)
2732 {
2733         u32 data, mask;
2734
2735         data = RREG32(mmCC_RB_BACKEND_DISABLE);
2736         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2737
2738         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2739
2740         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2741
2742         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
2743
2744         return data & mask;
2745 }
2746
2747 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
2748                               u32 se_num, u32 sh_per_se,
2749                               u32 max_rb_num_per_se)
2750 {
2751         int i, j;
2752         u32 data, mask;
2753         u32 disabled_rbs = 0;
2754         u32 enabled_rbs = 0;
2755
2756         mutex_lock(&adev->grbm_idx_mutex);
2757         for (i = 0; i < se_num; i++) {
2758                 for (j = 0; j < sh_per_se; j++) {
2759                         gfx_v8_0_select_se_sh(adev, i, j);
2760                         data = gfx_v8_0_get_rb_disabled(adev,
2761                                               max_rb_num_per_se, sh_per_se);
2762                         disabled_rbs |= data << ((i * sh_per_se + j) *
2763                                                  RB_BITMAP_WIDTH_PER_SH);
2764                 }
2765         }
2766         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2767         mutex_unlock(&adev->grbm_idx_mutex);
2768
2769         mask = 1;
2770         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
2771                 if (!(disabled_rbs & mask))
2772                         enabled_rbs |= mask;
2773                 mask <<= 1;
2774         }
2775
2776         adev->gfx.config.backend_enable_mask = enabled_rbs;
2777
2778         mutex_lock(&adev->grbm_idx_mutex);
2779         for (i = 0; i < se_num; i++) {
2780                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
2781                 data = 0;
2782                 for (j = 0; j < sh_per_se; j++) {
2783                         switch (enabled_rbs & 3) {
2784                         case 0:
2785                                 if (j == 0)
2786                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
2787                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2788                                 else
2789                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
2790                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2791                                 break;
2792                         case 1:
2793                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
2794                                          (i * sh_per_se + j) * 2);
2795                                 break;
2796                         case 2:
2797                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
2798                                          (i * sh_per_se + j) * 2);
2799                                 break;
2800                         case 3:
2801                         default:
2802                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
2803                                          (i * sh_per_se + j) * 2);
2804                                 break;
2805                         }
2806                         enabled_rbs >>= 2;
2807                 }
2808                 WREG32(mmPA_SC_RASTER_CONFIG, data);
2809         }
2810         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2811         mutex_unlock(&adev->grbm_idx_mutex);
2812 }
2813
2814 /**
2815  * gfx_v8_0_init_compute_vmid - gart enable
2816  *
2817  * @rdev: amdgpu_device pointer
2818  *
2819  * Initialize compute vmid sh_mem registers
2820  *
2821  */
2822 #define DEFAULT_SH_MEM_BASES    (0x6000)
2823 #define FIRST_COMPUTE_VMID      (8)
2824 #define LAST_COMPUTE_VMID       (16)
2825 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2826 {
2827         int i;
2828         uint32_t sh_mem_config;
2829         uint32_t sh_mem_bases;
2830
2831         /*
2832          * Configure apertures:
2833          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2834          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2835          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2836          */
2837         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2838
2839         sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2840                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2841                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2842                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2843                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2844                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2845
2846         mutex_lock(&adev->srbm_mutex);
2847         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2848                 vi_srbm_select(adev, 0, 0, 0, i);
2849                 /* CP and shaders */
2850                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2851                 WREG32(mmSH_MEM_APE1_BASE, 1);
2852                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2853                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2854         }
2855         vi_srbm_select(adev, 0, 0, 0, 0);
2856         mutex_unlock(&adev->srbm_mutex);
2857 }
2858
2859 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2860 {
2861         u32 tmp;
2862         int i;
2863
2864         tmp = RREG32(mmGRBM_CNTL);
2865         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2866         WREG32(mmGRBM_CNTL, tmp);
2867
2868         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2869         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2870         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
2871         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2872                adev->gfx.config.gb_addr_config & 0x70);
2873         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2874                adev->gfx.config.gb_addr_config & 0x70);
2875         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2876         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2877         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2878
2879         gfx_v8_0_tiling_mode_table_init(adev);
2880
2881         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2882                                  adev->gfx.config.max_sh_per_se,
2883                                  adev->gfx.config.max_backends_per_se);
2884
2885         /* XXX SH_MEM regs */
2886         /* where to put LDS, scratch, GPUVM in FSA64 space */
2887         mutex_lock(&adev->srbm_mutex);
2888         for (i = 0; i < 16; i++) {
2889                 vi_srbm_select(adev, 0, 0, 0, i);
2890                 /* CP and shaders */
2891                 if (i == 0) {
2892                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2893                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2894                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2895                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2896                         WREG32(mmSH_MEM_CONFIG, tmp);
2897                 } else {
2898                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2899                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2900                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2901                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2902                         WREG32(mmSH_MEM_CONFIG, tmp);
2903                 }
2904
2905                 WREG32(mmSH_MEM_APE1_BASE, 1);
2906                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2907                 WREG32(mmSH_MEM_BASES, 0);
2908         }
2909         vi_srbm_select(adev, 0, 0, 0, 0);
2910         mutex_unlock(&adev->srbm_mutex);
2911
2912         gfx_v8_0_init_compute_vmid(adev);
2913
2914         mutex_lock(&adev->grbm_idx_mutex);
2915         /*
2916          * making sure that the following register writes will be broadcasted
2917          * to all the shaders
2918          */
2919         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2920
2921         WREG32(mmPA_SC_FIFO_SIZE,
2922                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2923                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2924                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2925                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2926                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2927                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2928                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2929                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2930         mutex_unlock(&adev->grbm_idx_mutex);
2931
2932 }
2933
2934 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2935 {
2936         u32 i, j, k;
2937         u32 mask;
2938
2939         mutex_lock(&adev->grbm_idx_mutex);
2940         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2941                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2942                         gfx_v8_0_select_se_sh(adev, i, j);
2943                         for (k = 0; k < adev->usec_timeout; k++) {
2944                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2945                                         break;
2946                                 udelay(1);
2947                         }
2948                 }
2949         }
2950         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2951         mutex_unlock(&adev->grbm_idx_mutex);
2952
2953         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2954                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2955                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2956                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2957         for (k = 0; k < adev->usec_timeout; k++) {
2958                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2959                         break;
2960                 udelay(1);
2961         }
2962 }
2963
2964 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2965                                                bool enable)
2966 {
2967         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2968
2969         if (enable) {
2970                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2971                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2972                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2973                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2974         } else {
2975                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2976                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2977                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2978                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2979         }
2980         WREG32(mmCP_INT_CNTL_RING0, tmp);
2981 }
2982
2983 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2984 {
2985         u32 tmp = RREG32(mmRLC_CNTL);
2986
2987         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2988         WREG32(mmRLC_CNTL, tmp);
2989
2990         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2991
2992         gfx_v8_0_wait_for_rlc_serdes(adev);
2993 }
2994
2995 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2996 {
2997         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2998
2999         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3000         WREG32(mmGRBM_SOFT_RESET, tmp);
3001         udelay(50);
3002         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3003         WREG32(mmGRBM_SOFT_RESET, tmp);
3004         udelay(50);
3005 }
3006
3007 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
3008 {
3009         u32 tmp = RREG32(mmRLC_CNTL);
3010
3011         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
3012         WREG32(mmRLC_CNTL, tmp);
3013
3014         /* carrizo do enable cp interrupt after cp inited */
3015         if (!(adev->flags & AMD_IS_APU))
3016                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3017
3018         udelay(50);
3019 }
3020
3021 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
3022 {
3023         const struct rlc_firmware_header_v2_0 *hdr;
3024         const __le32 *fw_data;
3025         unsigned i, fw_size;
3026
3027         if (!adev->gfx.rlc_fw)
3028                 return -EINVAL;
3029
3030         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3031         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3032
3033         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
3034                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3035         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3036
3037         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3038         for (i = 0; i < fw_size; i++)
3039                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3040         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3041
3042         return 0;
3043 }
3044
3045 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
3046 {
3047         int r;
3048
3049         gfx_v8_0_rlc_stop(adev);
3050
3051         /* disable CG */
3052         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
3053
3054         /* disable PG */
3055         WREG32(mmRLC_PG_CNTL, 0);
3056
3057         gfx_v8_0_rlc_reset(adev);
3058
3059         if (!adev->firmware.smu_load) {
3060                 /* legacy rlc firmware loading */
3061                 r = gfx_v8_0_rlc_load_microcode(adev);
3062                 if (r)
3063                         return r;
3064         } else {
3065                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3066                                                 AMDGPU_UCODE_ID_RLC_G);
3067                 if (r)
3068                         return -EINVAL;
3069         }
3070
3071         gfx_v8_0_rlc_start(adev);
3072
3073         return 0;
3074 }
3075
3076 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
3077 {
3078         int i;
3079         u32 tmp = RREG32(mmCP_ME_CNTL);
3080
3081         if (enable) {
3082                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
3083                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
3084                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
3085         } else {
3086                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
3087                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
3088                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
3089                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3090                         adev->gfx.gfx_ring[i].ready = false;
3091         }
3092         WREG32(mmCP_ME_CNTL, tmp);
3093         udelay(50);
3094 }
3095
3096 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3097 {
3098         const struct gfx_firmware_header_v1_0 *pfp_hdr;
3099         const struct gfx_firmware_header_v1_0 *ce_hdr;
3100         const struct gfx_firmware_header_v1_0 *me_hdr;
3101         const __le32 *fw_data;
3102         unsigned i, fw_size;
3103
3104         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
3105                 return -EINVAL;
3106
3107         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
3108                 adev->gfx.pfp_fw->data;
3109         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
3110                 adev->gfx.ce_fw->data;
3111         me_hdr = (const struct gfx_firmware_header_v1_0 *)
3112                 adev->gfx.me_fw->data;
3113
3114         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3115         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
3116         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
3117
3118         gfx_v8_0_cp_gfx_enable(adev, false);
3119
3120         /* PFP */
3121         fw_data = (const __le32 *)
3122                 (adev->gfx.pfp_fw->data +
3123                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3124         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3125         WREG32(mmCP_PFP_UCODE_ADDR, 0);
3126         for (i = 0; i < fw_size; i++)
3127                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3128         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3129
3130         /* CE */
3131         fw_data = (const __le32 *)
3132                 (adev->gfx.ce_fw->data +
3133                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3134         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3135         WREG32(mmCP_CE_UCODE_ADDR, 0);
3136         for (i = 0; i < fw_size; i++)
3137                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3138         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
3139
3140         /* ME */
3141         fw_data = (const __le32 *)
3142                 (adev->gfx.me_fw->data +
3143                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3144         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3145         WREG32(mmCP_ME_RAM_WADDR, 0);
3146         for (i = 0; i < fw_size; i++)
3147                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3148         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
3149
3150         return 0;
3151 }
3152
3153 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
3154 {
3155         u32 count = 0;
3156         const struct cs_section_def *sect = NULL;
3157         const struct cs_extent_def *ext = NULL;
3158
3159         /* begin clear state */
3160         count += 2;
3161         /* context control state */
3162         count += 3;
3163
3164         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3165                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3166                         if (sect->id == SECT_CONTEXT)
3167                                 count += 2 + ext->reg_count;
3168                         else
3169                                 return 0;
3170                 }
3171         }
3172         /* pa_sc_raster_config/pa_sc_raster_config1 */
3173         count += 4;
3174         /* end clear state */
3175         count += 2;
3176         /* clear state */
3177         count += 2;
3178
3179         return count;
3180 }
3181
3182 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
3183 {
3184         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3185         const struct cs_section_def *sect = NULL;
3186         const struct cs_extent_def *ext = NULL;
3187         int r, i;
3188
3189         /* init the CP */
3190         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3191         WREG32(mmCP_ENDIAN_SWAP, 0);
3192         WREG32(mmCP_DEVICE_ID, 1);
3193
3194         gfx_v8_0_cp_gfx_enable(adev, true);
3195
3196         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
3197         if (r) {
3198                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3199                 return r;
3200         }
3201
3202         /* clear state buffer */
3203         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3204         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3205
3206         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3207         amdgpu_ring_write(ring, 0x80000000);
3208         amdgpu_ring_write(ring, 0x80000000);
3209
3210         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3211                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3212                         if (sect->id == SECT_CONTEXT) {
3213                                 amdgpu_ring_write(ring,
3214                                        PACKET3(PACKET3_SET_CONTEXT_REG,
3215                                                ext->reg_count));
3216                                 amdgpu_ring_write(ring,
3217                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3218                                 for (i = 0; i < ext->reg_count; i++)
3219                                         amdgpu_ring_write(ring, ext->extent[i]);
3220                         }
3221                 }
3222         }
3223
3224         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3225         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3226         switch (adev->asic_type) {
3227         case CHIP_TONGA:
3228                 amdgpu_ring_write(ring, 0x16000012);
3229                 amdgpu_ring_write(ring, 0x0000002A);
3230                 break;
3231         case CHIP_FIJI:
3232                 amdgpu_ring_write(ring, 0x3a00161a);
3233                 amdgpu_ring_write(ring, 0x0000002e);
3234                 break;
3235         case CHIP_TOPAZ:
3236         case CHIP_CARRIZO:
3237                 amdgpu_ring_write(ring, 0x00000002);
3238                 amdgpu_ring_write(ring, 0x00000000);
3239                 break;
3240         case CHIP_STONEY:
3241                 amdgpu_ring_write(ring, 0x00000000);
3242                 amdgpu_ring_write(ring, 0x00000000);
3243                 break;
3244         default:
3245                 BUG();
3246         }
3247
3248         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3249         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3250
3251         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3252         amdgpu_ring_write(ring, 0);
3253
3254         /* init the CE partitions */
3255         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3256         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3257         amdgpu_ring_write(ring, 0x8000);
3258         amdgpu_ring_write(ring, 0x8000);
3259
3260         amdgpu_ring_unlock_commit(ring);
3261
3262         return 0;
3263 }
3264
3265 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
3266 {
3267         struct amdgpu_ring *ring;
3268         u32 tmp;
3269         u32 rb_bufsz;
3270         u64 rb_addr, rptr_addr;
3271         int r;
3272
3273         /* Set the write pointer delay */
3274         WREG32(mmCP_RB_WPTR_DELAY, 0);
3275
3276         /* set the RB to use vmid 0 */
3277         WREG32(mmCP_RB_VMID, 0);
3278
3279         /* Set ring buffer size */
3280         ring = &adev->gfx.gfx_ring[0];
3281         rb_bufsz = order_base_2(ring->ring_size / 8);
3282         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3283         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3284         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
3285         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
3286 #ifdef __BIG_ENDIAN
3287         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3288 #endif
3289         WREG32(mmCP_RB0_CNTL, tmp);
3290
3291         /* Initialize the ring buffer's read and write pointers */
3292         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
3293         ring->wptr = 0;
3294         WREG32(mmCP_RB0_WPTR, ring->wptr);
3295
3296         /* set the wb address wether it's enabled or not */
3297         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3298         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3299         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
3300
3301         mdelay(1);
3302         WREG32(mmCP_RB0_CNTL, tmp);
3303
3304         rb_addr = ring->gpu_addr >> 8;
3305         WREG32(mmCP_RB0_BASE, rb_addr);
3306         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3307
3308         /* no gfx doorbells on iceland */
3309         if (adev->asic_type != CHIP_TOPAZ) {
3310                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
3311                 if (ring->use_doorbell) {
3312                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3313                                             DOORBELL_OFFSET, ring->doorbell_index);
3314                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3315                                             DOORBELL_EN, 1);
3316                 } else {
3317                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3318                                             DOORBELL_EN, 0);
3319                 }
3320                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
3321
3322                 if (adev->asic_type == CHIP_TONGA) {
3323                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3324                                             DOORBELL_RANGE_LOWER,
3325                                             AMDGPU_DOORBELL_GFX_RING0);
3326                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3327
3328                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
3329                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3330                 }
3331
3332         }
3333
3334         /* start the ring */
3335         gfx_v8_0_cp_gfx_start(adev);
3336         ring->ready = true;
3337         r = amdgpu_ring_test_ring(ring);
3338         if (r) {
3339                 ring->ready = false;
3340                 return r;
3341         }
3342
3343         return 0;
3344 }
3345
3346 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3347 {
3348         int i;
3349
3350         if (enable) {
3351                 WREG32(mmCP_MEC_CNTL, 0);
3352         } else {
3353                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3354                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3355                         adev->gfx.compute_ring[i].ready = false;
3356         }
3357         udelay(50);
3358 }
3359
3360 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
3361 {
3362         gfx_v8_0_cp_compute_enable(adev, true);
3363
3364         return 0;
3365 }
3366
3367 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3368 {
3369         const struct gfx_firmware_header_v1_0 *mec_hdr;
3370         const __le32 *fw_data;
3371         unsigned i, fw_size;
3372
3373         if (!adev->gfx.mec_fw)
3374                 return -EINVAL;
3375
3376         gfx_v8_0_cp_compute_enable(adev, false);
3377
3378         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3379         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3380
3381         fw_data = (const __le32 *)
3382                 (adev->gfx.mec_fw->data +
3383                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3384         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3385
3386         /* MEC1 */
3387         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3388         for (i = 0; i < fw_size; i++)
3389                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
3390         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3391
3392         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3393         if (adev->gfx.mec2_fw) {
3394                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3395
3396                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3397                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3398
3399                 fw_data = (const __le32 *)
3400                         (adev->gfx.mec2_fw->data +
3401                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3402                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3403
3404                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3405                 for (i = 0; i < fw_size; i++)
3406                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
3407                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
3408         }
3409
3410         return 0;
3411 }
3412
3413 struct vi_mqd {
3414         uint32_t header;  /* ordinal0 */
3415         uint32_t compute_dispatch_initiator;  /* ordinal1 */
3416         uint32_t compute_dim_x;  /* ordinal2 */
3417         uint32_t compute_dim_y;  /* ordinal3 */
3418         uint32_t compute_dim_z;  /* ordinal4 */
3419         uint32_t compute_start_x;  /* ordinal5 */
3420         uint32_t compute_start_y;  /* ordinal6 */
3421         uint32_t compute_start_z;  /* ordinal7 */
3422         uint32_t compute_num_thread_x;  /* ordinal8 */
3423         uint32_t compute_num_thread_y;  /* ordinal9 */
3424         uint32_t compute_num_thread_z;  /* ordinal10 */
3425         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
3426         uint32_t compute_perfcount_enable;  /* ordinal12 */
3427         uint32_t compute_pgm_lo;  /* ordinal13 */
3428         uint32_t compute_pgm_hi;  /* ordinal14 */
3429         uint32_t compute_tba_lo;  /* ordinal15 */
3430         uint32_t compute_tba_hi;  /* ordinal16 */
3431         uint32_t compute_tma_lo;  /* ordinal17 */
3432         uint32_t compute_tma_hi;  /* ordinal18 */
3433         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
3434         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
3435         uint32_t compute_vmid;  /* ordinal21 */
3436         uint32_t compute_resource_limits;  /* ordinal22 */
3437         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
3438         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
3439         uint32_t compute_tmpring_size;  /* ordinal25 */
3440         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
3441         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
3442         uint32_t compute_restart_x;  /* ordinal28 */
3443         uint32_t compute_restart_y;  /* ordinal29 */
3444         uint32_t compute_restart_z;  /* ordinal30 */
3445         uint32_t compute_thread_trace_enable;  /* ordinal31 */
3446         uint32_t compute_misc_reserved;  /* ordinal32 */
3447         uint32_t compute_dispatch_id;  /* ordinal33 */
3448         uint32_t compute_threadgroup_id;  /* ordinal34 */
3449         uint32_t compute_relaunch;  /* ordinal35 */
3450         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
3451         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
3452         uint32_t compute_wave_restore_control;  /* ordinal38 */
3453         uint32_t reserved9;  /* ordinal39 */
3454         uint32_t reserved10;  /* ordinal40 */
3455         uint32_t reserved11;  /* ordinal41 */
3456         uint32_t reserved12;  /* ordinal42 */
3457         uint32_t reserved13;  /* ordinal43 */
3458         uint32_t reserved14;  /* ordinal44 */
3459         uint32_t reserved15;  /* ordinal45 */
3460         uint32_t reserved16;  /* ordinal46 */
3461         uint32_t reserved17;  /* ordinal47 */
3462         uint32_t reserved18;  /* ordinal48 */
3463         uint32_t reserved19;  /* ordinal49 */
3464         uint32_t reserved20;  /* ordinal50 */
3465         uint32_t reserved21;  /* ordinal51 */
3466         uint32_t reserved22;  /* ordinal52 */
3467         uint32_t reserved23;  /* ordinal53 */
3468         uint32_t reserved24;  /* ordinal54 */
3469         uint32_t reserved25;  /* ordinal55 */
3470         uint32_t reserved26;  /* ordinal56 */
3471         uint32_t reserved27;  /* ordinal57 */
3472         uint32_t reserved28;  /* ordinal58 */
3473         uint32_t reserved29;  /* ordinal59 */
3474         uint32_t reserved30;  /* ordinal60 */
3475         uint32_t reserved31;  /* ordinal61 */
3476         uint32_t reserved32;  /* ordinal62 */
3477         uint32_t reserved33;  /* ordinal63 */
3478         uint32_t reserved34;  /* ordinal64 */
3479         uint32_t compute_user_data_0;  /* ordinal65 */
3480         uint32_t compute_user_data_1;  /* ordinal66 */
3481         uint32_t compute_user_data_2;  /* ordinal67 */
3482         uint32_t compute_user_data_3;  /* ordinal68 */
3483         uint32_t compute_user_data_4;  /* ordinal69 */
3484         uint32_t compute_user_data_5;  /* ordinal70 */
3485         uint32_t compute_user_data_6;  /* ordinal71 */
3486         uint32_t compute_user_data_7;  /* ordinal72 */
3487         uint32_t compute_user_data_8;  /* ordinal73 */
3488         uint32_t compute_user_data_9;  /* ordinal74 */
3489         uint32_t compute_user_data_10;  /* ordinal75 */
3490         uint32_t compute_user_data_11;  /* ordinal76 */
3491         uint32_t compute_user_data_12;  /* ordinal77 */
3492         uint32_t compute_user_data_13;  /* ordinal78 */
3493         uint32_t compute_user_data_14;  /* ordinal79 */
3494         uint32_t compute_user_data_15;  /* ordinal80 */
3495         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
3496         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
3497         uint32_t reserved35;  /* ordinal83 */
3498         uint32_t reserved36;  /* ordinal84 */
3499         uint32_t reserved37;  /* ordinal85 */
3500         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
3501         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
3502         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
3503         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
3504         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
3505         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
3506         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
3507         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
3508         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
3509         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
3510         uint32_t reserved38;  /* ordinal96 */
3511         uint32_t reserved39;  /* ordinal97 */
3512         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
3513         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
3514         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
3515         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
3516         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
3517         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
3518         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
3519         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
3520         uint32_t reserved40;  /* ordinal106 */
3521         uint32_t reserved41;  /* ordinal107 */
3522         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
3523         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
3524         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
3525         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
3526         uint32_t reserved42;  /* ordinal112 */
3527         uint32_t reserved43;  /* ordinal113 */
3528         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
3529         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
3530         uint32_t cp_packet_id_lo;  /* ordinal116 */
3531         uint32_t cp_packet_id_hi;  /* ordinal117 */
3532         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
3533         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
3534         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
3535         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
3536         uint32_t gds_save_mask_lo;  /* ordinal122 */
3537         uint32_t gds_save_mask_hi;  /* ordinal123 */
3538         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
3539         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
3540         uint32_t reserved44;  /* ordinal126 */
3541         uint32_t reserved45;  /* ordinal127 */
3542         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
3543         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
3544         uint32_t cp_hqd_active;  /* ordinal130 */
3545         uint32_t cp_hqd_vmid;  /* ordinal131 */
3546         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
3547         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
3548         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
3549         uint32_t cp_hqd_quantum;  /* ordinal135 */
3550         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
3551         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
3552         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
3553         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
3554         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
3555         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
3556         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
3557         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
3558         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
3559         uint32_t cp_hqd_pq_control;  /* ordinal145 */
3560         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
3561         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
3562         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
3563         uint32_t cp_hqd_ib_control;  /* ordinal149 */
3564         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
3565         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
3566         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
3567         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
3568         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
3569         uint32_t cp_hqd_msg_type;  /* ordinal155 */
3570         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
3571         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
3572         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
3573         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
3574         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
3575         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
3576         uint32_t cp_mqd_control;  /* ordinal162 */
3577         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
3578         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
3579         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
3580         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
3581         uint32_t cp_hqd_eop_control;  /* ordinal167 */
3582         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
3583         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
3584         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
3585         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
3586         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
3587         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
3588         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
3589         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
3590         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
3591         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
3592         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
3593         uint32_t cp_hqd_error;  /* ordinal179 */
3594         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
3595         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
3596         uint32_t reserved46;  /* ordinal182 */
3597         uint32_t reserved47;  /* ordinal183 */
3598         uint32_t reserved48;  /* ordinal184 */
3599         uint32_t reserved49;  /* ordinal185 */
3600         uint32_t reserved50;  /* ordinal186 */
3601         uint32_t reserved51;  /* ordinal187 */
3602         uint32_t reserved52;  /* ordinal188 */
3603         uint32_t reserved53;  /* ordinal189 */
3604         uint32_t reserved54;  /* ordinal190 */
3605         uint32_t reserved55;  /* ordinal191 */
3606         uint32_t iqtimer_pkt_header;  /* ordinal192 */
3607         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
3608         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
3609         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
3610         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
3611         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
3612         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
3613         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
3614         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
3615         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
3616         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
3617         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
3618         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
3619         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
3620         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
3621         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
3622         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
3623         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
3624         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
3625         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
3626         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
3627         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
3628         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
3629         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
3630         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
3631         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
3632         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
3633         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
3634         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
3635         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
3636         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
3637         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
3638         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
3639         uint32_t reserved56;  /* ordinal225 */
3640         uint32_t reserved57;  /* ordinal226 */
3641         uint32_t reserved58;  /* ordinal227 */
3642         uint32_t set_resources_header;  /* ordinal228 */
3643         uint32_t set_resources_dw1;  /* ordinal229 */
3644         uint32_t set_resources_dw2;  /* ordinal230 */
3645         uint32_t set_resources_dw3;  /* ordinal231 */
3646         uint32_t set_resources_dw4;  /* ordinal232 */
3647         uint32_t set_resources_dw5;  /* ordinal233 */
3648         uint32_t set_resources_dw6;  /* ordinal234 */
3649         uint32_t set_resources_dw7;  /* ordinal235 */
3650         uint32_t reserved59;  /* ordinal236 */
3651         uint32_t reserved60;  /* ordinal237 */
3652         uint32_t reserved61;  /* ordinal238 */
3653         uint32_t reserved62;  /* ordinal239 */
3654         uint32_t reserved63;  /* ordinal240 */
3655         uint32_t reserved64;  /* ordinal241 */
3656         uint32_t reserved65;  /* ordinal242 */
3657         uint32_t reserved66;  /* ordinal243 */
3658         uint32_t reserved67;  /* ordinal244 */
3659         uint32_t reserved68;  /* ordinal245 */
3660         uint32_t reserved69;  /* ordinal246 */
3661         uint32_t reserved70;  /* ordinal247 */
3662         uint32_t reserved71;  /* ordinal248 */
3663         uint32_t reserved72;  /* ordinal249 */
3664         uint32_t reserved73;  /* ordinal250 */
3665         uint32_t reserved74;  /* ordinal251 */
3666         uint32_t reserved75;  /* ordinal252 */
3667         uint32_t reserved76;  /* ordinal253 */
3668         uint32_t reserved77;  /* ordinal254 */
3669         uint32_t reserved78;  /* ordinal255 */
3670
3671         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3672 };
3673
3674 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3675 {
3676         int i, r;
3677
3678         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3679                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3680
3681                 if (ring->mqd_obj) {
3682                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3683                         if (unlikely(r != 0))
3684                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3685
3686                         amdgpu_bo_unpin(ring->mqd_obj);
3687                         amdgpu_bo_unreserve(ring->mqd_obj);
3688
3689                         amdgpu_bo_unref(&ring->mqd_obj);
3690                         ring->mqd_obj = NULL;
3691                 }
3692         }
3693 }
3694
3695 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3696 {
3697         int r, i, j;
3698         u32 tmp;
3699         bool use_doorbell = true;
3700         u64 hqd_gpu_addr;
3701         u64 mqd_gpu_addr;
3702         u64 eop_gpu_addr;
3703         u64 wb_gpu_addr;
3704         u32 *buf;
3705         struct vi_mqd *mqd;
3706
3707         /* init the pipes */
3708         mutex_lock(&adev->srbm_mutex);
3709         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3710                 int me = (i < 4) ? 1 : 2;
3711                 int pipe = (i < 4) ? i : (i - 4);
3712
3713                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3714                 eop_gpu_addr >>= 8;
3715
3716                 vi_srbm_select(adev, me, pipe, 0, 0);
3717
3718                 /* write the EOP addr */
3719                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3720                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3721
3722                 /* set the VMID assigned */
3723                 WREG32(mmCP_HQD_VMID, 0);
3724
3725                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3726                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3727                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3728                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
3729                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3730         }
3731         vi_srbm_select(adev, 0, 0, 0, 0);
3732         mutex_unlock(&adev->srbm_mutex);
3733
3734         /* init the queues.  Just two for now. */
3735         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3736                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3737
3738                 if (ring->mqd_obj == NULL) {
3739                         r = amdgpu_bo_create(adev,
3740                                              sizeof(struct vi_mqd),
3741                                              PAGE_SIZE, true,
3742                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3743                                              NULL, &ring->mqd_obj);
3744                         if (r) {
3745                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3746                                 return r;
3747                         }
3748                 }
3749
3750                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3751                 if (unlikely(r != 0)) {
3752                         gfx_v8_0_cp_compute_fini(adev);
3753                         return r;
3754                 }
3755                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3756                                   &mqd_gpu_addr);
3757                 if (r) {
3758                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3759                         gfx_v8_0_cp_compute_fini(adev);
3760                         return r;
3761                 }
3762                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3763                 if (r) {
3764                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3765                         gfx_v8_0_cp_compute_fini(adev);
3766                         return r;
3767                 }
3768
3769                 /* init the mqd struct */
3770                 memset(buf, 0, sizeof(struct vi_mqd));
3771
3772                 mqd = (struct vi_mqd *)buf;
3773                 mqd->header = 0xC0310800;
3774                 mqd->compute_pipelinestat_enable = 0x00000001;
3775                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3776                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3777                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3778                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3779                 mqd->compute_misc_reserved = 0x00000003;
3780
3781                 mutex_lock(&adev->srbm_mutex);
3782                 vi_srbm_select(adev, ring->me,
3783                                ring->pipe,
3784                                ring->queue, 0);
3785
3786                 /* disable wptr polling */
3787                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3788                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3789                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3790
3791                 mqd->cp_hqd_eop_base_addr_lo =
3792                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
3793                 mqd->cp_hqd_eop_base_addr_hi =
3794                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3795
3796                 /* enable doorbell? */
3797                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3798                 if (use_doorbell) {
3799                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3800                 } else {
3801                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3802                 }
3803                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3804                 mqd->cp_hqd_pq_doorbell_control = tmp;
3805
3806                 /* disable the queue if it's active */
3807                 mqd->cp_hqd_dequeue_request = 0;
3808                 mqd->cp_hqd_pq_rptr = 0;
3809                 mqd->cp_hqd_pq_wptr= 0;
3810                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3811                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3812                         for (j = 0; j < adev->usec_timeout; j++) {
3813                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3814                                         break;
3815                                 udelay(1);
3816                         }
3817                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3818                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3819                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3820                 }
3821
3822                 /* set the pointer to the MQD */
3823                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3824                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3825                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3826                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3827
3828                 /* set MQD vmid to 0 */
3829                 tmp = RREG32(mmCP_MQD_CONTROL);
3830                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3831                 WREG32(mmCP_MQD_CONTROL, tmp);
3832                 mqd->cp_mqd_control = tmp;
3833
3834                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3835                 hqd_gpu_addr = ring->gpu_addr >> 8;
3836                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3837                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3838                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3839                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3840
3841                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3842                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3843                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3844                                     (order_base_2(ring->ring_size / 4) - 1));
3845                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3846                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3847 #ifdef __BIG_ENDIAN
3848                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3849 #endif
3850                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3851                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3852                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3853                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3854                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3855                 mqd->cp_hqd_pq_control = tmp;
3856
3857                 /* set the wb address wether it's enabled or not */
3858                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3859                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3860                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3861                         upper_32_bits(wb_gpu_addr) & 0xffff;
3862                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3863                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3864                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3865                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3866
3867                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3868                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3869                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3870                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3871                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3872                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3873                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3874
3875                 /* enable the doorbell if requested */
3876                 if (use_doorbell) {
3877                         if ((adev->asic_type == CHIP_CARRIZO) ||
3878                             (adev->asic_type == CHIP_FIJI) ||
3879                             (adev->asic_type == CHIP_STONEY)) {
3880                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3881                                        AMDGPU_DOORBELL_KIQ << 2);
3882                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3883                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3884                         }
3885                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3886                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3887                                             DOORBELL_OFFSET, ring->doorbell_index);
3888                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3889                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3890                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3891                         mqd->cp_hqd_pq_doorbell_control = tmp;
3892
3893                 } else {
3894                         mqd->cp_hqd_pq_doorbell_control = 0;
3895                 }
3896                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3897                        mqd->cp_hqd_pq_doorbell_control);
3898
3899                 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3900                 ring->wptr = 0;
3901                 mqd->cp_hqd_pq_wptr = ring->wptr;
3902                 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3903                 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3904
3905                 /* set the vmid for the queue */
3906                 mqd->cp_hqd_vmid = 0;
3907                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3908
3909                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3910                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3911                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3912                 mqd->cp_hqd_persistent_state = tmp;
3913
3914                 /* activate the queue */
3915                 mqd->cp_hqd_active = 1;
3916                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3917
3918                 vi_srbm_select(adev, 0, 0, 0, 0);
3919                 mutex_unlock(&adev->srbm_mutex);
3920
3921                 amdgpu_bo_kunmap(ring->mqd_obj);
3922                 amdgpu_bo_unreserve(ring->mqd_obj);
3923         }
3924
3925         if (use_doorbell) {
3926                 tmp = RREG32(mmCP_PQ_STATUS);
3927                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3928                 WREG32(mmCP_PQ_STATUS, tmp);
3929         }
3930
3931         r = gfx_v8_0_cp_compute_start(adev);
3932         if (r)
3933                 return r;
3934
3935         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3936                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3937
3938                 ring->ready = true;
3939                 r = amdgpu_ring_test_ring(ring);
3940                 if (r)
3941                         ring->ready = false;
3942         }
3943
3944         return 0;
3945 }
3946
3947 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3948 {
3949         int r;
3950
3951         if (!(adev->flags & AMD_IS_APU))
3952                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3953
3954         if (!adev->firmware.smu_load) {
3955                 /* legacy firmware loading */
3956                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3957                 if (r)
3958                         return r;
3959
3960                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3961                 if (r)
3962                         return r;
3963         } else {
3964                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3965                                                 AMDGPU_UCODE_ID_CP_CE);
3966                 if (r)
3967                         return -EINVAL;
3968
3969                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3970                                                 AMDGPU_UCODE_ID_CP_PFP);
3971                 if (r)
3972                         return -EINVAL;
3973
3974                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3975                                                 AMDGPU_UCODE_ID_CP_ME);
3976                 if (r)
3977                         return -EINVAL;
3978
3979                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3980                                                 AMDGPU_UCODE_ID_CP_MEC1);
3981                 if (r)
3982                         return -EINVAL;
3983         }
3984
3985         r = gfx_v8_0_cp_gfx_resume(adev);
3986         if (r)
3987                 return r;
3988
3989         r = gfx_v8_0_cp_compute_resume(adev);
3990         if (r)
3991                 return r;
3992
3993         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3994
3995         return 0;
3996 }
3997
3998 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3999 {
4000         gfx_v8_0_cp_gfx_enable(adev, enable);
4001         gfx_v8_0_cp_compute_enable(adev, enable);
4002 }
4003
4004 static int gfx_v8_0_hw_init(void *handle)
4005 {
4006         int r;
4007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4008
4009         gfx_v8_0_init_golden_registers(adev);
4010
4011         gfx_v8_0_gpu_init(adev);
4012
4013         r = gfx_v8_0_rlc_resume(adev);
4014         if (r)
4015                 return r;
4016
4017         r = gfx_v8_0_cp_resume(adev);
4018         if (r)
4019                 return r;
4020
4021         return r;
4022 }
4023
4024 static int gfx_v8_0_hw_fini(void *handle)
4025 {
4026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4027
4028         gfx_v8_0_cp_enable(adev, false);
4029         gfx_v8_0_rlc_stop(adev);
4030         gfx_v8_0_cp_compute_fini(adev);
4031
4032         return 0;
4033 }
4034
4035 static int gfx_v8_0_suspend(void *handle)
4036 {
4037         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4038
4039         return gfx_v8_0_hw_fini(adev);
4040 }
4041
4042 static int gfx_v8_0_resume(void *handle)
4043 {
4044         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4045
4046         return gfx_v8_0_hw_init(adev);
4047 }
4048
4049 static bool gfx_v8_0_is_idle(void *handle)
4050 {
4051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4052
4053         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
4054                 return false;
4055         else
4056                 return true;
4057 }
4058
4059 static int gfx_v8_0_wait_for_idle(void *handle)
4060 {
4061         unsigned i;
4062         u32 tmp;
4063         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4064
4065         for (i = 0; i < adev->usec_timeout; i++) {
4066                 /* read MC_STATUS */
4067                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4068
4069                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4070                         return 0;
4071                 udelay(1);
4072         }
4073         return -ETIMEDOUT;
4074 }
4075
4076 static void gfx_v8_0_print_status(void *handle)
4077 {
4078         int i;
4079         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4080
4081         dev_info(adev->dev, "GFX 8.x registers\n");
4082         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
4083                  RREG32(mmGRBM_STATUS));
4084         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
4085                  RREG32(mmGRBM_STATUS2));
4086         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
4087                  RREG32(mmGRBM_STATUS_SE0));
4088         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
4089                  RREG32(mmGRBM_STATUS_SE1));
4090         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
4091                  RREG32(mmGRBM_STATUS_SE2));
4092         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
4093                  RREG32(mmGRBM_STATUS_SE3));
4094         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4095         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
4096                  RREG32(mmCP_STALLED_STAT1));
4097         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
4098                  RREG32(mmCP_STALLED_STAT2));
4099         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
4100                  RREG32(mmCP_STALLED_STAT3));
4101         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
4102                  RREG32(mmCP_CPF_BUSY_STAT));
4103         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
4104                  RREG32(mmCP_CPF_STALLED_STAT1));
4105         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4106         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4107         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
4108                  RREG32(mmCP_CPC_STALLED_STAT1));
4109         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4110
4111         for (i = 0; i < 32; i++) {
4112                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
4113                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4114         }
4115         for (i = 0; i < 16; i++) {
4116                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
4117                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4118         }
4119         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4120                 dev_info(adev->dev, "  se: %d\n", i);
4121                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
4122                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
4123                          RREG32(mmPA_SC_RASTER_CONFIG));
4124                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
4125                          RREG32(mmPA_SC_RASTER_CONFIG_1));
4126         }
4127         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4128
4129         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
4130                  RREG32(mmGB_ADDR_CONFIG));
4131         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
4132                  RREG32(mmHDP_ADDR_CONFIG));
4133         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
4134                  RREG32(mmDMIF_ADDR_CALC));
4135         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
4136                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
4137         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
4138                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
4139         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
4140                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
4141         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
4142                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
4143         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
4144                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
4145
4146         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
4147                  RREG32(mmCP_MEQ_THRESHOLDS));
4148         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
4149                  RREG32(mmSX_DEBUG_1));
4150         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
4151                  RREG32(mmTA_CNTL_AUX));
4152         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
4153                  RREG32(mmSPI_CONFIG_CNTL));
4154         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
4155                  RREG32(mmSQ_CONFIG));
4156         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
4157                  RREG32(mmDB_DEBUG));
4158         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
4159                  RREG32(mmDB_DEBUG2));
4160         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
4161                  RREG32(mmDB_DEBUG3));
4162         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
4163                  RREG32(mmCB_HW_CONTROL));
4164         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
4165                  RREG32(mmSPI_CONFIG_CNTL_1));
4166         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
4167                  RREG32(mmPA_SC_FIFO_SIZE));
4168         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
4169                  RREG32(mmVGT_NUM_INSTANCES));
4170         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
4171                  RREG32(mmCP_PERFMON_CNTL));
4172         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4173                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4174         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
4175                  RREG32(mmVGT_CACHE_INVALIDATION));
4176         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
4177                  RREG32(mmVGT_GS_VERTEX_REUSE));
4178         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4179                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4180         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
4181                  RREG32(mmPA_CL_ENHANCE));
4182         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
4183                  RREG32(mmPA_SC_ENHANCE));
4184
4185         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
4186                  RREG32(mmCP_ME_CNTL));
4187         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
4188                  RREG32(mmCP_MAX_CONTEXT));
4189         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
4190                  RREG32(mmCP_ENDIAN_SWAP));
4191         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
4192                  RREG32(mmCP_DEVICE_ID));
4193
4194         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
4195                  RREG32(mmCP_SEM_WAIT_TIMER));
4196
4197         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
4198                  RREG32(mmCP_RB_WPTR_DELAY));
4199         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
4200                  RREG32(mmCP_RB_VMID));
4201         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
4202                  RREG32(mmCP_RB0_CNTL));
4203         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
4204                  RREG32(mmCP_RB0_WPTR));
4205         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
4206                  RREG32(mmCP_RB0_RPTR_ADDR));
4207         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4208                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
4209         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
4210                  RREG32(mmCP_RB0_CNTL));
4211         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
4212                  RREG32(mmCP_RB0_BASE));
4213         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
4214                  RREG32(mmCP_RB0_BASE_HI));
4215         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
4216                  RREG32(mmCP_MEC_CNTL));
4217         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
4218                  RREG32(mmCP_CPF_DEBUG));
4219
4220         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
4221                  RREG32(mmSCRATCH_ADDR));
4222         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
4223                  RREG32(mmSCRATCH_UMSK));
4224
4225         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
4226                  RREG32(mmCP_INT_CNTL_RING0));
4227         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
4228                  RREG32(mmRLC_LB_CNTL));
4229         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
4230                  RREG32(mmRLC_CNTL));
4231         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
4232                  RREG32(mmRLC_CGCG_CGLS_CTRL));
4233         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
4234                  RREG32(mmRLC_LB_CNTR_INIT));
4235         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
4236                  RREG32(mmRLC_LB_CNTR_MAX));
4237         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
4238                  RREG32(mmRLC_LB_INIT_CU_MASK));
4239         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
4240                  RREG32(mmRLC_LB_PARAMS));
4241         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
4242                  RREG32(mmRLC_LB_CNTL));
4243         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
4244                  RREG32(mmRLC_MC_CNTL));
4245         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
4246                  RREG32(mmRLC_UCODE_CNTL));
4247
4248         mutex_lock(&adev->srbm_mutex);
4249         for (i = 0; i < 16; i++) {
4250                 vi_srbm_select(adev, 0, 0, 0, i);
4251                 dev_info(adev->dev, "  VM %d:\n", i);
4252                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
4253                          RREG32(mmSH_MEM_CONFIG));
4254                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
4255                          RREG32(mmSH_MEM_APE1_BASE));
4256                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
4257                          RREG32(mmSH_MEM_APE1_LIMIT));
4258                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
4259                          RREG32(mmSH_MEM_BASES));
4260         }
4261         vi_srbm_select(adev, 0, 0, 0, 0);
4262         mutex_unlock(&adev->srbm_mutex);
4263 }
4264
4265 static int gfx_v8_0_soft_reset(void *handle)
4266 {
4267         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4268         u32 tmp;
4269         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4270
4271         /* GRBM_STATUS */
4272         tmp = RREG32(mmGRBM_STATUS);
4273         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4274                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4275                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4276                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4277                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4278                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
4279                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4280                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4281                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4282                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4283         }
4284
4285         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4286                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4287                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4288                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4289                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4290         }
4291
4292         /* GRBM_STATUS2 */
4293         tmp = RREG32(mmGRBM_STATUS2);
4294         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4295                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4296                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4297
4298         /* SRBM_STATUS */
4299         tmp = RREG32(mmSRBM_STATUS);
4300         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4301                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4302                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4303
4304         if (grbm_soft_reset || srbm_soft_reset) {
4305                 gfx_v8_0_print_status((void *)adev);
4306                 /* stop the rlc */
4307                 gfx_v8_0_rlc_stop(adev);
4308
4309                 /* Disable GFX parsing/prefetching */
4310                 gfx_v8_0_cp_gfx_enable(adev, false);
4311
4312                 /* Disable MEC parsing/prefetching */
4313                 /* XXX todo */
4314
4315                 if (grbm_soft_reset) {
4316                         tmp = RREG32(mmGRBM_SOFT_RESET);
4317                         tmp |= grbm_soft_reset;
4318                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4319                         WREG32(mmGRBM_SOFT_RESET, tmp);
4320                         tmp = RREG32(mmGRBM_SOFT_RESET);
4321
4322                         udelay(50);
4323
4324                         tmp &= ~grbm_soft_reset;
4325                         WREG32(mmGRBM_SOFT_RESET, tmp);
4326                         tmp = RREG32(mmGRBM_SOFT_RESET);
4327                 }
4328
4329                 if (srbm_soft_reset) {
4330                         tmp = RREG32(mmSRBM_SOFT_RESET);
4331                         tmp |= srbm_soft_reset;
4332                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4333                         WREG32(mmSRBM_SOFT_RESET, tmp);
4334                         tmp = RREG32(mmSRBM_SOFT_RESET);
4335
4336                         udelay(50);
4337
4338                         tmp &= ~srbm_soft_reset;
4339                         WREG32(mmSRBM_SOFT_RESET, tmp);
4340                         tmp = RREG32(mmSRBM_SOFT_RESET);
4341                 }
4342                 /* Wait a little for things to settle down */
4343                 udelay(50);
4344                 gfx_v8_0_print_status((void *)adev);
4345         }
4346         return 0;
4347 }
4348
4349 /**
4350  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
4351  *
4352  * @adev: amdgpu_device pointer
4353  *
4354  * Fetches a GPU clock counter snapshot.
4355  * Returns the 64 bit clock counter snapshot.
4356  */
4357 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4358 {
4359         uint64_t clock;
4360
4361         mutex_lock(&adev->gfx.gpu_clock_mutex);
4362         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4363         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4364                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4365         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4366         return clock;
4367 }
4368
4369 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4370                                           uint32_t vmid,
4371                                           uint32_t gds_base, uint32_t gds_size,
4372                                           uint32_t gws_base, uint32_t gws_size,
4373                                           uint32_t oa_base, uint32_t oa_size)
4374 {
4375         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4376         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4377
4378         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4379         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4380
4381         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4382         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4383
4384         /* GDS Base */
4385         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4386         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4387                                 WRITE_DATA_DST_SEL(0)));
4388         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4389         amdgpu_ring_write(ring, 0);
4390         amdgpu_ring_write(ring, gds_base);
4391
4392         /* GDS Size */
4393         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4394         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4395                                 WRITE_DATA_DST_SEL(0)));
4396         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4397         amdgpu_ring_write(ring, 0);
4398         amdgpu_ring_write(ring, gds_size);
4399
4400         /* GWS */
4401         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4402         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4403                                 WRITE_DATA_DST_SEL(0)));
4404         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4405         amdgpu_ring_write(ring, 0);
4406         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4407
4408         /* OA */
4409         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4410         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4411                                 WRITE_DATA_DST_SEL(0)));
4412         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4413         amdgpu_ring_write(ring, 0);
4414         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4415 }
4416
4417 static int gfx_v8_0_early_init(void *handle)
4418 {
4419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4420
4421         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
4422         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
4423         gfx_v8_0_set_ring_funcs(adev);
4424         gfx_v8_0_set_irq_funcs(adev);
4425         gfx_v8_0_set_gds_init(adev);
4426
4427         return 0;
4428 }
4429
4430 static int gfx_v8_0_set_powergating_state(void *handle,
4431                                           enum amd_powergating_state state)
4432 {
4433         return 0;
4434 }
4435
4436 static int gfx_v8_0_set_clockgating_state(void *handle,
4437                                           enum amd_clockgating_state state)
4438 {
4439         return 0;
4440 }
4441
4442 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4443 {
4444         u32 rptr;
4445
4446         rptr = ring->adev->wb.wb[ring->rptr_offs];
4447
4448         return rptr;
4449 }
4450
4451 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4452 {
4453         struct amdgpu_device *adev = ring->adev;
4454         u32 wptr;
4455
4456         if (ring->use_doorbell)
4457                 /* XXX check if swapping is necessary on BE */
4458                 wptr = ring->adev->wb.wb[ring->wptr_offs];
4459         else
4460                 wptr = RREG32(mmCP_RB0_WPTR);
4461
4462         return wptr;
4463 }
4464
4465 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4466 {
4467         struct amdgpu_device *adev = ring->adev;
4468
4469         if (ring->use_doorbell) {
4470                 /* XXX check if swapping is necessary on BE */
4471                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4472                 WDOORBELL32(ring->doorbell_index, ring->wptr);
4473         } else {
4474                 WREG32(mmCP_RB0_WPTR, ring->wptr);
4475                 (void)RREG32(mmCP_RB0_WPTR);
4476         }
4477 }
4478
4479 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4480 {
4481         u32 ref_and_mask, reg_mem_engine;
4482
4483         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
4484                 switch (ring->me) {
4485                 case 1:
4486                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
4487                         break;
4488                 case 2:
4489                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
4490                         break;
4491                 default:
4492                         return;
4493                 }
4494                 reg_mem_engine = 0;
4495         } else {
4496                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
4497                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
4498         }
4499
4500         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4501         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
4502                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
4503                                  reg_mem_engine));
4504         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
4505         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
4506         amdgpu_ring_write(ring, ref_and_mask);
4507         amdgpu_ring_write(ring, ref_and_mask);
4508         amdgpu_ring_write(ring, 0x20); /* poll interval */
4509 }
4510
4511 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4512                                   struct amdgpu_ib *ib)
4513 {
4514         bool need_ctx_switch = ring->current_ctx != ib->ctx;
4515         u32 header, control = 0;
4516         u32 next_rptr = ring->wptr + 5;
4517
4518         /* drop the CE preamble IB for the same context */
4519         if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
4520                 return;
4521
4522         if (need_ctx_switch)
4523                 next_rptr += 2;
4524
4525         next_rptr += 4;
4526         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4527         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4528         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4529         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4530         amdgpu_ring_write(ring, next_rptr);
4531
4532         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
4533         if (need_ctx_switch) {
4534                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4535                 amdgpu_ring_write(ring, 0);
4536         }
4537
4538         if (ib->flags & AMDGPU_IB_FLAG_CE)
4539                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4540         else
4541                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4542
4543         control |= ib->length_dw |
4544                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4545
4546         amdgpu_ring_write(ring, header);
4547         amdgpu_ring_write(ring,
4548 #ifdef __BIG_ENDIAN
4549                           (2 << 0) |
4550 #endif
4551                           (ib->gpu_addr & 0xFFFFFFFC));
4552         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4553         amdgpu_ring_write(ring, control);
4554 }
4555
4556 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4557                                   struct amdgpu_ib *ib)
4558 {
4559         u32 header, control = 0;
4560         u32 next_rptr = ring->wptr + 5;
4561
4562         control |= INDIRECT_BUFFER_VALID;
4563
4564         next_rptr += 4;
4565         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4566         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4567         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4568         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4569         amdgpu_ring_write(ring, next_rptr);
4570
4571         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4572
4573         control |= ib->length_dw |
4574                            (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4575
4576         amdgpu_ring_write(ring, header);
4577         amdgpu_ring_write(ring,
4578 #ifdef __BIG_ENDIAN
4579                                           (2 << 0) |
4580 #endif
4581                                           (ib->gpu_addr & 0xFFFFFFFC));
4582         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4583         amdgpu_ring_write(ring, control);
4584 }
4585
4586 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
4587                                          u64 seq, unsigned flags)
4588 {
4589         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4590         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4591
4592         /* EVENT_WRITE_EOP - flush caches, send int */
4593         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
4594         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4595                                  EOP_TC_ACTION_EN |
4596                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4597                                  EVENT_INDEX(5)));
4598         amdgpu_ring_write(ring, addr & 0xfffffffc);
4599         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
4600                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4601         amdgpu_ring_write(ring, lower_32_bits(seq));
4602         amdgpu_ring_write(ring, upper_32_bits(seq));
4603
4604 }
4605
4606 /**
4607  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
4608  *
4609  * @ring: amdgpu ring buffer object
4610  * @semaphore: amdgpu semaphore object
4611  * @emit_wait: Is this a sempahore wait?
4612  *
4613  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
4614  * from running ahead of semaphore waits.
4615  */
4616 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
4617                                          struct amdgpu_semaphore *semaphore,
4618                                          bool emit_wait)
4619 {
4620         uint64_t addr = semaphore->gpu_addr;
4621         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
4622
4623         if (ring->adev->asic_type == CHIP_TOPAZ ||
4624             ring->adev->asic_type == CHIP_TONGA ||
4625             ring->adev->asic_type == CHIP_FIJI)
4626                 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
4627                 return false;
4628         else {
4629                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
4630                 amdgpu_ring_write(ring, lower_32_bits(addr));
4631                 amdgpu_ring_write(ring, upper_32_bits(addr));
4632                 amdgpu_ring_write(ring, sel);
4633         }
4634
4635         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
4636                 /* Prevent the PFP from running ahead of the semaphore wait */
4637                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4638                 amdgpu_ring_write(ring, 0x0);
4639         }
4640
4641         return true;
4642 }
4643
4644 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4645                                         unsigned vm_id, uint64_t pd_addr)
4646 {
4647         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4648         uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
4649         uint64_t addr = ring->fence_drv.gpu_addr;
4650
4651         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4652         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4653                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
4654                                  WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
4655         amdgpu_ring_write(ring, addr & 0xfffffffc);
4656         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4657         amdgpu_ring_write(ring, seq);
4658         amdgpu_ring_write(ring, 0xffffffff);
4659         amdgpu_ring_write(ring, 4); /* poll interval */
4660
4661         if (usepfp) {
4662                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4663                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4664                 amdgpu_ring_write(ring, 0);
4665                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4666                 amdgpu_ring_write(ring, 0);
4667         }
4668
4669         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4670         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4671                                  WRITE_DATA_DST_SEL(0)) |
4672                                  WR_CONFIRM);
4673         if (vm_id < 8) {
4674                 amdgpu_ring_write(ring,
4675                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4676         } else {
4677                 amdgpu_ring_write(ring,
4678                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4679         }
4680         amdgpu_ring_write(ring, 0);
4681         amdgpu_ring_write(ring, pd_addr >> 12);
4682
4683         /* bits 0-15 are the VM contexts0-15 */
4684         /* invalidate the cache */
4685         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4686         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4687                                  WRITE_DATA_DST_SEL(0)));
4688         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4689         amdgpu_ring_write(ring, 0);
4690         amdgpu_ring_write(ring, 1 << vm_id);
4691
4692         /* wait for the invalidate to complete */
4693         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4694         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4695                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
4696                                  WAIT_REG_MEM_ENGINE(0))); /* me */
4697         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4698         amdgpu_ring_write(ring, 0);
4699         amdgpu_ring_write(ring, 0); /* ref */
4700         amdgpu_ring_write(ring, 0); /* mask */
4701         amdgpu_ring_write(ring, 0x20); /* poll interval */
4702
4703         /* compute doesn't have PFP */
4704         if (usepfp) {
4705                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4706                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4707                 amdgpu_ring_write(ring, 0x0);
4708                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4709                 amdgpu_ring_write(ring, 0);
4710                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4711                 amdgpu_ring_write(ring, 0);
4712         }
4713 }
4714
4715 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4716 {
4717         return ring->adev->wb.wb[ring->rptr_offs];
4718 }
4719
4720 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4721 {
4722         return ring->adev->wb.wb[ring->wptr_offs];
4723 }
4724
4725 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4726 {
4727         struct amdgpu_device *adev = ring->adev;
4728
4729         /* XXX check if swapping is necessary on BE */
4730         adev->wb.wb[ring->wptr_offs] = ring->wptr;
4731         WDOORBELL32(ring->doorbell_index, ring->wptr);
4732 }
4733
4734 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4735                                              u64 addr, u64 seq,
4736                                              unsigned flags)
4737 {
4738         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4739         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4740
4741         /* RELEASE_MEM - flush caches, send int */
4742         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4743         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4744                                  EOP_TC_ACTION_EN |
4745                                  EOP_TC_WB_ACTION_EN |
4746                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4747                                  EVENT_INDEX(5)));
4748         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4749         amdgpu_ring_write(ring, addr & 0xfffffffc);
4750         amdgpu_ring_write(ring, upper_32_bits(addr));
4751         amdgpu_ring_write(ring, lower_32_bits(seq));
4752         amdgpu_ring_write(ring, upper_32_bits(seq));
4753 }
4754
4755 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4756                                                  enum amdgpu_interrupt_state state)
4757 {
4758         u32 cp_int_cntl;
4759
4760         switch (state) {
4761         case AMDGPU_IRQ_STATE_DISABLE:
4762                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4763                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4764                                             TIME_STAMP_INT_ENABLE, 0);
4765                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4766                 break;
4767         case AMDGPU_IRQ_STATE_ENABLE:
4768                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4769                 cp_int_cntl =
4770                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4771                                       TIME_STAMP_INT_ENABLE, 1);
4772                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4773                 break;
4774         default:
4775                 break;
4776         }
4777 }
4778
4779 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4780                                                      int me, int pipe,
4781                                                      enum amdgpu_interrupt_state state)
4782 {
4783         u32 mec_int_cntl, mec_int_cntl_reg;
4784
4785         /*
4786          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4787          * handles the setting of interrupts for this specific pipe. All other
4788          * pipes' interrupts are set by amdkfd.
4789          */
4790
4791         if (me == 1) {
4792                 switch (pipe) {
4793                 case 0:
4794                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4795                         break;
4796                 default:
4797                         DRM_DEBUG("invalid pipe %d\n", pipe);
4798                         return;
4799                 }
4800         } else {
4801                 DRM_DEBUG("invalid me %d\n", me);
4802                 return;
4803         }
4804
4805         switch (state) {
4806         case AMDGPU_IRQ_STATE_DISABLE:
4807                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4808                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4809                                              TIME_STAMP_INT_ENABLE, 0);
4810                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4811                 break;
4812         case AMDGPU_IRQ_STATE_ENABLE:
4813                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4814                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4815                                              TIME_STAMP_INT_ENABLE, 1);
4816                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4817                 break;
4818         default:
4819                 break;
4820         }
4821 }
4822
4823 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4824                                              struct amdgpu_irq_src *source,
4825                                              unsigned type,
4826                                              enum amdgpu_interrupt_state state)
4827 {
4828         u32 cp_int_cntl;
4829
4830         switch (state) {
4831         case AMDGPU_IRQ_STATE_DISABLE:
4832                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4833                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4834                                             PRIV_REG_INT_ENABLE, 0);
4835                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4836                 break;
4837         case AMDGPU_IRQ_STATE_ENABLE:
4838                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4839                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4840                                             PRIV_REG_INT_ENABLE, 0);
4841                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4842                 break;
4843         default:
4844                 break;
4845         }
4846
4847         return 0;
4848 }
4849
4850 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4851                                               struct amdgpu_irq_src *source,
4852                                               unsigned type,
4853                                               enum amdgpu_interrupt_state state)
4854 {
4855         u32 cp_int_cntl;
4856
4857         switch (state) {
4858         case AMDGPU_IRQ_STATE_DISABLE:
4859                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4860                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4861                                             PRIV_INSTR_INT_ENABLE, 0);
4862                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4863                 break;
4864         case AMDGPU_IRQ_STATE_ENABLE:
4865                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4866                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4867                                             PRIV_INSTR_INT_ENABLE, 1);
4868                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4869                 break;
4870         default:
4871                 break;
4872         }
4873
4874         return 0;
4875 }
4876
4877 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4878                                             struct amdgpu_irq_src *src,
4879                                             unsigned type,
4880                                             enum amdgpu_interrupt_state state)
4881 {
4882         switch (type) {
4883         case AMDGPU_CP_IRQ_GFX_EOP:
4884                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4885                 break;
4886         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4887                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4888                 break;
4889         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4890                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4891                 break;
4892         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4893                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4894                 break;
4895         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4896                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4897                 break;
4898         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4899                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4900                 break;
4901         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4902                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4903                 break;
4904         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4905                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4906                 break;
4907         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4908                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4909                 break;
4910         default:
4911                 break;
4912         }
4913         return 0;
4914 }
4915
4916 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4917                             struct amdgpu_irq_src *source,
4918                             struct amdgpu_iv_entry *entry)
4919 {
4920         int i;
4921         u8 me_id, pipe_id, queue_id;
4922         struct amdgpu_ring *ring;
4923
4924         DRM_DEBUG("IH: CP EOP\n");
4925         me_id = (entry->ring_id & 0x0c) >> 2;
4926         pipe_id = (entry->ring_id & 0x03) >> 0;
4927         queue_id = (entry->ring_id & 0x70) >> 4;
4928
4929         switch (me_id) {
4930         case 0:
4931                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4932                 break;
4933         case 1:
4934         case 2:
4935                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4936                         ring = &adev->gfx.compute_ring[i];
4937                         /* Per-queue interrupt is supported for MEC starting from VI.
4938                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4939                           */
4940                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4941                                 amdgpu_fence_process(ring);
4942                 }
4943                 break;
4944         }
4945         return 0;
4946 }
4947
4948 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4949                                  struct amdgpu_irq_src *source,
4950                                  struct amdgpu_iv_entry *entry)
4951 {
4952         DRM_ERROR("Illegal register access in command stream\n");
4953         schedule_work(&adev->reset_work);
4954         return 0;
4955 }
4956
4957 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4958                                   struct amdgpu_irq_src *source,
4959                                   struct amdgpu_iv_entry *entry)
4960 {
4961         DRM_ERROR("Illegal instruction in command stream\n");
4962         schedule_work(&adev->reset_work);
4963         return 0;
4964 }
4965
4966 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4967         .early_init = gfx_v8_0_early_init,
4968         .late_init = NULL,
4969         .sw_init = gfx_v8_0_sw_init,
4970         .sw_fini = gfx_v8_0_sw_fini,
4971         .hw_init = gfx_v8_0_hw_init,
4972         .hw_fini = gfx_v8_0_hw_fini,
4973         .suspend = gfx_v8_0_suspend,
4974         .resume = gfx_v8_0_resume,
4975         .is_idle = gfx_v8_0_is_idle,
4976         .wait_for_idle = gfx_v8_0_wait_for_idle,
4977         .soft_reset = gfx_v8_0_soft_reset,
4978         .print_status = gfx_v8_0_print_status,
4979         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4980         .set_powergating_state = gfx_v8_0_set_powergating_state,
4981 };
4982
4983 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4984         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4985         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4986         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4987         .parse_cs = NULL,
4988         .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4989         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4990         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4991         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4992         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4993         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4994         .test_ring = gfx_v8_0_ring_test_ring,
4995         .test_ib = gfx_v8_0_ring_test_ib,
4996         .insert_nop = amdgpu_ring_insert_nop,
4997 };
4998
4999 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
5000         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
5001         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
5002         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
5003         .parse_cs = NULL,
5004         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
5005         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
5006         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
5007         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
5008         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
5009         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
5010         .test_ring = gfx_v8_0_ring_test_ring,
5011         .test_ib = gfx_v8_0_ring_test_ib,
5012         .insert_nop = amdgpu_ring_insert_nop,
5013 };
5014
5015 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
5016 {
5017         int i;
5018
5019         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5020                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
5021
5022         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5023                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
5024 }
5025
5026 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
5027         .set = gfx_v8_0_set_eop_interrupt_state,
5028         .process = gfx_v8_0_eop_irq,
5029 };
5030
5031 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
5032         .set = gfx_v8_0_set_priv_reg_fault_state,
5033         .process = gfx_v8_0_priv_reg_irq,
5034 };
5035
5036 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
5037         .set = gfx_v8_0_set_priv_inst_fault_state,
5038         .process = gfx_v8_0_priv_inst_irq,
5039 };
5040
5041 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
5042 {
5043         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5044         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
5045
5046         adev->gfx.priv_reg_irq.num_types = 1;
5047         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
5048
5049         adev->gfx.priv_inst_irq.num_types = 1;
5050         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
5051 }
5052
5053 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
5054 {
5055         /* init asci gds info */
5056         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5057         adev->gds.gws.total_size = 64;
5058         adev->gds.oa.total_size = 16;
5059
5060         if (adev->gds.mem.total_size == 64 * 1024) {
5061                 adev->gds.mem.gfx_partition_size = 4096;
5062                 adev->gds.mem.cs_partition_size = 4096;
5063
5064                 adev->gds.gws.gfx_partition_size = 4;
5065                 adev->gds.gws.cs_partition_size = 4;
5066
5067                 adev->gds.oa.gfx_partition_size = 4;
5068                 adev->gds.oa.cs_partition_size = 1;
5069         } else {
5070                 adev->gds.mem.gfx_partition_size = 1024;
5071                 adev->gds.mem.cs_partition_size = 1024;
5072
5073                 adev->gds.gws.gfx_partition_size = 16;
5074                 adev->gds.gws.cs_partition_size = 16;
5075
5076                 adev->gds.oa.gfx_partition_size = 4;
5077                 adev->gds.oa.cs_partition_size = 4;
5078         }
5079 }
5080
5081 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
5082                 u32 se, u32 sh)
5083 {
5084         u32 mask = 0, tmp, tmp1;
5085         int i;
5086
5087         gfx_v8_0_select_se_sh(adev, se, sh);
5088         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
5089         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
5090         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5091
5092         tmp &= 0xffff0000;
5093
5094         tmp |= tmp1;
5095         tmp >>= 16;
5096
5097         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
5098                 mask <<= 1;
5099                 mask |= 1;
5100         }
5101
5102         return (~tmp) & mask;
5103 }
5104
5105 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
5106                                                  struct amdgpu_cu_info *cu_info)
5107 {
5108         int i, j, k, counter, active_cu_number = 0;
5109         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5110
5111         if (!adev || !cu_info)
5112                 return -EINVAL;
5113
5114         mutex_lock(&adev->grbm_idx_mutex);
5115         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5116                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5117                         mask = 1;
5118                         ao_bitmap = 0;
5119                         counter = 0;
5120                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
5121                         cu_info->bitmap[i][j] = bitmap;
5122
5123                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5124                                 if (bitmap & mask) {
5125                                         if (counter < 2)
5126                                                 ao_bitmap |= mask;
5127                                         counter ++;
5128                                 }
5129                                 mask <<= 1;
5130                         }
5131                         active_cu_number += counter;
5132                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5133                 }
5134         }
5135
5136         cu_info->number = active_cu_number;
5137         cu_info->ao_cu_mask = ao_cu_mask;
5138         mutex_unlock(&adev->grbm_idx_mutex);
5139         return 0;
5140 }