drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  42
  43 #define GFX9_NUM_GFX_RINGS     1
  44 #define GFX9_MEC_HPD_SIZE 2048
  45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  47
  48 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  54
  55 /*(DEBLOBBED)*/
  56
  57 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  58 {
  59         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
  60         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
  61         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
  62         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
  63         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
  64         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
  65         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
  76 };
  77
  78 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
  79 {
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
  98 };
  99
 100 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 101 {
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 113 };
 114
 115 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 116 {
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 138 };
 139
 140 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 141 {
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 149 };
 150
 151 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 152 {
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 155 };
 156
 157 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 158 {
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 175 };
 176
 177 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 178 {
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
 189 };
 190
 191 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 192 {
 193         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 194         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 195         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 196         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 197         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 198         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 199         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 200         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 201 };
 202
 203 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 204 {
 205         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 206         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 207         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 208         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 209         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 210         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 211         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 212         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 213 };
 214
 215 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 216 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 217 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 218
 219 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 220 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 221 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 222 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 223 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 224                                  struct amdgpu_cu_info *cu_info);
 225 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 226 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 227 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 228
 229 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 230 {
 231         switch (adev->asic_type) {
 232         case CHIP_VEGA10:
 233                 soc15_program_register_sequence(adev,
 234                                                  golden_settings_gc_9_0,
 235                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 236                 soc15_program_register_sequence(adev,
 237                                                  golden_settings_gc_9_0_vg10,
 238                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 239                 break;
 240         case CHIP_VEGA12:
 241                 soc15_program_register_sequence(adev,
 242                                                 golden_settings_gc_9_2_1,
 243                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 244                 soc15_program_register_sequence(adev,
 245                                                 golden_settings_gc_9_2_1_vg12,
 246                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 247                 break;
 248         case CHIP_VEGA20:
 249                 soc15_program_register_sequence(adev,
 250                                                 golden_settings_gc_9_0,
 251                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 252                 soc15_program_register_sequence(adev,
 253                                                 golden_settings_gc_9_0_vg20,
 254                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 255                 break;
 256         case CHIP_RAVEN:
 257                 soc15_program_register_sequence(adev,
 258                                                  golden_settings_gc_9_1,
 259                                                  ARRAY_SIZE(golden_settings_gc_9_1));
 260                 soc15_program_register_sequence(adev,
 261                                                  golden_settings_gc_9_1_rv1,
 262                                                  ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 263                 break;
 264         default:
 265                 break;
 266         }
 267
 268         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 269                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 270 }
 271
 272 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 273 {
 274         adev->gfx.scratch.num_reg = 8;
 275         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 276         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 277 }
 278
 279 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 280                                        bool wc, uint32_t reg, uint32_t val)
 281 {
 282         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 283         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 284                                 WRITE_DATA_DST_SEL(0) |
 285                                 (wc ? WR_CONFIRM : 0));
 286         amdgpu_ring_write(ring, reg);
 287         amdgpu_ring_write(ring, 0);
 288         amdgpu_ring_write(ring, val);
 289 }
 290
 291 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 292                                   int mem_space, int opt, uint32_t addr0,
 293                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 294                                   uint32_t inv)
 295 {
 296         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 297         amdgpu_ring_write(ring,
 298                                  /* memory (1) or register (0) */
 299                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 300                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 301                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 302                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 303
 304         if (mem_space)
 305                 BUG_ON(addr0 & 0x3); /* Dword align */
 306         amdgpu_ring_write(ring, addr0);
 307         amdgpu_ring_write(ring, addr1);
 308         amdgpu_ring_write(ring, ref);
 309         amdgpu_ring_write(ring, mask);
 310         amdgpu_ring_write(ring, inv); /* poll interval */
 311 }
 312
 313 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 314 {
 315         struct amdgpu_device *adev = ring->adev;
 316         uint32_t scratch;
 317         uint32_t tmp = 0;
 318         unsigned i;
 319         int r;
 320
 321         r = amdgpu_gfx_scratch_get(adev, &scratch);
 322         if (r) {
 323                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 324                 return r;
 325         }
 326         WREG32(scratch, 0xCAFEDEAD);
 327         r = amdgpu_ring_alloc(ring, 3);
 328         if (r) {
 329                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 330                           ring->idx, r);
 331                 amdgpu_gfx_scratch_free(adev, scratch);
 332                 return r;
 333         }
 334         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 335         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 336         amdgpu_ring_write(ring, 0xDEADBEEF);
 337         amdgpu_ring_commit(ring);
 338
 339         for (i = 0; i < adev->usec_timeout; i++) {
 340                 tmp = RREG32(scratch);
 341                 if (tmp == 0xDEADBEEF)
 342                         break;
 343                 DRM_UDELAY(1);
 344         }
 345         if (i < adev->usec_timeout) {
 346                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 347                          ring->idx, i);
 348         } else {
 349                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 350                           ring->idx, scratch, tmp);
 351                 r = -EINVAL;
 352         }
 353         amdgpu_gfx_scratch_free(adev, scratch);
 354         return r;
 355 }
 356
 357 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 358 {
 359         struct amdgpu_device *adev = ring->adev;
 360         struct amdgpu_ib ib;
 361         struct dma_fence *f = NULL;
 362
 363         unsigned index;
 364         uint64_t gpu_addr;
 365         uint32_t tmp;
 366         long r;
 367
 368         r = amdgpu_device_wb_get(adev, &index);
 369         if (r) {
 370                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 371                 return r;
 372         }
 373
 374         gpu_addr = adev->wb.gpu_addr + (index * 4);
 375         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 376         memset(&ib, 0, sizeof(ib));
 377         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 378         if (r) {
 379                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 380                 goto err1;
 381         }
 382         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 383         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 384         ib.ptr[2] = lower_32_bits(gpu_addr);
 385         ib.ptr[3] = upper_32_bits(gpu_addr);
 386         ib.ptr[4] = 0xDEADBEEF;
 387         ib.length_dw = 5;
 388
 389         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 390         if (r)
 391                 goto err2;
 392
 393         r = dma_fence_wait_timeout(f, false, timeout);
 394         if (r == 0) {
 395                         DRM_ERROR("amdgpu: IB test timed out.\n");
 396                         r = -ETIMEDOUT;
 397                         goto err2;
 398         } else if (r < 0) {
 399                         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 400                         goto err2;
 401         }
 402
 403         tmp = adev->wb.wb[index];
 404         if (tmp == 0xDEADBEEF) {
 405                         DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 406                         r = 0;
 407         } else {
 408                         DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 409                         r = -EINVAL;
 410         }
 411
 412 err2:
 413         amdgpu_ib_free(adev, &ib, NULL);
 414         dma_fence_put(f);
 415 err1:
 416         amdgpu_device_wb_free(adev, index);
 417         return r;
 418 }
 419
 420
 421 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 422 {
 423         release_firmware(adev->gfx.pfp_fw);
 424         adev->gfx.pfp_fw = NULL;
 425         release_firmware(adev->gfx.me_fw);
 426         adev->gfx.me_fw = NULL;
 427         release_firmware(adev->gfx.ce_fw);
 428         adev->gfx.ce_fw = NULL;
 429         release_firmware(adev->gfx.rlc_fw);
 430         adev->gfx.rlc_fw = NULL;
 431         release_firmware(adev->gfx.mec_fw);
 432         adev->gfx.mec_fw = NULL;
 433         release_firmware(adev->gfx.mec2_fw);
 434         adev->gfx.mec2_fw = NULL;
 435
 436         kfree(adev->gfx.rlc.register_list_format);
 437 }
 438
 439 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 440 {
 441         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 442
 443         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 444         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 445         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 446         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 447         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 448         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 449         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 450         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 451         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 452         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 453         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 454         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 455         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 456         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 457                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 458 }
 459
 460 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 461 {
 462         const char *chip_name;
 463         char fw_name[30];
 464         int err;
 465         struct amdgpu_firmware_info *info = NULL;
 466         const struct common_firmware_header *header = NULL;
 467         const struct gfx_firmware_header_v1_0 *cp_hdr;
 468         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 469         unsigned int *tmp = NULL;
 470         unsigned int i = 0;
 471         uint16_t version_major;
 472         uint16_t version_minor;
 473
 474         DRM_DEBUG("\n");
 475
 476         switch (adev->asic_type) {
 477         case CHIP_VEGA10:
 478                 chip_name = "vega10";
 479                 break;
 480         case CHIP_VEGA12:
 481                 chip_name = "vega12";
 482                 break;
 483         case CHIP_VEGA20:
 484                 chip_name = "vega20";
 485                 break;
 486         case CHIP_RAVEN:
 487                 chip_name = "raven";
 488                 break;
 489         default:
 490                 BUG();
 491         }
 492
 493         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 494         err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 495         if (err)
 496                 goto out;
 497         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 498         if (err)
 499                 goto out;
 500         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 501         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 502         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 503
 504         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 505         err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 506         if (err)
 507                 goto out;
 508         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 509         if (err)
 510                 goto out;
 511         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 512         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 513         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 514
 515         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 516         err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 517         if (err)
 518                 goto out;
 519         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 520         if (err)
 521                 goto out;
 522         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 523         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 524         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 525
 526         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 527         err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 528         if (err)
 529                 goto out;
 530         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 531         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 532
 533         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 534         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 535         if (version_major == 2 && version_minor == 1)
 536                 adev->gfx.rlc.is_rlc_v2_1 = true;
 537
 538         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 539         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 540         adev->gfx.rlc.save_and_restore_offset =
 541                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 542         adev->gfx.rlc.clear_state_descriptor_offset =
 543                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 544         adev->gfx.rlc.avail_scratch_ram_locations =
 545                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 546         adev->gfx.rlc.reg_restore_list_size =
 547                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 548         adev->gfx.rlc.reg_list_format_start =
 549                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 550         adev->gfx.rlc.reg_list_format_separate_start =
 551                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 552         adev->gfx.rlc.starting_offsets_start =
 553                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 554         adev->gfx.rlc.reg_list_format_size_bytes =
 555                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 556         adev->gfx.rlc.reg_list_size_bytes =
 557                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 558         adev->gfx.rlc.register_list_format =
 559                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 560                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 561         if (!adev->gfx.rlc.register_list_format) {
 562                 err = -ENOMEM;
 563                 goto out;
 564         }
 565
 566         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 567                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 568         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 569                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 570
 571         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 572
 573         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 574                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 575         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 576                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 577
 578         if (adev->gfx.rlc.is_rlc_v2_1)
 579                 gfx_v9_0_init_rlc_ext_microcode(adev);
 580
 581         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 582         err = reject_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 583         if (err)
 584                 goto out;
 585         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 586         if (err)
 587                 goto out;
 588         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 589         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 590         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 591
 592
 593         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 594         err = reject_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 595         if (!err) {
 596                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 597                 if (err)
 598                         goto out;
 599                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 600                 adev->gfx.mec2_fw->data;
 601                 adev->gfx.mec2_fw_version =
 602                 le32_to_cpu(cp_hdr->header.ucode_version);
 603                 adev->gfx.mec2_feature_version =
 604                 le32_to_cpu(cp_hdr->ucode_feature_version);
 605         } else {
 606                 err = 0;
 607                 adev->gfx.mec2_fw = NULL;
 608         }
 609
 610         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 611                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 612                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 613                 info->fw = adev->gfx.pfp_fw;
 614                 header = (const struct common_firmware_header *)info->fw->data;
 615                 adev->firmware.fw_size +=
 616                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 617
 618                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 619                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 620                 info->fw = adev->gfx.me_fw;
 621                 header = (const struct common_firmware_header *)info->fw->data;
 622                 adev->firmware.fw_size +=
 623                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 624
 625                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 626                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 627                 info->fw = adev->gfx.ce_fw;
 628                 header = (const struct common_firmware_header *)info->fw->data;
 629                 adev->firmware.fw_size +=
 630                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 631
 632                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 633                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 634                 info->fw = adev->gfx.rlc_fw;
 635                 header = (const struct common_firmware_header *)info->fw->data;
 636                 adev->firmware.fw_size +=
 637                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 638
 639                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 640                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 641                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 642                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 643                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 644                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 645                         info->fw = adev->gfx.rlc_fw;
 646                         adev->firmware.fw_size +=
 647                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 648
 649                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 650                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 651                         info->fw = adev->gfx.rlc_fw;
 652                         adev->firmware.fw_size +=
 653                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 654
 655                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 656                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 657                         info->fw = adev->gfx.rlc_fw;
 658                         adev->firmware.fw_size +=
 659                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 660                 }
 661
 662                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 663                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 664                 info->fw = adev->gfx.mec_fw;
 665                 header = (const struct common_firmware_header *)info->fw->data;
 666                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 667                 adev->firmware.fw_size +=
 668                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 669
 670                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 671                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 672                 info->fw = adev->gfx.mec_fw;
 673                 adev->firmware.fw_size +=
 674                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 675
 676                 if (adev->gfx.mec2_fw) {
 677                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 678                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 679                         info->fw = adev->gfx.mec2_fw;
 680                         header = (const struct common_firmware_header *)info->fw->data;
 681                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 682                         adev->firmware.fw_size +=
 683                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 684                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 685                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 686                         info->fw = adev->gfx.mec2_fw;
 687                         adev->firmware.fw_size +=
 688                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 689                 }
 690
 691         }
 692
 693 out:
 694         if (err) {
 695                 dev_err(adev->dev,
 696                         "gfx9: Failed to load firmware \"%s\"\n",
 697                         fw_name);
 698                 release_firmware(adev->gfx.pfp_fw);
 699                 adev->gfx.pfp_fw = NULL;
 700                 release_firmware(adev->gfx.me_fw);
 701                 adev->gfx.me_fw = NULL;
 702                 release_firmware(adev->gfx.ce_fw);
 703                 adev->gfx.ce_fw = NULL;
 704                 release_firmware(adev->gfx.rlc_fw);
 705                 adev->gfx.rlc_fw = NULL;
 706                 release_firmware(adev->gfx.mec_fw);
 707                 adev->gfx.mec_fw = NULL;
 708                 release_firmware(adev->gfx.mec2_fw);
 709                 adev->gfx.mec2_fw = NULL;
 710         }
 711         return err;
 712 }
 713
 714 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 715 {
 716         u32 count = 0;
 717         const struct cs_section_def *sect = NULL;
 718         const struct cs_extent_def *ext = NULL;
 719
 720         /* begin clear state */
 721         count += 2;
 722         /* context control state */
 723         count += 3;
 724
 725         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 726                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 727                         if (sect->id == SECT_CONTEXT)
 728                                 count += 2 + ext->reg_count;
 729                         else
 730                                 return 0;
 731                 }
 732         }
 733
 734         /* end clear state */
 735         count += 2;
 736         /* clear state */
 737         count += 2;
 738
 739         return count;
 740 }
 741
 742 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 743                                     volatile u32 *buffer)
 744 {
 745         u32 count = 0, i;
 746         const struct cs_section_def *sect = NULL;
 747         const struct cs_extent_def *ext = NULL;
 748
 749         if (adev->gfx.rlc.cs_data == NULL)
 750                 return;
 751         if (buffer == NULL)
 752                 return;
 753
 754         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 755         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 756
 757         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 758         buffer[count++] = cpu_to_le32(0x80000000);
 759         buffer[count++] = cpu_to_le32(0x80000000);
 760
 761         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 762                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 763                         if (sect->id == SECT_CONTEXT) {
 764                                 buffer[count++] =
 765                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 766                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 767                                                 PACKET3_SET_CONTEXT_REG_START);
 768                                 for (i = 0; i < ext->reg_count; i++)
 769                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 770                         } else {
 771                                 return;
 772                         }
 773                 }
 774         }
 775
 776         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 777         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 778
 779         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 780         buffer[count++] = cpu_to_le32(0);
 781 }
 782
 783 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 784 {
 785         uint32_t data;
 786
 787         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 788         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 789         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 790         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 791         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 792
 793         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 794         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 795
 796         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 797         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 798
 799         mutex_lock(&adev->grbm_idx_mutex);
 800         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 801         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 802         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 803
 804         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 805         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 806         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 807         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 808         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 809
 810         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 811         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 812         data &= 0x0000FFFF;
 813         data |= 0x00C00000;
 814         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 815
 816         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 817         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 818
 819         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 820          * but used for RLC_LB_CNTL configuration */
 821         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 822         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
 823         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
 824         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 825         mutex_unlock(&adev->grbm_idx_mutex);
 826 }
 827
 828 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 829 {
 830         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
 831 }
 832
 833 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 834 {
 835         const __le32 *fw_data;
 836         volatile u32 *dst_ptr;
 837         int me, i, max_me = 5;
 838         u32 bo_offset = 0;
 839         u32 table_offset, table_size;
 840
 841         /* write the cp table buffer */
 842         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 843         for (me = 0; me < max_me; me++) {
 844                 if (me == 0) {
 845                         const struct gfx_firmware_header_v1_0 *hdr =
 846                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 847                         fw_data = (const __le32 *)
 848                                 (adev->gfx.ce_fw->data +
 849                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 850                         table_offset = le32_to_cpu(hdr->jt_offset);
 851                         table_size = le32_to_cpu(hdr->jt_size);
 852                 } else if (me == 1) {
 853                         const struct gfx_firmware_header_v1_0 *hdr =
 854                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 855                         fw_data = (const __le32 *)
 856                                 (adev->gfx.pfp_fw->data +
 857                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 858                         table_offset = le32_to_cpu(hdr->jt_offset);
 859                         table_size = le32_to_cpu(hdr->jt_size);
 860                 } else if (me == 2) {
 861                         const struct gfx_firmware_header_v1_0 *hdr =
 862                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 863                         fw_data = (const __le32 *)
 864                                 (adev->gfx.me_fw->data +
 865                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 866                         table_offset = le32_to_cpu(hdr->jt_offset);
 867                         table_size = le32_to_cpu(hdr->jt_size);
 868                 } else if (me == 3) {
 869                         const struct gfx_firmware_header_v1_0 *hdr =
 870                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 871                         fw_data = (const __le32 *)
 872                                 (adev->gfx.mec_fw->data +
 873                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 874                         table_offset = le32_to_cpu(hdr->jt_offset);
 875                         table_size = le32_to_cpu(hdr->jt_size);
 876                 } else  if (me == 4) {
 877                         const struct gfx_firmware_header_v1_0 *hdr =
 878                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 879                         fw_data = (const __le32 *)
 880                                 (adev->gfx.mec2_fw->data +
 881                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 882                         table_offset = le32_to_cpu(hdr->jt_offset);
 883                         table_size = le32_to_cpu(hdr->jt_size);
 884                 }
 885
 886                 for (i = 0; i < table_size; i ++) {
 887                         dst_ptr[bo_offset + i] =
 888                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
 889                 }
 890
 891                 bo_offset += table_size;
 892         }
 893 }
 894
 895 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
 896 {
 897         /* clear state block */
 898         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 899                         &adev->gfx.rlc.clear_state_gpu_addr,
 900                         (void **)&adev->gfx.rlc.cs_ptr);
 901
 902         /* jump table block */
 903         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 904                         &adev->gfx.rlc.cp_table_gpu_addr,
 905                         (void **)&adev->gfx.rlc.cp_table_ptr);
 906 }
 907
 908 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 909 {
 910         volatile u32 *dst_ptr;
 911         u32 dws;
 912         const struct cs_section_def *cs_data;
 913         int r;
 914
 915         adev->gfx.rlc.cs_data = gfx9_cs_data;
 916
 917         cs_data = adev->gfx.rlc.cs_data;
 918
 919         if (cs_data) {
 920                 /* clear state block */
 921                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
 922                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
 923                                               AMDGPU_GEM_DOMAIN_VRAM,
 924                                               &adev->gfx.rlc.clear_state_obj,
 925                                               &adev->gfx.rlc.clear_state_gpu_addr,
 926                                               (void **)&adev->gfx.rlc.cs_ptr);
 927                 if (r) {
 928                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
 929                                 r);
 930                         gfx_v9_0_rlc_fini(adev);
 931                         return r;
 932                 }
 933                 /* set up the cs buffer */
 934                 dst_ptr = adev->gfx.rlc.cs_ptr;
 935                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 936                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
 937                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
 938                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 939         }
 940
 941         if (adev->asic_type == CHIP_RAVEN) {
 942                 /* TODO: double check the cp_table_size for RV */
 943                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 944                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
 945                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 946                                               &adev->gfx.rlc.cp_table_obj,
 947                                               &adev->gfx.rlc.cp_table_gpu_addr,
 948                                               (void **)&adev->gfx.rlc.cp_table_ptr);
 949                 if (r) {
 950                         dev_err(adev->dev,
 951                                 "(%d) failed to create cp table bo\n", r);
 952                         gfx_v9_0_rlc_fini(adev);
 953                         return r;
 954                 }
 955
 956                 rv_init_cp_jump_table(adev);
 957                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
 958                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
 959
 960                 gfx_v9_0_init_lbpw(adev);
 961         }
 962
 963         return 0;
 964 }
 965
 966 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
 967 {
 968         int r;
 969
 970         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
 971         if (unlikely(r != 0))
 972                 return r;
 973
 974         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
 975                         AMDGPU_GEM_DOMAIN_VRAM);
 976         if (!r)
 977                 adev->gfx.rlc.clear_state_gpu_addr =
 978                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
 979
 980         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 981
 982         return r;
 983 }
 984
 985 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
 986 {
 987         int r;
 988
 989         if (!adev->gfx.rlc.clear_state_obj)
 990                 return;
 991
 992         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
 993         if (likely(r == 0)) {
 994                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
 995                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 996         }
 997 }
 998
 999 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1000 {
1001         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1002         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1003 }
1004
1005 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1006 {
1007         int r;
1008         u32 *hpd;
1009         const __le32 *fw_data;
1010         unsigned fw_size;
1011         u32 *fw;
1012         size_t mec_hpd_size;
1013
1014         const struct gfx_firmware_header_v1_0 *mec_hdr;
1015
1016         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1017
1018         /* take ownership of the relevant compute queues */
1019         amdgpu_gfx_compute_queue_acquire(adev);
1020         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1021
1022         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1023                                       AMDGPU_GEM_DOMAIN_GTT,
1024                                       &adev->gfx.mec.hpd_eop_obj,
1025                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1026                                       (void **)&hpd);
1027         if (r) {
1028                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1029                 gfx_v9_0_mec_fini(adev);
1030                 return r;
1031         }
1032
1033         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1034
1035         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1036         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1037
1038         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1039
1040         fw_data = (const __le32 *)
1041                 (adev->gfx.mec_fw->data +
1042                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1043         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1044
1045         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1046                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1047                                       &adev->gfx.mec.mec_fw_obj,
1048                                       &adev->gfx.mec.mec_fw_gpu_addr,
1049                                       (void **)&fw);
1050         if (r) {
1051                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1052                 gfx_v9_0_mec_fini(adev);
1053                 return r;
1054         }
1055
1056         memcpy(fw, fw_data, fw_size);
1057
1058         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1059         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1060
1061         return 0;
1062 }
1063
1064 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1065 {
1066         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1067                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1068                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1069                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1070                 (SQ_IND_INDEX__FORCE_READ_MASK));
1071         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1072 }
1073
1074 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1075                            uint32_t wave, uint32_t thread,
1076                            uint32_t regno, uint32_t num, uint32_t *out)
1077 {
1078         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1079                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1080                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1081                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1082                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1083                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1084                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1085         while (num--)
1086                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1087 }
1088
1089 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1090 {
1091         /* type 1 wave data */
1092         dst[(*no_fields)++] = 1;
1093         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1094         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1095         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1096         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1097         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1098         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1099         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1100         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1101         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1102         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1103         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1104         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1105         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1106         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1107 }
1108
1109 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1110                                      uint32_t wave, uint32_t start,
1111                                      uint32_t size, uint32_t *dst)
1112 {
1113         wave_read_regs(
1114                 adev, simd, wave, 0,
1115                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1116 }
1117
1118 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1119                                      uint32_t wave, uint32_t thread,
1120                                      uint32_t start, uint32_t size,
1121                                      uint32_t *dst)
1122 {
1123         wave_read_regs(
1124                 adev, simd, wave, thread,
1125                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1126 }
1127
1128 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1129                                   u32 me, u32 pipe, u32 q)
1130 {
1131         soc15_grbm_select(adev, me, pipe, q, 0);
1132 }
1133
1134 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1135         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1136         .select_se_sh = &gfx_v9_0_select_se_sh,
1137         .read_wave_data = &gfx_v9_0_read_wave_data,
1138         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1139         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1140         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1141 };
1142
1143 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1144 {
1145         u32 gb_addr_config;
1146         int err;
1147
1148         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1149
1150         switch (adev->asic_type) {
1151         case CHIP_VEGA10:
1152                 adev->gfx.config.max_hw_contexts = 8;
1153                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1154                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1155                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1156                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1157                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1158                 break;
1159         case CHIP_VEGA12:
1160                 adev->gfx.config.max_hw_contexts = 8;
1161                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1162                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1163                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1164                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1165                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1166                 DRM_INFO("fix gfx.config for vega12\n");
1167                 break;
1168         case CHIP_VEGA20:
1169                 adev->gfx.config.max_hw_contexts = 8;
1170                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1171                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1172                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1173                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1174                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1175                 gb_addr_config &= ~0xf3e777ff;
1176                 gb_addr_config |= 0x22014042;
1177                 /* check vbios table if gpu info is not available */
1178                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1179                 if (err)
1180                         return err;
1181                 break;
1182         case CHIP_RAVEN:
1183                 adev->gfx.config.max_hw_contexts = 8;
1184                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1185                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1186                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1187                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1188                 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1189                 break;
1190         default:
1191                 BUG();
1192                 break;
1193         }
1194
1195         adev->gfx.config.gb_addr_config = gb_addr_config;
1196
1197         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1198                         REG_GET_FIELD(
1199                                         adev->gfx.config.gb_addr_config,
1200                                         GB_ADDR_CONFIG,
1201                                         NUM_PIPES);
1202
1203         adev->gfx.config.max_tile_pipes =
1204                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1205
1206         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1207                         REG_GET_FIELD(
1208                                         adev->gfx.config.gb_addr_config,
1209                                         GB_ADDR_CONFIG,
1210                                         NUM_BANKS);
1211         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1212                         REG_GET_FIELD(
1213                                         adev->gfx.config.gb_addr_config,
1214                                         GB_ADDR_CONFIG,
1215                                         MAX_COMPRESSED_FRAGS);
1216         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1217                         REG_GET_FIELD(
1218                                         adev->gfx.config.gb_addr_config,
1219                                         GB_ADDR_CONFIG,
1220                                         NUM_RB_PER_SE);
1221         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1222                         REG_GET_FIELD(
1223                                         adev->gfx.config.gb_addr_config,
1224                                         GB_ADDR_CONFIG,
1225                                         NUM_SHADER_ENGINES);
1226         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1227                         REG_GET_FIELD(
1228                                         adev->gfx.config.gb_addr_config,
1229                                         GB_ADDR_CONFIG,
1230                                         PIPE_INTERLEAVE_SIZE));
1231
1232         return 0;
1233 }
1234
1235 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1236                                    struct amdgpu_ngg_buf *ngg_buf,
1237                                    int size_se,
1238                                    int default_size_se)
1239 {
1240         int r;
1241
1242         if (size_se < 0) {
1243                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1244                 return -EINVAL;
1245         }
1246         size_se = size_se ? size_se : default_size_se;
1247
1248         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1249         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1250                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1251                                     &ngg_buf->bo,
1252                                     &ngg_buf->gpu_addr,
1253                                     NULL);
1254         if (r) {
1255                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1256                 return r;
1257         }
1258         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1259
1260         return r;
1261 }
1262
1263 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1264 {
1265         int i;
1266
1267         for (i = 0; i < NGG_BUF_MAX; i++)
1268                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1269                                       &adev->gfx.ngg.buf[i].gpu_addr,
1270                                       NULL);
1271
1272         memset(&adev->gfx.ngg.buf[0], 0,
1273                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1274
1275         adev->gfx.ngg.init = false;
1276
1277         return 0;
1278 }
1279
1280 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1281 {
1282         int r;
1283
1284         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1285                 return 0;
1286
1287         /* GDS reserve memory: 64 bytes alignment */
1288         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1289         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1290         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1291         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1292         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1293
1294         /* Primitive Buffer */
1295         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1296                                     amdgpu_prim_buf_per_se,
1297                                     64 * 1024);
1298         if (r) {
1299                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1300                 goto err;
1301         }
1302
1303         /* Position Buffer */
1304         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1305                                     amdgpu_pos_buf_per_se,
1306                                     256 * 1024);
1307         if (r) {
1308                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1309                 goto err;
1310         }
1311
1312         /* Control Sideband */
1313         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1314                                     amdgpu_cntl_sb_buf_per_se,
1315                                     256);
1316         if (r) {
1317                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1318                 goto err;
1319         }
1320
1321         /* Parameter Cache, not created by default */
1322         if (amdgpu_param_buf_per_se <= 0)
1323                 goto out;
1324
1325         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1326                                     amdgpu_param_buf_per_se,
1327                                     512 * 1024);
1328         if (r) {
1329                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1330                 goto err;
1331         }
1332
1333 out:
1334         adev->gfx.ngg.init = true;
1335         return 0;
1336 err:
1337         gfx_v9_0_ngg_fini(adev);
1338         return r;
1339 }
1340
1341 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1342 {
1343         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1344         int r;
1345         u32 data, base;
1346
1347         if (!amdgpu_ngg)
1348                 return 0;
1349
1350         /* Program buffer size */
1351         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1352                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1353         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1354                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1355         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1356
1357         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1358                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1359         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1360                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1361         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1362
1363         /* Program buffer base address */
1364         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1365         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1366         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1367
1368         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1369         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1370         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1371
1372         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1373         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1374         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1375
1376         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1377         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1378         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1379
1380         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1381         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1382         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1383
1384         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1385         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1386         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1387
1388         /* Clear GDS reserved memory */
1389         r = amdgpu_ring_alloc(ring, 17);
1390         if (r) {
1391                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1392                           ring->idx, r);
1393                 return r;
1394         }
1395
1396         gfx_v9_0_write_data_to_reg(ring, 0, false,
1397                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1398                                    (adev->gds.mem.total_size +
1399                                     adev->gfx.ngg.gds_reserve_size) >>
1400                                    AMDGPU_GDS_SHIFT);
1401
1402         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1403         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1404                                 PACKET3_DMA_DATA_DST_SEL(1) |
1405                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1406         amdgpu_ring_write(ring, 0);
1407         amdgpu_ring_write(ring, 0);
1408         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1409         amdgpu_ring_write(ring, 0);
1410         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1411                                 adev->gfx.ngg.gds_reserve_size);
1412
1413         gfx_v9_0_write_data_to_reg(ring, 0, false,
1414                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1415
1416         amdgpu_ring_commit(ring);
1417
1418         return 0;
1419 }
1420
1421 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1422                                       int mec, int pipe, int queue)
1423 {
1424         int r;
1425         unsigned irq_type;
1426         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1427
1428         ring = &adev->gfx.compute_ring[ring_id];
1429
1430         /* mec0 is me1 */
1431         ring->me = mec + 1;
1432         ring->pipe = pipe;
1433         ring->queue = queue;
1434
1435         ring->ring_obj = NULL;
1436         ring->use_doorbell = true;
1437         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1438         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1439                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1440         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1441
1442         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1443                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1444                 + ring->pipe;
1445
1446         /* type-2 packets are deprecated on MEC, use type-3 instead */
1447         r = amdgpu_ring_init(adev, ring, 1024,
1448                              &adev->gfx.eop_irq, irq_type);
1449         if (r)
1450                 return r;
1451
1452
1453         return 0;
1454 }
1455
1456 static int gfx_v9_0_sw_init(void *handle)
1457 {
1458         int i, j, k, r, ring_id;
1459         struct amdgpu_ring *ring;
1460         struct amdgpu_kiq *kiq;
1461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462
1463         switch (adev->asic_type) {
1464         case CHIP_VEGA10:
1465         case CHIP_VEGA12:
1466         case CHIP_VEGA20:
1467         case CHIP_RAVEN:
1468                 adev->gfx.mec.num_mec = 2;
1469                 break;
1470         default:
1471                 adev->gfx.mec.num_mec = 1;
1472                 break;
1473         }
1474
1475         adev->gfx.mec.num_pipe_per_mec = 4;
1476         adev->gfx.mec.num_queue_per_pipe = 8;
1477
1478         /* KIQ event */
1479         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT, &adev->gfx.kiq.irq);
1480         if (r)
1481                 return r;
1482
1483         /* EOP Event */
1484         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
1485         if (r)
1486                 return r;
1487
1488         /* Privileged reg */
1489         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
1490                               &adev->gfx.priv_reg_irq);
1491         if (r)
1492                 return r;
1493
1494         /* Privileged inst */
1495         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
1496                               &adev->gfx.priv_inst_irq);
1497         if (r)
1498                 return r;
1499
1500         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1501
1502         gfx_v9_0_scratch_init(adev);
1503
1504         r = gfx_v9_0_init_microcode(adev);
1505         if (r) {
1506                 DRM_ERROR("Failed to load gfx firmware!\n");
1507                 return r;
1508         }
1509
1510         r = gfx_v9_0_rlc_init(adev);
1511         if (r) {
1512                 DRM_ERROR("Failed to init rlc BOs!\n");
1513                 return r;
1514         }
1515
1516         r = gfx_v9_0_mec_init(adev);
1517         if (r) {
1518                 DRM_ERROR("Failed to init MEC BOs!\n");
1519                 return r;
1520         }
1521
1522         /* set up the gfx ring */
1523         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1524                 ring = &adev->gfx.gfx_ring[i];
1525                 ring->ring_obj = NULL;
1526                 if (!i)
1527                         sprintf(ring->name, "gfx");
1528                 else
1529                         sprintf(ring->name, "gfx_%d", i);
1530                 ring->use_doorbell = true;
1531                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1532                 r = amdgpu_ring_init(adev, ring, 1024,
1533                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1534                 if (r)
1535                         return r;
1536         }
1537
1538         /* set up the compute queues - allocate horizontally across pipes */
1539         ring_id = 0;
1540         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1541                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1542                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1543                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1544                                         continue;
1545
1546                                 r = gfx_v9_0_compute_ring_init(adev,
1547                                                                ring_id,
1548                                                                i, k, j);
1549                                 if (r)
1550                                         return r;
1551
1552                                 ring_id++;
1553                         }
1554                 }
1555         }
1556
1557         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1558         if (r) {
1559                 DRM_ERROR("Failed to init KIQ BOs!\n");
1560                 return r;
1561         }
1562
1563         kiq = &adev->gfx.kiq;
1564         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1565         if (r)
1566                 return r;
1567
1568         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1569         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1570         if (r)
1571                 return r;
1572
1573         /* reserve GDS, GWS and OA resource for gfx */
1574         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1575                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1576                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1577         if (r)
1578                 return r;
1579
1580         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1581                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1582                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1583         if (r)
1584                 return r;
1585
1586         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1587                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1588                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1589         if (r)
1590                 return r;
1591
1592         adev->gfx.ce_ram_size = 0x8000;
1593
1594         r = gfx_v9_0_gpu_early_init(adev);
1595         if (r)
1596                 return r;
1597
1598         r = gfx_v9_0_ngg_init(adev);
1599         if (r)
1600                 return r;
1601
1602         return 0;
1603 }
1604
1605
1606 static int gfx_v9_0_sw_fini(void *handle)
1607 {
1608         int i;
1609         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1610
1611         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1612         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1613         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1614
1615         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1616                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1617         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1618                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1619
1620         amdgpu_gfx_compute_mqd_sw_fini(adev);
1621         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1622         amdgpu_gfx_kiq_fini(adev);
1623
1624         gfx_v9_0_mec_fini(adev);
1625         gfx_v9_0_ngg_fini(adev);
1626         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1627                                 &adev->gfx.rlc.clear_state_gpu_addr,
1628                                 (void **)&adev->gfx.rlc.cs_ptr);
1629         if (adev->asic_type == CHIP_RAVEN) {
1630                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1631                                 &adev->gfx.rlc.cp_table_gpu_addr,
1632                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1633         }
1634         gfx_v9_0_free_microcode(adev);
1635
1636         return 0;
1637 }
1638
1639
1640 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1641 {
1642         /* TODO */
1643 }
1644
1645 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1646 {
1647         u32 data;
1648
1649         if (instance == 0xffffffff)
1650                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1651         else
1652                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1653
1654         if (se_num == 0xffffffff)
1655                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1656         else
1657                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1658
1659         if (sh_num == 0xffffffff)
1660                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1661         else
1662                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1663
1664         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1665 }
1666
1667 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1668 {
1669         u32 data, mask;
1670
1671         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1672         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1673
1674         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1675         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1676
1677         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1678                                          adev->gfx.config.max_sh_per_se);
1679
1680         return (~data) & mask;
1681 }
1682
1683 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1684 {
1685         int i, j;
1686         u32 data;
1687         u32 active_rbs = 0;
1688         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1689                                         adev->gfx.config.max_sh_per_se;
1690
1691         mutex_lock(&adev->grbm_idx_mutex);
1692         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1693                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1694                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1695                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1696                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1697                                                rb_bitmap_width_per_sh);
1698                 }
1699         }
1700         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1701         mutex_unlock(&adev->grbm_idx_mutex);
1702
1703         adev->gfx.config.backend_enable_mask = active_rbs;
1704         adev->gfx.config.num_rbs = hweight32(active_rbs);
1705 }
1706
1707 #define DEFAULT_SH_MEM_BASES    (0x6000)
1708 #define FIRST_COMPUTE_VMID      (8)
1709 #define LAST_COMPUTE_VMID       (16)
1710 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1711 {
1712         int i;
1713         uint32_t sh_mem_config;
1714         uint32_t sh_mem_bases;
1715
1716         /*
1717          * Configure apertures:
1718          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1719          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1720          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1721          */
1722         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1723
1724         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1725                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1726                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1727
1728         mutex_lock(&adev->srbm_mutex);
1729         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1730                 soc15_grbm_select(adev, 0, 0, 0, i);
1731                 /* CP and shaders */
1732                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1733                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1734         }
1735         soc15_grbm_select(adev, 0, 0, 0, 0);
1736         mutex_unlock(&adev->srbm_mutex);
1737 }
1738
1739 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1740 {
1741         u32 tmp;
1742         int i;
1743
1744         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1745
1746         gfx_v9_0_tiling_mode_table_init(adev);
1747
1748         if (adev->gfx.num_gfx_rings)
1749                 gfx_v9_0_setup_rb(adev);
1750         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1751         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1752
1753         /* XXX SH_MEM regs */
1754         /* where to put LDS, scratch, GPUVM in FSA64 space */
1755         mutex_lock(&adev->srbm_mutex);
1756         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1757                 soc15_grbm_select(adev, 0, 0, 0, i);
1758                 /* CP and shaders */
1759                 if (i == 0) {
1760                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1761                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1762                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1763                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1764                 } else {
1765                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1766                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1767                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1768                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1769                                 (adev->gmc.private_aperture_start >> 48));
1770                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1771                                 (adev->gmc.shared_aperture_start >> 48));
1772                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1773                 }
1774         }
1775         soc15_grbm_select(adev, 0, 0, 0, 0);
1776
1777         mutex_unlock(&adev->srbm_mutex);
1778
1779         gfx_v9_0_init_compute_vmid(adev);
1780 }
1781
1782 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1783 {
1784         u32 i, j, k;
1785         u32 mask;
1786
1787         mutex_lock(&adev->grbm_idx_mutex);
1788         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1789                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1790                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1791                         for (k = 0; k < adev->usec_timeout; k++) {
1792                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1793                                         break;
1794                                 udelay(1);
1795                         }
1796                         if (k == adev->usec_timeout) {
1797                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1798                                                       0xffffffff, 0xffffffff);
1799                                 mutex_unlock(&adev->grbm_idx_mutex);
1800                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1801                                          i, j);
1802                                 return;
1803                         }
1804                 }
1805         }
1806         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1807         mutex_unlock(&adev->grbm_idx_mutex);
1808
1809         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1810                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1811                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1812                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1813         for (k = 0; k < adev->usec_timeout; k++) {
1814                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1815                         break;
1816                 udelay(1);
1817         }
1818 }
1819
1820 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1821                                                bool enable)
1822 {
1823         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1824
1825         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1826         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1827         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1828         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1829
1830         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1831 }
1832
1833 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1834 {
1835         /* csib */
1836         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1837                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1838         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1839                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1840         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1841                         adev->gfx.rlc.clear_state_size);
1842 }
1843
1844 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1845                                 int indirect_offset,
1846                                 int list_size,
1847                                 int *unique_indirect_regs,
1848                                 int unique_indirect_reg_count,
1849                                 int *indirect_start_offsets,
1850                                 int *indirect_start_offsets_count,
1851                                 int max_start_offsets_count)
1852 {
1853         int idx;
1854
1855         for (; indirect_offset < list_size; indirect_offset++) {
1856                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
1857                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1858                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1859
1860                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1861                         indirect_offset += 2;
1862
1863                         /* look for the matching indice */
1864                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
1865                                 if (unique_indirect_regs[idx] ==
1866                                         register_list_format[indirect_offset] ||
1867                                         !unique_indirect_regs[idx])
1868                                         break;
1869                         }
1870
1871                         BUG_ON(idx >= unique_indirect_reg_count);
1872
1873                         if (!unique_indirect_regs[idx])
1874                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
1875
1876                         indirect_offset++;
1877                 }
1878         }
1879 }
1880
1881 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
1882 {
1883         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1884         int unique_indirect_reg_count = 0;
1885
1886         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1887         int indirect_start_offsets_count = 0;
1888
1889         int list_size = 0;
1890         int i = 0, j = 0;
1891         u32 tmp = 0;
1892
1893         u32 *register_list_format =
1894                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1895         if (!register_list_format)
1896                 return -ENOMEM;
1897         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1898                 adev->gfx.rlc.reg_list_format_size_bytes);
1899
1900         /* setup unique_indirect_regs array and indirect_start_offsets array */
1901         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
1902         gfx_v9_1_parse_ind_reg_list(register_list_format,
1903                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
1904                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1905                                     unique_indirect_regs,
1906                                     unique_indirect_reg_count,
1907                                     indirect_start_offsets,
1908                                     &indirect_start_offsets_count,
1909                                     ARRAY_SIZE(indirect_start_offsets));
1910
1911         /* enable auto inc in case it is disabled */
1912         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1913         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1914         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1915
1916         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1917         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1918                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1919         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1920                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1921                         adev->gfx.rlc.register_restore[i]);
1922
1923         /* load indirect register */
1924         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1925                 adev->gfx.rlc.reg_list_format_start);
1926
1927         /* direct register portion */
1928         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
1929                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1930                         register_list_format[i]);
1931
1932         /* indirect register portion */
1933         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
1934                 if (register_list_format[i] == 0xFFFFFFFF) {
1935                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1936                         continue;
1937                 }
1938
1939                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1940                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1941
1942                 for (j = 0; j < unique_indirect_reg_count; j++) {
1943                         if (register_list_format[i] == unique_indirect_regs[j]) {
1944                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
1945                                 break;
1946                         }
1947                 }
1948
1949                 BUG_ON(j >= unique_indirect_reg_count);
1950
1951                 i++;
1952         }
1953
1954         /* set save/restore list size */
1955         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1956         list_size = list_size >> 1;
1957         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1958                 adev->gfx.rlc.reg_restore_list_size);
1959         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1960
1961         /* write the starting offsets to RLC scratch ram */
1962         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1963                 adev->gfx.rlc.starting_offsets_start);
1964         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
1965                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1966                        indirect_start_offsets[i]);
1967
1968         /* load unique indirect regs*/
1969         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
1970                 if (unique_indirect_regs[i] != 0) {
1971                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
1972                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
1973                                unique_indirect_regs[i] & 0x3FFFF);
1974
1975                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
1976                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
1977                                unique_indirect_regs[i] >> 20);
1978                 }
1979         }
1980
1981         kfree(register_list_format);
1982         return 0;
1983 }
1984
1985 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1986 {
1987         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
1988 }
1989
1990 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1991                                              bool enable)
1992 {
1993         uint32_t data = 0;
1994         uint32_t default_data = 0;
1995
1996         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1997         if (enable == true) {
1998                 /* enable GFXIP control over CGPG */
1999                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2000                 if(default_data != data)
2001                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2002
2003                 /* update status */
2004                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2005                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2006                 if(default_data != data)
2007                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2008         } else {
2009                 /* restore GFXIP control over GCPG */
2010                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2011                 if(default_data != data)
2012                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2013         }
2014 }
2015
2016 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2017 {
2018         uint32_t data = 0;
2019
2020         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2021                               AMD_PG_SUPPORT_GFX_SMG |
2022                               AMD_PG_SUPPORT_GFX_DMG)) {
2023                 /* init IDLE_POLL_COUNT = 60 */
2024                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2025                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2026                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2027                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2028
2029                 /* init RLC PG Delay */
2030                 data = 0;
2031                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2032                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2033                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2034                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2035                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2036
2037                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2038                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2039                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2040                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2041
2042                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2043                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2044                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2045                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2046
2047                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2048                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2049
2050                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2051                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2052                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2053
2054                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2055         }
2056 }
2057
2058 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2059                                                 bool enable)
2060 {
2061         uint32_t data = 0;
2062         uint32_t default_data = 0;
2063
2064         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2065         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2066                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2067                              enable ? 1 : 0);
2068         if (default_data != data)
2069                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2070 }
2071
2072 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2073                                                 bool enable)
2074 {
2075         uint32_t data = 0;
2076         uint32_t default_data = 0;
2077
2078         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2079         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2080                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2081                              enable ? 1 : 0);
2082         if(default_data != data)
2083                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2084 }
2085
2086 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2087                                         bool enable)
2088 {
2089         uint32_t data = 0;
2090         uint32_t default_data = 0;
2091
2092         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2093         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2094                              CP_PG_DISABLE,
2095                              enable ? 0 : 1);
2096         if(default_data != data)
2097                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2098 }
2099
2100 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2101                                                 bool enable)
2102 {
2103         uint32_t data, default_data;
2104
2105         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2106         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2107                              GFX_POWER_GATING_ENABLE,
2108                              enable ? 1 : 0);
2109         if(default_data != data)
2110                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2111 }
2112
2113 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2114                                                 bool enable)
2115 {
2116         uint32_t data, default_data;
2117
2118         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2119         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2120                              GFX_PIPELINE_PG_ENABLE,
2121                              enable ? 1 : 0);
2122         if(default_data != data)
2123                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2124
2125         if (!enable)
2126                 /* read any GFX register to wake up GFX */
2127                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2128 }
2129
2130 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2131                                                        bool enable)
2132 {
2133         uint32_t data, default_data;
2134
2135         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2136         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2137                              STATIC_PER_CU_PG_ENABLE,
2138                              enable ? 1 : 0);
2139         if(default_data != data)
2140                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2141 }
2142
2143 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2144                                                 bool enable)
2145 {
2146         uint32_t data, default_data;
2147
2148         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2149         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2150                              DYN_PER_CU_PG_ENABLE,
2151                              enable ? 1 : 0);
2152         if(default_data != data)
2153                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2154 }
2155
2156 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2157 {
2158         gfx_v9_0_init_csb(adev);
2159
2160         /*
2161          * Rlc save restore list is workable since v2_1.
2162          * And it's needed by gfxoff feature.
2163          */
2164         if (adev->gfx.rlc.is_rlc_v2_1) {
2165                 if (adev->asic_type == CHIP_VEGA12)
2166                         gfx_v9_1_init_rlc_save_restore_list(adev);
2167                 gfx_v9_0_enable_save_restore_machine(adev);
2168         }
2169
2170         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2171                               AMD_PG_SUPPORT_GFX_SMG |
2172                               AMD_PG_SUPPORT_GFX_DMG |
2173                               AMD_PG_SUPPORT_CP |
2174                               AMD_PG_SUPPORT_GDS |
2175                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2176                 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE,
2177                              adev->gfx.rlc.cp_table_gpu_addr >> 8);
2178                 gfx_v9_0_init_gfx_power_gating(adev);
2179         }
2180 }
2181
2182 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2183 {
2184         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2185         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2186         gfx_v9_0_wait_for_rlc_serdes(adev);
2187 }
2188
2189 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2190 {
2191         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2192         udelay(50);
2193         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2194         udelay(50);
2195 }
2196
2197 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2198 {
2199 #ifdef AMDGPU_RLC_DEBUG_RETRY
2200         u32 rlc_ucode_ver;
2201 #endif
2202
2203         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2204         udelay(50);
2205
2206         /* carrizo do enable cp interrupt after cp inited */
2207         if (!(adev->flags & AMD_IS_APU)) {
2208                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2209                 udelay(50);
2210         }
2211
2212 #ifdef AMDGPU_RLC_DEBUG_RETRY
2213         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2214         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2215         if(rlc_ucode_ver == 0x108) {
2216                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2217                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2218                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2219                  * default is 0x9C4 to create a 100us interval */
2220                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2221                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2222                  * to disable the page fault retry interrupts, default is
2223                  * 0x100 (256) */
2224                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2225         }
2226 #endif
2227 }
2228
2229 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2230 {
2231         const struct rlc_firmware_header_v2_0 *hdr;
2232         const __le32 *fw_data;
2233         unsigned i, fw_size;
2234
2235         if (!adev->gfx.rlc_fw)
2236                 return -EINVAL;
2237
2238         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2239         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2240
2241         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2242                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2243         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2244
2245         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2246                         RLCG_UCODE_LOADING_START_ADDRESS);
2247         for (i = 0; i < fw_size; i++)
2248                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2249         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2250
2251         return 0;
2252 }
2253
2254 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2255 {
2256         int r;
2257
2258         if (amdgpu_sriov_vf(adev)) {
2259                 gfx_v9_0_init_csb(adev);
2260                 return 0;
2261         }
2262
2263         gfx_v9_0_rlc_stop(adev);
2264
2265         /* disable CG */
2266         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2267
2268         gfx_v9_0_rlc_reset(adev);
2269
2270         gfx_v9_0_init_pg(adev);
2271
2272         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2273                 /* legacy rlc firmware loading */
2274                 r = gfx_v9_0_rlc_load_microcode(adev);
2275                 if (r)
2276                         return r;
2277         }
2278
2279         if (adev->asic_type == CHIP_RAVEN) {
2280                 if (amdgpu_lbpw != 0)
2281                         gfx_v9_0_enable_lbpw(adev, true);
2282                 else
2283                         gfx_v9_0_enable_lbpw(adev, false);
2284         }
2285
2286         gfx_v9_0_rlc_start(adev);
2287
2288         return 0;
2289 }
2290
2291 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2292 {
2293         int i;
2294         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2295
2296         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2297         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2298         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2299         if (!enable) {
2300                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2301                         adev->gfx.gfx_ring[i].ready = false;
2302         }
2303         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2304         udelay(50);
2305 }
2306
2307 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2308 {
2309         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2310         const struct gfx_firmware_header_v1_0 *ce_hdr;
2311         const struct gfx_firmware_header_v1_0 *me_hdr;
2312         const __le32 *fw_data;
2313         unsigned i, fw_size;
2314
2315         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2316                 return -EINVAL;
2317
2318         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2319                 adev->gfx.pfp_fw->data;
2320         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2321                 adev->gfx.ce_fw->data;
2322         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2323                 adev->gfx.me_fw->data;
2324
2325         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2326         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2327         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2328
2329         gfx_v9_0_cp_gfx_enable(adev, false);
2330
2331         /* PFP */
2332         fw_data = (const __le32 *)
2333                 (adev->gfx.pfp_fw->data +
2334                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2335         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2336         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2337         for (i = 0; i < fw_size; i++)
2338                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2339         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2340
2341         /* CE */
2342         fw_data = (const __le32 *)
2343                 (adev->gfx.ce_fw->data +
2344                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2345         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2346         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2347         for (i = 0; i < fw_size; i++)
2348                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2349         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2350
2351         /* ME */
2352         fw_data = (const __le32 *)
2353                 (adev->gfx.me_fw->data +
2354                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2355         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2356         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2357         for (i = 0; i < fw_size; i++)
2358                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2359         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2360
2361         return 0;
2362 }
2363
2364 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2365 {
2366         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2367         const struct cs_section_def *sect = NULL;
2368         const struct cs_extent_def *ext = NULL;
2369         int r, i, tmp;
2370
2371         /* init the CP */
2372         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2373         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2374
2375         gfx_v9_0_cp_gfx_enable(adev, true);
2376
2377         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2378         if (r) {
2379                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2380                 return r;
2381         }
2382
2383         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2384         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2385
2386         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2387         amdgpu_ring_write(ring, 0x80000000);
2388         amdgpu_ring_write(ring, 0x80000000);
2389
2390         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2391                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2392                         if (sect->id == SECT_CONTEXT) {
2393                                 amdgpu_ring_write(ring,
2394                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2395                                                ext->reg_count));
2396                                 amdgpu_ring_write(ring,
2397                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2398                                 for (i = 0; i < ext->reg_count; i++)
2399                                         amdgpu_ring_write(ring, ext->extent[i]);
2400                         }
2401                 }
2402         }
2403
2404         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2405         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2406
2407         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2408         amdgpu_ring_write(ring, 0);
2409
2410         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2411         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2412         amdgpu_ring_write(ring, 0x8000);
2413         amdgpu_ring_write(ring, 0x8000);
2414
2415         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2416         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2417                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2418         amdgpu_ring_write(ring, tmp);
2419         amdgpu_ring_write(ring, 0);
2420
2421         amdgpu_ring_commit(ring);
2422
2423         return 0;
2424 }
2425
2426 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2427 {
2428         struct amdgpu_ring *ring;
2429         u32 tmp;
2430         u32 rb_bufsz;
2431         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2432
2433         /* Set the write pointer delay */
2434         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2435
2436         /* set the RB to use vmid 0 */
2437         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2438
2439         /* Set ring buffer size */
2440         ring = &adev->gfx.gfx_ring[0];
2441         rb_bufsz = order_base_2(ring->ring_size / 8);
2442         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2443         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2444 #ifdef __BIG_ENDIAN
2445         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2446 #endif
2447         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2448
2449         /* Initialize the ring buffer's write pointers */
2450         ring->wptr = 0;
2451         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2452         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2453
2454         /* set the wb address wether it's enabled or not */
2455         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2456         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2457         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2458
2459         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2460         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2461         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2462
2463         mdelay(1);
2464         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2465
2466         rb_addr = ring->gpu_addr >> 8;
2467         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2468         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2469
2470         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2471         if (ring->use_doorbell) {
2472                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2473                                     DOORBELL_OFFSET, ring->doorbell_index);
2474                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2475                                     DOORBELL_EN, 1);
2476         } else {
2477                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2478         }
2479         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2480
2481         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2482                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2483         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2484
2485         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2486                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2487
2488
2489         /* start the ring */
2490         gfx_v9_0_cp_gfx_start(adev);
2491         ring->ready = true;
2492
2493         return 0;
2494 }
2495
2496 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2497 {
2498         int i;
2499
2500         if (enable) {
2501                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2502         } else {
2503                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2504                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2505                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2506                         adev->gfx.compute_ring[i].ready = false;
2507                 adev->gfx.kiq.ring.ready = false;
2508         }
2509         udelay(50);
2510 }
2511
2512 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2513 {
2514         const struct gfx_firmware_header_v1_0 *mec_hdr;
2515         const __le32 *fw_data;
2516         unsigned i;
2517         u32 tmp;
2518
2519         if (!adev->gfx.mec_fw)
2520                 return -EINVAL;
2521
2522         gfx_v9_0_cp_compute_enable(adev, false);
2523
2524         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2525         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2526
2527         fw_data = (const __le32 *)
2528                 (adev->gfx.mec_fw->data +
2529                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2530         tmp = 0;
2531         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2532         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2533         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2534
2535         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2536                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2537         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2538                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2539
2540         /* MEC1 */
2541         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2542                          mec_hdr->jt_offset);
2543         for (i = 0; i < mec_hdr->jt_size; i++)
2544                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2545                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2546
2547         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2548                         adev->gfx.mec_fw_version);
2549         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2550
2551         return 0;
2552 }
2553
2554 /* KIQ functions */
2555 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2556 {
2557         uint32_t tmp;
2558         struct amdgpu_device *adev = ring->adev;
2559
2560         /* tell RLC which is KIQ queue */
2561         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2562         tmp &= 0xffffff00;
2563         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2564         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2565         tmp |= 0x80;
2566         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2567 }
2568
2569 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2570 {
2571         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2572         uint32_t scratch, tmp = 0;
2573         uint64_t queue_mask = 0;
2574         int r, i;
2575
2576         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2577                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2578                         continue;
2579
2580                 /* This situation may be hit in the future if a new HW
2581                  * generation exposes more than 64 queues. If so, the
2582                  * definition of queue_mask needs updating */
2583                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2584                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2585                         break;
2586                 }
2587
2588                 queue_mask |= (1ull << i);
2589         }
2590
2591         r = amdgpu_gfx_scratch_get(adev, &scratch);
2592         if (r) {
2593                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2594                 return r;
2595         }
2596         WREG32(scratch, 0xCAFEDEAD);
2597
2598         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2599         if (r) {
2600                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2601                 amdgpu_gfx_scratch_free(adev, scratch);
2602                 return r;
2603         }
2604
2605         /* set resources */
2606         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2607         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2608                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2609         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2610         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2611         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2612         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2613         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2614         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2615         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2616                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2617                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2618                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2619
2620                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2621                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2622                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2623                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2624                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2625                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2626                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2627                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2628                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2629                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2630                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2631                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2632                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2633                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2634                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2635                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2636                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2637         }
2638         /* write to scratch for completion */
2639         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2640         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2641         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2642         amdgpu_ring_commit(kiq_ring);
2643
2644         for (i = 0; i < adev->usec_timeout; i++) {
2645                 tmp = RREG32(scratch);
2646                 if (tmp == 0xDEADBEEF)
2647                         break;
2648                 DRM_UDELAY(1);
2649         }
2650         if (i >= adev->usec_timeout) {
2651                 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2652                           scratch, tmp);
2653                 r = -EINVAL;
2654         }
2655         amdgpu_gfx_scratch_free(adev, scratch);
2656
2657         return r;
2658 }
2659
2660 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2661 {
2662         struct amdgpu_device *adev = ring->adev;
2663         struct v9_mqd *mqd = ring->mqd_ptr;
2664         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2665         uint32_t tmp;
2666
2667         mqd->header = 0xC0310800;
2668         mqd->compute_pipelinestat_enable = 0x00000001;
2669         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2670         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2671         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2672         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2673         mqd->compute_misc_reserved = 0x00000003;
2674
2675         mqd->dynamic_cu_mask_addr_lo =
2676                 lower_32_bits(ring->mqd_gpu_addr
2677                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2678         mqd->dynamic_cu_mask_addr_hi =
2679                 upper_32_bits(ring->mqd_gpu_addr
2680                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2681
2682         eop_base_addr = ring->eop_gpu_addr >> 8;
2683         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2684         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2685
2686         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2687         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2688         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2689                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2690
2691         mqd->cp_hqd_eop_control = tmp;
2692
2693         /* enable doorbell? */
2694         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2695
2696         if (ring->use_doorbell) {
2697                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2698                                     DOORBELL_OFFSET, ring->doorbell_index);
2699                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2700                                     DOORBELL_EN, 1);
2701                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2702                                     DOORBELL_SOURCE, 0);
2703                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2704                                     DOORBELL_HIT, 0);
2705         } else {
2706                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2707                                          DOORBELL_EN, 0);
2708         }
2709
2710         mqd->cp_hqd_pq_doorbell_control = tmp;
2711
2712         /* disable the queue if it's active */
2713         ring->wptr = 0;
2714         mqd->cp_hqd_dequeue_request = 0;
2715         mqd->cp_hqd_pq_rptr = 0;
2716         mqd->cp_hqd_pq_wptr_lo = 0;
2717         mqd->cp_hqd_pq_wptr_hi = 0;
2718
2719         /* set the pointer to the MQD */
2720         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2721         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2722
2723         /* set MQD vmid to 0 */
2724         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2725         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2726         mqd->cp_mqd_control = tmp;
2727
2728         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2729         hqd_gpu_addr = ring->gpu_addr >> 8;
2730         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2731         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2732
2733         /* set up the HQD, this is similar to CP_RB0_CNTL */
2734         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2735         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2736                             (order_base_2(ring->ring_size / 4) - 1));
2737         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2738                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2739 #ifdef __BIG_ENDIAN
2740         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2741 #endif
2742         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2743         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2744         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2745         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2746         mqd->cp_hqd_pq_control = tmp;
2747
2748         /* set the wb address whether it's enabled or not */
2749         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2750         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2751         mqd->cp_hqd_pq_rptr_report_addr_hi =
2752                 upper_32_bits(wb_gpu_addr) & 0xffff;
2753
2754         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2755         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2756         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2757         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2758
2759         tmp = 0;
2760         /* enable the doorbell if requested */
2761         if (ring->use_doorbell) {
2762                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2763                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2764                                 DOORBELL_OFFSET, ring->doorbell_index);
2765
2766                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2767                                          DOORBELL_EN, 1);
2768                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2769                                          DOORBELL_SOURCE, 0);
2770                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2771                                          DOORBELL_HIT, 0);
2772         }
2773
2774         mqd->cp_hqd_pq_doorbell_control = tmp;
2775
2776         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2777         ring->wptr = 0;
2778         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2779
2780         /* set the vmid for the queue */
2781         mqd->cp_hqd_vmid = 0;
2782
2783         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2784         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2785         mqd->cp_hqd_persistent_state = tmp;
2786
2787         /* set MIN_IB_AVAIL_SIZE */
2788         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2789         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2790         mqd->cp_hqd_ib_control = tmp;
2791
2792         /* activate the queue */
2793         mqd->cp_hqd_active = 1;
2794
2795         return 0;
2796 }
2797
2798 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2799 {
2800         struct amdgpu_device *adev = ring->adev;
2801         struct v9_mqd *mqd = ring->mqd_ptr;
2802         int j;
2803
2804         /* disable wptr polling */
2805         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2806
2807         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2808                mqd->cp_hqd_eop_base_addr_lo);
2809         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2810                mqd->cp_hqd_eop_base_addr_hi);
2811
2812         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2813         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2814                mqd->cp_hqd_eop_control);
2815
2816         /* enable doorbell? */
2817         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2818                mqd->cp_hqd_pq_doorbell_control);
2819
2820         /* disable the queue if it's active */
2821         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2822                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2823                 for (j = 0; j < adev->usec_timeout; j++) {
2824                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2825                                 break;
2826                         udelay(1);
2827                 }
2828                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2829                        mqd->cp_hqd_dequeue_request);
2830                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2831                        mqd->cp_hqd_pq_rptr);
2832                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2833                        mqd->cp_hqd_pq_wptr_lo);
2834                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2835                        mqd->cp_hqd_pq_wptr_hi);
2836         }
2837
2838         /* set the pointer to the MQD */
2839         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2840                mqd->cp_mqd_base_addr_lo);
2841         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2842                mqd->cp_mqd_base_addr_hi);
2843
2844         /* set MQD vmid to 0 */
2845         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2846                mqd->cp_mqd_control);
2847
2848         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2849         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2850                mqd->cp_hqd_pq_base_lo);
2851         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2852                mqd->cp_hqd_pq_base_hi);
2853
2854         /* set up the HQD, this is similar to CP_RB0_CNTL */
2855         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2856                mqd->cp_hqd_pq_control);
2857
2858         /* set the wb address whether it's enabled or not */
2859         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2860                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2861         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2862                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2863
2864         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2865         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2866                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2867         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2868                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2869
2870         /* enable the doorbell if requested */
2871         if (ring->use_doorbell) {
2872                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2873                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2874                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2875                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2876         }
2877
2878         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2879                mqd->cp_hqd_pq_doorbell_control);
2880
2881         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2882         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2883                mqd->cp_hqd_pq_wptr_lo);
2884         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2885                mqd->cp_hqd_pq_wptr_hi);
2886
2887         /* set the vmid for the queue */
2888         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2889
2890         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2891                mqd->cp_hqd_persistent_state);
2892
2893         /* activate the queue */
2894         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2895                mqd->cp_hqd_active);
2896
2897         if (ring->use_doorbell)
2898                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2899
2900         return 0;
2901 }
2902
2903 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
2904 {
2905         struct amdgpu_device *adev = ring->adev;
2906         int j;
2907
2908         /* disable the queue if it's active */
2909         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2910
2911                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2912
2913                 for (j = 0; j < adev->usec_timeout; j++) {
2914                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2915                                 break;
2916                         udelay(1);
2917                 }
2918
2919                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
2920                         DRM_DEBUG("KIQ dequeue request failed.\n");
2921
2922                         /* Manual disable if dequeue request times out */
2923                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
2924                 }
2925
2926                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2927                       0);
2928         }
2929
2930         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
2931         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
2932         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
2933         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
2934         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
2935         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
2936         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
2937         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
2938
2939         return 0;
2940 }
2941
2942 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2943 {
2944         struct amdgpu_device *adev = ring->adev;
2945         struct v9_mqd *mqd = ring->mqd_ptr;
2946         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2947
2948         gfx_v9_0_kiq_setting(ring);
2949
2950         if (adev->in_gpu_reset) { /* for GPU_RESET case */
2951                 /* reset MQD to a clean status */
2952                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2953                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2954
2955                 /* reset ring buffer */
2956                 ring->wptr = 0;
2957                 amdgpu_ring_clear_ring(ring);
2958
2959                 mutex_lock(&adev->srbm_mutex);
2960                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2961                 gfx_v9_0_kiq_init_register(ring);
2962                 soc15_grbm_select(adev, 0, 0, 0, 0);
2963                 mutex_unlock(&adev->srbm_mutex);
2964         } else {
2965                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2966                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2967                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2968                 mutex_lock(&adev->srbm_mutex);
2969                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2970                 gfx_v9_0_mqd_init(ring);
2971                 gfx_v9_0_kiq_init_register(ring);
2972                 soc15_grbm_select(adev, 0, 0, 0, 0);
2973                 mutex_unlock(&adev->srbm_mutex);
2974
2975                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2976                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
2977         }
2978
2979         return 0;
2980 }
2981
2982 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2983 {
2984         struct amdgpu_device *adev = ring->adev;
2985         struct v9_mqd *mqd = ring->mqd_ptr;
2986         int mqd_idx = ring - &adev->gfx.compute_ring[0];
2987
2988         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
2989                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2990                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2991                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2992                 mutex_lock(&adev->srbm_mutex);
2993                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2994                 gfx_v9_0_mqd_init(ring);
2995                 soc15_grbm_select(adev, 0, 0, 0, 0);
2996                 mutex_unlock(&adev->srbm_mutex);
2997
2998                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2999                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3000         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3001                 /* reset MQD to a clean status */
3002                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3003                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3004
3005                 /* reset ring buffer */
3006                 ring->wptr = 0;
3007                 amdgpu_ring_clear_ring(ring);
3008         } else {
3009                 amdgpu_ring_clear_ring(ring);
3010         }
3011
3012         return 0;
3013 }
3014
3015 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3016 {
3017         struct amdgpu_ring *ring = NULL;
3018         int r = 0, i;
3019
3020         gfx_v9_0_cp_compute_enable(adev, true);
3021
3022         ring = &adev->gfx.kiq.ring;
3023
3024         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3025         if (unlikely(r != 0))
3026                 goto done;
3027
3028         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3029         if (!r) {
3030                 r = gfx_v9_0_kiq_init_queue(ring);
3031                 amdgpu_bo_kunmap(ring->mqd_obj);
3032                 ring->mqd_ptr = NULL;
3033         }
3034         amdgpu_bo_unreserve(ring->mqd_obj);
3035         if (r)
3036                 goto done;
3037
3038         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3039                 ring = &adev->gfx.compute_ring[i];
3040
3041                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3042                 if (unlikely(r != 0))
3043                         goto done;
3044                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3045                 if (!r) {
3046                         r = gfx_v9_0_kcq_init_queue(ring);
3047                         amdgpu_bo_kunmap(ring->mqd_obj);
3048                         ring->mqd_ptr = NULL;
3049                 }
3050                 amdgpu_bo_unreserve(ring->mqd_obj);
3051                 if (r)
3052                         goto done;
3053         }
3054
3055         r = gfx_v9_0_kiq_kcq_enable(adev);
3056 done:
3057         return r;
3058 }
3059
3060 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3061 {
3062         int r, i;
3063         struct amdgpu_ring *ring;
3064
3065         if (!(adev->flags & AMD_IS_APU))
3066                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3067
3068         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3069                 /* legacy firmware loading */
3070                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3071                 if (r)
3072                         return r;
3073
3074                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3075                 if (r)
3076                         return r;
3077         }
3078
3079         r = gfx_v9_0_cp_gfx_resume(adev);
3080         if (r)
3081                 return r;
3082
3083         r = gfx_v9_0_kiq_resume(adev);
3084         if (r)
3085                 return r;
3086
3087         ring = &adev->gfx.gfx_ring[0];
3088         r = amdgpu_ring_test_ring(ring);
3089         if (r) {
3090                 ring->ready = false;
3091                 return r;
3092         }
3093
3094         ring = &adev->gfx.kiq.ring;
3095         ring->ready = true;
3096         r = amdgpu_ring_test_ring(ring);
3097         if (r)
3098                 ring->ready = false;
3099
3100         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3101                 ring = &adev->gfx.compute_ring[i];
3102
3103                 ring->ready = true;
3104                 r = amdgpu_ring_test_ring(ring);
3105                 if (r)
3106                         ring->ready = false;
3107         }
3108
3109         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3110
3111         return 0;
3112 }
3113
3114 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3115 {
3116         gfx_v9_0_cp_gfx_enable(adev, enable);
3117         gfx_v9_0_cp_compute_enable(adev, enable);
3118 }
3119
3120 static int gfx_v9_0_hw_init(void *handle)
3121 {
3122         int r;
3123         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3124
3125         gfx_v9_0_init_golden_registers(adev);
3126
3127         gfx_v9_0_gpu_init(adev);
3128
3129         r = gfx_v9_0_csb_vram_pin(adev);
3130         if (r)
3131                 return r;
3132
3133         r = gfx_v9_0_rlc_resume(adev);
3134         if (r)
3135                 return r;
3136
3137         r = gfx_v9_0_cp_resume(adev);
3138         if (r)
3139                 return r;
3140
3141         r = gfx_v9_0_ngg_en(adev);
3142         if (r)
3143                 return r;
3144
3145         return r;
3146 }
3147
3148 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
3149 {
3150         struct amdgpu_device *adev = kiq_ring->adev;
3151         uint32_t scratch, tmp = 0;
3152         int r, i;
3153
3154         r = amdgpu_gfx_scratch_get(adev, &scratch);
3155         if (r) {
3156                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
3157                 return r;
3158         }
3159         WREG32(scratch, 0xCAFEDEAD);
3160
3161         r = amdgpu_ring_alloc(kiq_ring, 10);
3162         if (r) {
3163                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3164                 amdgpu_gfx_scratch_free(adev, scratch);
3165                 return r;
3166         }
3167
3168         /* unmap queues */
3169         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3170         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3171                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3172                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3173                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3174                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3175         amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3176         amdgpu_ring_write(kiq_ring, 0);
3177         amdgpu_ring_write(kiq_ring, 0);
3178         amdgpu_ring_write(kiq_ring, 0);
3179         /* write to scratch for completion */
3180         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3181         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3182         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
3183         amdgpu_ring_commit(kiq_ring);
3184
3185         for (i = 0; i < adev->usec_timeout; i++) {
3186                 tmp = RREG32(scratch);
3187                 if (tmp == 0xDEADBEEF)
3188                         break;
3189                 DRM_UDELAY(1);
3190         }
3191         if (i >= adev->usec_timeout) {
3192                 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
3193                 r = -EINVAL;
3194         }
3195         amdgpu_gfx_scratch_free(adev, scratch);
3196         return r;
3197 }
3198
3199 static int gfx_v9_0_hw_fini(void *handle)
3200 {
3201         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3202         int i;
3203
3204         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3205                                                AMD_PG_STATE_UNGATE);
3206
3207         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3208         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3209
3210         /* disable KCQ to avoid CPC touch memory not valid anymore */
3211         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3212                 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
3213
3214         if (amdgpu_sriov_vf(adev)) {
3215                 gfx_v9_0_cp_gfx_enable(adev, false);
3216                 /* must disable polling for SRIOV when hw finished, otherwise
3217                  * CPC engine may still keep fetching WB address which is already
3218                  * invalid after sw finished and trigger DMAR reading error in
3219                  * hypervisor side.
3220                  */
3221                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3222                 return 0;
3223         }
3224
3225         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3226          * otherwise KIQ is hanging when binding back
3227          */
3228         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3229                 mutex_lock(&adev->srbm_mutex);
3230                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3231                                 adev->gfx.kiq.ring.pipe,
3232                                 adev->gfx.kiq.ring.queue, 0);
3233                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3234                 soc15_grbm_select(adev, 0, 0, 0, 0);
3235                 mutex_unlock(&adev->srbm_mutex);
3236         }
3237
3238         gfx_v9_0_cp_enable(adev, false);
3239         gfx_v9_0_rlc_stop(adev);
3240
3241         gfx_v9_0_csb_vram_unpin(adev);
3242
3243         return 0;
3244 }
3245
3246 static int gfx_v9_0_suspend(void *handle)
3247 {
3248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3249
3250         adev->gfx.in_suspend = true;
3251         return gfx_v9_0_hw_fini(adev);
3252 }
3253
3254 static int gfx_v9_0_resume(void *handle)
3255 {
3256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3257         int r;
3258
3259         r = gfx_v9_0_hw_init(adev);
3260         adev->gfx.in_suspend = false;
3261         return r;
3262 }
3263
3264 static bool gfx_v9_0_is_idle(void *handle)
3265 {
3266         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3267
3268         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3269                                 GRBM_STATUS, GUI_ACTIVE))
3270                 return false;
3271         else
3272                 return true;
3273 }
3274
3275 static int gfx_v9_0_wait_for_idle(void *handle)
3276 {
3277         unsigned i;
3278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3279
3280         for (i = 0; i < adev->usec_timeout; i++) {
3281                 if (gfx_v9_0_is_idle(handle))
3282                         return 0;
3283                 udelay(1);
3284         }
3285         return -ETIMEDOUT;
3286 }
3287
3288 static int gfx_v9_0_soft_reset(void *handle)
3289 {
3290         u32 grbm_soft_reset = 0;
3291         u32 tmp;
3292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3293
3294         /* GRBM_STATUS */
3295         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3296         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3297                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3298                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3299                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3300                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3301                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3302                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3303                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3304                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3305                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3306         }
3307
3308         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3309                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3310                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3311         }
3312
3313         /* GRBM_STATUS2 */
3314         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3315         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3316                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3317                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3318
3319
3320         if (grbm_soft_reset) {
3321                 /* stop the rlc */
3322                 gfx_v9_0_rlc_stop(adev);
3323
3324                 /* Disable GFX parsing/prefetching */
3325                 gfx_v9_0_cp_gfx_enable(adev, false);
3326
3327                 /* Disable MEC parsing/prefetching */
3328                 gfx_v9_0_cp_compute_enable(adev, false);
3329
3330                 if (grbm_soft_reset) {
3331                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3332                         tmp |= grbm_soft_reset;
3333                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3334                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3335                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3336
3337                         udelay(50);
3338
3339                         tmp &= ~grbm_soft_reset;
3340                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3341                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3342                 }
3343
3344                 /* Wait a little for things to settle down */
3345                 udelay(50);
3346         }
3347         return 0;
3348 }
3349
3350 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3351 {
3352         uint64_t clock;
3353
3354         mutex_lock(&adev->gfx.gpu_clock_mutex);
3355         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3356         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3357                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3358         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3359         return clock;
3360 }
3361
3362 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3363                                           uint32_t vmid,
3364                                           uint32_t gds_base, uint32_t gds_size,
3365                                           uint32_t gws_base, uint32_t gws_size,
3366                                           uint32_t oa_base, uint32_t oa_size)
3367 {
3368         struct amdgpu_device *adev = ring->adev;
3369
3370         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3371         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3372
3373         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3374         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3375
3376         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3377         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3378
3379         /* GDS Base */
3380         gfx_v9_0_write_data_to_reg(ring, 0, false,
3381                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3382                                    gds_base);
3383
3384         /* GDS Size */
3385         gfx_v9_0_write_data_to_reg(ring, 0, false,
3386                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3387                                    gds_size);
3388
3389         /* GWS */
3390         gfx_v9_0_write_data_to_reg(ring, 0, false,
3391                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3392                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3393
3394         /* OA */
3395         gfx_v9_0_write_data_to_reg(ring, 0, false,
3396                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3397                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3398 }
3399
3400 static int gfx_v9_0_early_init(void *handle)
3401 {
3402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3403
3404         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3405         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3406         gfx_v9_0_set_ring_funcs(adev);
3407         gfx_v9_0_set_irq_funcs(adev);
3408         gfx_v9_0_set_gds_init(adev);
3409         gfx_v9_0_set_rlc_funcs(adev);
3410
3411         return 0;
3412 }
3413
3414 static int gfx_v9_0_late_init(void *handle)
3415 {
3416         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3417         int r;
3418
3419         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3420         if (r)
3421                 return r;
3422
3423         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3424         if (r)
3425                 return r;
3426
3427         return 0;
3428 }
3429
3430 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3431 {
3432         uint32_t rlc_setting, data;
3433         unsigned i;
3434
3435         if (adev->gfx.rlc.in_safe_mode)
3436                 return;
3437
3438         /* if RLC is not enabled, do nothing */
3439         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3440         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3441                 return;
3442
3443         if (adev->cg_flags &
3444             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3445              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3446                 data = RLC_SAFE_MODE__CMD_MASK;
3447                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3448                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3449
3450                 /* wait for RLC_SAFE_MODE */
3451                 for (i = 0; i < adev->usec_timeout; i++) {
3452                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3453                                 break;
3454                         udelay(1);
3455                 }
3456                 adev->gfx.rlc.in_safe_mode = true;
3457         }
3458 }
3459
3460 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3461 {
3462         uint32_t rlc_setting, data;
3463
3464         if (!adev->gfx.rlc.in_safe_mode)
3465                 return;
3466
3467         /* if RLC is not enabled, do nothing */
3468         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3469         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3470                 return;
3471
3472         if (adev->cg_flags &
3473             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3474                 /*
3475                  * Try to exit safe mode only if it is already in safe
3476                  * mode.
3477                  */
3478                 data = RLC_SAFE_MODE__CMD_MASK;
3479                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3480                 adev->gfx.rlc.in_safe_mode = false;
3481         }
3482 }
3483
3484 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3485                                                 bool enable)
3486 {
3487         gfx_v9_0_enter_rlc_safe_mode(adev);
3488
3489         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3490                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3491                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3492                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3493         } else {
3494                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3495                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3496         }
3497
3498         gfx_v9_0_exit_rlc_safe_mode(adev);
3499 }
3500
3501 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3502                                                 bool enable)
3503 {
3504         /* TODO: double check if we need to perform under safe mode */
3505         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3506
3507         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3508                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3509         else
3510                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3511
3512         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3513                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3514         else
3515                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3516
3517         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3518 }
3519
3520 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3521                                                       bool enable)
3522 {
3523         uint32_t data, def;
3524
3525         /* It is disabled by HW by default */
3526         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3527                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3528                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3529
3530                 if (adev->asic_type != CHIP_VEGA12)
3531                         data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3532
3533                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3534                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3535                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3536
3537                 /* only for Vega10 & Raven1 */
3538                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3539
3540                 if (def != data)
3541                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3542
3543                 /* MGLS is a global flag to control all MGLS in GFX */
3544                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3545                         /* 2 - RLC memory Light sleep */
3546                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3547                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3548                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3549                                 if (def != data)
3550                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3551                         }
3552                         /* 3 - CP memory Light sleep */
3553                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3554                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3555                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3556                                 if (def != data)
3557                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3558                         }
3559                 }
3560         } else {
3561                 /* 1 - MGCG_OVERRIDE */
3562                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3563
3564                 if (adev->asic_type != CHIP_VEGA12)
3565                         data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3566
3567                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3568                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3569                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3570                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3571
3572                 if (def != data)
3573                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3574
3575                 /* 2 - disable MGLS in RLC */
3576                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3577                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3578                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3579                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3580                 }
3581
3582                 /* 3 - disable MGLS in CP */
3583                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3584                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3585                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3586                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3587                 }
3588         }
3589 }
3590
3591 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3592                                            bool enable)
3593 {
3594         uint32_t data, def;
3595
3596         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3597
3598         /* Enable 3D CGCG/CGLS */
3599         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3600                 /* write cmd to clear cgcg/cgls ov */
3601                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3602                 /* unset CGCG override */
3603                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3604                 /* update CGCG and CGLS override bits */
3605                 if (def != data)
3606                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3607
3608                 /* enable 3Dcgcg FSM(0x0000363f) */
3609                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3610
3611                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3612                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3613                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3614                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3615                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3616                 if (def != data)
3617                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3618
3619                 /* set IDLE_POLL_COUNT(0x00900100) */
3620                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3621                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3622                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3623                 if (def != data)
3624                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3625         } else {
3626                 /* Disable CGCG/CGLS */
3627                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3628                 /* disable cgcg, cgls should be disabled */
3629                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3630                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3631                 /* disable cgcg and cgls in FSM */
3632                 if (def != data)
3633                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3634         }
3635
3636         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3637 }
3638
3639 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3640                                                       bool enable)
3641 {
3642         uint32_t def, data;
3643
3644         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3645
3646         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3647                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3648                 /* unset CGCG override */
3649                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3650                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3651                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3652                 else
3653                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3654                 /* update CGCG and CGLS override bits */
3655                 if (def != data)
3656                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3657
3658                 /* enable cgcg FSM(0x0000363F) */
3659                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3660
3661                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3662                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3663                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3664                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3665                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3666                 if (def != data)
3667                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3668
3669                 /* set IDLE_POLL_COUNT(0x00900100) */
3670                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3671                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3672                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3673                 if (def != data)
3674                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3675         } else {
3676                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3677                 /* reset CGCG/CGLS bits */
3678                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3679                 /* disable cgcg and cgls in FSM */
3680                 if (def != data)
3681                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3682         }
3683
3684         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3685 }
3686
3687 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3688                                             bool enable)
3689 {
3690         if (enable) {
3691                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3692                  * ===  MGCG + MGLS ===
3693                  */
3694                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3695                 /* ===  CGCG /CGLS for GFX 3D Only === */
3696                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3697                 /* ===  CGCG + CGLS === */
3698                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3699         } else {
3700                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3701                  * ===  CGCG + CGLS ===
3702                  */
3703                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3704                 /* ===  CGCG /CGLS for GFX 3D Only === */
3705                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3706                 /* ===  MGCG + MGLS === */
3707                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3708         }
3709         return 0;
3710 }
3711
3712 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3713         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3714         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3715 };
3716
3717 static int gfx_v9_0_set_powergating_state(void *handle,
3718                                           enum amd_powergating_state state)
3719 {
3720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3721         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3722
3723         switch (adev->asic_type) {
3724         case CHIP_RAVEN:
3725                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3726                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3727                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3728                 } else {
3729                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3730                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3731                 }
3732
3733                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3734                         gfx_v9_0_enable_cp_power_gating(adev, true);
3735                 else
3736                         gfx_v9_0_enable_cp_power_gating(adev, false);
3737
3738                 /* update gfx cgpg state */
3739                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3740
3741                 /* update mgcg state */
3742                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3743
3744                 /* set gfx off through smu */
3745                 if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
3746                         amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
3747                 break;
3748         case CHIP_VEGA12:
3749                 /* set gfx off through smu */
3750                 if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
3751                         amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
3752                 break;
3753         default:
3754                 break;
3755         }
3756
3757         return 0;
3758 }
3759
3760 static int gfx_v9_0_set_clockgating_state(void *handle,
3761                                           enum amd_clockgating_state state)
3762 {
3763         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3764
3765         if (amdgpu_sriov_vf(adev))
3766                 return 0;
3767
3768         switch (adev->asic_type) {
3769         case CHIP_VEGA10:
3770         case CHIP_VEGA12:
3771         case CHIP_VEGA20:
3772         case CHIP_RAVEN:
3773                 gfx_v9_0_update_gfx_clock_gating(adev,
3774                                                  state == AMD_CG_STATE_GATE ? true : false);
3775                 break;
3776         default:
3777                 break;
3778         }
3779         return 0;
3780 }
3781
3782 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3783 {
3784         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3785         int data;
3786
3787         if (amdgpu_sriov_vf(adev))
3788                 *flags = 0;
3789
3790         /* AMD_CG_SUPPORT_GFX_MGCG */
3791         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3792         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3793                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3794
3795         /* AMD_CG_SUPPORT_GFX_CGCG */
3796         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3797         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3798                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3799
3800         /* AMD_CG_SUPPORT_GFX_CGLS */
3801         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3802                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3803
3804         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3805         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3806         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3807                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3808
3809         /* AMD_CG_SUPPORT_GFX_CP_LS */
3810         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3811         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3812                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3813
3814         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3815         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3816         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3817                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3818
3819         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3820         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3821                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3822 }
3823
3824 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3825 {
3826         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3827 }
3828
3829 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3830 {
3831         struct amdgpu_device *adev = ring->adev;
3832         u64 wptr;
3833
3834         /* XXX check if swapping is necessary on BE */
3835         if (ring->use_doorbell) {
3836                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3837         } else {
3838                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3839                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3840         }
3841
3842         return wptr;
3843 }
3844
3845 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3846 {
3847         struct amdgpu_device *adev = ring->adev;
3848
3849         if (ring->use_doorbell) {
3850                 /* XXX check if swapping is necessary on BE */
3851                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3852                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3853         } else {
3854                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3855                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3856         }
3857 }
3858
3859 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3860 {
3861         struct amdgpu_device *adev = ring->adev;
3862         u32 ref_and_mask, reg_mem_engine;
3863         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3864
3865         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3866                 switch (ring->me) {
3867                 case 1:
3868                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3869                         break;
3870                 case 2:
3871                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3872                         break;
3873                 default:
3874                         return;
3875                 }
3876                 reg_mem_engine = 0;
3877         } else {
3878                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3879                 reg_mem_engine = 1; /* pfp */
3880         }
3881
3882         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3883                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3884                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3885                               ref_and_mask, ref_and_mask, 0x20);
3886 }
3887
3888 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3889                                       struct amdgpu_ib *ib,
3890                                       unsigned vmid, bool ctx_switch)
3891 {
3892         u32 header, control = 0;
3893
3894         if (ib->flags & AMDGPU_IB_FLAG_CE)
3895                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3896         else
3897                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3898
3899         control |= ib->length_dw | (vmid << 24);
3900
3901         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3902                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3903
3904                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3905                         gfx_v9_0_ring_emit_de_meta(ring);
3906         }
3907
3908         amdgpu_ring_write(ring, header);
3909         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3910         amdgpu_ring_write(ring,
3911 #ifdef __BIG_ENDIAN
3912                 (2 << 0) |
3913 #endif
3914                 lower_32_bits(ib->gpu_addr));
3915         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3916         amdgpu_ring_write(ring, control);
3917 }
3918
3919 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3920                                           struct amdgpu_ib *ib,
3921                                           unsigned vmid, bool ctx_switch)
3922 {
3923         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
3924
3925         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3926         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3927         amdgpu_ring_write(ring,
3928 #ifdef __BIG_ENDIAN
3929                                 (2 << 0) |
3930 #endif
3931                                 lower_32_bits(ib->gpu_addr));
3932         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3933         amdgpu_ring_write(ring, control);
3934 }
3935
3936 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3937                                      u64 seq, unsigned flags)
3938 {
3939         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3940         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3941         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
3942
3943         /* RELEASE_MEM - flush caches, send int */
3944         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3945         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
3946                                                EOP_TC_NC_ACTION_EN) :
3947                                               (EOP_TCL1_ACTION_EN |
3948                                                EOP_TC_ACTION_EN |
3949                                                EOP_TC_WB_ACTION_EN |
3950                                                EOP_TC_MD_ACTION_EN)) |
3951                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3952                                  EVENT_INDEX(5)));
3953         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3954
3955         /*
3956          * the address should be Qword aligned if 64bit write, Dword
3957          * aligned if only send 32bit data low (discard data high)
3958          */
3959         if (write64bit)
3960                 BUG_ON(addr & 0x7);
3961         else
3962                 BUG_ON(addr & 0x3);
3963         amdgpu_ring_write(ring, lower_32_bits(addr));
3964         amdgpu_ring_write(ring, upper_32_bits(addr));
3965         amdgpu_ring_write(ring, lower_32_bits(seq));
3966         amdgpu_ring_write(ring, upper_32_bits(seq));
3967         amdgpu_ring_write(ring, 0);
3968 }
3969
3970 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3971 {
3972         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3973         uint32_t seq = ring->fence_drv.sync_seq;
3974         uint64_t addr = ring->fence_drv.gpu_addr;
3975
3976         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3977                               lower_32_bits(addr), upper_32_bits(addr),
3978                               seq, 0xffffffff, 4);
3979 }
3980
3981 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3982                                         unsigned vmid, uint64_t pd_addr)
3983 {
3984         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3985
3986         /* compute doesn't have PFP */
3987         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
3988                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3989                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3990                 amdgpu_ring_write(ring, 0x0);
3991         }
3992 }
3993
3994 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3995 {
3996         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3997 }
3998
3999 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4000 {
4001         u64 wptr;
4002
4003         /* XXX check if swapping is necessary on BE */
4004         if (ring->use_doorbell)
4005                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4006         else
4007                 BUG();
4008         return wptr;
4009 }
4010
4011 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4012                                            bool acquire)
4013 {
4014         struct amdgpu_device *adev = ring->adev;
4015         int pipe_num, tmp, reg;
4016         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4017
4018         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4019
4020         /* first me only has 2 entries, GFX and HP3D */
4021         if (ring->me > 0)
4022                 pipe_num -= 2;
4023
4024         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4025         tmp = RREG32(reg);
4026         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4027         WREG32(reg, tmp);
4028 }
4029
4030 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4031                                             struct amdgpu_ring *ring,
4032                                             bool acquire)
4033 {
4034         int i, pipe;
4035         bool reserve;
4036         struct amdgpu_ring *iring;
4037
4038         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4039         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4040         if (acquire)
4041                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4042         else
4043                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4044
4045         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4046                 /* Clear all reservations - everyone reacquires all resources */
4047                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4048                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4049                                                        true);
4050
4051                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4052                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4053                                                        true);
4054         } else {
4055                 /* Lower all pipes without a current reservation */
4056                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4057                         iring = &adev->gfx.gfx_ring[i];
4058                         pipe = amdgpu_gfx_queue_to_bit(adev,
4059                                                        iring->me,
4060                                                        iring->pipe,
4061                                                        0);
4062                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4063                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4064                 }
4065
4066                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4067                         iring = &adev->gfx.compute_ring[i];
4068                         pipe = amdgpu_gfx_queue_to_bit(adev,
4069                                                        iring->me,
4070                                                        iring->pipe,
4071                                                        0);
4072                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4073                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4074                 }
4075         }
4076
4077         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4078 }
4079
4080 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4081                                       struct amdgpu_ring *ring,
4082                                       bool acquire)
4083 {
4084         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4085         uint32_t queue_priority = acquire ? 0xf : 0x0;
4086
4087         mutex_lock(&adev->srbm_mutex);
4088         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4089
4090         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4091         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4092
4093         soc15_grbm_select(adev, 0, 0, 0, 0);
4094         mutex_unlock(&adev->srbm_mutex);
4095 }
4096
4097 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4098                                                enum drm_sched_priority priority)
4099 {
4100         struct amdgpu_device *adev = ring->adev;
4101         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4102
4103         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4104                 return;
4105
4106         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4107         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4108 }
4109
4110 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4111 {
4112         struct amdgpu_device *adev = ring->adev;
4113
4114         /* XXX check if swapping is necessary on BE */
4115         if (ring->use_doorbell) {
4116                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4117                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4118         } else{
4119                 BUG(); /* only DOORBELL method supported on gfx9 now */
4120         }
4121 }
4122
4123 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4124                                          u64 seq, unsigned int flags)
4125 {
4126         struct amdgpu_device *adev = ring->adev;
4127
4128         /* we only allocate 32bit for each seq wb address */
4129         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4130
4131         /* write fence seq to the "addr" */
4132         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4133         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4134                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4135         amdgpu_ring_write(ring, lower_32_bits(addr));
4136         amdgpu_ring_write(ring, upper_32_bits(addr));
4137         amdgpu_ring_write(ring, lower_32_bits(seq));
4138
4139         if (flags & AMDGPU_FENCE_FLAG_INT) {
4140                 /* set register to trigger INT */
4141                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4142                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4143                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4144                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4145                 amdgpu_ring_write(ring, 0);
4146                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4147         }
4148 }
4149
4150 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4151 {
4152         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4153         amdgpu_ring_write(ring, 0);
4154 }
4155
4156 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4157 {
4158         struct v9_ce_ib_state ce_payload = {0};
4159         uint64_t csa_addr;
4160         int cnt;
4161
4162         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4163         csa_addr = amdgpu_csa_vaddr(ring->adev);
4164
4165         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4166         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4167                                  WRITE_DATA_DST_SEL(8) |
4168                                  WR_CONFIRM) |
4169                                  WRITE_DATA_CACHE_POLICY(0));
4170         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4171         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4172         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4173 }
4174
4175 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4176 {
4177         struct v9_de_ib_state de_payload = {0};
4178         uint64_t csa_addr, gds_addr;
4179         int cnt;
4180
4181         csa_addr = amdgpu_csa_vaddr(ring->adev);
4182         gds_addr = csa_addr + 4096;
4183         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4184         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4185
4186         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4187         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4188         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4189                                  WRITE_DATA_DST_SEL(8) |
4190                                  WR_CONFIRM) |
4191                                  WRITE_DATA_CACHE_POLICY(0));
4192         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4193         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4194         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4195 }
4196
4197 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4198 {
4199         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4200         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4201 }
4202
4203 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4204 {
4205         uint32_t dw2 = 0;
4206
4207         if (amdgpu_sriov_vf(ring->adev))
4208                 gfx_v9_0_ring_emit_ce_meta(ring);
4209
4210         gfx_v9_0_ring_emit_tmz(ring, true);
4211
4212         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4213         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4214                 /* set load_global_config & load_global_uconfig */
4215                 dw2 |= 0x8001;
4216                 /* set load_cs_sh_regs */
4217                 dw2 |= 0x01000000;
4218                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4219                 dw2 |= 0x10002;
4220
4221                 /* set load_ce_ram if preamble presented */
4222                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4223                         dw2 |= 0x10000000;
4224         } else {
4225                 /* still load_ce_ram if this is the first time preamble presented
4226                  * although there is no context switch happens.
4227                  */
4228                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4229                         dw2 |= 0x10000000;
4230         }
4231
4232         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4233         amdgpu_ring_write(ring, dw2);
4234         amdgpu_ring_write(ring, 0);
4235 }
4236
4237 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4238 {
4239         unsigned ret;
4240         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4241         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4242         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4243         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4244         ret = ring->wptr & ring->buf_mask;
4245         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4246         return ret;
4247 }
4248
4249 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4250 {
4251         unsigned cur;
4252         BUG_ON(offset > ring->buf_mask);
4253         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4254
4255         cur = (ring->wptr & ring->buf_mask) - 1;
4256         if (likely(cur > offset))
4257                 ring->ring[offset] = cur - offset;
4258         else
4259                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4260 }
4261
4262 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4263 {
4264         struct amdgpu_device *adev = ring->adev;
4265
4266         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4267         amdgpu_ring_write(ring, 0 |     /* src: register*/
4268                                 (5 << 8) |      /* dst: memory */
4269                                 (1 << 20));     /* write confirm */
4270         amdgpu_ring_write(ring, reg);
4271         amdgpu_ring_write(ring, 0);
4272         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4273                                 adev->virt.reg_val_offs * 4));
4274         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4275                                 adev->virt.reg_val_offs * 4));
4276 }
4277
4278 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4279                                     uint32_t val)
4280 {
4281         uint32_t cmd = 0;
4282
4283         switch (ring->funcs->type) {
4284         case AMDGPU_RING_TYPE_GFX:
4285                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4286                 break;
4287         case AMDGPU_RING_TYPE_KIQ:
4288                 cmd = (1 << 16); /* no inc addr */
4289                 break;
4290         default:
4291                 cmd = WR_CONFIRM;
4292                 break;
4293         }
4294         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4295         amdgpu_ring_write(ring, cmd);
4296         amdgpu_ring_write(ring, reg);
4297         amdgpu_ring_write(ring, 0);
4298         amdgpu_ring_write(ring, val);
4299 }
4300
4301 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4302                                         uint32_t val, uint32_t mask)
4303 {
4304         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4305 }
4306
4307 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4308                                                   uint32_t reg0, uint32_t reg1,
4309                                                   uint32_t ref, uint32_t mask)
4310 {
4311         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4312
4313         if (amdgpu_sriov_vf(ring->adev))
4314                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4315                                       ref, mask, 0x20);
4316         else
4317                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4318                                                            ref, mask);
4319 }
4320
4321 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4322                                                  enum amdgpu_interrupt_state state)
4323 {
4324         switch (state) {
4325         case AMDGPU_IRQ_STATE_DISABLE:
4326         case AMDGPU_IRQ_STATE_ENABLE:
4327                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4328                                TIME_STAMP_INT_ENABLE,
4329                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4330                 break;
4331         default:
4332                 break;
4333         }
4334 }
4335
4336 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4337                                                      int me, int pipe,
4338                                                      enum amdgpu_interrupt_state state)
4339 {
4340         u32 mec_int_cntl, mec_int_cntl_reg;
4341
4342         /*
4343          * amdgpu controls only the first MEC. That's why this function only
4344          * handles the setting of interrupts for this specific MEC. All other
4345          * pipes' interrupts are set by amdkfd.
4346          */
4347
4348         if (me == 1) {
4349                 switch (pipe) {
4350                 case 0:
4351                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4352                         break;
4353                 case 1:
4354                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4355                         break;
4356                 case 2:
4357                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4358                         break;
4359                 case 3:
4360                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4361                         break;
4362                 default:
4363                         DRM_DEBUG("invalid pipe %d\n", pipe);
4364                         return;
4365                 }
4366         } else {
4367                 DRM_DEBUG("invalid me %d\n", me);
4368                 return;
4369         }
4370
4371         switch (state) {
4372         case AMDGPU_IRQ_STATE_DISABLE:
4373                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4374                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4375                                              TIME_STAMP_INT_ENABLE, 0);
4376                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4377                 break;
4378         case AMDGPU_IRQ_STATE_ENABLE:
4379                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4380                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4381                                              TIME_STAMP_INT_ENABLE, 1);
4382                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4383                 break;
4384         default:
4385                 break;
4386         }
4387 }
4388
4389 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4390                                              struct amdgpu_irq_src *source,
4391                                              unsigned type,
4392                                              enum amdgpu_interrupt_state state)
4393 {
4394         switch (state) {
4395         case AMDGPU_IRQ_STATE_DISABLE:
4396         case AMDGPU_IRQ_STATE_ENABLE:
4397                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4398                                PRIV_REG_INT_ENABLE,
4399                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4400                 break;
4401         default:
4402                 break;
4403         }
4404
4405         return 0;
4406 }
4407
4408 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4409                                               struct amdgpu_irq_src *source,
4410                                               unsigned type,
4411                                               enum amdgpu_interrupt_state state)
4412 {
4413         switch (state) {
4414         case AMDGPU_IRQ_STATE_DISABLE:
4415         case AMDGPU_IRQ_STATE_ENABLE:
4416                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4417                                PRIV_INSTR_INT_ENABLE,
4418                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4419         default:
4420                 break;
4421         }
4422
4423         return 0;
4424 }
4425
4426 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4427                                             struct amdgpu_irq_src *src,
4428                                             unsigned type,
4429                                             enum amdgpu_interrupt_state state)
4430 {
4431         switch (type) {
4432         case AMDGPU_CP_IRQ_GFX_EOP:
4433                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4434                 break;
4435         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4436                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4437                 break;
4438         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4439                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4440                 break;
4441         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4442                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4443                 break;
4444         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4445                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4446                 break;
4447         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4448                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4449                 break;
4450         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4451                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4452                 break;
4453         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4454                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4455                 break;
4456         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4457                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4458                 break;
4459         default:
4460                 break;
4461         }
4462         return 0;
4463 }
4464
4465 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4466                             struct amdgpu_irq_src *source,
4467                             struct amdgpu_iv_entry *entry)
4468 {
4469         int i;
4470         u8 me_id, pipe_id, queue_id;
4471         struct amdgpu_ring *ring;
4472
4473         DRM_DEBUG("IH: CP EOP\n");
4474         me_id = (entry->ring_id & 0x0c) >> 2;
4475         pipe_id = (entry->ring_id & 0x03) >> 0;
4476         queue_id = (entry->ring_id & 0x70) >> 4;
4477
4478         switch (me_id) {
4479         case 0:
4480                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4481                 break;
4482         case 1:
4483         case 2:
4484                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4485                         ring = &adev->gfx.compute_ring[i];
4486                         /* Per-queue interrupt is supported for MEC starting from VI.
4487                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4488                           */
4489                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4490                                 amdgpu_fence_process(ring);
4491                 }
4492                 break;
4493         }
4494         return 0;
4495 }
4496
4497 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4498                                  struct amdgpu_irq_src *source,
4499                                  struct amdgpu_iv_entry *entry)
4500 {
4501         DRM_ERROR("Illegal register access in command stream\n");
4502         schedule_work(&adev->reset_work);
4503         return 0;
4504 }
4505
4506 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4507                                   struct amdgpu_irq_src *source,
4508                                   struct amdgpu_iv_entry *entry)
4509 {
4510         DRM_ERROR("Illegal instruction in command stream\n");
4511         schedule_work(&adev->reset_work);
4512         return 0;
4513 }
4514
4515 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4516                                             struct amdgpu_irq_src *src,
4517                                             unsigned int type,
4518                                             enum amdgpu_interrupt_state state)
4519 {
4520         uint32_t tmp, target;
4521         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4522
4523         if (ring->me == 1)
4524                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4525         else
4526                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4527         target += ring->pipe;
4528
4529         switch (type) {
4530         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4531                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4532                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4533                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4534                                                  GENERIC2_INT_ENABLE, 0);
4535                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4536
4537                         tmp = RREG32(target);
4538                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4539                                                  GENERIC2_INT_ENABLE, 0);
4540                         WREG32(target, tmp);
4541                 } else {
4542                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4543                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4544                                                  GENERIC2_INT_ENABLE, 1);
4545                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4546
4547                         tmp = RREG32(target);
4548                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4549                                                  GENERIC2_INT_ENABLE, 1);
4550                         WREG32(target, tmp);
4551                 }
4552                 break;
4553         default:
4554                 BUG(); /* kiq only support GENERIC2_INT now */
4555                 break;
4556         }
4557         return 0;
4558 }
4559
4560 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4561                             struct amdgpu_irq_src *source,
4562                             struct amdgpu_iv_entry *entry)
4563 {
4564         u8 me_id, pipe_id, queue_id;
4565         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4566
4567         me_id = (entry->ring_id & 0x0c) >> 2;
4568         pipe_id = (entry->ring_id & 0x03) >> 0;
4569         queue_id = (entry->ring_id & 0x70) >> 4;
4570         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4571                    me_id, pipe_id, queue_id);
4572
4573         amdgpu_fence_process(ring);
4574         return 0;
4575 }
4576
4577 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4578         .name = "gfx_v9_0",
4579         .early_init = gfx_v9_0_early_init,
4580         .late_init = gfx_v9_0_late_init,
4581         .sw_init = gfx_v9_0_sw_init,
4582         .sw_fini = gfx_v9_0_sw_fini,
4583         .hw_init = gfx_v9_0_hw_init,
4584         .hw_fini = gfx_v9_0_hw_fini,
4585         .suspend = gfx_v9_0_suspend,
4586         .resume = gfx_v9_0_resume,
4587         .is_idle = gfx_v9_0_is_idle,
4588         .wait_for_idle = gfx_v9_0_wait_for_idle,
4589         .soft_reset = gfx_v9_0_soft_reset,
4590         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4591         .set_powergating_state = gfx_v9_0_set_powergating_state,
4592         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4593 };
4594
4595 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4596         .type = AMDGPU_RING_TYPE_GFX,
4597         .align_mask = 0xff,
4598         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4599         .support_64bit_ptrs = true,
4600         .vmhub = AMDGPU_GFXHUB,
4601         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4602         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4603         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4604         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4605                 5 +  /* COND_EXEC */
4606                 7 +  /* PIPELINE_SYNC */
4607                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4608                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4609                 2 + /* VM_FLUSH */
4610                 8 +  /* FENCE for VM_FLUSH */
4611                 20 + /* GDS switch */
4612                 4 + /* double SWITCH_BUFFER,
4613                        the first COND_EXEC jump to the place just
4614                            prior to this double SWITCH_BUFFER  */
4615                 5 + /* COND_EXEC */
4616                 7 +      /*     HDP_flush */
4617                 4 +      /*     VGT_flush */
4618                 14 + /* CE_META */
4619                 31 + /* DE_META */
4620                 3 + /* CNTX_CTRL */
4621                 5 + /* HDP_INVL */
4622                 8 + 8 + /* FENCE x2 */
4623                 2, /* SWITCH_BUFFER */
4624         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4625         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4626         .emit_fence = gfx_v9_0_ring_emit_fence,
4627         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4628         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4629         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4630         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4631         .test_ring = gfx_v9_0_ring_test_ring,
4632         .test_ib = gfx_v9_0_ring_test_ib,
4633         .insert_nop = amdgpu_ring_insert_nop,
4634         .pad_ib = amdgpu_ring_generic_pad_ib,
4635         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4636         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4637         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4638         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4639         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4640         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4641         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4642         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4643 };
4644
4645 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4646         .type = AMDGPU_RING_TYPE_COMPUTE,
4647         .align_mask = 0xff,
4648         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4649         .support_64bit_ptrs = true,
4650         .vmhub = AMDGPU_GFXHUB,
4651         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4652         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4653         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4654         .emit_frame_size =
4655                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4656                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4657                 5 + /* hdp invalidate */
4658                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4659                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4660                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4661                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4662                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4663         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4664         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4665         .emit_fence = gfx_v9_0_ring_emit_fence,
4666         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4667         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4668         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4669         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4670         .test_ring = gfx_v9_0_ring_test_ring,
4671         .test_ib = gfx_v9_0_ring_test_ib,
4672         .insert_nop = amdgpu_ring_insert_nop,
4673         .pad_ib = amdgpu_ring_generic_pad_ib,
4674         .set_priority = gfx_v9_0_ring_set_priority_compute,
4675         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4676         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4677         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4678 };
4679
4680 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4681         .type = AMDGPU_RING_TYPE_KIQ,
4682         .align_mask = 0xff,
4683         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4684         .support_64bit_ptrs = true,
4685         .vmhub = AMDGPU_GFXHUB,
4686         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4687         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4688         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4689         .emit_frame_size =
4690                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4691                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4692                 5 + /* hdp invalidate */
4693                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4694                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4695                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4696                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4697                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4698         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4699         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4700         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4701         .test_ring = gfx_v9_0_ring_test_ring,
4702         .test_ib = gfx_v9_0_ring_test_ib,
4703         .insert_nop = amdgpu_ring_insert_nop,
4704         .pad_ib = amdgpu_ring_generic_pad_ib,
4705         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4706         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4707         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4708         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4709 };
4710
4711 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4712 {
4713         int i;
4714
4715         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4716
4717         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4718                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4719
4720         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4721                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4722 }
4723
4724 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4725         .set = gfx_v9_0_kiq_set_interrupt_state,
4726         .process = gfx_v9_0_kiq_irq,
4727 };
4728
4729 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4730         .set = gfx_v9_0_set_eop_interrupt_state,
4731         .process = gfx_v9_0_eop_irq,
4732 };
4733
4734 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4735         .set = gfx_v9_0_set_priv_reg_fault_state,
4736         .process = gfx_v9_0_priv_reg_irq,
4737 };
4738
4739 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4740         .set = gfx_v9_0_set_priv_inst_fault_state,
4741         .process = gfx_v9_0_priv_inst_irq,
4742 };
4743
4744 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4745 {
4746         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4747         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4748
4749         adev->gfx.priv_reg_irq.num_types = 1;
4750         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4751
4752         adev->gfx.priv_inst_irq.num_types = 1;
4753         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4754
4755         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4756         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4757 }
4758
4759 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4760 {
4761         switch (adev->asic_type) {
4762         case CHIP_VEGA10:
4763         case CHIP_VEGA12:
4764         case CHIP_VEGA20:
4765         case CHIP_RAVEN:
4766                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4767                 break;
4768         default:
4769                 break;
4770         }
4771 }
4772
4773 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4774 {
4775         /* init asci gds info */
4776         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4777         adev->gds.gws.total_size = 64;
4778         adev->gds.oa.total_size = 16;
4779
4780         if (adev->gds.mem.total_size == 64 * 1024) {
4781                 adev->gds.mem.gfx_partition_size = 4096;
4782                 adev->gds.mem.cs_partition_size = 4096;
4783
4784                 adev->gds.gws.gfx_partition_size = 4;
4785                 adev->gds.gws.cs_partition_size = 4;
4786
4787                 adev->gds.oa.gfx_partition_size = 4;
4788                 adev->gds.oa.cs_partition_size = 1;
4789         } else {
4790                 adev->gds.mem.gfx_partition_size = 1024;
4791                 adev->gds.mem.cs_partition_size = 1024;
4792
4793                 adev->gds.gws.gfx_partition_size = 16;
4794                 adev->gds.gws.cs_partition_size = 16;
4795
4796                 adev->gds.oa.gfx_partition_size = 4;
4797                 adev->gds.oa.cs_partition_size = 4;
4798         }
4799 }
4800
4801 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4802                                                  u32 bitmap)
4803 {
4804         u32 data;
4805
4806         if (!bitmap)
4807                 return;
4808
4809         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4810         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4811
4812         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4813 }
4814
4815 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4816 {
4817         u32 data, mask;
4818
4819         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4820         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4821
4822         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4823         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4824
4825         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4826
4827         return (~data) & mask;
4828 }
4829
4830 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4831                                  struct amdgpu_cu_info *cu_info)
4832 {
4833         int i, j, k, counter, active_cu_number = 0;
4834         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4835         unsigned disable_masks[4 * 2];
4836
4837         if (!adev || !cu_info)
4838                 return -EINVAL;
4839
4840         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4841
4842         mutex_lock(&adev->grbm_idx_mutex);
4843         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4844                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4845                         mask = 1;
4846                         ao_bitmap = 0;
4847                         counter = 0;
4848                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4849                         if (i < 4 && j < 2)
4850                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4851                                         adev, disable_masks[i * 2 + j]);
4852                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4853                         cu_info->bitmap[i][j] = bitmap;
4854
4855                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4856                                 if (bitmap & mask) {
4857                                         if (counter < adev->gfx.config.max_cu_per_sh)
4858                                                 ao_bitmap |= mask;
4859                                         counter ++;
4860                                 }
4861                                 mask <<= 1;
4862                         }
4863                         active_cu_number += counter;
4864                         if (i < 2 && j < 2)
4865                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4866                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4867                 }
4868         }
4869         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4870         mutex_unlock(&adev->grbm_idx_mutex);
4871
4872         cu_info->number = active_cu_number;
4873         cu_info->ao_cu_mask = ao_cu_mask;
4874         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4875
4876         return 0;
4877 }
4878
4879 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4880 {
4881         .type = AMD_IP_BLOCK_TYPE_GFX,
4882         .major = 9,
4883         .minor = 0,
4884         .rev = 0,
4885         .funcs = &gfx_v9_0_ip_funcs,
4886 };