drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  42
  43 /*(DEBLOBBED)*/
  44
  45 static const u32 golden_settings_iceland_a11[] =
  46 {
  47         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  48         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  49         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  50         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  51 };
  52
  53 static const u32 iceland_mgcg_cgcg_init[] =
  54 {
  55         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  56 };
  57
  58 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  59 {
  60         switch (adev->asic_type) {
  61         case CHIP_TOPAZ:
  62                 amdgpu_program_register_sequence(adev,
  63                                                  iceland_mgcg_cgcg_init,
  64                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  65                 amdgpu_program_register_sequence(adev,
  66                                                  golden_settings_iceland_a11,
  67                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  68                 break;
  69         default:
  70                 break;
  71         }
  72 }
  73
  74 /**
  75  * gmc7_mc_wait_for_idle - wait for MC idle callback.
  76  *
  77  * @adev: amdgpu_device pointer
  78  *
  79  * Wait for the MC (memory controller) to be idle.
  80  * (evergreen+).
  81  * Returns 0 if the MC is idle, -1 if not.
  82  */
  83 int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev)
  84 {
  85         unsigned i;
  86         u32 tmp;
  87
  88         for (i = 0; i < adev->usec_timeout; i++) {
  89                 /* read MC_STATUS */
  90                 tmp = RREG32(mmSRBM_STATUS) & 0x1F00;
  91                 if (!tmp)
  92                         return 0;
  93                 udelay(1);
  94         }
  95         return -1;
  96 }
  97
  98 void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
  99                       struct amdgpu_mode_mc_save *save)
 100 {
 101         u32 blackout;
 102
 103         if (adev->mode_info.num_crtc)
 104                 amdgpu_display_stop_mc_access(adev, save);
 105
 106         amdgpu_asic_wait_for_mc_idle(adev);
 107
 108         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 109         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 110                 /* Block CPU access */
 111                 WREG32(mmBIF_FB_EN, 0);
 112                 /* blackout the MC */
 113                 blackout = REG_SET_FIELD(blackout,
 114                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 115                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 116         }
 117         /* wait for the MC to settle */
 118         udelay(100);
 119 }
 120
 121 void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
 122                         struct amdgpu_mode_mc_save *save)
 123 {
 124         u32 tmp;
 125
 126         /* unblackout the MC */
 127         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 128         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 129         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 130         /* allow CPU access */
 131         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 132         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 133         WREG32(mmBIF_FB_EN, tmp);
 134
 135         if (adev->mode_info.num_crtc)
 136                 amdgpu_display_resume_mc_access(adev, save);
 137 }
 138
 139 /**
 140  * gmc_v7_0_init_microcode - load ucode images from disk
 141  *
 142  * @adev: amdgpu_device pointer
 143  *
 144  * Use the firmware interface to load the ucode images into
 145  * the driver (not loaded into hw).
 146  * Returns 0 on success, error on failure.
 147  */
 148 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 149 {
 150         const char *chip_name;
 151         char fw_name[30];
 152         int err;
 153
 154         DRM_DEBUG("\n");
 155
 156         switch (adev->asic_type) {
 157         case CHIP_BONAIRE:
 158                 chip_name = "bonaire";
 159                 break;
 160         case CHIP_HAWAII:
 161                 chip_name = "hawaii";
 162                 break;
 163         case CHIP_TOPAZ:
 164                 chip_name = "topaz";
 165                 break;
 166         case CHIP_KAVERI:
 167         case CHIP_KABINI:
 168         case CHIP_MULLINS:
 169                 return 0;
 170         default: BUG();
 171         }
 172
 173         if (adev->asic_type == CHIP_TOPAZ)
 174                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 175         else
 176                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 177
 178         err = reject_firmware(&adev->mc.fw, fw_name, adev->dev);
 179         if (err)
 180                 goto out;
 181         err = amdgpu_ucode_validate(adev->mc.fw);
 182
 183 out:
 184         if (err) {
 185                 printk(KERN_ERR
 186                        "cik_mc: Failed to load firmware \"%s\"\n",
 187                        fw_name);
 188                 release_firmware(adev->mc.fw);
 189                 adev->mc.fw = NULL;
 190         }
 191         return err;
 192 }
 193
 194 /**
 195  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 196  *
 197  * @adev: amdgpu_device pointer
 198  *
 199  * Load the GDDR MC ucode into the hw (CIK).
 200  * Returns 0 on success, error on failure.
 201  */
 202 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 203 {
 204         const struct mc_firmware_header_v1_0 *hdr;
 205         const __le32 *fw_data = NULL;
 206         const __le32 *io_mc_regs = NULL;
 207         u32 running, blackout = 0;
 208         int i, ucode_size, regs_size;
 209
 210         if (!adev->mc.fw)
 211                 return -EINVAL;
 212
 213         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 214         amdgpu_ucode_print_mc_hdr(&hdr->header);
 215
 216         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 217         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 218         io_mc_regs = (const __le32 *)
 219                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 220         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 221         fw_data = (const __le32 *)
 222                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 223
 224         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 225
 226         if (running == 0) {
 227                 if (running) {
 228                         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 229                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 230                 }
 231
 232                 /* reset the engine and set to writable */
 233                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 234                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 235
 236                 /* load mc io regs */
 237                 for (i = 0; i < regs_size; i++) {
 238                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 239                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 240                 }
 241                 /* load the MC ucode */
 242                 for (i = 0; i < ucode_size; i++)
 243                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 244
 245                 /* put the engine back into the active state */
 246                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 247                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 248                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 249
 250                 /* wait for training to complete */
 251                 for (i = 0; i < adev->usec_timeout; i++) {
 252                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 253                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 254                                 break;
 255                         udelay(1);
 256                 }
 257                 for (i = 0; i < adev->usec_timeout; i++) {
 258                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 259                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 260                                 break;
 261                         udelay(1);
 262                 }
 263
 264                 if (running)
 265                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 266         }
 267
 268         return 0;
 269 }
 270
 271 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 272                                        struct amdgpu_mc *mc)
 273 {
 274         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 275                 /* leave room for at least 1024M GTT */
 276                 dev_warn(adev->dev, "limiting VRAM\n");
 277                 mc->real_vram_size = 0xFFC0000000ULL;
 278                 mc->mc_vram_size = 0xFFC0000000ULL;
 279         }
 280         amdgpu_vram_location(adev, &adev->mc, 0);
 281         adev->mc.gtt_base_align = 0;
 282         amdgpu_gtt_location(adev, mc);
 283 }
 284
 285 /**
 286  * gmc_v7_0_mc_program - program the GPU memory controller
 287  *
 288  * @adev: amdgpu_device pointer
 289  *
 290  * Set the location of vram, gart, and AGP in the GPU's
 291  * physical address space (CIK).
 292  */
 293 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 294 {
 295         struct amdgpu_mode_mc_save save;
 296         u32 tmp;
 297         int i, j;
 298
 299         /* Initialize HDP */
 300         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 301                 WREG32((0xb05 + j), 0x00000000);
 302                 WREG32((0xb06 + j), 0x00000000);
 303                 WREG32((0xb07 + j), 0x00000000);
 304                 WREG32((0xb08 + j), 0x00000000);
 305                 WREG32((0xb09 + j), 0x00000000);
 306         }
 307         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 308
 309         if (adev->mode_info.num_crtc)
 310                 amdgpu_display_set_vga_render_state(adev, false);
 311
 312         gmc_v7_0_mc_stop(adev, &save);
 313         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 314                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 315         }
 316         /* Update configuration */
 317         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 318                adev->mc.vram_start >> 12);
 319         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 320                adev->mc.vram_end >> 12);
 321         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 322                adev->vram_scratch.gpu_addr >> 12);
 323         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 324         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 325         WREG32(mmMC_VM_FB_LOCATION, tmp);
 326         /* XXX double check these! */
 327         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 328         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 329         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 330         WREG32(mmMC_VM_AGP_BASE, 0);
 331         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 332         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 333         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 334                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 335         }
 336         gmc_v7_0_mc_resume(adev, &save);
 337
 338         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 339
 340         tmp = RREG32(mmHDP_MISC_CNTL);
 341         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 342         WREG32(mmHDP_MISC_CNTL, tmp);
 343
 344         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 345         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 346 }
 347
 348 /**
 349  * gmc_v7_0_mc_init - initialize the memory controller driver params
 350  *
 351  * @adev: amdgpu_device pointer
 352  *
 353  * Look up the amount of vram, vram width, and decide how to place
 354  * vram and gart within the GPU's physical address space (CIK).
 355  * Returns 0 for success.
 356  */
 357 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 358 {
 359         u32 tmp;
 360         int chansize, numchan;
 361
 362         /* Get VRAM informations */
 363         tmp = RREG32(mmMC_ARB_RAMCFG);
 364         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 365                 chansize = 64;
 366         } else {
 367                 chansize = 32;
 368         }
 369         tmp = RREG32(mmMC_SHARED_CHMAP);
 370         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 371         case 0:
 372         default:
 373                 numchan = 1;
 374                 break;
 375         case 1:
 376                 numchan = 2;
 377                 break;
 378         case 2:
 379                 numchan = 4;
 380                 break;
 381         case 3:
 382                 numchan = 8;
 383                 break;
 384         case 4:
 385                 numchan = 3;
 386                 break;
 387         case 5:
 388                 numchan = 6;
 389                 break;
 390         case 6:
 391                 numchan = 10;
 392                 break;
 393         case 7:
 394                 numchan = 12;
 395                 break;
 396         case 8:
 397                 numchan = 16;
 398                 break;
 399         }
 400         adev->mc.vram_width = numchan * chansize;
 401         /* Could aper size report 0 ? */
 402         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 403         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 404         /* size in MB on si */
 405         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 406         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 407         adev->mc.visible_vram_size = adev->mc.aper_size;
 408
 409         /* unless the user had overridden it, set the gart
 410          * size equal to the 1024 or vram, whichever is larger.
 411          */
 412         if (amdgpu_gart_size == -1)
 413                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 414         else
 415                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 416
 417         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 418
 419         return 0;
 420 }
 421
 422 /*
 423  * GART
 424  * VMID 0 is the physical GPU addresses as used by the kernel.
 425  * VMIDs 1-15 are used for userspace clients and are handled
 426  * by the amdgpu vm/hsa code.
 427  */
 428
 429 /**
 430  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 431  *
 432  * @adev: amdgpu_device pointer
 433  * @vmid: vm instance to flush
 434  *
 435  * Flush the TLB for the requested page table (CIK).
 436  */
 437 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 438                                         uint32_t vmid)
 439 {
 440         /* flush hdp cache */
 441         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 442
 443         /* bits 0-15 are the VM contexts0-15 */
 444         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 445 }
 446
 447 /**
 448  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 449  *
 450  * @adev: amdgpu_device pointer
 451  * @cpu_pt_addr: cpu address of the page table
 452  * @gpu_page_idx: entry in the page table to update
 453  * @addr: dst addr to write into pte/pde
 454  * @flags: access flags
 455  *
 456  * Update the page tables using the CPU.
 457  */
 458 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 459                                      void *cpu_pt_addr,
 460                                      uint32_t gpu_page_idx,
 461                                      uint64_t addr,
 462                                      uint32_t flags)
 463 {
 464         void __iomem *ptr = (void *)cpu_pt_addr;
 465         uint64_t value;
 466
 467         value = addr & 0xFFFFFFFFFFFFF000ULL;
 468         value |= flags;
 469         writeq(value, ptr + (gpu_page_idx * 8));
 470
 471         return 0;
 472 }
 473
 474 /**
 475  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 476  *
 477  * @adev: amdgpu_device pointer
 478  * @value: true redirects VM faults to the default page
 479  */
 480 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 481                                               bool value)
 482 {
 483         u32 tmp;
 484
 485         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 486         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 487                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 488         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 489                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 490         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 491                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 492         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 493                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 494         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 495                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 496         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 497                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 498         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 499 }
 500
 501 /**
 502  * gmc_v7_0_gart_enable - gart enable
 503  *
 504  * @adev: amdgpu_device pointer
 505  *
 506  * This sets up the TLBs, programs the page tables for VMID0,
 507  * sets up the hw for VMIDs 1-15 which are allocated on
 508  * demand, and sets up the global locations for the LDS, GDS,
 509  * and GPUVM for FSA64 clients (CIK).
 510  * Returns 0 for success, errors for failure.
 511  */
 512 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 513 {
 514         int r, i;
 515         u32 tmp;
 516
 517         if (adev->gart.robj == NULL) {
 518                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 519                 return -EINVAL;
 520         }
 521         r = amdgpu_gart_table_vram_pin(adev);
 522         if (r)
 523                 return r;
 524         /* Setup TLB control */
 525         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 526         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 527         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 528         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 529         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 530         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 531         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 532         /* Setup L2 cache */
 533         tmp = RREG32(mmVM_L2_CNTL);
 534         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 535         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 536         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 537         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 538         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 539         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 540         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 541         WREG32(mmVM_L2_CNTL, tmp);
 542         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 543         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 544         WREG32(mmVM_L2_CNTL2, tmp);
 545         tmp = RREG32(mmVM_L2_CNTL3);
 546         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 547         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 548         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 549         WREG32(mmVM_L2_CNTL3, tmp);
 550         /* setup context0 */
 551         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 552         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 553         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 554         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 555                         (u32)(adev->dummy_page.addr >> 12));
 556         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 557         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 558         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 559         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 560         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 561         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 562
 563         WREG32(0x575, 0);
 564         WREG32(0x576, 0);
 565         WREG32(0x577, 0);
 566
 567         /* empty context1-15 */
 568         /* FIXME start with 4G, once using 2 level pt switch to full
 569          * vm size space
 570          */
 571         /* set vm size, must be a multiple of 4 */
 572         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 573         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 574         for (i = 1; i < 16; i++) {
 575                 if (i < 8)
 576                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 577                                adev->gart.table_addr >> 12);
 578                 else
 579                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 580                                adev->gart.table_addr >> 12);
 581         }
 582
 583         /* enable context1-15 */
 584         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 585                (u32)(adev->dummy_page.addr >> 12));
 586         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 587         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 588         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 589         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 590         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 591                             amdgpu_vm_block_size - 9);
 592         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 593         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 594                 gmc_v7_0_set_fault_enable_default(adev, false);
 595         else
 596                 gmc_v7_0_set_fault_enable_default(adev, true);
 597
 598         if (adev->asic_type == CHIP_KAVERI) {
 599                 tmp = RREG32(mmCHUB_CONTROL);
 600                 tmp &= ~BYPASS_VM;
 601                 WREG32(mmCHUB_CONTROL, tmp);
 602         }
 603
 604         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 605         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 606                  (unsigned)(adev->mc.gtt_size >> 20),
 607                  (unsigned long long)adev->gart.table_addr);
 608         adev->gart.ready = true;
 609         return 0;
 610 }
 611
 612 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 613 {
 614         int r;
 615
 616         if (adev->gart.robj) {
 617                 WARN(1, "R600 PCIE GART already initialized\n");
 618                 return 0;
 619         }
 620         /* Initialize common gart structure */
 621         r = amdgpu_gart_init(adev);
 622         if (r)
 623                 return r;
 624         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 625         return amdgpu_gart_table_vram_alloc(adev);
 626 }
 627
 628 /**
 629  * gmc_v7_0_gart_disable - gart disable
 630  *
 631  * @adev: amdgpu_device pointer
 632  *
 633  * This disables all VM page table (CIK).
 634  */
 635 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 636 {
 637         u32 tmp;
 638
 639         /* Disable all tables */
 640         WREG32(mmVM_CONTEXT0_CNTL, 0);
 641         WREG32(mmVM_CONTEXT1_CNTL, 0);
 642         /* Setup TLB control */
 643         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 644         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 645         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 646         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 647         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 648         /* Setup L2 cache */
 649         tmp = RREG32(mmVM_L2_CNTL);
 650         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 651         WREG32(mmVM_L2_CNTL, tmp);
 652         WREG32(mmVM_L2_CNTL2, 0);
 653         amdgpu_gart_table_vram_unpin(adev);
 654 }
 655
 656 /**
 657  * gmc_v7_0_gart_fini - vm fini callback
 658  *
 659  * @adev: amdgpu_device pointer
 660  *
 661  * Tears down the driver GART/VM setup (CIK).
 662  */
 663 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 664 {
 665         amdgpu_gart_table_vram_free(adev);
 666         amdgpu_gart_fini(adev);
 667 }
 668
 669 /*
 670  * vm
 671  * VMID 0 is the physical GPU addresses as used by the kernel.
 672  * VMIDs 1-15 are used for userspace clients and are handled
 673  * by the amdgpu vm/hsa code.
 674  */
 675 /**
 676  * gmc_v7_0_vm_init - cik vm init callback
 677  *
 678  * @adev: amdgpu_device pointer
 679  *
 680  * Inits cik specific vm parameters (number of VMs, base of vram for
 681  * VMIDs 1-15) (CIK).
 682  * Returns 0 for success.
 683  */
 684 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 685 {
 686         /*
 687          * number of VMs
 688          * VMID 0 is reserved for System
 689          * amdgpu graphics/compute will use VMIDs 1-7
 690          * amdkfd will use VMIDs 8-15
 691          */
 692         adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
 693
 694         /* base offset of vram pages */
 695         if (adev->flags & AMD_IS_APU) {
 696                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 697                 tmp <<= 22;
 698                 adev->vm_manager.vram_base_offset = tmp;
 699         } else
 700                 adev->vm_manager.vram_base_offset = 0;
 701
 702         return 0;
 703 }
 704
 705 /**
 706  * gmc_v7_0_vm_fini - cik vm fini callback
 707  *
 708  * @adev: amdgpu_device pointer
 709  *
 710  * Tear down any asic specific VM setup (CIK).
 711  */
 712 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
 713 {
 714 }
 715
 716 /**
 717  * gmc_v7_0_vm_decode_fault - print human readable fault info
 718  *
 719  * @adev: amdgpu_device pointer
 720  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 721  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 722  *
 723  * Print human readable fault information (CIK).
 724  */
 725 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 726                                      u32 status, u32 addr, u32 mc_client)
 727 {
 728         u32 mc_id;
 729         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 730         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 731                                         PROTECTIONS);
 732         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 733                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 734
 735         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 736                               MEMORY_CLIENT_ID);
 737
 738         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 739                protections, vmid, addr,
 740                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 741                              MEMORY_CLIENT_RW) ?
 742                "write" : "read", block, mc_client, mc_id);
 743 }
 744
 745
 746 static const u32 mc_cg_registers[] = {
 747         mmMC_HUB_MISC_HUB_CG,
 748         mmMC_HUB_MISC_SIP_CG,
 749         mmMC_HUB_MISC_VM_CG,
 750         mmMC_XPB_CLK_GAT,
 751         mmATC_MISC_CG,
 752         mmMC_CITF_MISC_WR_CG,
 753         mmMC_CITF_MISC_RD_CG,
 754         mmMC_CITF_MISC_VM_CG,
 755         mmVM_L2_CG,
 756 };
 757
 758 static const u32 mc_cg_ls_en[] = {
 759         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 760         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 761         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 762         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 763         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 764         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 765         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 766         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 767         VM_L2_CG__MEM_LS_ENABLE_MASK,
 768 };
 769
 770 static const u32 mc_cg_en[] = {
 771         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 772         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 773         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 774         MC_XPB_CLK_GAT__ENABLE_MASK,
 775         ATC_MISC_CG__ENABLE_MASK,
 776         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 777         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 778         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 779         VM_L2_CG__ENABLE_MASK,
 780 };
 781
 782 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 783                                   bool enable)
 784 {
 785         int i;
 786         u32 orig, data;
 787
 788         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 789                 orig = data = RREG32(mc_cg_registers[i]);
 790                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 791                         data |= mc_cg_ls_en[i];
 792                 else
 793                         data &= ~mc_cg_ls_en[i];
 794                 if (data != orig)
 795                         WREG32(mc_cg_registers[i], data);
 796         }
 797 }
 798
 799 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 800                                     bool enable)
 801 {
 802         int i;
 803         u32 orig, data;
 804
 805         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 806                 orig = data = RREG32(mc_cg_registers[i]);
 807                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 808                         data |= mc_cg_en[i];
 809                 else
 810                         data &= ~mc_cg_en[i];
 811                 if (data != orig)
 812                         WREG32(mc_cg_registers[i], data);
 813         }
 814 }
 815
 816 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 817                                      bool enable)
 818 {
 819         u32 orig, data;
 820
 821         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 822
 823         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 824                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 825                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 826                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 827                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 828         } else {
 829                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 830                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 831                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 832                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 833         }
 834
 835         if (orig != data)
 836                 WREG32_PCIE(ixPCIE_CNTL2, data);
 837 }
 838
 839 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 840                                      bool enable)
 841 {
 842         u32 orig, data;
 843
 844         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 845
 846         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 847                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 848         else
 849                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 850
 851         if (orig != data)
 852                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 853 }
 854
 855 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 856                                    bool enable)
 857 {
 858         u32 orig, data;
 859
 860         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 861
 862         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 863                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 864         else
 865                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 866
 867         if (orig != data)
 868                 WREG32(mmHDP_MEM_POWER_LS, data);
 869 }
 870
 871 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 872 {
 873         switch (mc_seq_vram_type) {
 874         case MC_SEQ_MISC0__MT__GDDR1:
 875                 return AMDGPU_VRAM_TYPE_GDDR1;
 876         case MC_SEQ_MISC0__MT__DDR2:
 877                 return AMDGPU_VRAM_TYPE_DDR2;
 878         case MC_SEQ_MISC0__MT__GDDR3:
 879                 return AMDGPU_VRAM_TYPE_GDDR3;
 880         case MC_SEQ_MISC0__MT__GDDR4:
 881                 return AMDGPU_VRAM_TYPE_GDDR4;
 882         case MC_SEQ_MISC0__MT__GDDR5:
 883                 return AMDGPU_VRAM_TYPE_GDDR5;
 884         case MC_SEQ_MISC0__MT__HBM:
 885                 return AMDGPU_VRAM_TYPE_HBM;
 886         case MC_SEQ_MISC0__MT__DDR3:
 887                 return AMDGPU_VRAM_TYPE_DDR3;
 888         default:
 889                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 890         }
 891 }
 892
 893 static int gmc_v7_0_early_init(void *handle)
 894 {
 895         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 896
 897         gmc_v7_0_set_gart_funcs(adev);
 898         gmc_v7_0_set_irq_funcs(adev);
 899
 900         return 0;
 901 }
 902
 903 static int gmc_v7_0_late_init(void *handle)
 904 {
 905         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 906
 907         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 908 }
 909
 910 static int gmc_v7_0_sw_init(void *handle)
 911 {
 912         int r;
 913         int dma_bits;
 914         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 915
 916         r = amdgpu_gem_init(adev);
 917         if (r)
 918                 return r;
 919
 920         if (adev->flags & AMD_IS_APU) {
 921                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 922         } else {
 923                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 924                 tmp &= MC_SEQ_MISC0__MT__MASK;
 925                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 926         }
 927
 928         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 929         if (r)
 930                 return r;
 931
 932         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 933         if (r)
 934                 return r;
 935
 936         /* Adjust VM size here.
 937          * Currently set to 4GB ((1 << 20) 4k pages).
 938          * Max GPUVM size for cayman and SI is 40 bits.
 939          */
 940         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 941
 942         /* Set the internal MC address mask
 943          * This is the max address of the GPU's
 944          * internal address space.
 945          */
 946         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 947
 948         /* set DMA mask + need_dma32 flags.
 949          * PCIE - can handle 40-bits.
 950          * IGP - can handle 40-bits
 951          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 952          */
 953         adev->need_dma32 = false;
 954         dma_bits = adev->need_dma32 ? 32 : 40;
 955         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 956         if (r) {
 957                 adev->need_dma32 = true;
 958                 dma_bits = 32;
 959                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 960         }
 961         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 962         if (r) {
 963                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 964                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 965         }
 966
 967         r = gmc_v7_0_init_microcode(adev);
 968         if (r) {
 969                 DRM_ERROR("Failed to load mc firmware!\n");
 970                 return r;
 971         }
 972
 973         r = gmc_v7_0_mc_init(adev);
 974         if (r)
 975                 return r;
 976
 977         /* Memory manager */
 978         r = amdgpu_bo_init(adev);
 979         if (r)
 980                 return r;
 981
 982         r = gmc_v7_0_gart_init(adev);
 983         if (r)
 984                 return r;
 985
 986         if (!adev->vm_manager.enabled) {
 987                 r = gmc_v7_0_vm_init(adev);
 988                 if (r) {
 989                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 990                         return r;
 991                 }
 992                 adev->vm_manager.enabled = true;
 993         }
 994
 995         return r;
 996 }
 997
 998 static int gmc_v7_0_sw_fini(void *handle)
 999 {
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         if (adev->vm_manager.enabled) {
1003                 amdgpu_vm_manager_fini(adev);
1004                 gmc_v7_0_vm_fini(adev);
1005                 adev->vm_manager.enabled = false;
1006         }
1007         gmc_v7_0_gart_fini(adev);
1008         amdgpu_gem_fini(adev);
1009         amdgpu_bo_fini(adev);
1010
1011         return 0;
1012 }
1013
1014 static int gmc_v7_0_hw_init(void *handle)
1015 {
1016         int r;
1017         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019         gmc_v7_0_init_golden_registers(adev);
1020
1021         gmc_v7_0_mc_program(adev);
1022
1023         if (!(adev->flags & AMD_IS_APU)) {
1024                 r = gmc_v7_0_mc_load_microcode(adev);
1025                 if (r) {
1026                         DRM_ERROR("Failed to load MC firmware!\n");
1027                         return r;
1028                 }
1029         }
1030
1031         r = gmc_v7_0_gart_enable(adev);
1032         if (r)
1033                 return r;
1034
1035         return r;
1036 }
1037
1038 static int gmc_v7_0_hw_fini(void *handle)
1039 {
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041
1042         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1043         gmc_v7_0_gart_disable(adev);
1044
1045         return 0;
1046 }
1047
1048 static int gmc_v7_0_suspend(void *handle)
1049 {
1050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1051
1052         if (adev->vm_manager.enabled) {
1053                 amdgpu_vm_manager_fini(adev);
1054                 gmc_v7_0_vm_fini(adev);
1055                 adev->vm_manager.enabled = false;
1056         }
1057         gmc_v7_0_hw_fini(adev);
1058
1059         return 0;
1060 }
1061
1062 static int gmc_v7_0_resume(void *handle)
1063 {
1064         int r;
1065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1066
1067         r = gmc_v7_0_hw_init(adev);
1068         if (r)
1069                 return r;
1070
1071         if (!adev->vm_manager.enabled) {
1072                 r = gmc_v7_0_vm_init(adev);
1073                 if (r) {
1074                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1075                         return r;
1076                 }
1077                 adev->vm_manager.enabled = true;
1078         }
1079
1080         return r;
1081 }
1082
1083 static bool gmc_v7_0_is_idle(void *handle)
1084 {
1085         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1086         u32 tmp = RREG32(mmSRBM_STATUS);
1087
1088         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1089                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1090                 return false;
1091
1092         return true;
1093 }
1094
1095 static int gmc_v7_0_wait_for_idle(void *handle)
1096 {
1097         unsigned i;
1098         u32 tmp;
1099         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1100
1101         for (i = 0; i < adev->usec_timeout; i++) {
1102                 /* read MC_STATUS */
1103                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1104                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1105                                                SRBM_STATUS__MCC_BUSY_MASK |
1106                                                SRBM_STATUS__MCD_BUSY_MASK |
1107                                                SRBM_STATUS__VMC_BUSY_MASK);
1108                 if (!tmp)
1109                         return 0;
1110                 udelay(1);
1111         }
1112         return -ETIMEDOUT;
1113
1114 }
1115
1116 static void gmc_v7_0_print_status(void *handle)
1117 {
1118         int i, j;
1119         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120
1121         dev_info(adev->dev, "GMC 8.x registers\n");
1122         dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
1123                 RREG32(mmSRBM_STATUS));
1124         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1125                 RREG32(mmSRBM_STATUS2));
1126
1127         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1128                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1129         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1130                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1131         dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1132                  RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1133         dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
1134                  RREG32(mmVM_L2_CNTL));
1135         dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
1136                  RREG32(mmVM_L2_CNTL2));
1137         dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
1138                  RREG32(mmVM_L2_CNTL3));
1139         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1140                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1141         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1142                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1143         dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1144                  RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1145         dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
1146                  RREG32(mmVM_CONTEXT0_CNTL2));
1147         dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
1148                  RREG32(mmVM_CONTEXT0_CNTL));
1149         dev_info(adev->dev, "  0x15D4=0x%08X\n",
1150                  RREG32(0x575));
1151         dev_info(adev->dev, "  0x15D8=0x%08X\n",
1152                  RREG32(0x576));
1153         dev_info(adev->dev, "  0x15DC=0x%08X\n",
1154                  RREG32(0x577));
1155         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1156                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1157         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1158                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1159         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1160                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1161         dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
1162                  RREG32(mmVM_CONTEXT1_CNTL2));
1163         dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
1164                  RREG32(mmVM_CONTEXT1_CNTL));
1165         for (i = 0; i < 16; i++) {
1166                 if (i < 8)
1167                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1168                                  i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1169                 else
1170                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1171                                  i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1172         }
1173         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1174                  RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1175         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1176                  RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1177         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1178                  RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1179         dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
1180                  RREG32(mmMC_VM_FB_LOCATION));
1181         dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
1182                  RREG32(mmMC_VM_AGP_BASE));
1183         dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
1184                  RREG32(mmMC_VM_AGP_TOP));
1185         dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
1186                  RREG32(mmMC_VM_AGP_BOT));
1187
1188         if (adev->asic_type == CHIP_KAVERI) {
1189                 dev_info(adev->dev, "  CHUB_CONTROL=0x%08X\n",
1190                          RREG32(mmCHUB_CONTROL));
1191         }
1192
1193         dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1194                  RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1195         dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
1196                  RREG32(mmHDP_NONSURFACE_BASE));
1197         dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
1198                  RREG32(mmHDP_NONSURFACE_INFO));
1199         dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
1200                  RREG32(mmHDP_NONSURFACE_SIZE));
1201         dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
1202                  RREG32(mmHDP_MISC_CNTL));
1203         dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
1204                  RREG32(mmHDP_HOST_PATH_CNTL));
1205
1206         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1207                 dev_info(adev->dev, "  %d:\n", i);
1208                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1209                          0xb05 + j, RREG32(0xb05 + j));
1210                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1211                          0xb06 + j, RREG32(0xb06 + j));
1212                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1213                          0xb07 + j, RREG32(0xb07 + j));
1214                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1215                          0xb08 + j, RREG32(0xb08 + j));
1216                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1217                          0xb09 + j, RREG32(0xb09 + j));
1218         }
1219
1220         dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
1221                  RREG32(mmBIF_FB_EN));
1222 }
1223
1224 static int gmc_v7_0_soft_reset(void *handle)
1225 {
1226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227         struct amdgpu_mode_mc_save save;
1228         u32 srbm_soft_reset = 0;
1229         u32 tmp = RREG32(mmSRBM_STATUS);
1230
1231         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1232                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1233                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1234
1235         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1236                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1237                 if (!(adev->flags & AMD_IS_APU))
1238                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1239                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1240         }
1241
1242         if (srbm_soft_reset) {
1243                 gmc_v7_0_print_status((void *)adev);
1244
1245                 gmc_v7_0_mc_stop(adev, &save);
1246                 if (gmc_v7_0_wait_for_idle(adev)) {
1247                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1248                 }
1249
1250
1251                 tmp = RREG32(mmSRBM_SOFT_RESET);
1252                 tmp |= srbm_soft_reset;
1253                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1254                 WREG32(mmSRBM_SOFT_RESET, tmp);
1255                 tmp = RREG32(mmSRBM_SOFT_RESET);
1256
1257                 udelay(50);
1258
1259                 tmp &= ~srbm_soft_reset;
1260                 WREG32(mmSRBM_SOFT_RESET, tmp);
1261                 tmp = RREG32(mmSRBM_SOFT_RESET);
1262
1263                 /* Wait a little for things to settle down */
1264                 udelay(50);
1265
1266                 gmc_v7_0_mc_resume(adev, &save);
1267                 udelay(50);
1268
1269                 gmc_v7_0_print_status((void *)adev);
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1276                                              struct amdgpu_irq_src *src,
1277                                              unsigned type,
1278                                              enum amdgpu_interrupt_state state)
1279 {
1280         u32 tmp;
1281         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1282                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1283                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1284                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1285                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1286                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1287
1288         switch (state) {
1289         case AMDGPU_IRQ_STATE_DISABLE:
1290                 /* system context */
1291                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1292                 tmp &= ~bits;
1293                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1294                 /* VMs */
1295                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1296                 tmp &= ~bits;
1297                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1298                 break;
1299         case AMDGPU_IRQ_STATE_ENABLE:
1300                 /* system context */
1301                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1302                 tmp |= bits;
1303                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1304                 /* VMs */
1305                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1306                 tmp |= bits;
1307                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1308                 break;
1309         default:
1310                 break;
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1317                                       struct amdgpu_irq_src *source,
1318                                       struct amdgpu_iv_entry *entry)
1319 {
1320         u32 addr, status, mc_client;
1321
1322         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1323         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1324         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1325         /* reset addr and status */
1326         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1327
1328         if (!addr && !status)
1329                 return 0;
1330
1331         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1332                 gmc_v7_0_set_fault_enable_default(adev, false);
1333
1334         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1335                 entry->src_id, entry->src_data);
1336         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1337                 addr);
1338         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1339                 status);
1340         gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1341
1342         return 0;
1343 }
1344
1345 static int gmc_v7_0_set_clockgating_state(void *handle,
1346                                           enum amd_clockgating_state state)
1347 {
1348         bool gate = false;
1349         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350
1351         if (state == AMD_CG_STATE_GATE)
1352                 gate = true;
1353
1354         if (!(adev->flags & AMD_IS_APU)) {
1355                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1356                 gmc_v7_0_enable_mc_ls(adev, gate);
1357         }
1358         gmc_v7_0_enable_bif_mgls(adev, gate);
1359         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1360         gmc_v7_0_enable_hdp_ls(adev, gate);
1361
1362         return 0;
1363 }
1364
1365 static int gmc_v7_0_set_powergating_state(void *handle,
1366                                           enum amd_powergating_state state)
1367 {
1368         return 0;
1369 }
1370
1371 const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1372         .early_init = gmc_v7_0_early_init,
1373         .late_init = gmc_v7_0_late_init,
1374         .sw_init = gmc_v7_0_sw_init,
1375         .sw_fini = gmc_v7_0_sw_fini,
1376         .hw_init = gmc_v7_0_hw_init,
1377         .hw_fini = gmc_v7_0_hw_fini,
1378         .suspend = gmc_v7_0_suspend,
1379         .resume = gmc_v7_0_resume,
1380         .is_idle = gmc_v7_0_is_idle,
1381         .wait_for_idle = gmc_v7_0_wait_for_idle,
1382         .soft_reset = gmc_v7_0_soft_reset,
1383         .print_status = gmc_v7_0_print_status,
1384         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1385         .set_powergating_state = gmc_v7_0_set_powergating_state,
1386 };
1387
1388 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1389         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1390         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1391 };
1392
1393 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1394         .set = gmc_v7_0_vm_fault_interrupt_state,
1395         .process = gmc_v7_0_process_interrupt,
1396 };
1397
1398 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1399 {
1400         if (adev->gart.gart_funcs == NULL)
1401                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1402 }
1403
1404 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1405 {
1406         adev->mc.vm_fault.num_types = 1;
1407         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1408 }