drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41
  42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int gmc_v8_0_wait_for_idle(void *handle);
  45
  46 /*(DEBLOBBED)*/
  47
  48 static const u32 golden_settings_tonga_a11[] =
  49 {
  50         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  51         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  52         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  53         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  54         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  55         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  57 };
  58
  59 static const u32 tonga_mgcg_cgcg_init[] =
  60 {
  61         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  62 };
  63
  64 static const u32 golden_settings_fiji_a10[] =
  65 {
  66         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  67         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  68         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  69         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  70 };
  71
  72 static const u32 fiji_mgcg_cgcg_init[] =
  73 {
  74         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  75 };
  76
  77 static const u32 golden_settings_polaris11_a11[] =
  78 {
  79         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  80         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  81         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  82         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  83 };
  84
  85 static const u32 golden_settings_polaris10_a11[] =
  86 {
  87         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  88         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  89         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  91         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  92 };
  93
  94 static const u32 cz_mgcg_cgcg_init[] =
  95 {
  96         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  97 };
  98
  99 static const u32 stoney_mgcg_cgcg_init[] =
 100 {
 101         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 102         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 103 };
 104
 105 static const u32 golden_settings_stoney_common[] =
 106 {
 107         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 108         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 109 };
 110
 111 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 112 {
 113         switch (adev->asic_type) {
 114         case CHIP_FIJI:
 115                 amdgpu_program_register_sequence(adev,
 116                                                  fiji_mgcg_cgcg_init,
 117                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 118                 amdgpu_program_register_sequence(adev,
 119                                                  golden_settings_fiji_a10,
 120                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 121                 break;
 122         case CHIP_TONGA:
 123                 amdgpu_program_register_sequence(adev,
 124                                                  tonga_mgcg_cgcg_init,
 125                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 126                 amdgpu_program_register_sequence(adev,
 127                                                  golden_settings_tonga_a11,
 128                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 129                 break;
 130         case CHIP_POLARIS11:
 131                 amdgpu_program_register_sequence(adev,
 132                                                  golden_settings_polaris11_a11,
 133                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 134                 break;
 135         case CHIP_POLARIS10:
 136                 amdgpu_program_register_sequence(adev,
 137                                                  golden_settings_polaris10_a11,
 138                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 139                 break;
 140         case CHIP_CARRIZO:
 141                 amdgpu_program_register_sequence(adev,
 142                                                  cz_mgcg_cgcg_init,
 143                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 144                 break;
 145         case CHIP_STONEY:
 146                 amdgpu_program_register_sequence(adev,
 147                                                  stoney_mgcg_cgcg_init,
 148                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 149                 amdgpu_program_register_sequence(adev,
 150                                                  golden_settings_stoney_common,
 151                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 152                 break;
 153         default:
 154                 break;
 155         }
 156 }
 157
 158 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
 159                              struct amdgpu_mode_mc_save *save)
 160 {
 161         u32 blackout;
 162
 163         if (adev->mode_info.num_crtc)
 164                 amdgpu_display_stop_mc_access(adev, save);
 165
 166         gmc_v8_0_wait_for_idle(adev);
 167
 168         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 169         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 170                 /* Block CPU access */
 171                 WREG32(mmBIF_FB_EN, 0);
 172                 /* blackout the MC */
 173                 blackout = REG_SET_FIELD(blackout,
 174                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 175                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 176         }
 177         /* wait for the MC to settle */
 178         udelay(100);
 179 }
 180
 181 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
 182                                struct amdgpu_mode_mc_save *save)
 183 {
 184         u32 tmp;
 185
 186         /* unblackout the MC */
 187         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 188         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 189         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 190         /* allow CPU access */
 191         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 192         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 193         WREG32(mmBIF_FB_EN, tmp);
 194
 195         if (adev->mode_info.num_crtc)
 196                 amdgpu_display_resume_mc_access(adev, save);
 197 }
 198
 199 /**
 200  * gmc_v8_0_init_microcode - load ucode images from disk
 201  *
 202  * @adev: amdgpu_device pointer
 203  *
 204  * Use the firmware interface to load the ucode images into
 205  * the driver (not loaded into hw).
 206  * Returns 0 on success, error on failure.
 207  */
 208 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 209 {
 210         const char *chip_name;
 211         char fw_name[30];
 212         int err;
 213
 214         DRM_DEBUG("\n");
 215
 216         switch (adev->asic_type) {
 217         case CHIP_TONGA:
 218                 chip_name = "tonga";
 219                 break;
 220         case CHIP_POLARIS11:
 221                 chip_name = "polaris11";
 222                 break;
 223         case CHIP_POLARIS10:
 224                 chip_name = "polaris10";
 225                 break;
 226         case CHIP_FIJI:
 227         case CHIP_CARRIZO:
 228         case CHIP_STONEY:
 229                 return 0;
 230         default: BUG();
 231         }
 232
 233         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 234         err = reject_firmware(&adev->mc.fw, fw_name, adev->dev);
 235         if (err)
 236                 goto out;
 237         err = amdgpu_ucode_validate(adev->mc.fw);
 238
 239 out:
 240         if (err) {
 241                 printk(KERN_ERR
 242                        "mc: Failed to load firmware \"%s\"\n",
 243                        fw_name);
 244                 release_firmware(adev->mc.fw);
 245                 adev->mc.fw = NULL;
 246         }
 247         return err;
 248 }
 249
 250 /**
 251  * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
 252  *
 253  * @adev: amdgpu_device pointer
 254  *
 255  * Load the GDDR MC ucode into the hw (CIK).
 256  * Returns 0 on success, error on failure.
 257  */
 258 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
 259 {
 260         const struct mc_firmware_header_v1_0 *hdr;
 261         const __le32 *fw_data = NULL;
 262         const __le32 *io_mc_regs = NULL;
 263         u32 running;
 264         int i, ucode_size, regs_size;
 265
 266         if (!adev->mc.fw)
 267                 return -EINVAL;
 268
 269         /* Skip MC ucode loading on SR-IOV capable boards.
 270          * vbios does this for us in asic_init in that case.
 271          * Skip MC ucode loading on VF, because hypervisor will do that
 272          * for this adaptor.
 273          */
 274         if (amdgpu_sriov_bios(adev))
 275                 return 0;
 276
 277         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 278         amdgpu_ucode_print_mc_hdr(&hdr->header);
 279
 280         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 281         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 282         io_mc_regs = (const __le32 *)
 283                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 284         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 285         fw_data = (const __le32 *)
 286                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 287
 288         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 289
 290         if (running == 0) {
 291                 /* reset the engine and set to writable */
 292                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 293                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 294
 295                 /* load mc io regs */
 296                 for (i = 0; i < regs_size; i++) {
 297                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 298                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 299                 }
 300                 /* load the MC ucode */
 301                 for (i = 0; i < ucode_size; i++)
 302                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 303
 304                 /* put the engine back into the active state */
 305                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 306                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 307                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 308
 309                 /* wait for training to complete */
 310                 for (i = 0; i < adev->usec_timeout; i++) {
 311                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 312                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 313                                 break;
 314                         udelay(1);
 315                 }
 316                 for (i = 0; i < adev->usec_timeout; i++) {
 317                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 318                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 319                                 break;
 320                         udelay(1);
 321                 }
 322         }
 323
 324         return 0;
 325 }
 326
 327 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 328                                        struct amdgpu_mc *mc)
 329 {
 330         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 331                 /* leave room for at least 1024M GTT */
 332                 dev_warn(adev->dev, "limiting VRAM\n");
 333                 mc->real_vram_size = 0xFFC0000000ULL;
 334                 mc->mc_vram_size = 0xFFC0000000ULL;
 335         }
 336         amdgpu_vram_location(adev, &adev->mc, 0);
 337         adev->mc.gtt_base_align = 0;
 338         amdgpu_gtt_location(adev, mc);
 339 }
 340
 341 /**
 342  * gmc_v8_0_mc_program - program the GPU memory controller
 343  *
 344  * @adev: amdgpu_device pointer
 345  *
 346  * Set the location of vram, gart, and AGP in the GPU's
 347  * physical address space (CIK).
 348  */
 349 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 350 {
 351         struct amdgpu_mode_mc_save save;
 352         u32 tmp;
 353         int i, j;
 354
 355         /* Initialize HDP */
 356         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 357                 WREG32((0xb05 + j), 0x00000000);
 358                 WREG32((0xb06 + j), 0x00000000);
 359                 WREG32((0xb07 + j), 0x00000000);
 360                 WREG32((0xb08 + j), 0x00000000);
 361                 WREG32((0xb09 + j), 0x00000000);
 362         }
 363         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 364
 365         if (adev->mode_info.num_crtc)
 366                 amdgpu_display_set_vga_render_state(adev, false);
 367
 368         gmc_v8_0_mc_stop(adev, &save);
 369         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 370                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 371         }
 372         /* Update configuration */
 373         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 374                adev->mc.vram_start >> 12);
 375         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 376                adev->mc.vram_end >> 12);
 377         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 378                adev->vram_scratch.gpu_addr >> 12);
 379         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 380         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 381         WREG32(mmMC_VM_FB_LOCATION, tmp);
 382         /* XXX double check these! */
 383         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 384         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 385         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 386         WREG32(mmMC_VM_AGP_BASE, 0);
 387         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 388         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 389         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 390                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 391         }
 392         gmc_v8_0_mc_resume(adev, &save);
 393
 394         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 395
 396         tmp = RREG32(mmHDP_MISC_CNTL);
 397         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 398         WREG32(mmHDP_MISC_CNTL, tmp);
 399
 400         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 401         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 402 }
 403
 404 /**
 405  * gmc_v8_0_mc_init - initialize the memory controller driver params
 406  *
 407  * @adev: amdgpu_device pointer
 408  *
 409  * Look up the amount of vram, vram width, and decide how to place
 410  * vram and gart within the GPU's physical address space (CIK).
 411  * Returns 0 for success.
 412  */
 413 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 414 {
 415         u32 tmp;
 416         int chansize, numchan;
 417
 418         /* Get VRAM informations */
 419         tmp = RREG32(mmMC_ARB_RAMCFG);
 420         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 421                 chansize = 64;
 422         } else {
 423                 chansize = 32;
 424         }
 425         tmp = RREG32(mmMC_SHARED_CHMAP);
 426         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 427         case 0:
 428         default:
 429                 numchan = 1;
 430                 break;
 431         case 1:
 432                 numchan = 2;
 433                 break;
 434         case 2:
 435                 numchan = 4;
 436                 break;
 437         case 3:
 438                 numchan = 8;
 439                 break;
 440         case 4:
 441                 numchan = 3;
 442                 break;
 443         case 5:
 444                 numchan = 6;
 445                 break;
 446         case 6:
 447                 numchan = 10;
 448                 break;
 449         case 7:
 450                 numchan = 12;
 451                 break;
 452         case 8:
 453                 numchan = 16;
 454                 break;
 455         }
 456         adev->mc.vram_width = numchan * chansize;
 457         /* Could aper size report 0 ? */
 458         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 459         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 460         /* size in MB on si */
 461         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 462         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 463         adev->mc.visible_vram_size = adev->mc.aper_size;
 464
 465         /* In case the PCI BAR is larger than the actual amount of vram */
 466         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 467                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 468
 469         /* unless the user had overridden it, set the gart
 470          * size equal to the 1024 or vram, whichever is larger.
 471          */
 472         if (amdgpu_gart_size == -1)
 473                 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
 474         else
 475                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 476
 477         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 478
 479         return 0;
 480 }
 481
 482 /*
 483  * GART
 484  * VMID 0 is the physical GPU addresses as used by the kernel.
 485  * VMIDs 1-15 are used for userspace clients and are handled
 486  * by the amdgpu vm/hsa code.
 487  */
 488
 489 /**
 490  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 491  *
 492  * @adev: amdgpu_device pointer
 493  * @vmid: vm instance to flush
 494  *
 495  * Flush the TLB for the requested page table (CIK).
 496  */
 497 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 498                                         uint32_t vmid)
 499 {
 500         /* flush hdp cache */
 501         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 502
 503         /* bits 0-15 are the VM contexts0-15 */
 504         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 505 }
 506
 507 /**
 508  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 509  *
 510  * @adev: amdgpu_device pointer
 511  * @cpu_pt_addr: cpu address of the page table
 512  * @gpu_page_idx: entry in the page table to update
 513  * @addr: dst addr to write into pte/pde
 514  * @flags: access flags
 515  *
 516  * Update the page tables using the CPU.
 517  */
 518 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 519                                      void *cpu_pt_addr,
 520                                      uint32_t gpu_page_idx,
 521                                      uint64_t addr,
 522                                      uint32_t flags)
 523 {
 524         void __iomem *ptr = (void *)cpu_pt_addr;
 525         uint64_t value;
 526
 527         /*
 528          * PTE format on VI:
 529          * 63:40 reserved
 530          * 39:12 4k physical page base address
 531          * 11:7 fragment
 532          * 6 write
 533          * 5 read
 534          * 4 exe
 535          * 3 reserved
 536          * 2 snooped
 537          * 1 system
 538          * 0 valid
 539          *
 540          * PDE format on VI:
 541          * 63:59 block fragment size
 542          * 58:40 reserved
 543          * 39:1 physical base address of PTE
 544          * bits 5:1 must be 0.
 545          * 0 valid
 546          */
 547         value = addr & 0x000000FFFFFFF000ULL;
 548         value |= flags;
 549         writeq(value, ptr + (gpu_page_idx * 8));
 550
 551         return 0;
 552 }
 553
 554 /**
 555  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 556  *
 557  * @adev: amdgpu_device pointer
 558  * @value: true redirects VM faults to the default page
 559  */
 560 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 561                                               bool value)
 562 {
 563         u32 tmp;
 564
 565         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 566         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 567                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 568         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 569                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 570         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 571                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 572         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 573                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 574         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 575                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 576         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 577                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 578         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 579                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 580         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 581 }
 582
 583 /**
 584  * gmc_v8_0_gart_enable - gart enable
 585  *
 586  * @adev: amdgpu_device pointer
 587  *
 588  * This sets up the TLBs, programs the page tables for VMID0,
 589  * sets up the hw for VMIDs 1-15 which are allocated on
 590  * demand, and sets up the global locations for the LDS, GDS,
 591  * and GPUVM for FSA64 clients (CIK).
 592  * Returns 0 for success, errors for failure.
 593  */
 594 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 595 {
 596         int r, i;
 597         u32 tmp;
 598
 599         if (adev->gart.robj == NULL) {
 600                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 601                 return -EINVAL;
 602         }
 603         r = amdgpu_gart_table_vram_pin(adev);
 604         if (r)
 605                 return r;
 606         /* Setup TLB control */
 607         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 608         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 609         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 610         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 611         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 612         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 613         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 614         /* Setup L2 cache */
 615         tmp = RREG32(mmVM_L2_CNTL);
 616         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 617         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 618         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 619         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 620         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 621         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 622         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 623         WREG32(mmVM_L2_CNTL, tmp);
 624         tmp = RREG32(mmVM_L2_CNTL2);
 625         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 626         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 627         WREG32(mmVM_L2_CNTL2, tmp);
 628         tmp = RREG32(mmVM_L2_CNTL3);
 629         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 630         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 631         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 632         WREG32(mmVM_L2_CNTL3, tmp);
 633         /* XXX: set to enable PTE/PDE in system memory */
 634         tmp = RREG32(mmVM_L2_CNTL4);
 635         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 636         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 637         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 638         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 639         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 640         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 641         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 642         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 643         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 644         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 645         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 646         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 647         WREG32(mmVM_L2_CNTL4, tmp);
 648         /* setup context0 */
 649         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 650         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 651         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 652         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 653                         (u32)(adev->dummy_page.addr >> 12));
 654         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 655         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 656         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 657         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 658         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 659         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 660
 661         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 662         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 663         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 664
 665         /* empty context1-15 */
 666         /* FIXME start with 4G, once using 2 level pt switch to full
 667          * vm size space
 668          */
 669         /* set vm size, must be a multiple of 4 */
 670         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 671         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 672         for (i = 1; i < 16; i++) {
 673                 if (i < 8)
 674                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 675                                adev->gart.table_addr >> 12);
 676                 else
 677                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 678                                adev->gart.table_addr >> 12);
 679         }
 680
 681         /* enable context1-15 */
 682         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 683                (u32)(adev->dummy_page.addr >> 12));
 684         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 685         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 686         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 687         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 688         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 689         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 690         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 691         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 692         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 693         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 694         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 695         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 696                             amdgpu_vm_block_size - 9);
 697         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 698         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 699                 gmc_v8_0_set_fault_enable_default(adev, false);
 700         else
 701                 gmc_v8_0_set_fault_enable_default(adev, true);
 702
 703         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 704         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 705                  (unsigned)(adev->mc.gtt_size >> 20),
 706                  (unsigned long long)adev->gart.table_addr);
 707         adev->gart.ready = true;
 708         return 0;
 709 }
 710
 711 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 712 {
 713         int r;
 714
 715         if (adev->gart.robj) {
 716                 WARN(1, "R600 PCIE GART already initialized\n");
 717                 return 0;
 718         }
 719         /* Initialize common gart structure */
 720         r = amdgpu_gart_init(adev);
 721         if (r)
 722                 return r;
 723         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 724         return amdgpu_gart_table_vram_alloc(adev);
 725 }
 726
 727 /**
 728  * gmc_v8_0_gart_disable - gart disable
 729  *
 730  * @adev: amdgpu_device pointer
 731  *
 732  * This disables all VM page table (CIK).
 733  */
 734 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 735 {
 736         u32 tmp;
 737
 738         /* Disable all tables */
 739         WREG32(mmVM_CONTEXT0_CNTL, 0);
 740         WREG32(mmVM_CONTEXT1_CNTL, 0);
 741         /* Setup TLB control */
 742         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 743         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 744         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 745         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 746         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 747         /* Setup L2 cache */
 748         tmp = RREG32(mmVM_L2_CNTL);
 749         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 750         WREG32(mmVM_L2_CNTL, tmp);
 751         WREG32(mmVM_L2_CNTL2, 0);
 752         amdgpu_gart_table_vram_unpin(adev);
 753 }
 754
 755 /**
 756  * gmc_v8_0_gart_fini - vm fini callback
 757  *
 758  * @adev: amdgpu_device pointer
 759  *
 760  * Tears down the driver GART/VM setup (CIK).
 761  */
 762 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 763 {
 764         amdgpu_gart_table_vram_free(adev);
 765         amdgpu_gart_fini(adev);
 766 }
 767
 768 /*
 769  * vm
 770  * VMID 0 is the physical GPU addresses as used by the kernel.
 771  * VMIDs 1-15 are used for userspace clients and are handled
 772  * by the amdgpu vm/hsa code.
 773  */
 774 /**
 775  * gmc_v8_0_vm_init - cik vm init callback
 776  *
 777  * @adev: amdgpu_device pointer
 778  *
 779  * Inits cik specific vm parameters (number of VMs, base of vram for
 780  * VMIDs 1-15) (CIK).
 781  * Returns 0 for success.
 782  */
 783 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 784 {
 785         /*
 786          * number of VMs
 787          * VMID 0 is reserved for System
 788          * amdgpu graphics/compute will use VMIDs 1-7
 789          * amdkfd will use VMIDs 8-15
 790          */
 791         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 792         amdgpu_vm_manager_init(adev);
 793
 794         /* base offset of vram pages */
 795         if (adev->flags & AMD_IS_APU) {
 796                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 797                 tmp <<= 22;
 798                 adev->vm_manager.vram_base_offset = tmp;
 799         } else
 800                 adev->vm_manager.vram_base_offset = 0;
 801
 802         return 0;
 803 }
 804
 805 /**
 806  * gmc_v8_0_vm_fini - cik vm fini callback
 807  *
 808  * @adev: amdgpu_device pointer
 809  *
 810  * Tear down any asic specific VM setup (CIK).
 811  */
 812 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
 813 {
 814 }
 815
 816 /**
 817  * gmc_v8_0_vm_decode_fault - print human readable fault info
 818  *
 819  * @adev: amdgpu_device pointer
 820  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 821  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 822  *
 823  * Print human readable fault information (CIK).
 824  */
 825 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 826                                      u32 status, u32 addr, u32 mc_client)
 827 {
 828         u32 mc_id;
 829         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 830         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 831                                         PROTECTIONS);
 832         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 833                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 834
 835         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 836                               MEMORY_CLIENT_ID);
 837
 838         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 839                protections, vmid, addr,
 840                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 841                              MEMORY_CLIENT_RW) ?
 842                "write" : "read", block, mc_client, mc_id);
 843 }
 844
 845 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 846 {
 847         switch (mc_seq_vram_type) {
 848         case MC_SEQ_MISC0__MT__GDDR1:
 849                 return AMDGPU_VRAM_TYPE_GDDR1;
 850         case MC_SEQ_MISC0__MT__DDR2:
 851                 return AMDGPU_VRAM_TYPE_DDR2;
 852         case MC_SEQ_MISC0__MT__GDDR3:
 853                 return AMDGPU_VRAM_TYPE_GDDR3;
 854         case MC_SEQ_MISC0__MT__GDDR4:
 855                 return AMDGPU_VRAM_TYPE_GDDR4;
 856         case MC_SEQ_MISC0__MT__GDDR5:
 857                 return AMDGPU_VRAM_TYPE_GDDR5;
 858         case MC_SEQ_MISC0__MT__HBM:
 859                 return AMDGPU_VRAM_TYPE_HBM;
 860         case MC_SEQ_MISC0__MT__DDR3:
 861                 return AMDGPU_VRAM_TYPE_DDR3;
 862         default:
 863                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 864         }
 865 }
 866
 867 static int gmc_v8_0_early_init(void *handle)
 868 {
 869         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 870
 871         gmc_v8_0_set_gart_funcs(adev);
 872         gmc_v8_0_set_irq_funcs(adev);
 873
 874         return 0;
 875 }
 876
 877 static int gmc_v8_0_late_init(void *handle)
 878 {
 879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 880
 881         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 882                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 883         else
 884                 return 0;
 885 }
 886
 887 #define mmMC_SEQ_MISC0_FIJI 0xA71
 888
 889 static int gmc_v8_0_sw_init(void *handle)
 890 {
 891         int r;
 892         int dma_bits;
 893         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 894
 895         if (adev->flags & AMD_IS_APU) {
 896                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 897         } else {
 898                 u32 tmp;
 899
 900                 if (adev->asic_type == CHIP_FIJI)
 901                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
 902                 else
 903                         tmp = RREG32(mmMC_SEQ_MISC0);
 904                 tmp &= MC_SEQ_MISC0__MT__MASK;
 905                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
 906         }
 907
 908         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 909         if (r)
 910                 return r;
 911
 912         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 913         if (r)
 914                 return r;
 915
 916         /* Adjust VM size here.
 917          * Currently set to 4GB ((1 << 20) 4k pages).
 918          * Max GPUVM size for cayman and SI is 40 bits.
 919          */
 920         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 921
 922         /* Set the internal MC address mask
 923          * This is the max address of the GPU's
 924          * internal address space.
 925          */
 926         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 927
 928         /* set DMA mask + need_dma32 flags.
 929          * PCIE - can handle 40-bits.
 930          * IGP - can handle 40-bits
 931          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 932          */
 933         adev->need_dma32 = false;
 934         dma_bits = adev->need_dma32 ? 32 : 40;
 935         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 936         if (r) {
 937                 adev->need_dma32 = true;
 938                 dma_bits = 32;
 939                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 940         }
 941         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 942         if (r) {
 943                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 944                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 945         }
 946
 947         r = gmc_v8_0_init_microcode(adev);
 948         if (r) {
 949                 DRM_ERROR("Failed to load mc firmware!\n");
 950                 return r;
 951         }
 952
 953         r = amdgpu_ttm_global_init(adev);
 954         if (r) {
 955                 return r;
 956         }
 957
 958         r = gmc_v8_0_mc_init(adev);
 959         if (r)
 960                 return r;
 961
 962         /* Memory manager */
 963         r = amdgpu_bo_init(adev);
 964         if (r)
 965                 return r;
 966
 967         r = gmc_v8_0_gart_init(adev);
 968         if (r)
 969                 return r;
 970
 971         if (!adev->vm_manager.enabled) {
 972                 r = gmc_v8_0_vm_init(adev);
 973                 if (r) {
 974                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 975                         return r;
 976                 }
 977                 adev->vm_manager.enabled = true;
 978         }
 979
 980         return r;
 981 }
 982
 983 static int gmc_v8_0_sw_fini(void *handle)
 984 {
 985         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 986
 987         if (adev->vm_manager.enabled) {
 988                 amdgpu_vm_manager_fini(adev);
 989                 gmc_v8_0_vm_fini(adev);
 990                 adev->vm_manager.enabled = false;
 991         }
 992         gmc_v8_0_gart_fini(adev);
 993         amdgpu_gem_force_release(adev);
 994         amdgpu_bo_fini(adev);
 995
 996         return 0;
 997 }
 998
 999 static int gmc_v8_0_hw_init(void *handle)
1000 {
1001         int r;
1002         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1003
1004         gmc_v8_0_init_golden_registers(adev);
1005
1006         gmc_v8_0_mc_program(adev);
1007
1008         if (adev->asic_type == CHIP_TONGA) {
1009                 r = gmc_v8_0_mc_load_microcode(adev);
1010                 if (r) {
1011                         DRM_ERROR("Failed to load MC firmware!\n");
1012                         return r;
1013                 }
1014         }
1015
1016         r = gmc_v8_0_gart_enable(adev);
1017         if (r)
1018                 return r;
1019
1020         return r;
1021 }
1022
1023 static int gmc_v8_0_hw_fini(void *handle)
1024 {
1025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
1027         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1028         gmc_v8_0_gart_disable(adev);
1029
1030         return 0;
1031 }
1032
1033 static int gmc_v8_0_suspend(void *handle)
1034 {
1035         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036
1037         if (adev->vm_manager.enabled) {
1038                 gmc_v8_0_vm_fini(adev);
1039                 adev->vm_manager.enabled = false;
1040         }
1041         gmc_v8_0_hw_fini(adev);
1042
1043         return 0;
1044 }
1045
1046 static int gmc_v8_0_resume(void *handle)
1047 {
1048         int r;
1049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050
1051         r = gmc_v8_0_hw_init(adev);
1052         if (r)
1053                 return r;
1054
1055         if (!adev->vm_manager.enabled) {
1056                 r = gmc_v8_0_vm_init(adev);
1057                 if (r) {
1058                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1059                         return r;
1060                 }
1061                 adev->vm_manager.enabled = true;
1062         }
1063
1064         return r;
1065 }
1066
1067 static bool gmc_v8_0_is_idle(void *handle)
1068 {
1069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070         u32 tmp = RREG32(mmSRBM_STATUS);
1071
1072         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1073                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1074                 return false;
1075
1076         return true;
1077 }
1078
1079 static int gmc_v8_0_wait_for_idle(void *handle)
1080 {
1081         unsigned i;
1082         u32 tmp;
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
1085         for (i = 0; i < adev->usec_timeout; i++) {
1086                 /* read MC_STATUS */
1087                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1088                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1089                                                SRBM_STATUS__MCC_BUSY_MASK |
1090                                                SRBM_STATUS__MCD_BUSY_MASK |
1091                                                SRBM_STATUS__VMC_BUSY_MASK |
1092                                                SRBM_STATUS__VMC1_BUSY_MASK);
1093                 if (!tmp)
1094                         return 0;
1095                 udelay(1);
1096         }
1097         return -ETIMEDOUT;
1098
1099 }
1100
1101 static bool gmc_v8_0_check_soft_reset(void *handle)
1102 {
1103         u32 srbm_soft_reset = 0;
1104         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1105         u32 tmp = RREG32(mmSRBM_STATUS);
1106
1107         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1108                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1109                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1110
1111         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1112                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1113                 if (!(adev->flags & AMD_IS_APU))
1114                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1115                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1116         }
1117         if (srbm_soft_reset) {
1118                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1119                 return true;
1120         } else {
1121                 adev->mc.srbm_soft_reset = 0;
1122                 return false;
1123         }
1124 }
1125
1126 static int gmc_v8_0_pre_soft_reset(void *handle)
1127 {
1128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1129
1130         if (!adev->mc.srbm_soft_reset)
1131                 return 0;
1132
1133         gmc_v8_0_mc_stop(adev, &adev->mc.save);
1134         if (gmc_v8_0_wait_for_idle(adev)) {
1135                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1136         }
1137
1138         return 0;
1139 }
1140
1141 static int gmc_v8_0_soft_reset(void *handle)
1142 {
1143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1144         u32 srbm_soft_reset;
1145
1146         if (!adev->mc.srbm_soft_reset)
1147                 return 0;
1148         srbm_soft_reset = adev->mc.srbm_soft_reset;
1149
1150         if (srbm_soft_reset) {
1151                 u32 tmp;
1152
1153                 tmp = RREG32(mmSRBM_SOFT_RESET);
1154                 tmp |= srbm_soft_reset;
1155                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1156                 WREG32(mmSRBM_SOFT_RESET, tmp);
1157                 tmp = RREG32(mmSRBM_SOFT_RESET);
1158
1159                 udelay(50);
1160
1161                 tmp &= ~srbm_soft_reset;
1162                 WREG32(mmSRBM_SOFT_RESET, tmp);
1163                 tmp = RREG32(mmSRBM_SOFT_RESET);
1164
1165                 /* Wait a little for things to settle down */
1166                 udelay(50);
1167         }
1168
1169         return 0;
1170 }
1171
1172 static int gmc_v8_0_post_soft_reset(void *handle)
1173 {
1174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175
1176         if (!adev->mc.srbm_soft_reset)
1177                 return 0;
1178
1179         gmc_v8_0_mc_resume(adev, &adev->mc.save);
1180         return 0;
1181 }
1182
1183 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1184                                              struct amdgpu_irq_src *src,
1185                                              unsigned type,
1186                                              enum amdgpu_interrupt_state state)
1187 {
1188         u32 tmp;
1189         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1190                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1191                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1192                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1193                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1194                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1195                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1196
1197         switch (state) {
1198         case AMDGPU_IRQ_STATE_DISABLE:
1199                 /* system context */
1200                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1201                 tmp &= ~bits;
1202                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1203                 /* VMs */
1204                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1205                 tmp &= ~bits;
1206                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1207                 break;
1208         case AMDGPU_IRQ_STATE_ENABLE:
1209                 /* system context */
1210                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1211                 tmp |= bits;
1212                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1213                 /* VMs */
1214                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1215                 tmp |= bits;
1216                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1217                 break;
1218         default:
1219                 break;
1220         }
1221
1222         return 0;
1223 }
1224
1225 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1226                                       struct amdgpu_irq_src *source,
1227                                       struct amdgpu_iv_entry *entry)
1228 {
1229         u32 addr, status, mc_client;
1230
1231         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1232         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1233         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1234         /* reset addr and status */
1235         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1236
1237         if (!addr && !status)
1238                 return 0;
1239
1240         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1241                 gmc_v8_0_set_fault_enable_default(adev, false);
1242
1243         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1244                 entry->src_id, entry->src_data);
1245         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1246                 addr);
1247         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1248                 status);
1249         gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1250
1251         return 0;
1252 }
1253
1254 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1255                                                      bool enable)
1256 {
1257         uint32_t data;
1258
1259         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1260                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1261                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1262                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1263
1264                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1265                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1266                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1267
1268                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1269                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1270                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1271
1272                 data = RREG32(mmMC_XPB_CLK_GAT);
1273                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1274                 WREG32(mmMC_XPB_CLK_GAT, data);
1275
1276                 data = RREG32(mmATC_MISC_CG);
1277                 data |= ATC_MISC_CG__ENABLE_MASK;
1278                 WREG32(mmATC_MISC_CG, data);
1279
1280                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1281                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1282                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1283
1284                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1285                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1286                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1287
1288                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1289                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1290                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1291
1292                 data = RREG32(mmVM_L2_CG);
1293                 data |= VM_L2_CG__ENABLE_MASK;
1294                 WREG32(mmVM_L2_CG, data);
1295         } else {
1296                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1297                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1298                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1299
1300                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1301                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1302                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1303
1304                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1305                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1306                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1307
1308                 data = RREG32(mmMC_XPB_CLK_GAT);
1309                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1310                 WREG32(mmMC_XPB_CLK_GAT, data);
1311
1312                 data = RREG32(mmATC_MISC_CG);
1313                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1314                 WREG32(mmATC_MISC_CG, data);
1315
1316                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1317                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1318                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1319
1320                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1321                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1322                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1323
1324                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1325                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1326                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1327
1328                 data = RREG32(mmVM_L2_CG);
1329                 data &= ~VM_L2_CG__ENABLE_MASK;
1330                 WREG32(mmVM_L2_CG, data);
1331         }
1332 }
1333
1334 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1335                                        bool enable)
1336 {
1337         uint32_t data;
1338
1339         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1340                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1341                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1342                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1343
1344                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1345                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1346                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1347
1348                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1349                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1350                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1351
1352                 data = RREG32(mmMC_XPB_CLK_GAT);
1353                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1354                 WREG32(mmMC_XPB_CLK_GAT, data);
1355
1356                 data = RREG32(mmATC_MISC_CG);
1357                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1358                 WREG32(mmATC_MISC_CG, data);
1359
1360                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1361                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1362                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1363
1364                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1365                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1366                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1367
1368                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1369                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1370                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1371
1372                 data = RREG32(mmVM_L2_CG);
1373                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1374                 WREG32(mmVM_L2_CG, data);
1375         } else {
1376                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1377                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1378                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1379
1380                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1381                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1382                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1383
1384                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1385                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1386                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1387
1388                 data = RREG32(mmMC_XPB_CLK_GAT);
1389                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1390                 WREG32(mmMC_XPB_CLK_GAT, data);
1391
1392                 data = RREG32(mmATC_MISC_CG);
1393                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1394                 WREG32(mmATC_MISC_CG, data);
1395
1396                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1397                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1398                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1399
1400                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1401                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1402                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1403
1404                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1405                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1406                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1407
1408                 data = RREG32(mmVM_L2_CG);
1409                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1410                 WREG32(mmVM_L2_CG, data);
1411         }
1412 }
1413
1414 static int gmc_v8_0_set_clockgating_state(void *handle,
1415                                           enum amd_clockgating_state state)
1416 {
1417         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1418
1419         switch (adev->asic_type) {
1420         case CHIP_FIJI:
1421                 fiji_update_mc_medium_grain_clock_gating(adev,
1422                                 state == AMD_CG_STATE_GATE ? true : false);
1423                 fiji_update_mc_light_sleep(adev,
1424                                 state == AMD_CG_STATE_GATE ? true : false);
1425                 break;
1426         default:
1427                 break;
1428         }
1429         return 0;
1430 }
1431
1432 static int gmc_v8_0_set_powergating_state(void *handle,
1433                                           enum amd_powergating_state state)
1434 {
1435         return 0;
1436 }
1437
1438 const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1439         .name = "gmc_v8_0",
1440         .early_init = gmc_v8_0_early_init,
1441         .late_init = gmc_v8_0_late_init,
1442         .sw_init = gmc_v8_0_sw_init,
1443         .sw_fini = gmc_v8_0_sw_fini,
1444         .hw_init = gmc_v8_0_hw_init,
1445         .hw_fini = gmc_v8_0_hw_fini,
1446         .suspend = gmc_v8_0_suspend,
1447         .resume = gmc_v8_0_resume,
1448         .is_idle = gmc_v8_0_is_idle,
1449         .wait_for_idle = gmc_v8_0_wait_for_idle,
1450         .check_soft_reset = gmc_v8_0_check_soft_reset,
1451         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1452         .soft_reset = gmc_v8_0_soft_reset,
1453         .post_soft_reset = gmc_v8_0_post_soft_reset,
1454         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1455         .set_powergating_state = gmc_v8_0_set_powergating_state,
1456 };
1457
1458 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1459         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1460         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1461 };
1462
1463 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1464         .set = gmc_v8_0_vm_fault_interrupt_state,
1465         .process = gmc_v8_0_process_interrupt,
1466 };
1467
1468 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1469 {
1470         if (adev->gart.gart_funcs == NULL)
1471                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1472 }
1473
1474 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1475 {
1476         adev->mc.vm_fault.num_types = 1;
1477         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1478 }