drivers/gpu/drm/amd/amdgpu/kv_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_dpm.h"
  31 #include "kv_dpm.h"
  32 #include "gfx_v7_0.h"
  33 #include <linux/seq_file.h>
  34
  35 #include "smu/smu_7_0_0_d.h"
  36 #include "smu/smu_7_0_0_sh_mask.h"
  37
  38 #include "gca/gfx_7_2_d.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  42 #define KV_MINIMUM_ENGINE_CLOCK         800
  43 #define SMC_RAM_END                     0x40000
  44
  45 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
  46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
  47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
  48                             bool enable);
  49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
  50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
  51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
  52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
  53 static void kv_enable_new_levels(struct amdgpu_device *adev);
  54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
  55                                            struct amdgpu_ps *new_rps);
  56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
  57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
  58 static int kv_force_dpm_highest(struct amdgpu_device *adev);
  59 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
  60 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
  61                                         struct amdgpu_ps *new_rps,
  62                                         struct amdgpu_ps *old_rps);
  63 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
  64                                             int min_temp, int max_temp);
  65 static int kv_init_fps_limits(struct amdgpu_device *adev);
  66
  67 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
  68 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
  69 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
  70 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
  71
  72
  73 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
  74                                    struct sumo_vid_mapping_table *vid_mapping_table,
  75                                    u32 vid_2bit)
  76 {
  77         struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  78                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  79         u32 i;
  80
  81         if (vddc_sclk_table && vddc_sclk_table->count) {
  82                 if (vid_2bit < vddc_sclk_table->count)
  83                         return vddc_sclk_table->entries[vid_2bit].v;
  84                 else
  85                         return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
  86         } else {
  87                 for (i = 0; i < vid_mapping_table->num_entries; i++) {
  88                         if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
  89                                 return vid_mapping_table->entries[i].vid_7bit;
  90                 }
  91                 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
  92         }
  93 }
  94
  95 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
  96                                    struct sumo_vid_mapping_table *vid_mapping_table,
  97                                    u32 vid_7bit)
  98 {
  99         struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
 100                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 101         u32 i;
 102
 103         if (vddc_sclk_table && vddc_sclk_table->count) {
 104                 for (i = 0; i < vddc_sclk_table->count; i++) {
 105                         if (vddc_sclk_table->entries[i].v == vid_7bit)
 106                                 return i;
 107                 }
 108                 return vddc_sclk_table->count - 1;
 109         } else {
 110                 for (i = 0; i < vid_mapping_table->num_entries; i++) {
 111                         if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
 112                                 return vid_mapping_table->entries[i].vid_2bit;
 113                 }
 114
 115                 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
 116         }
 117 }
 118
 119 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
 120 {
 121 /* This bit selects who handles display phy powergating.
 122  * Clear the bit to let atom handle it.
 123  * Set it to let the driver handle it.
 124  * For now we just let atom handle it.
 125  */
 126 #if 0
 127         u32 v = RREG32(mmDOUT_SCRATCH3);
 128
 129         if (enable)
 130                 v |= 0x4;
 131         else
 132                 v &= 0xFFFFFFFB;
 133
 134         WREG32(mmDOUT_SCRATCH3, v);
 135 #endif
 136 }
 137
 138 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
 139                                                       struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
 140                                                       ATOM_AVAILABLE_SCLK_LIST *table)
 141 {
 142         u32 i;
 143         u32 n = 0;
 144         u32 prev_sclk = 0;
 145
 146         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 147                 if (table[i].ulSupportedSCLK > prev_sclk) {
 148                         sclk_voltage_mapping_table->entries[n].sclk_frequency =
 149                                 table[i].ulSupportedSCLK;
 150                         sclk_voltage_mapping_table->entries[n].vid_2bit =
 151                                 table[i].usVoltageIndex;
 152                         prev_sclk = table[i].ulSupportedSCLK;
 153                         n++;
 154                 }
 155         }
 156
 157         sclk_voltage_mapping_table->num_max_dpm_entries = n;
 158 }
 159
 160 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
 161                                              struct sumo_vid_mapping_table *vid_mapping_table,
 162                                              ATOM_AVAILABLE_SCLK_LIST *table)
 163 {
 164         u32 i, j;
 165
 166         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 167                 if (table[i].ulSupportedSCLK != 0) {
 168                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
 169                                 table[i].usVoltageID;
 170                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
 171                                 table[i].usVoltageIndex;
 172                 }
 173         }
 174
 175         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
 176                 if (vid_mapping_table->entries[i].vid_7bit == 0) {
 177                         for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
 178                                 if (vid_mapping_table->entries[j].vid_7bit != 0) {
 179                                         vid_mapping_table->entries[i] =
 180                                                 vid_mapping_table->entries[j];
 181                                         vid_mapping_table->entries[j].vid_7bit = 0;
 182                                         break;
 183                                 }
 184                         }
 185
 186                         if (j == SUMO_MAX_NUMBER_VOLTAGES)
 187                                 break;
 188                 }
 189         }
 190
 191         vid_mapping_table->num_entries = i;
 192 }
 193
 194 #if 0
 195 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
 196 {
 197         {  0,       4,        1    },
 198         {  1,       4,        1    },
 199         {  2,       5,        1    },
 200         {  3,       4,        2    },
 201         {  4,       1,        1    },
 202         {  5,       5,        2    },
 203         {  6,       6,        1    },
 204         {  7,       9,        2    },
 205         { 0xffffffff }
 206 };
 207
 208 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
 209 {
 210         {  0,       4,        1    },
 211         { 0xffffffff }
 212 };
 213
 214 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
 215 {
 216         {  0,       4,        1    },
 217         { 0xffffffff }
 218 };
 219
 220 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
 221 {
 222         {  0,       4,        1    },
 223         { 0xffffffff }
 224 };
 225
 226 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
 227 {
 228         {  0,       4,        1    },
 229         { 0xffffffff }
 230 };
 231
 232 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
 233 {
 234         {  0,       4,        1    },
 235         {  1,       4,        1    },
 236         {  2,       5,        1    },
 237         {  3,       4,        1    },
 238         {  4,       1,        1    },
 239         {  5,       5,        1    },
 240         {  6,       6,        1    },
 241         {  7,       9,        1    },
 242         {  8,       4,        1    },
 243         {  9,       2,        1    },
 244         {  10,      3,        1    },
 245         {  11,      6,        1    },
 246         {  12,      8,        2    },
 247         {  13,      1,        1    },
 248         {  14,      2,        1    },
 249         {  15,      3,        1    },
 250         {  16,      1,        1    },
 251         {  17,      4,        1    },
 252         {  18,      3,        1    },
 253         {  19,      1,        1    },
 254         {  20,      8,        1    },
 255         {  21,      5,        1    },
 256         {  22,      1,        1    },
 257         {  23,      1,        1    },
 258         {  24,      4,        1    },
 259         {  27,      6,        1    },
 260         {  28,      1,        1    },
 261         { 0xffffffff }
 262 };
 263
 264 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 265 {
 266         { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 267 };
 268
 269 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 270 {
 271         { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 272 };
 273
 274 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 275 {
 276         { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 277 };
 278
 279 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 280 {
 281         { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 282 };
 283
 284 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 285 {
 286         { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 287 };
 288
 289 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 290 {
 291         { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 292 };
 293 #endif
 294
 295 static const struct kv_pt_config_reg didt_config_kv[] =
 296 {
 297         { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 298         { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 299         { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 300         { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 301         { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 302         { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 303         { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 304         { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 305         { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 306         { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 307         { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 308         { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 309         { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 310         { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 311         { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 312         { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 313         { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 314         { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 315         { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 316         { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 317         { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 318         { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 319         { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 320         { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 321         { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 322         { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 323         { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 324         { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 325         { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 326         { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 327         { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 328         { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 329         { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 330         { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 331         { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 332         { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 333         { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 334         { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 335         { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 336         { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 337         { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 338         { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 339         { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 340         { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 341         { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 342         { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 343         { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 344         { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 345         { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 346         { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 347         { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 348         { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 349         { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 350         { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 351         { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 352         { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 353         { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 354         { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 355         { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 356         { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 357         { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 358         { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 359         { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 360         { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 361         { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 362         { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 363         { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 364         { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 365         { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 366         { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 367         { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 368         { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 369         { 0xFFFFFFFF }
 370 };
 371
 372 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
 373 {
 374         struct kv_ps *ps = rps->ps_priv;
 375
 376         return ps;
 377 }
 378
 379 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
 380 {
 381         struct kv_power_info *pi = adev->pm.dpm.priv;
 382
 383         return pi;
 384 }
 385
 386 #if 0
 387 static void kv_program_local_cac_table(struct amdgpu_device *adev,
 388                                        const struct kv_lcac_config_values *local_cac_table,
 389                                        const struct kv_lcac_config_reg *local_cac_reg)
 390 {
 391         u32 i, count, data;
 392         const struct kv_lcac_config_values *values = local_cac_table;
 393
 394         while (values->block_id != 0xffffffff) {
 395                 count = values->signal_id;
 396                 for (i = 0; i < count; i++) {
 397                         data = ((values->block_id << local_cac_reg->block_shift) &
 398                                 local_cac_reg->block_mask);
 399                         data |= ((i << local_cac_reg->signal_shift) &
 400                                  local_cac_reg->signal_mask);
 401                         data |= ((values->t << local_cac_reg->t_shift) &
 402                                  local_cac_reg->t_mask);
 403                         data |= ((1 << local_cac_reg->enable_shift) &
 404                                  local_cac_reg->enable_mask);
 405                         WREG32_SMC(local_cac_reg->cntl, data);
 406                 }
 407                 values++;
 408         }
 409 }
 410 #endif
 411
 412 static int kv_program_pt_config_registers(struct amdgpu_device *adev,
 413                                           const struct kv_pt_config_reg *cac_config_regs)
 414 {
 415         const struct kv_pt_config_reg *config_regs = cac_config_regs;
 416         u32 data;
 417         u32 cache = 0;
 418
 419         if (config_regs == NULL)
 420                 return -EINVAL;
 421
 422         while (config_regs->offset != 0xFFFFFFFF) {
 423                 if (config_regs->type == KV_CONFIGREG_CACHE) {
 424                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 425                 } else {
 426                         switch (config_regs->type) {
 427                         case KV_CONFIGREG_SMC_IND:
 428                                 data = RREG32_SMC(config_regs->offset);
 429                                 break;
 430                         case KV_CONFIGREG_DIDT_IND:
 431                                 data = RREG32_DIDT(config_regs->offset);
 432                                 break;
 433                         default:
 434                                 data = RREG32(config_regs->offset);
 435                                 break;
 436                         }
 437
 438                         data &= ~config_regs->mask;
 439                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 440                         data |= cache;
 441                         cache = 0;
 442
 443                         switch (config_regs->type) {
 444                         case KV_CONFIGREG_SMC_IND:
 445                                 WREG32_SMC(config_regs->offset, data);
 446                                 break;
 447                         case KV_CONFIGREG_DIDT_IND:
 448                                 WREG32_DIDT(config_regs->offset, data);
 449                                 break;
 450                         default:
 451                                 WREG32(config_regs->offset, data);
 452                                 break;
 453                         }
 454                 }
 455                 config_regs++;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
 462 {
 463         struct kv_power_info *pi = kv_get_pi(adev);
 464         u32 data;
 465
 466         if (pi->caps_sq_ramping) {
 467                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 468                 if (enable)
 469                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 470                 else
 471                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 472                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 473         }
 474
 475         if (pi->caps_db_ramping) {
 476                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 477                 if (enable)
 478                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 479                 else
 480                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 481                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 482         }
 483
 484         if (pi->caps_td_ramping) {
 485                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 486                 if (enable)
 487                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 488                 else
 489                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 490                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 491         }
 492
 493         if (pi->caps_tcp_ramping) {
 494                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 495                 if (enable)
 496                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 497                 else
 498                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 499                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 500         }
 501 }
 502
 503 static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
 504 {
 505         struct kv_power_info *pi = kv_get_pi(adev);
 506         int ret;
 507
 508         if (pi->caps_sq_ramping ||
 509             pi->caps_db_ramping ||
 510             pi->caps_td_ramping ||
 511             pi->caps_tcp_ramping) {
 512                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 513
 514                 if (enable) {
 515                         ret = kv_program_pt_config_registers(adev, didt_config_kv);
 516                         if (ret) {
 517                                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 518                                 return ret;
 519                         }
 520                 }
 521
 522                 kv_do_enable_didt(adev, enable);
 523
 524                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 525         }
 526
 527         return 0;
 528 }
 529
 530 #if 0
 531 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
 532 {
 533         struct kv_power_info *pi = kv_get_pi(adev);
 534
 535         if (pi->caps_cac) {
 536                 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
 537                 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
 538                 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 539
 540                 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
 541                 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
 542                 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 543
 544                 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
 545                 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
 546                 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 547
 548                 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
 549                 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
 550                 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 551
 552                 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
 553                 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
 554                 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 555
 556                 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
 557                 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
 558                 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 559         }
 560 }
 561 #endif
 562
 563 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 564 {
 565         struct kv_power_info *pi = kv_get_pi(adev);
 566         int ret = 0;
 567
 568         if (pi->caps_cac) {
 569                 if (enable) {
 570                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
 571                         if (ret)
 572                                 pi->cac_enabled = false;
 573                         else
 574                                 pi->cac_enabled = true;
 575                 } else if (pi->cac_enabled) {
 576                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
 577                         pi->cac_enabled = false;
 578                 }
 579         }
 580
 581         return ret;
 582 }
 583
 584 static int kv_process_firmware_header(struct amdgpu_device *adev)
 585 {
 586         struct kv_power_info *pi = kv_get_pi(adev);
 587         u32 tmp;
 588         int ret;
 589
 590         ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 591                                      offsetof(SMU7_Firmware_Header, DpmTable),
 592                                      &tmp, pi->sram_end);
 593
 594         if (ret == 0)
 595                 pi->dpm_table_start = tmp;
 596
 597         ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 598                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
 599                                      &tmp, pi->sram_end);
 600
 601         if (ret == 0)
 602                 pi->soft_regs_start = tmp;
 603
 604         return ret;
 605 }
 606
 607 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
 608 {
 609         struct kv_power_info *pi = kv_get_pi(adev);
 610         int ret;
 611
 612         pi->graphics_voltage_change_enable = 1;
 613
 614         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 615                                    pi->dpm_table_start +
 616                                    offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 617                                    &pi->graphics_voltage_change_enable,
 618                                    sizeof(u8), pi->sram_end);
 619
 620         return ret;
 621 }
 622
 623 static int kv_set_dpm_interval(struct amdgpu_device *adev)
 624 {
 625         struct kv_power_info *pi = kv_get_pi(adev);
 626         int ret;
 627
 628         pi->graphics_interval = 1;
 629
 630         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 631                                    pi->dpm_table_start +
 632                                    offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 633                                    &pi->graphics_interval,
 634                                    sizeof(u8), pi->sram_end);
 635
 636         return ret;
 637 }
 638
 639 static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
 640 {
 641         struct kv_power_info *pi = kv_get_pi(adev);
 642         int ret;
 643
 644         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 645                                    pi->dpm_table_start +
 646                                    offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 647                                    &pi->graphics_boot_level,
 648                                    sizeof(u8), pi->sram_end);
 649
 650         return ret;
 651 }
 652
 653 static void kv_program_vc(struct amdgpu_device *adev)
 654 {
 655         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
 656 }
 657
 658 static void kv_clear_vc(struct amdgpu_device *adev)
 659 {
 660         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
 661 }
 662
 663 static int kv_set_divider_value(struct amdgpu_device *adev,
 664                                 u32 index, u32 sclk)
 665 {
 666         struct kv_power_info *pi = kv_get_pi(adev);
 667         struct atom_clock_dividers dividers;
 668         int ret;
 669
 670         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 671                                                  sclk, false, &dividers);
 672         if (ret)
 673                 return ret;
 674
 675         pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 676         pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 677
 678         return 0;
 679 }
 680
 681 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
 682                                             u16 voltage)
 683 {
 684         return 6200 - (voltage * 25);
 685 }
 686
 687 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
 688                                             u32 vid_2bit)
 689 {
 690         struct kv_power_info *pi = kv_get_pi(adev);
 691         u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
 692                                                &pi->sys_info.vid_mapping_table,
 693                                                vid_2bit);
 694
 695         return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
 696 }
 697
 698
 699 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
 700 {
 701         struct kv_power_info *pi = kv_get_pi(adev);
 702
 703         pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 704         pi->graphics_level[index].MinVddNb =
 705                 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
 706
 707         return 0;
 708 }
 709
 710 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
 711 {
 712         struct kv_power_info *pi = kv_get_pi(adev);
 713
 714         pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 715
 716         return 0;
 717 }
 718
 719 static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
 720                                       u32 index, bool enable)
 721 {
 722         struct kv_power_info *pi = kv_get_pi(adev);
 723
 724         pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 725 }
 726
 727 static void kv_start_dpm(struct amdgpu_device *adev)
 728 {
 729         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
 730
 731         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
 732         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
 733
 734         amdgpu_kv_smc_dpm_enable(adev, true);
 735 }
 736
 737 static void kv_stop_dpm(struct amdgpu_device *adev)
 738 {
 739         amdgpu_kv_smc_dpm_enable(adev, false);
 740 }
 741
 742 static void kv_start_am(struct amdgpu_device *adev)
 743 {
 744         u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 745
 746         sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 747                         SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 748         sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
 749
 750         WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 751 }
 752
 753 static void kv_reset_am(struct amdgpu_device *adev)
 754 {
 755         u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 756
 757         sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 758                         SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 759
 760         WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 761 }
 762
 763 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
 764 {
 765         return amdgpu_kv_notify_message_to_smu(adev, freeze ?
 766                                         PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 767 }
 768
 769 static int kv_force_lowest_valid(struct amdgpu_device *adev)
 770 {
 771         return kv_force_dpm_lowest(adev);
 772 }
 773
 774 static int kv_unforce_levels(struct amdgpu_device *adev)
 775 {
 776         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
 777                 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
 778         else
 779                 return kv_set_enabled_levels(adev);
 780 }
 781
 782 static int kv_update_sclk_t(struct amdgpu_device *adev)
 783 {
 784         struct kv_power_info *pi = kv_get_pi(adev);
 785         u32 low_sclk_interrupt_t = 0;
 786         int ret = 0;
 787
 788         if (pi->caps_sclk_throttle_low_notification) {
 789                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 790
 791                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
 792                                            pi->dpm_table_start +
 793                                            offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 794                                            (u8 *)&low_sclk_interrupt_t,
 795                                            sizeof(u32), pi->sram_end);
 796         }
 797         return ret;
 798 }
 799
 800 static int kv_program_bootup_state(struct amdgpu_device *adev)
 801 {
 802         struct kv_power_info *pi = kv_get_pi(adev);
 803         u32 i;
 804         struct amdgpu_clock_voltage_dependency_table *table =
 805                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 806
 807         if (table && table->count) {
 808                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 809                         if (table->entries[i].clk == pi->boot_pl.sclk)
 810                                 break;
 811                 }
 812
 813                 pi->graphics_boot_level = (u8)i;
 814                 kv_dpm_power_level_enable(adev, i, true);
 815         } else {
 816                 struct sumo_sclk_voltage_mapping_table *table =
 817                         &pi->sys_info.sclk_voltage_mapping_table;
 818
 819                 if (table->num_max_dpm_entries == 0)
 820                         return -EINVAL;
 821
 822                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 823                         if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
 824                                 break;
 825                 }
 826
 827                 pi->graphics_boot_level = (u8)i;
 828                 kv_dpm_power_level_enable(adev, i, true);
 829         }
 830         return 0;
 831 }
 832
 833 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
 834 {
 835         struct kv_power_info *pi = kv_get_pi(adev);
 836         int ret;
 837
 838         pi->graphics_therm_throttle_enable = 1;
 839
 840         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 841                                    pi->dpm_table_start +
 842                                    offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 843                                    &pi->graphics_therm_throttle_enable,
 844                                    sizeof(u8), pi->sram_end);
 845
 846         return ret;
 847 }
 848
 849 static int kv_upload_dpm_settings(struct amdgpu_device *adev)
 850 {
 851         struct kv_power_info *pi = kv_get_pi(adev);
 852         int ret;
 853
 854         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 855                                    pi->dpm_table_start +
 856                                    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 857                                    (u8 *)&pi->graphics_level,
 858                                    sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 859                                    pi->sram_end);
 860
 861         if (ret)
 862                 return ret;
 863
 864         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 865                                    pi->dpm_table_start +
 866                                    offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 867                                    &pi->graphics_dpm_level_count,
 868                                    sizeof(u8), pi->sram_end);
 869
 870         return ret;
 871 }
 872
 873 static u32 kv_get_clock_difference(u32 a, u32 b)
 874 {
 875         return (a >= b) ? a - b : b - a;
 876 }
 877
 878 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
 879 {
 880         struct kv_power_info *pi = kv_get_pi(adev);
 881         u32 value;
 882
 883         if (pi->caps_enable_dfs_bypass) {
 884                 if (kv_get_clock_difference(clk, 40000) < 200)
 885                         value = 3;
 886                 else if (kv_get_clock_difference(clk, 30000) < 200)
 887                         value = 2;
 888                 else if (kv_get_clock_difference(clk, 20000) < 200)
 889                         value = 7;
 890                 else if (kv_get_clock_difference(clk, 15000) < 200)
 891                         value = 6;
 892                 else if (kv_get_clock_difference(clk, 10000) < 200)
 893                         value = 8;
 894                 else
 895                         value = 0;
 896         } else {
 897                 value = 0;
 898         }
 899
 900         return value;
 901 }
 902
 903 static int kv_populate_uvd_table(struct amdgpu_device *adev)
 904 {
 905         struct kv_power_info *pi = kv_get_pi(adev);
 906         struct amdgpu_uvd_clock_voltage_dependency_table *table =
 907                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 908         struct atom_clock_dividers dividers;
 909         int ret;
 910         u32 i;
 911
 912         if (table == NULL || table->count == 0)
 913                 return 0;
 914
 915         pi->uvd_level_count = 0;
 916         for (i = 0; i < table->count; i++) {
 917                 if (pi->high_voltage_t &&
 918                     (pi->high_voltage_t < table->entries[i].v))
 919                         break;
 920
 921                 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 922                 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 923                 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 924
 925                 pi->uvd_level[i].VClkBypassCntl =
 926                         (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
 927                 pi->uvd_level[i].DClkBypassCntl =
 928                         (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
 929
 930                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 931                                                          table->entries[i].vclk, false, &dividers);
 932                 if (ret)
 933                         return ret;
 934                 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 935
 936                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 937                                                          table->entries[i].dclk, false, &dividers);
 938                 if (ret)
 939                         return ret;
 940                 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 941
 942                 pi->uvd_level_count++;
 943         }
 944
 945         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 946                                    pi->dpm_table_start +
 947                                    offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 948                                    (u8 *)&pi->uvd_level_count,
 949                                    sizeof(u8), pi->sram_end);
 950         if (ret)
 951                 return ret;
 952
 953         pi->uvd_interval = 1;
 954
 955         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 956                                    pi->dpm_table_start +
 957                                    offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 958                                    &pi->uvd_interval,
 959                                    sizeof(u8), pi->sram_end);
 960         if (ret)
 961                 return ret;
 962
 963         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 964                                    pi->dpm_table_start +
 965                                    offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 966                                    (u8 *)&pi->uvd_level,
 967                                    sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 968                                    pi->sram_end);
 969
 970         return ret;
 971
 972 }
 973
 974 static int kv_populate_vce_table(struct amdgpu_device *adev)
 975 {
 976         struct kv_power_info *pi = kv_get_pi(adev);
 977         int ret;
 978         u32 i;
 979         struct amdgpu_vce_clock_voltage_dependency_table *table =
 980                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 981         struct atom_clock_dividers dividers;
 982
 983         if (table == NULL || table->count == 0)
 984                 return 0;
 985
 986         pi->vce_level_count = 0;
 987         for (i = 0; i < table->count; i++) {
 988                 if (pi->high_voltage_t &&
 989                     pi->high_voltage_t < table->entries[i].v)
 990                         break;
 991
 992                 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 993                 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 994
 995                 pi->vce_level[i].ClkBypassCntl =
 996                         (u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
 997
 998                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 999                                                          table->entries[i].evclk, false, &dividers);
1000                 if (ret)
1001                         return ret;
1002                 pi->vce_level[i].Divider = (u8)dividers.post_div;
1003
1004                 pi->vce_level_count++;
1005         }
1006
1007         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1008                                    pi->dpm_table_start +
1009                                    offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
1010                                    (u8 *)&pi->vce_level_count,
1011                                    sizeof(u8),
1012                                    pi->sram_end);
1013         if (ret)
1014                 return ret;
1015
1016         pi->vce_interval = 1;
1017
1018         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1019                                    pi->dpm_table_start +
1020                                    offsetof(SMU7_Fusion_DpmTable, VCEInterval),
1021                                    (u8 *)&pi->vce_interval,
1022                                    sizeof(u8),
1023                                    pi->sram_end);
1024         if (ret)
1025                 return ret;
1026
1027         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1028                                    pi->dpm_table_start +
1029                                    offsetof(SMU7_Fusion_DpmTable, VceLevel),
1030                                    (u8 *)&pi->vce_level,
1031                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
1032                                    pi->sram_end);
1033
1034         return ret;
1035 }
1036
1037 static int kv_populate_samu_table(struct amdgpu_device *adev)
1038 {
1039         struct kv_power_info *pi = kv_get_pi(adev);
1040         struct amdgpu_clock_voltage_dependency_table *table =
1041                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1042         struct atom_clock_dividers dividers;
1043         int ret;
1044         u32 i;
1045
1046         if (table == NULL || table->count == 0)
1047                 return 0;
1048
1049         pi->samu_level_count = 0;
1050         for (i = 0; i < table->count; i++) {
1051                 if (pi->high_voltage_t &&
1052                     pi->high_voltage_t < table->entries[i].v)
1053                         break;
1054
1055                 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1056                 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1057
1058                 pi->samu_level[i].ClkBypassCntl =
1059                         (u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1060
1061                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1062                                                          table->entries[i].clk, false, &dividers);
1063                 if (ret)
1064                         return ret;
1065                 pi->samu_level[i].Divider = (u8)dividers.post_div;
1066
1067                 pi->samu_level_count++;
1068         }
1069
1070         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1071                                    pi->dpm_table_start +
1072                                    offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
1073                                    (u8 *)&pi->samu_level_count,
1074                                    sizeof(u8),
1075                                    pi->sram_end);
1076         if (ret)
1077                 return ret;
1078
1079         pi->samu_interval = 1;
1080
1081         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1082                                    pi->dpm_table_start +
1083                                    offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
1084                                    (u8 *)&pi->samu_interval,
1085                                    sizeof(u8),
1086                                    pi->sram_end);
1087         if (ret)
1088                 return ret;
1089
1090         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1091                                    pi->dpm_table_start +
1092                                    offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1093                                    (u8 *)&pi->samu_level,
1094                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1095                                    pi->sram_end);
1096         if (ret)
1097                 return ret;
1098
1099         return ret;
1100 }
1101
1102
1103 static int kv_populate_acp_table(struct amdgpu_device *adev)
1104 {
1105         struct kv_power_info *pi = kv_get_pi(adev);
1106         struct amdgpu_clock_voltage_dependency_table *table =
1107                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1108         struct atom_clock_dividers dividers;
1109         int ret;
1110         u32 i;
1111
1112         if (table == NULL || table->count == 0)
1113                 return 0;
1114
1115         pi->acp_level_count = 0;
1116         for (i = 0; i < table->count; i++) {
1117                 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1118                 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1119
1120                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1121                                                          table->entries[i].clk, false, &dividers);
1122                 if (ret)
1123                         return ret;
1124                 pi->acp_level[i].Divider = (u8)dividers.post_div;
1125
1126                 pi->acp_level_count++;
1127         }
1128
1129         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1130                                    pi->dpm_table_start +
1131                                    offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1132                                    (u8 *)&pi->acp_level_count,
1133                                    sizeof(u8),
1134                                    pi->sram_end);
1135         if (ret)
1136                 return ret;
1137
1138         pi->acp_interval = 1;
1139
1140         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1141                                    pi->dpm_table_start +
1142                                    offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1143                                    (u8 *)&pi->acp_interval,
1144                                    sizeof(u8),
1145                                    pi->sram_end);
1146         if (ret)
1147                 return ret;
1148
1149         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1150                                    pi->dpm_table_start +
1151                                    offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1152                                    (u8 *)&pi->acp_level,
1153                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1154                                    pi->sram_end);
1155         if (ret)
1156                 return ret;
1157
1158         return ret;
1159 }
1160
1161 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
1162 {
1163         struct kv_power_info *pi = kv_get_pi(adev);
1164         u32 i;
1165         struct amdgpu_clock_voltage_dependency_table *table =
1166                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1167
1168         if (table && table->count) {
1169                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1170                         if (pi->caps_enable_dfs_bypass) {
1171                                 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1172                                         pi->graphics_level[i].ClkBypassCntl = 3;
1173                                 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1174                                         pi->graphics_level[i].ClkBypassCntl = 2;
1175                                 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1176                                         pi->graphics_level[i].ClkBypassCntl = 7;
1177                                 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1178                                         pi->graphics_level[i].ClkBypassCntl = 6;
1179                                 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1180                                         pi->graphics_level[i].ClkBypassCntl = 8;
1181                                 else
1182                                         pi->graphics_level[i].ClkBypassCntl = 0;
1183                         } else {
1184                                 pi->graphics_level[i].ClkBypassCntl = 0;
1185                         }
1186                 }
1187         } else {
1188                 struct sumo_sclk_voltage_mapping_table *table =
1189                         &pi->sys_info.sclk_voltage_mapping_table;
1190                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1191                         if (pi->caps_enable_dfs_bypass) {
1192                                 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1193                                         pi->graphics_level[i].ClkBypassCntl = 3;
1194                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1195                                         pi->graphics_level[i].ClkBypassCntl = 2;
1196                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1197                                         pi->graphics_level[i].ClkBypassCntl = 7;
1198                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1199                                         pi->graphics_level[i].ClkBypassCntl = 6;
1200                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1201                                         pi->graphics_level[i].ClkBypassCntl = 8;
1202                                 else
1203                                         pi->graphics_level[i].ClkBypassCntl = 0;
1204                         } else {
1205                                 pi->graphics_level[i].ClkBypassCntl = 0;
1206                         }
1207                 }
1208         }
1209 }
1210
1211 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
1212 {
1213         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1214                                         PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1215 }
1216
1217 static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
1218 {
1219         struct kv_power_info *pi = kv_get_pi(adev);
1220
1221         pi->acp_boot_level = 0xff;
1222 }
1223
1224 static void kv_update_current_ps(struct amdgpu_device *adev,
1225                                  struct amdgpu_ps *rps)
1226 {
1227         struct kv_ps *new_ps = kv_get_ps(rps);
1228         struct kv_power_info *pi = kv_get_pi(adev);
1229
1230         pi->current_rps = *rps;
1231         pi->current_ps = *new_ps;
1232         pi->current_rps.ps_priv = &pi->current_ps;
1233 }
1234
1235 static void kv_update_requested_ps(struct amdgpu_device *adev,
1236                                    struct amdgpu_ps *rps)
1237 {
1238         struct kv_ps *new_ps = kv_get_ps(rps);
1239         struct kv_power_info *pi = kv_get_pi(adev);
1240
1241         pi->requested_rps = *rps;
1242         pi->requested_ps = *new_ps;
1243         pi->requested_rps.ps_priv = &pi->requested_ps;
1244 }
1245
1246 static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
1247 {
1248         struct kv_power_info *pi = kv_get_pi(adev);
1249         int ret;
1250
1251         if (pi->bapm_enable) {
1252                 ret = amdgpu_kv_smc_bapm_enable(adev, enable);
1253                 if (ret)
1254                         DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1255         }
1256 }
1257
1258 static int kv_dpm_enable(struct amdgpu_device *adev)
1259 {
1260         struct kv_power_info *pi = kv_get_pi(adev);
1261         int ret;
1262
1263         ret = kv_process_firmware_header(adev);
1264         if (ret) {
1265                 DRM_ERROR("kv_process_firmware_header failed\n");
1266                 return ret;
1267         }
1268         kv_init_fps_limits(adev);
1269         kv_init_graphics_levels(adev);
1270         ret = kv_program_bootup_state(adev);
1271         if (ret) {
1272                 DRM_ERROR("kv_program_bootup_state failed\n");
1273                 return ret;
1274         }
1275         kv_calculate_dfs_bypass_settings(adev);
1276         ret = kv_upload_dpm_settings(adev);
1277         if (ret) {
1278                 DRM_ERROR("kv_upload_dpm_settings failed\n");
1279                 return ret;
1280         }
1281         ret = kv_populate_uvd_table(adev);
1282         if (ret) {
1283                 DRM_ERROR("kv_populate_uvd_table failed\n");
1284                 return ret;
1285         }
1286         ret = kv_populate_vce_table(adev);
1287         if (ret) {
1288                 DRM_ERROR("kv_populate_vce_table failed\n");
1289                 return ret;
1290         }
1291         ret = kv_populate_samu_table(adev);
1292         if (ret) {
1293                 DRM_ERROR("kv_populate_samu_table failed\n");
1294                 return ret;
1295         }
1296         ret = kv_populate_acp_table(adev);
1297         if (ret) {
1298                 DRM_ERROR("kv_populate_acp_table failed\n");
1299                 return ret;
1300         }
1301         kv_program_vc(adev);
1302 #if 0
1303         kv_initialize_hardware_cac_manager(adev);
1304 #endif
1305         kv_start_am(adev);
1306         if (pi->enable_auto_thermal_throttling) {
1307                 ret = kv_enable_auto_thermal_throttling(adev);
1308                 if (ret) {
1309                         DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1310                         return ret;
1311                 }
1312         }
1313         ret = kv_enable_dpm_voltage_scaling(adev);
1314         if (ret) {
1315                 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1316                 return ret;
1317         }
1318         ret = kv_set_dpm_interval(adev);
1319         if (ret) {
1320                 DRM_ERROR("kv_set_dpm_interval failed\n");
1321                 return ret;
1322         }
1323         ret = kv_set_dpm_boot_state(adev);
1324         if (ret) {
1325                 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1326                 return ret;
1327         }
1328         ret = kv_enable_ulv(adev, true);
1329         if (ret) {
1330                 DRM_ERROR("kv_enable_ulv failed\n");
1331                 return ret;
1332         }
1333         kv_start_dpm(adev);
1334         ret = kv_enable_didt(adev, true);
1335         if (ret) {
1336                 DRM_ERROR("kv_enable_didt failed\n");
1337                 return ret;
1338         }
1339         ret = kv_enable_smc_cac(adev, true);
1340         if (ret) {
1341                 DRM_ERROR("kv_enable_smc_cac failed\n");
1342                 return ret;
1343         }
1344
1345         kv_reset_acp_boot_level(adev);
1346
1347         ret = amdgpu_kv_smc_bapm_enable(adev, false);
1348         if (ret) {
1349                 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1350                 return ret;
1351         }
1352
1353         if (adev->irq.installed &&
1354             amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
1355                 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
1356                 if (ret) {
1357                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1358                         return ret;
1359                 }
1360                 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1361                                AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1362                 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1363                                AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1364         }
1365
1366         return ret;
1367 }
1368
1369 static void kv_dpm_disable(struct amdgpu_device *adev)
1370 {
1371         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1372                        AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1373         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1374                        AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1375
1376         amdgpu_kv_smc_bapm_enable(adev, false);
1377
1378         if (adev->asic_type == CHIP_MULLINS)
1379                 kv_enable_nb_dpm(adev, false);
1380
1381         /* powerup blocks */
1382         kv_dpm_powergate_acp(adev, false);
1383         kv_dpm_powergate_samu(adev, false);
1384         kv_dpm_powergate_vce(adev, false);
1385         kv_dpm_powergate_uvd(adev, false);
1386
1387         kv_enable_smc_cac(adev, false);
1388         kv_enable_didt(adev, false);
1389         kv_clear_vc(adev);
1390         kv_stop_dpm(adev);
1391         kv_enable_ulv(adev, false);
1392         kv_reset_am(adev);
1393
1394         kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1395 }
1396
1397 #if 0
1398 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1399                                       u16 reg_offset, u32 value)
1400 {
1401         struct kv_power_info *pi = kv_get_pi(adev);
1402
1403         return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1404                                     (u8 *)&value, sizeof(u16), pi->sram_end);
1405 }
1406
1407 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1408                                      u16 reg_offset, u32 *value)
1409 {
1410         struct kv_power_info *pi = kv_get_pi(adev);
1411
1412         return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1413                                       value, pi->sram_end);
1414 }
1415 #endif
1416
1417 static void kv_init_sclk_t(struct amdgpu_device *adev)
1418 {
1419         struct kv_power_info *pi = kv_get_pi(adev);
1420
1421         pi->low_sclk_interrupt_t = 0;
1422 }
1423
1424 static int kv_init_fps_limits(struct amdgpu_device *adev)
1425 {
1426         struct kv_power_info *pi = kv_get_pi(adev);
1427         int ret = 0;
1428
1429         if (pi->caps_fps) {
1430                 u16 tmp;
1431
1432                 tmp = 45;
1433                 pi->fps_high_t = cpu_to_be16(tmp);
1434                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1435                                            pi->dpm_table_start +
1436                                            offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1437                                            (u8 *)&pi->fps_high_t,
1438                                            sizeof(u16), pi->sram_end);
1439
1440                 tmp = 30;
1441                 pi->fps_low_t = cpu_to_be16(tmp);
1442
1443                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1444                                            pi->dpm_table_start +
1445                                            offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1446                                            (u8 *)&pi->fps_low_t,
1447                                            sizeof(u16), pi->sram_end);
1448
1449         }
1450         return ret;
1451 }
1452
1453 static void kv_init_powergate_state(struct amdgpu_device *adev)
1454 {
1455         struct kv_power_info *pi = kv_get_pi(adev);
1456
1457         pi->uvd_power_gated = false;
1458         pi->vce_power_gated = false;
1459         pi->samu_power_gated = false;
1460         pi->acp_power_gated = false;
1461
1462 }
1463
1464 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1465 {
1466         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1467                                         PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1468 }
1469
1470 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1471 {
1472         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1473                                         PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1474 }
1475
1476 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
1477 {
1478         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1479                                         PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1480 }
1481
1482 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
1483 {
1484         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1485                                         PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1486 }
1487
1488 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1489 {
1490         struct kv_power_info *pi = kv_get_pi(adev);
1491         struct amdgpu_uvd_clock_voltage_dependency_table *table =
1492                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1493         int ret;
1494         u32 mask;
1495
1496         if (!gate) {
1497                 if (table->count)
1498                         pi->uvd_boot_level = table->count - 1;
1499                 else
1500                         pi->uvd_boot_level = 0;
1501
1502                 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1503                         mask = 1 << pi->uvd_boot_level;
1504                 } else {
1505                         mask = 0x1f;
1506                 }
1507
1508                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1509                                            pi->dpm_table_start +
1510                                            offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1511                                            (uint8_t *)&pi->uvd_boot_level,
1512                                            sizeof(u8), pi->sram_end);
1513                 if (ret)
1514                         return ret;
1515
1516                 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1517                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
1518                                                   mask);
1519         }
1520
1521         return kv_enable_uvd_dpm(adev, !gate);
1522 }
1523
1524 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
1525 {
1526         u8 i;
1527         struct amdgpu_vce_clock_voltage_dependency_table *table =
1528                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1529
1530         for (i = 0; i < table->count; i++) {
1531                 if (table->entries[i].evclk >= evclk)
1532                         break;
1533         }
1534
1535         return i;
1536 }
1537
1538 static int kv_update_vce_dpm(struct amdgpu_device *adev,
1539                              struct amdgpu_ps *amdgpu_new_state,
1540                              struct amdgpu_ps *amdgpu_current_state)
1541 {
1542         struct kv_power_info *pi = kv_get_pi(adev);
1543         struct amdgpu_vce_clock_voltage_dependency_table *table =
1544                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1545         int ret;
1546
1547         if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1548                 kv_dpm_powergate_vce(adev, false);
1549                 /* turn the clocks on when encoding */
1550                 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1551                                                     AMD_CG_STATE_UNGATE);
1552                 if (ret)
1553                         return ret;
1554                 if (pi->caps_stable_p_state)
1555                         pi->vce_boot_level = table->count - 1;
1556                 else
1557                         pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
1558
1559                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1560                                            pi->dpm_table_start +
1561                                            offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1562                                            (u8 *)&pi->vce_boot_level,
1563                                            sizeof(u8),
1564                                            pi->sram_end);
1565                 if (ret)
1566                         return ret;
1567
1568                 if (pi->caps_stable_p_state)
1569                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1570                                                           PPSMC_MSG_VCEDPM_SetEnabledMask,
1571                                                           (1 << pi->vce_boot_level));
1572
1573                 kv_enable_vce_dpm(adev, true);
1574         } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1575                 kv_enable_vce_dpm(adev, false);
1576                 /* turn the clocks off when not encoding */
1577                 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1578                                                     AMD_CG_STATE_GATE);
1579                 if (ret)
1580                         return ret;
1581                 kv_dpm_powergate_vce(adev, true);
1582         }
1583
1584         return 0;
1585 }
1586
1587 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
1588 {
1589         struct kv_power_info *pi = kv_get_pi(adev);
1590         struct amdgpu_clock_voltage_dependency_table *table =
1591                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1592         int ret;
1593
1594         if (!gate) {
1595                 if (pi->caps_stable_p_state)
1596                         pi->samu_boot_level = table->count - 1;
1597                 else
1598                         pi->samu_boot_level = 0;
1599
1600                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1601                                            pi->dpm_table_start +
1602                                            offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1603                                            (u8 *)&pi->samu_boot_level,
1604                                            sizeof(u8),
1605                                            pi->sram_end);
1606                 if (ret)
1607                         return ret;
1608
1609                 if (pi->caps_stable_p_state)
1610                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1611                                                           PPSMC_MSG_SAMUDPM_SetEnabledMask,
1612                                                           (1 << pi->samu_boot_level));
1613         }
1614
1615         return kv_enable_samu_dpm(adev, !gate);
1616 }
1617
1618 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
1619 {
1620         return 0;
1621 }
1622
1623 static void kv_update_acp_boot_level(struct amdgpu_device *adev)
1624 {
1625         struct kv_power_info *pi = kv_get_pi(adev);
1626         u8 acp_boot_level;
1627
1628         if (!pi->caps_stable_p_state) {
1629                 acp_boot_level = kv_get_acp_boot_level(adev);
1630                 if (acp_boot_level != pi->acp_boot_level) {
1631                         pi->acp_boot_level = acp_boot_level;
1632                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1633                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1634                                                           (1 << pi->acp_boot_level));
1635                 }
1636         }
1637 }
1638
1639 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
1640 {
1641         struct kv_power_info *pi = kv_get_pi(adev);
1642         struct amdgpu_clock_voltage_dependency_table *table =
1643                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1644         int ret;
1645
1646         if (!gate) {
1647                 if (pi->caps_stable_p_state)
1648                         pi->acp_boot_level = table->count - 1;
1649                 else
1650                         pi->acp_boot_level = kv_get_acp_boot_level(adev);
1651
1652                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1653                                            pi->dpm_table_start +
1654                                            offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1655                                            (u8 *)&pi->acp_boot_level,
1656                                            sizeof(u8),
1657                                            pi->sram_end);
1658                 if (ret)
1659                         return ret;
1660
1661                 if (pi->caps_stable_p_state)
1662                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1663                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1664                                                           (1 << pi->acp_boot_level));
1665         }
1666
1667         return kv_enable_acp_dpm(adev, !gate);
1668 }
1669
1670 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1671 {
1672         struct kv_power_info *pi = kv_get_pi(adev);
1673         int ret;
1674
1675         if (pi->uvd_power_gated == gate)
1676                 return;
1677
1678         pi->uvd_power_gated = gate;
1679
1680         if (gate) {
1681                 if (pi->caps_uvd_pg) {
1682                         /* disable clockgating so we can properly shut down the block */
1683                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1684                                                             AMD_CG_STATE_UNGATE);
1685                         /* shutdown the UVD block */
1686                         ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1687                                                             AMD_PG_STATE_GATE);
1688                         /* XXX: check for errors */
1689                 }
1690                 kv_update_uvd_dpm(adev, gate);
1691                 if (pi->caps_uvd_pg)
1692                         /* power off the UVD block */
1693                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1694         } else {
1695                 if (pi->caps_uvd_pg) {
1696                         /* power on the UVD block */
1697                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1698                         /* re-init the UVD block */
1699                         ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1700                                                             AMD_PG_STATE_UNGATE);
1701                         /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1702                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1703                                                             AMD_CG_STATE_GATE);
1704                         /* XXX: check for errors */
1705                 }
1706                 kv_update_uvd_dpm(adev, gate);
1707         }
1708 }
1709
1710 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1711 {
1712         struct kv_power_info *pi = kv_get_pi(adev);
1713         int ret;
1714
1715         if (pi->vce_power_gated == gate)
1716                 return;
1717
1718         pi->vce_power_gated = gate;
1719
1720         if (gate) {
1721                 if (pi->caps_vce_pg) {
1722                         /* shutdown the VCE block */
1723                         ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1724                                                             AMD_PG_STATE_GATE);
1725                         /* XXX: check for errors */
1726                         /* power off the VCE block */
1727                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1728                 }
1729         } else {
1730                 if (pi->caps_vce_pg) {
1731                         /* power on the VCE block */
1732                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1733                         /* re-init the VCE block */
1734                         ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1735                                                             AMD_PG_STATE_UNGATE);
1736                         /* XXX: check for errors */
1737                 }
1738         }
1739 }
1740
1741 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
1742 {
1743         struct kv_power_info *pi = kv_get_pi(adev);
1744
1745         if (pi->samu_power_gated == gate)
1746                 return;
1747
1748         pi->samu_power_gated = gate;
1749
1750         if (gate) {
1751                 kv_update_samu_dpm(adev, true);
1752                 if (pi->caps_samu_pg)
1753                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
1754         } else {
1755                 if (pi->caps_samu_pg)
1756                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
1757                 kv_update_samu_dpm(adev, false);
1758         }
1759 }
1760
1761 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
1762 {
1763         struct kv_power_info *pi = kv_get_pi(adev);
1764
1765         if (pi->acp_power_gated == gate)
1766                 return;
1767
1768         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
1769                 return;
1770
1771         pi->acp_power_gated = gate;
1772
1773         if (gate) {
1774                 kv_update_acp_dpm(adev, true);
1775                 if (pi->caps_acp_pg)
1776                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
1777         } else {
1778                 if (pi->caps_acp_pg)
1779                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
1780                 kv_update_acp_dpm(adev, false);
1781         }
1782 }
1783
1784 static void kv_set_valid_clock_range(struct amdgpu_device *adev,
1785                                      struct amdgpu_ps *new_rps)
1786 {
1787         struct kv_ps *new_ps = kv_get_ps(new_rps);
1788         struct kv_power_info *pi = kv_get_pi(adev);
1789         u32 i;
1790         struct amdgpu_clock_voltage_dependency_table *table =
1791                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1792
1793         if (table && table->count) {
1794                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1795                         if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1796                             (i == (pi->graphics_dpm_level_count - 1))) {
1797                                 pi->lowest_valid = i;
1798                                 break;
1799                         }
1800                 }
1801
1802                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1803                         if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1804                                 break;
1805                 }
1806                 pi->highest_valid = i;
1807
1808                 if (pi->lowest_valid > pi->highest_valid) {
1809                         if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1810                             (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1811                                 pi->highest_valid = pi->lowest_valid;
1812                         else
1813                                 pi->lowest_valid =  pi->highest_valid;
1814                 }
1815         } else {
1816                 struct sumo_sclk_voltage_mapping_table *table =
1817                         &pi->sys_info.sclk_voltage_mapping_table;
1818
1819                 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1820                         if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1821                             i == (int)(pi->graphics_dpm_level_count - 1)) {
1822                                 pi->lowest_valid = i;
1823                                 break;
1824                         }
1825                 }
1826
1827                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1828                         if (table->entries[i].sclk_frequency <=
1829                             new_ps->levels[new_ps->num_levels - 1].sclk)
1830                                 break;
1831                 }
1832                 pi->highest_valid = i;
1833
1834                 if (pi->lowest_valid > pi->highest_valid) {
1835                         if ((new_ps->levels[0].sclk -
1836                              table->entries[pi->highest_valid].sclk_frequency) >
1837                             (table->entries[pi->lowest_valid].sclk_frequency -
1838                              new_ps->levels[new_ps->num_levels -1].sclk))
1839                                 pi->highest_valid = pi->lowest_valid;
1840                         else
1841                                 pi->lowest_valid =  pi->highest_valid;
1842                 }
1843         }
1844 }
1845
1846 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
1847                                          struct amdgpu_ps *new_rps)
1848 {
1849         struct kv_ps *new_ps = kv_get_ps(new_rps);
1850         struct kv_power_info *pi = kv_get_pi(adev);
1851         int ret = 0;
1852         u8 clk_bypass_cntl;
1853
1854         if (pi->caps_enable_dfs_bypass) {
1855                 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1856                         pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1857                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1858                                            (pi->dpm_table_start +
1859                                             offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1860                                             (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1861                                             offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1862                                            &clk_bypass_cntl,
1863                                            sizeof(u8), pi->sram_end);
1864         }
1865
1866         return ret;
1867 }
1868
1869 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
1870                             bool enable)
1871 {
1872         struct kv_power_info *pi = kv_get_pi(adev);
1873         int ret = 0;
1874
1875         if (enable) {
1876                 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1877                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
1878                         if (ret == 0)
1879                                 pi->nb_dpm_enabled = true;
1880                 }
1881         } else {
1882                 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1883                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
1884                         if (ret == 0)
1885                                 pi->nb_dpm_enabled = false;
1886                 }
1887         }
1888
1889         return ret;
1890 }
1891
1892 static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
1893                                           enum amdgpu_dpm_forced_level level)
1894 {
1895         int ret;
1896
1897         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
1898                 ret = kv_force_dpm_highest(adev);
1899                 if (ret)
1900                         return ret;
1901         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
1902                 ret = kv_force_dpm_lowest(adev);
1903                 if (ret)
1904                         return ret;
1905         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
1906                 ret = kv_unforce_levels(adev);
1907                 if (ret)
1908                         return ret;
1909         }
1910
1911         adev->pm.dpm.forced_level = level;
1912
1913         return 0;
1914 }
1915
1916 static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
1917 {
1918         struct kv_power_info *pi = kv_get_pi(adev);
1919         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1920         struct amdgpu_ps *new_ps = &requested_ps;
1921
1922         kv_update_requested_ps(adev, new_ps);
1923
1924         kv_apply_state_adjust_rules(adev,
1925                                     &pi->requested_rps,
1926                                     &pi->current_rps);
1927
1928         return 0;
1929 }
1930
1931 static int kv_dpm_set_power_state(struct amdgpu_device *adev)
1932 {
1933         struct kv_power_info *pi = kv_get_pi(adev);
1934         struct amdgpu_ps *new_ps = &pi->requested_rps;
1935         struct amdgpu_ps *old_ps = &pi->current_rps;
1936         int ret;
1937
1938         if (pi->bapm_enable) {
1939                 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power);
1940                 if (ret) {
1941                         DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1942                         return ret;
1943                 }
1944         }
1945
1946         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
1947                 if (pi->enable_dpm) {
1948                         kv_set_valid_clock_range(adev, new_ps);
1949                         kv_update_dfs_bypass_settings(adev, new_ps);
1950                         ret = kv_calculate_ds_divider(adev);
1951                         if (ret) {
1952                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1953                                 return ret;
1954                         }
1955                         kv_calculate_nbps_level_settings(adev);
1956                         kv_calculate_dpm_settings(adev);
1957                         kv_force_lowest_valid(adev);
1958                         kv_enable_new_levels(adev);
1959                         kv_upload_dpm_settings(adev);
1960                         kv_program_nbps_index_settings(adev, new_ps);
1961                         kv_unforce_levels(adev);
1962                         kv_set_enabled_levels(adev);
1963                         kv_force_lowest_valid(adev);
1964                         kv_unforce_levels(adev);
1965
1966                         ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1967                         if (ret) {
1968                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1969                                 return ret;
1970                         }
1971                         kv_update_sclk_t(adev);
1972                         if (adev->asic_type == CHIP_MULLINS)
1973                                 kv_enable_nb_dpm(adev, true);
1974                 }
1975         } else {
1976                 if (pi->enable_dpm) {
1977                         kv_set_valid_clock_range(adev, new_ps);
1978                         kv_update_dfs_bypass_settings(adev, new_ps);
1979                         ret = kv_calculate_ds_divider(adev);
1980                         if (ret) {
1981                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1982                                 return ret;
1983                         }
1984                         kv_calculate_nbps_level_settings(adev);
1985                         kv_calculate_dpm_settings(adev);
1986                         kv_freeze_sclk_dpm(adev, true);
1987                         kv_upload_dpm_settings(adev);
1988                         kv_program_nbps_index_settings(adev, new_ps);
1989                         kv_freeze_sclk_dpm(adev, false);
1990                         kv_set_enabled_levels(adev);
1991                         ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1992                         if (ret) {
1993                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1994                                 return ret;
1995                         }
1996                         kv_update_acp_boot_level(adev);
1997                         kv_update_sclk_t(adev);
1998                         kv_enable_nb_dpm(adev, true);
1999                 }
2000         }
2001
2002         return 0;
2003 }
2004
2005 static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)
2006 {
2007         struct kv_power_info *pi = kv_get_pi(adev);
2008         struct amdgpu_ps *new_ps = &pi->requested_rps;
2009
2010         kv_update_current_ps(adev, new_ps);
2011 }
2012
2013 static void kv_dpm_setup_asic(struct amdgpu_device *adev)
2014 {
2015         sumo_take_smu_control(adev, true);
2016         kv_init_powergate_state(adev);
2017         kv_init_sclk_t(adev);
2018 }
2019
2020 #if 0
2021 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2022 {
2023         struct kv_power_info *pi = kv_get_pi(adev);
2024
2025         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2026                 kv_force_lowest_valid(adev);
2027                 kv_init_graphics_levels(adev);
2028                 kv_program_bootup_state(adev);
2029                 kv_upload_dpm_settings(adev);
2030                 kv_force_lowest_valid(adev);
2031                 kv_unforce_levels(adev);
2032         } else {
2033                 kv_init_graphics_levels(adev);
2034                 kv_program_bootup_state(adev);
2035                 kv_freeze_sclk_dpm(adev, true);
2036                 kv_upload_dpm_settings(adev);
2037                 kv_freeze_sclk_dpm(adev, false);
2038                 kv_set_enabled_level(adev, pi->graphics_boot_level);
2039         }
2040 }
2041 #endif
2042
2043 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
2044                                                 struct amdgpu_clock_and_voltage_limits *table)
2045 {
2046         struct kv_power_info *pi = kv_get_pi(adev);
2047
2048         if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
2049                 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
2050                 table->sclk =
2051                         pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
2052                 table->vddc =
2053                         kv_convert_2bit_index_to_voltage(adev,
2054                                                          pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
2055         }
2056
2057         table->mclk = pi->sys_info.nbp_memory_clock[0];
2058 }
2059
2060 static void kv_patch_voltage_values(struct amdgpu_device *adev)
2061 {
2062         int i;
2063         struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
2064                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
2065         struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
2066                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2067         struct amdgpu_clock_voltage_dependency_table *samu_table =
2068                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
2069         struct amdgpu_clock_voltage_dependency_table *acp_table =
2070                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
2071
2072         if (uvd_table->count) {
2073                 for (i = 0; i < uvd_table->count; i++)
2074                         uvd_table->entries[i].v =
2075                                 kv_convert_8bit_index_to_voltage(adev,
2076                                                                  uvd_table->entries[i].v);
2077         }
2078
2079         if (vce_table->count) {
2080                 for (i = 0; i < vce_table->count; i++)
2081                         vce_table->entries[i].v =
2082                                 kv_convert_8bit_index_to_voltage(adev,
2083                                                                  vce_table->entries[i].v);
2084         }
2085
2086         if (samu_table->count) {
2087                 for (i = 0; i < samu_table->count; i++)
2088                         samu_table->entries[i].v =
2089                                 kv_convert_8bit_index_to_voltage(adev,
2090                                                                  samu_table->entries[i].v);
2091         }
2092
2093         if (acp_table->count) {
2094                 for (i = 0; i < acp_table->count; i++)
2095                         acp_table->entries[i].v =
2096                                 kv_convert_8bit_index_to_voltage(adev,
2097                                                                  acp_table->entries[i].v);
2098         }
2099
2100 }
2101
2102 static void kv_construct_boot_state(struct amdgpu_device *adev)
2103 {
2104         struct kv_power_info *pi = kv_get_pi(adev);
2105
2106         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2107         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2108         pi->boot_pl.ds_divider_index = 0;
2109         pi->boot_pl.ss_divider_index = 0;
2110         pi->boot_pl.allow_gnb_slow = 1;
2111         pi->boot_pl.force_nbp_state = 0;
2112         pi->boot_pl.display_wm = 0;
2113         pi->boot_pl.vce_wm = 0;
2114 }
2115
2116 static int kv_force_dpm_highest(struct amdgpu_device *adev)
2117 {
2118         int ret;
2119         u32 enable_mask, i;
2120
2121         ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2122         if (ret)
2123                 return ret;
2124
2125         for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
2126                 if (enable_mask & (1 << i))
2127                         break;
2128         }
2129
2130         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2131                 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2132         else
2133                 return kv_set_enabled_level(adev, i);
2134 }
2135
2136 static int kv_force_dpm_lowest(struct amdgpu_device *adev)
2137 {
2138         int ret;
2139         u32 enable_mask, i;
2140
2141         ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2142         if (ret)
2143                 return ret;
2144
2145         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2146                 if (enable_mask & (1 << i))
2147                         break;
2148         }
2149
2150         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2151                 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2152         else
2153                 return kv_set_enabled_level(adev, i);
2154 }
2155
2156 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2157                                              u32 sclk, u32 min_sclk_in_sr)
2158 {
2159         struct kv_power_info *pi = kv_get_pi(adev);
2160         u32 i;
2161         u32 temp;
2162         u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);
2163
2164         if (sclk < min)
2165                 return 0;
2166
2167         if (!pi->caps_sclk_ds)
2168                 return 0;
2169
2170         for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2171                 temp = sclk >> i;
2172                 if (temp >= min)
2173                         break;
2174         }
2175
2176         return (u8)i;
2177 }
2178
2179 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
2180 {
2181         struct kv_power_info *pi = kv_get_pi(adev);
2182         struct amdgpu_clock_voltage_dependency_table *table =
2183                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2184         int i;
2185
2186         if (table && table->count) {
2187                 for (i = table->count - 1; i >= 0; i--) {
2188                         if (pi->high_voltage_t &&
2189                             (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
2190                              pi->high_voltage_t)) {
2191                                 *limit = i;
2192                                 return 0;
2193                         }
2194                 }
2195         } else {
2196                 struct sumo_sclk_voltage_mapping_table *table =
2197                         &pi->sys_info.sclk_voltage_mapping_table;
2198
2199                 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2200                         if (pi->high_voltage_t &&
2201                             (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
2202                              pi->high_voltage_t)) {
2203                                 *limit = i;
2204                                 return 0;
2205                         }
2206                 }
2207         }
2208
2209         *limit = 0;
2210         return 0;
2211 }
2212
2213 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
2214                                         struct amdgpu_ps *new_rps,
2215                                         struct amdgpu_ps *old_rps)
2216 {
2217         struct kv_ps *ps = kv_get_ps(new_rps);
2218         struct kv_power_info *pi = kv_get_pi(adev);
2219         u32 min_sclk = 10000; /* ??? */
2220         u32 sclk, mclk = 0;
2221         int i, limit;
2222         bool force_high;
2223         struct amdgpu_clock_voltage_dependency_table *table =
2224                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2225         u32 stable_p_state_sclk = 0;
2226         struct amdgpu_clock_and_voltage_limits *max_limits =
2227                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2228
2229         if (new_rps->vce_active) {
2230                 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
2231                 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
2232         } else {
2233                 new_rps->evclk = 0;
2234                 new_rps->ecclk = 0;
2235         }
2236
2237         mclk = max_limits->mclk;
2238         sclk = min_sclk;
2239
2240         if (pi->caps_stable_p_state) {
2241                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2242
2243                 for (i = table->count - 1; i >= 0; i--) {
2244                         if (stable_p_state_sclk >= table->entries[i].clk) {
2245                                 stable_p_state_sclk = table->entries[i].clk;
2246                                 break;
2247                         }
2248                 }
2249
2250                 if (i > 0)
2251                         stable_p_state_sclk = table->entries[0].clk;
2252
2253                 sclk = stable_p_state_sclk;
2254         }
2255
2256         if (new_rps->vce_active) {
2257                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
2258                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
2259         }
2260
2261         ps->need_dfs_bypass = true;
2262
2263         for (i = 0; i < ps->num_levels; i++) {
2264                 if (ps->levels[i].sclk < sclk)
2265                         ps->levels[i].sclk = sclk;
2266         }
2267
2268         if (table && table->count) {
2269                 for (i = 0; i < ps->num_levels; i++) {
2270                         if (pi->high_voltage_t &&
2271                             (pi->high_voltage_t <
2272                              kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2273                                 kv_get_high_voltage_limit(adev, &limit);
2274                                 ps->levels[i].sclk = table->entries[limit].clk;
2275                         }
2276                 }
2277         } else {
2278                 struct sumo_sclk_voltage_mapping_table *table =
2279                         &pi->sys_info.sclk_voltage_mapping_table;
2280
2281                 for (i = 0; i < ps->num_levels; i++) {
2282                         if (pi->high_voltage_t &&
2283                             (pi->high_voltage_t <
2284                              kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2285                                 kv_get_high_voltage_limit(adev, &limit);
2286                                 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2287                         }
2288                 }
2289         }
2290
2291         if (pi->caps_stable_p_state) {
2292                 for (i = 0; i < ps->num_levels; i++) {
2293                         ps->levels[i].sclk = stable_p_state_sclk;
2294                 }
2295         }
2296
2297         pi->video_start = new_rps->dclk || new_rps->vclk ||
2298                 new_rps->evclk || new_rps->ecclk;
2299
2300         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2301             ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2302                 pi->battery_state = true;
2303         else
2304                 pi->battery_state = false;
2305
2306         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2307                 ps->dpm0_pg_nb_ps_lo = 0x1;
2308                 ps->dpm0_pg_nb_ps_hi = 0x0;
2309                 ps->dpmx_nb_ps_lo = 0x1;
2310                 ps->dpmx_nb_ps_hi = 0x0;
2311         } else {
2312                 ps->dpm0_pg_nb_ps_lo = 0x3;
2313                 ps->dpm0_pg_nb_ps_hi = 0x0;
2314                 ps->dpmx_nb_ps_lo = 0x3;
2315                 ps->dpmx_nb_ps_hi = 0x0;
2316
2317                 if (pi->sys_info.nb_dpm_enable) {
2318                         force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2319                                 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
2320                                 pi->disable_nb_ps3_in_battery;
2321                         ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2322                         ps->dpm0_pg_nb_ps_hi = 0x2;
2323                         ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2324                         ps->dpmx_nb_ps_hi = 0x2;
2325                 }
2326         }
2327 }
2328
2329 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
2330                                                     u32 index, bool enable)
2331 {
2332         struct kv_power_info *pi = kv_get_pi(adev);
2333
2334         pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2335 }
2336
2337 static int kv_calculate_ds_divider(struct amdgpu_device *adev)
2338 {
2339         struct kv_power_info *pi = kv_get_pi(adev);
2340         u32 sclk_in_sr = 10000; /* ??? */
2341         u32 i;
2342
2343         if (pi->lowest_valid > pi->highest_valid)
2344                 return -EINVAL;
2345
2346         for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2347                 pi->graphics_level[i].DeepSleepDivId =
2348                         kv_get_sleep_divider_id_from_clock(adev,
2349                                                            be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2350                                                            sclk_in_sr);
2351         }
2352         return 0;
2353 }
2354
2355 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
2356 {
2357         struct kv_power_info *pi = kv_get_pi(adev);
2358         u32 i;
2359         bool force_high;
2360         struct amdgpu_clock_and_voltage_limits *max_limits =
2361                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2362         u32 mclk = max_limits->mclk;
2363
2364         if (pi->lowest_valid > pi->highest_valid)
2365                 return -EINVAL;
2366
2367         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2368                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2369                         pi->graphics_level[i].GnbSlow = 1;
2370                         pi->graphics_level[i].ForceNbPs1 = 0;
2371                         pi->graphics_level[i].UpH = 0;
2372                 }
2373
2374                 if (!pi->sys_info.nb_dpm_enable)
2375                         return 0;
2376
2377                 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2378                               (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2379
2380                 if (force_high) {
2381                         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2382                                 pi->graphics_level[i].GnbSlow = 0;
2383                 } else {
2384                         if (pi->battery_state)
2385                                 pi->graphics_level[0].ForceNbPs1 = 1;
2386
2387                         pi->graphics_level[1].GnbSlow = 0;
2388                         pi->graphics_level[2].GnbSlow = 0;
2389                         pi->graphics_level[3].GnbSlow = 0;
2390                         pi->graphics_level[4].GnbSlow = 0;
2391                 }
2392         } else {
2393                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2394                         pi->graphics_level[i].GnbSlow = 1;
2395                         pi->graphics_level[i].ForceNbPs1 = 0;
2396                         pi->graphics_level[i].UpH = 0;
2397                 }
2398
2399                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2400                         pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2401                         pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2402                         if (pi->lowest_valid != pi->highest_valid)
2403                                 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2404                 }
2405         }
2406         return 0;
2407 }
2408
2409 static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
2410 {
2411         struct kv_power_info *pi = kv_get_pi(adev);
2412         u32 i;
2413
2414         if (pi->lowest_valid > pi->highest_valid)
2415                 return -EINVAL;
2416
2417         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2418                 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2419
2420         return 0;
2421 }
2422
2423 static void kv_init_graphics_levels(struct amdgpu_device *adev)
2424 {
2425         struct kv_power_info *pi = kv_get_pi(adev);
2426         u32 i;
2427         struct amdgpu_clock_voltage_dependency_table *table =
2428                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2429
2430         if (table && table->count) {
2431                 u32 vid_2bit;
2432
2433                 pi->graphics_dpm_level_count = 0;
2434                 for (i = 0; i < table->count; i++) {
2435                         if (pi->high_voltage_t &&
2436                             (pi->high_voltage_t <
2437                              kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
2438                                 break;
2439
2440                         kv_set_divider_value(adev, i, table->entries[i].clk);
2441                         vid_2bit = kv_convert_vid7_to_vid2(adev,
2442                                                            &pi->sys_info.vid_mapping_table,
2443                                                            table->entries[i].v);
2444                         kv_set_vid(adev, i, vid_2bit);
2445                         kv_set_at(adev, i, pi->at[i]);
2446                         kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2447                         pi->graphics_dpm_level_count++;
2448                 }
2449         } else {
2450                 struct sumo_sclk_voltage_mapping_table *table =
2451                         &pi->sys_info.sclk_voltage_mapping_table;
2452
2453                 pi->graphics_dpm_level_count = 0;
2454                 for (i = 0; i < table->num_max_dpm_entries; i++) {
2455                         if (pi->high_voltage_t &&
2456                             pi->high_voltage_t <
2457                             kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
2458                                 break;
2459
2460                         kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
2461                         kv_set_vid(adev, i, table->entries[i].vid_2bit);
2462                         kv_set_at(adev, i, pi->at[i]);
2463                         kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2464                         pi->graphics_dpm_level_count++;
2465                 }
2466         }
2467
2468         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2469                 kv_dpm_power_level_enable(adev, i, false);
2470 }
2471
2472 static void kv_enable_new_levels(struct amdgpu_device *adev)
2473 {
2474         struct kv_power_info *pi = kv_get_pi(adev);
2475         u32 i;
2476
2477         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2478                 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2479                         kv_dpm_power_level_enable(adev, i, true);
2480         }
2481 }
2482
2483 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
2484 {
2485         u32 new_mask = (1 << level);
2486
2487         return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2488                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2489                                                  new_mask);
2490 }
2491
2492 static int kv_set_enabled_levels(struct amdgpu_device *adev)
2493 {
2494         struct kv_power_info *pi = kv_get_pi(adev);
2495         u32 i, new_mask = 0;
2496
2497         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2498                 new_mask |= (1 << i);
2499
2500         return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2501                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2502                                                  new_mask);
2503 }
2504
2505 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
2506                                            struct amdgpu_ps *new_rps)
2507 {
2508         struct kv_ps *new_ps = kv_get_ps(new_rps);
2509         struct kv_power_info *pi = kv_get_pi(adev);
2510         u32 nbdpmconfig1;
2511
2512         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2513                 return;
2514
2515         if (pi->sys_info.nb_dpm_enable) {
2516                 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2517                 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
2518                                 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
2519                                 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
2520                                 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
2521                 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
2522                                 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
2523                                 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
2524                                 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
2525                 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
2526         }
2527 }
2528
2529 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
2530                                             int min_temp, int max_temp)
2531 {
2532         int low_temp = 0 * 1000;
2533         int high_temp = 255 * 1000;
2534         u32 tmp;
2535
2536         if (low_temp < min_temp)
2537                 low_temp = min_temp;
2538         if (high_temp > max_temp)
2539                 high_temp = max_temp;
2540         if (high_temp < low_temp) {
2541                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2542                 return -EINVAL;
2543         }
2544
2545         tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2546         tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
2547                 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
2548         tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
2549                 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
2550         WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
2551
2552         adev->pm.dpm.thermal.min_temp = low_temp;
2553         adev->pm.dpm.thermal.max_temp = high_temp;
2554
2555         return 0;
2556 }
2557
2558 union igp_info {
2559         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2560         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2561         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2562         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2563         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2564         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2565 };
2566
2567 static int kv_parse_sys_info_table(struct amdgpu_device *adev)
2568 {
2569         struct kv_power_info *pi = kv_get_pi(adev);
2570         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2571         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2572         union igp_info *igp_info;
2573         u8 frev, crev;
2574         u16 data_offset;
2575         int i;
2576
2577         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2578                                    &frev, &crev, &data_offset)) {
2579                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2580                                               data_offset);
2581
2582                 if (crev != 8) {
2583                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2584                         return -EINVAL;
2585                 }
2586                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2587                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2588                 pi->sys_info.bootup_nb_voltage_index =
2589                         le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2590                 if (igp_info->info_8.ucHtcTmpLmt == 0)
2591                         pi->sys_info.htc_tmp_lmt = 203;
2592                 else
2593                         pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2594                 if (igp_info->info_8.ucHtcHystLmt == 0)
2595                         pi->sys_info.htc_hyst_lmt = 5;
2596                 else
2597                         pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2598                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2599                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2600                 }
2601
2602                 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2603                         pi->sys_info.nb_dpm_enable = true;
2604                 else
2605                         pi->sys_info.nb_dpm_enable = false;
2606
2607                 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2608                         pi->sys_info.nbp_memory_clock[i] =
2609                                 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2610                         pi->sys_info.nbp_n_clock[i] =
2611                                 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2612                 }
2613                 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2614                     SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2615                         pi->caps_enable_dfs_bypass = true;
2616
2617                 sumo_construct_sclk_voltage_mapping_table(adev,
2618                                                           &pi->sys_info.sclk_voltage_mapping_table,
2619                                                           igp_info->info_8.sAvail_SCLK);
2620
2621                 sumo_construct_vid_mapping_table(adev,
2622                                                  &pi->sys_info.vid_mapping_table,
2623                                                  igp_info->info_8.sAvail_SCLK);
2624
2625                 kv_construct_max_power_limits_table(adev,
2626                                                     &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2627         }
2628         return 0;
2629 }
2630
2631 union power_info {
2632         struct _ATOM_POWERPLAY_INFO info;
2633         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2634         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2635         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2636         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2637         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2638 };
2639
2640 union pplib_clock_info {
2641         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2642         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2643         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2644         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2645 };
2646
2647 union pplib_power_state {
2648         struct _ATOM_PPLIB_STATE v1;
2649         struct _ATOM_PPLIB_STATE_V2 v2;
2650 };
2651
2652 static void kv_patch_boot_state(struct amdgpu_device *adev,
2653                                 struct kv_ps *ps)
2654 {
2655         struct kv_power_info *pi = kv_get_pi(adev);
2656
2657         ps->num_levels = 1;
2658         ps->levels[0] = pi->boot_pl;
2659 }
2660
2661 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
2662                                           struct amdgpu_ps *rps,
2663                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2664                                           u8 table_rev)
2665 {
2666         struct kv_ps *ps = kv_get_ps(rps);
2667
2668         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2669         rps->class = le16_to_cpu(non_clock_info->usClassification);
2670         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2671
2672         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2673                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2674                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2675         } else {
2676                 rps->vclk = 0;
2677                 rps->dclk = 0;
2678         }
2679
2680         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2681                 adev->pm.dpm.boot_ps = rps;
2682                 kv_patch_boot_state(adev, ps);
2683         }
2684         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2685                 adev->pm.dpm.uvd_ps = rps;
2686 }
2687
2688 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
2689                                       struct amdgpu_ps *rps, int index,
2690                                         union pplib_clock_info *clock_info)
2691 {
2692         struct kv_power_info *pi = kv_get_pi(adev);
2693         struct kv_ps *ps = kv_get_ps(rps);
2694         struct kv_pl *pl = &ps->levels[index];
2695         u32 sclk;
2696
2697         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2698         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2699         pl->sclk = sclk;
2700         pl->vddc_index = clock_info->sumo.vddcIndex;
2701
2702         ps->num_levels = index + 1;
2703
2704         if (pi->caps_sclk_ds) {
2705                 pl->ds_divider_index = 5;
2706                 pl->ss_divider_index = 5;
2707         }
2708 }
2709
2710 static int kv_parse_power_table(struct amdgpu_device *adev)
2711 {
2712         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2713         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2714         union pplib_power_state *power_state;
2715         int i, j, k, non_clock_array_index, clock_array_index;
2716         union pplib_clock_info *clock_info;
2717         struct _StateArray *state_array;
2718         struct _ClockInfoArray *clock_info_array;
2719         struct _NonClockInfoArray *non_clock_info_array;
2720         union power_info *power_info;
2721         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2722         u16 data_offset;
2723         u8 frev, crev;
2724         u8 *power_state_offset;
2725         struct kv_ps *ps;
2726
2727         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2728                                    &frev, &crev, &data_offset))
2729                 return -EINVAL;
2730         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2731
2732         amdgpu_add_thermal_controller(adev);
2733
2734         state_array = (struct _StateArray *)
2735                 (mode_info->atom_context->bios + data_offset +
2736                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2737         clock_info_array = (struct _ClockInfoArray *)
2738                 (mode_info->atom_context->bios + data_offset +
2739                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2740         non_clock_info_array = (struct _NonClockInfoArray *)
2741                 (mode_info->atom_context->bios + data_offset +
2742                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2743
2744         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
2745                                   state_array->ucNumEntries, GFP_KERNEL);
2746         if (!adev->pm.dpm.ps)
2747                 return -ENOMEM;
2748         power_state_offset = (u8 *)state_array->states;
2749         for (i = 0; i < state_array->ucNumEntries; i++) {
2750                 u8 *idx;
2751                 power_state = (union pplib_power_state *)power_state_offset;
2752                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2753                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2754                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2755                 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2756                 if (ps == NULL) {
2757                         kfree(adev->pm.dpm.ps);
2758                         return -ENOMEM;
2759                 }
2760                 adev->pm.dpm.ps[i].ps_priv = ps;
2761                 k = 0;
2762                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2763                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2764                         clock_array_index = idx[j];
2765                         if (clock_array_index >= clock_info_array->ucNumEntries)
2766                                 continue;
2767                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2768                                 break;
2769                         clock_info = (union pplib_clock_info *)
2770                                 ((u8 *)&clock_info_array->clockInfo[0] +
2771                                  (clock_array_index * clock_info_array->ucEntrySize));
2772                         kv_parse_pplib_clock_info(adev,
2773                                                   &adev->pm.dpm.ps[i], k,
2774                                                   clock_info);
2775                         k++;
2776                 }
2777                 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
2778                                               non_clock_info,
2779                                               non_clock_info_array->ucEntrySize);
2780                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2781         }
2782         adev->pm.dpm.num_ps = state_array->ucNumEntries;
2783
2784         /* fill in the vce power states */
2785         for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
2786                 u32 sclk;
2787                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
2788                 clock_info = (union pplib_clock_info *)
2789                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2790                 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2791                 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2792                 adev->pm.dpm.vce_states[i].sclk = sclk;
2793                 adev->pm.dpm.vce_states[i].mclk = 0;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int kv_dpm_init(struct amdgpu_device *adev)
2800 {
2801         struct kv_power_info *pi;
2802         int ret, i;
2803
2804         pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2805         if (pi == NULL)
2806                 return -ENOMEM;
2807         adev->pm.dpm.priv = pi;
2808
2809         ret = amdgpu_get_platform_caps(adev);
2810         if (ret)
2811                 return ret;
2812
2813         ret = amdgpu_parse_extended_power_table(adev);
2814         if (ret)
2815                 return ret;
2816
2817         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2818                 pi->at[i] = TRINITY_AT_DFLT;
2819
2820         pi->sram_end = SMC_RAM_END;
2821
2822         pi->enable_nb_dpm = true;
2823
2824         pi->caps_power_containment = true;
2825         pi->caps_cac = true;
2826         pi->enable_didt = false;
2827         if (pi->enable_didt) {
2828                 pi->caps_sq_ramping = true;
2829                 pi->caps_db_ramping = true;
2830                 pi->caps_td_ramping = true;
2831                 pi->caps_tcp_ramping = true;
2832         }
2833
2834         if (amdgpu_sclk_deep_sleep_en)
2835                 pi->caps_sclk_ds = true;
2836         else
2837                 pi->caps_sclk_ds = false;
2838
2839         pi->enable_auto_thermal_throttling = true;
2840         pi->disable_nb_ps3_in_battery = false;
2841         if (amdgpu_bapm == 0)
2842                 pi->bapm_enable = false;
2843         else
2844                 pi->bapm_enable = true;
2845         pi->voltage_drop_t = 0;
2846         pi->caps_sclk_throttle_low_notification = false;
2847         pi->caps_fps = false; /* true? */
2848         pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2849         pi->caps_uvd_dpm = true;
2850         pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2851         pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2852         pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2853         pi->caps_stable_p_state = false;
2854
2855         ret = kv_parse_sys_info_table(adev);
2856         if (ret)
2857                 return ret;
2858
2859         kv_patch_voltage_values(adev);
2860         kv_construct_boot_state(adev);
2861
2862         ret = kv_parse_power_table(adev);
2863         if (ret)
2864                 return ret;
2865
2866         pi->enable_dpm = true;
2867
2868         return 0;
2869 }
2870
2871 static void
2872 kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
2873                                                struct seq_file *m)
2874 {
2875         struct kv_power_info *pi = kv_get_pi(adev);
2876         u32 current_index =
2877                 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2878                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
2879                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
2880         u32 sclk, tmp;
2881         u16 vddc;
2882
2883         if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2884                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2885         } else {
2886                 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2887                 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2888                         SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2889                         SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
2890                 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
2891                 seq_printf(m, "uvd    %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2892                 seq_printf(m, "vce    %sabled\n", pi->vce_power_gated ? "dis" : "en");
2893                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2894                            current_index, sclk, vddc);
2895         }
2896 }
2897
2898 static void
2899 kv_dpm_print_power_state(struct amdgpu_device *adev,
2900                          struct amdgpu_ps *rps)
2901 {
2902         int i;
2903         struct kv_ps *ps = kv_get_ps(rps);
2904
2905         amdgpu_dpm_print_class_info(rps->class, rps->class2);
2906         amdgpu_dpm_print_cap_info(rps->caps);
2907         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2908         for (i = 0; i < ps->num_levels; i++) {
2909                 struct kv_pl *pl = &ps->levels[i];
2910                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
2911                        i, pl->sclk,
2912                        kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
2913         }
2914         amdgpu_dpm_print_ps_status(adev, rps);
2915 }
2916
2917 static void kv_dpm_fini(struct amdgpu_device *adev)
2918 {
2919         int i;
2920
2921         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2922                 kfree(adev->pm.dpm.ps[i].ps_priv);
2923         }
2924         kfree(adev->pm.dpm.ps);
2925         kfree(adev->pm.dpm.priv);
2926         amdgpu_free_extended_power_table(adev);
2927 }
2928
2929 static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev)
2930 {
2931
2932 }
2933
2934 static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
2935 {
2936         struct kv_power_info *pi = kv_get_pi(adev);
2937         struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2938
2939         if (low)
2940                 return requested_state->levels[0].sclk;
2941         else
2942                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2943 }
2944
2945 static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low)
2946 {
2947         struct kv_power_info *pi = kv_get_pi(adev);
2948
2949         return pi->sys_info.bootup_uma_clk;
2950 }
2951
2952 /* get temperature in millidegrees */
2953 static int kv_dpm_get_temp(struct amdgpu_device *adev)
2954 {
2955         u32 temp;
2956         int actual_temp = 0;
2957
2958         temp = RREG32_SMC(0xC0300E0C);
2959
2960         if (temp)
2961                 actual_temp = (temp / 8) - 49;
2962         else
2963                 actual_temp = 0;
2964
2965         actual_temp = actual_temp * 1000;
2966
2967         return actual_temp;
2968 }
2969
2970 static int kv_dpm_early_init(void *handle)
2971 {
2972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2973
2974         kv_dpm_set_dpm_funcs(adev);
2975         kv_dpm_set_irq_funcs(adev);
2976
2977         return 0;
2978 }
2979
2980 static int kv_dpm_late_init(void *handle)
2981 {
2982         /* powerdown unused blocks for now */
2983         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2984         int ret;
2985
2986         if (!amdgpu_dpm)
2987                 return 0;
2988
2989         /* init the sysfs and debugfs files late */
2990         ret = amdgpu_pm_sysfs_init(adev);
2991         if (ret)
2992                 return ret;
2993
2994         kv_dpm_powergate_acp(adev, true);
2995         kv_dpm_powergate_samu(adev, true);
2996         kv_dpm_powergate_vce(adev, true);
2997         kv_dpm_powergate_uvd(adev, true);
2998
2999         return 0;
3000 }
3001
3002 static int kv_dpm_sw_init(void *handle)
3003 {
3004         int ret;
3005         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3006
3007         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
3008         if (ret)
3009                 return ret;
3010
3011         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
3012         if (ret)
3013                 return ret;
3014
3015         /* default to balanced state */
3016         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
3017         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
3018         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
3019         adev->pm.default_sclk = adev->clock.default_sclk;
3020         adev->pm.default_mclk = adev->clock.default_mclk;
3021         adev->pm.current_sclk = adev->clock.default_sclk;
3022         adev->pm.current_mclk = adev->clock.default_mclk;
3023         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
3024
3025         if (amdgpu_dpm == 0)
3026                 return 0;
3027
3028         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
3029         mutex_lock(&adev->pm.mutex);
3030         ret = kv_dpm_init(adev);
3031         if (ret)
3032                 goto dpm_failed;
3033         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3034         if (amdgpu_dpm == 1)
3035                 amdgpu_pm_print_power_states(adev);
3036         mutex_unlock(&adev->pm.mutex);
3037         DRM_INFO("amdgpu: dpm initialized\n");
3038
3039         return 0;
3040
3041 dpm_failed:
3042         kv_dpm_fini(adev);
3043         mutex_unlock(&adev->pm.mutex);
3044         DRM_ERROR("amdgpu: dpm initialization failed\n");
3045         return ret;
3046 }
3047
3048 static int kv_dpm_sw_fini(void *handle)
3049 {
3050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3051
3052         flush_work(&adev->pm.dpm.thermal.work);
3053
3054         mutex_lock(&adev->pm.mutex);
3055         amdgpu_pm_sysfs_fini(adev);
3056         kv_dpm_fini(adev);
3057         mutex_unlock(&adev->pm.mutex);
3058
3059         return 0;
3060 }
3061
3062 static int kv_dpm_hw_init(void *handle)
3063 {
3064         int ret;
3065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3066
3067         mutex_lock(&adev->pm.mutex);
3068         kv_dpm_setup_asic(adev);
3069         ret = kv_dpm_enable(adev);
3070         if (ret)
3071                 adev->pm.dpm_enabled = false;
3072         else
3073                 adev->pm.dpm_enabled = true;
3074         mutex_unlock(&adev->pm.mutex);
3075         amdgpu_pm_compute_clocks(adev);
3076         return ret;
3077 }
3078
3079 static int kv_dpm_hw_fini(void *handle)
3080 {
3081         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3082
3083         if (adev->pm.dpm_enabled) {
3084                 mutex_lock(&adev->pm.mutex);
3085                 kv_dpm_disable(adev);
3086                 mutex_unlock(&adev->pm.mutex);
3087         }
3088
3089         return 0;
3090 }
3091
3092 static int kv_dpm_suspend(void *handle)
3093 {
3094         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3095
3096         if (adev->pm.dpm_enabled) {
3097                 mutex_lock(&adev->pm.mutex);
3098                 /* disable dpm */
3099                 kv_dpm_disable(adev);
3100                 /* reset the power state */
3101                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3102                 mutex_unlock(&adev->pm.mutex);
3103         }
3104         return 0;
3105 }
3106
3107 static int kv_dpm_resume(void *handle)
3108 {
3109         int ret;
3110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3111
3112         if (adev->pm.dpm_enabled) {
3113                 /* asic init will reset to the boot state */
3114                 mutex_lock(&adev->pm.mutex);
3115                 kv_dpm_setup_asic(adev);
3116                 ret = kv_dpm_enable(adev);
3117                 if (ret)
3118                         adev->pm.dpm_enabled = false;
3119                 else
3120                         adev->pm.dpm_enabled = true;
3121                 mutex_unlock(&adev->pm.mutex);
3122                 if (adev->pm.dpm_enabled)
3123                         amdgpu_pm_compute_clocks(adev);
3124         }
3125         return 0;
3126 }
3127
3128 static bool kv_dpm_is_idle(void *handle)
3129 {
3130         return true;
3131 }
3132
3133 static int kv_dpm_wait_for_idle(void *handle)
3134 {
3135         return 0;
3136 }
3137
3138
3139 static int kv_dpm_soft_reset(void *handle)
3140 {
3141         return 0;
3142 }
3143
3144 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
3145                                       struct amdgpu_irq_src *src,
3146                                       unsigned type,
3147                                       enum amdgpu_interrupt_state state)
3148 {
3149         u32 cg_thermal_int;
3150
3151         switch (type) {
3152         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
3153                 switch (state) {
3154                 case AMDGPU_IRQ_STATE_DISABLE:
3155                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3156                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3157                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3158                         break;
3159                 case AMDGPU_IRQ_STATE_ENABLE:
3160                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3161                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3162                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3163                         break;
3164                 default:
3165                         break;
3166                 }
3167                 break;
3168
3169         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
3170                 switch (state) {
3171                 case AMDGPU_IRQ_STATE_DISABLE:
3172                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3173                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3174                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3175                         break;
3176                 case AMDGPU_IRQ_STATE_ENABLE:
3177                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3178                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3179                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3180                         break;
3181                 default:
3182                         break;
3183                 }
3184                 break;
3185
3186         default:
3187                 break;
3188         }
3189         return 0;
3190 }
3191
3192 static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
3193                                     struct amdgpu_irq_src *source,
3194                                     struct amdgpu_iv_entry *entry)
3195 {
3196         bool queue_thermal = false;
3197
3198         if (entry == NULL)
3199                 return -EINVAL;
3200
3201         switch (entry->src_id) {
3202         case 230: /* thermal low to high */
3203                 DRM_DEBUG("IH: thermal low to high\n");
3204                 adev->pm.dpm.thermal.high_to_low = false;
3205                 queue_thermal = true;
3206                 break;
3207         case 231: /* thermal high to low */
3208                 DRM_DEBUG("IH: thermal high to low\n");
3209                 adev->pm.dpm.thermal.high_to_low = true;
3210                 queue_thermal = true;
3211                 break;
3212         default:
3213                 break;
3214         }
3215
3216         if (queue_thermal)
3217                 schedule_work(&adev->pm.dpm.thermal.work);
3218
3219         return 0;
3220 }
3221
3222 static int kv_dpm_set_clockgating_state(void *handle,
3223                                           enum amd_clockgating_state state)
3224 {
3225         return 0;
3226 }
3227
3228 static int kv_dpm_set_powergating_state(void *handle,
3229                                           enum amd_powergating_state state)
3230 {
3231         return 0;
3232 }
3233
3234 const struct amd_ip_funcs kv_dpm_ip_funcs = {
3235         .name = "kv_dpm",
3236         .early_init = kv_dpm_early_init,
3237         .late_init = kv_dpm_late_init,
3238         .sw_init = kv_dpm_sw_init,
3239         .sw_fini = kv_dpm_sw_fini,
3240         .hw_init = kv_dpm_hw_init,
3241         .hw_fini = kv_dpm_hw_fini,
3242         .suspend = kv_dpm_suspend,
3243         .resume = kv_dpm_resume,
3244         .is_idle = kv_dpm_is_idle,
3245         .wait_for_idle = kv_dpm_wait_for_idle,
3246         .soft_reset = kv_dpm_soft_reset,
3247         .set_clockgating_state = kv_dpm_set_clockgating_state,
3248         .set_powergating_state = kv_dpm_set_powergating_state,
3249 };
3250
3251 static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
3252         .get_temperature = &kv_dpm_get_temp,
3253         .pre_set_power_state = &kv_dpm_pre_set_power_state,
3254         .set_power_state = &kv_dpm_set_power_state,
3255         .post_set_power_state = &kv_dpm_post_set_power_state,
3256         .display_configuration_changed = &kv_dpm_display_configuration_changed,
3257         .get_sclk = &kv_dpm_get_sclk,
3258         .get_mclk = &kv_dpm_get_mclk,
3259         .print_power_state = &kv_dpm_print_power_state,
3260         .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
3261         .force_performance_level = &kv_dpm_force_performance_level,
3262         .powergate_uvd = &kv_dpm_powergate_uvd,
3263         .enable_bapm = &kv_dpm_enable_bapm,
3264 };
3265
3266 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
3267 {
3268         if (adev->pm.funcs == NULL)
3269                 adev->pm.funcs = &kv_dpm_funcs;
3270 }
3271
3272 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
3273         .set = kv_dpm_set_interrupt_state,
3274         .process = kv_dpm_process_interrupt,
3275 };
3276
3277 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
3278 {
3279         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
3280         adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
3281 }