drivers/gpu/drm/amd/amdgpu/kv_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_dpm.h"
  31 #include "kv_dpm.h"
  32 #include "gfx_v7_0.h"
  33 #include <linux/seq_file.h>
  34
  35 #include "smu/smu_7_0_0_d.h"
  36 #include "smu/smu_7_0_0_sh_mask.h"
  37
  38 #include "gca/gfx_7_2_d.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  42 #define KV_MINIMUM_ENGINE_CLOCK         800
  43 #define SMC_RAM_END                     0x40000
  44
  45 static const struct amd_pm_funcs kv_dpm_funcs;
  46
  47 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
  48 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
  49                             bool enable);
  50 static void kv_init_graphics_levels(struct amdgpu_device *adev);
  51 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
  52 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
  53 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
  54 static void kv_enable_new_levels(struct amdgpu_device *adev);
  55 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
  56                                            struct amdgpu_ps *new_rps);
  57 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
  58 static int kv_set_enabled_levels(struct amdgpu_device *adev);
  59 static int kv_force_dpm_highest(struct amdgpu_device *adev);
  60 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
  61 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
  62                                         struct amdgpu_ps *new_rps,
  63                                         struct amdgpu_ps *old_rps);
  64 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
  65                                             int min_temp, int max_temp);
  66 static int kv_init_fps_limits(struct amdgpu_device *adev);
  67
  68 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
  69 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
  70
  71
  72 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
  73                                    struct sumo_vid_mapping_table *vid_mapping_table,
  74                                    u32 vid_2bit)
  75 {
  76         struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  77                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  78         u32 i;
  79
  80         if (vddc_sclk_table && vddc_sclk_table->count) {
  81                 if (vid_2bit < vddc_sclk_table->count)
  82                         return vddc_sclk_table->entries[vid_2bit].v;
  83                 else
  84                         return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
  85         } else {
  86                 for (i = 0; i < vid_mapping_table->num_entries; i++) {
  87                         if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
  88                                 return vid_mapping_table->entries[i].vid_7bit;
  89                 }
  90                 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
  91         }
  92 }
  93
  94 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
  95                                    struct sumo_vid_mapping_table *vid_mapping_table,
  96                                    u32 vid_7bit)
  97 {
  98         struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  99                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 100         u32 i;
 101
 102         if (vddc_sclk_table && vddc_sclk_table->count) {
 103                 for (i = 0; i < vddc_sclk_table->count; i++) {
 104                         if (vddc_sclk_table->entries[i].v == vid_7bit)
 105                                 return i;
 106                 }
 107                 return vddc_sclk_table->count - 1;
 108         } else {
 109                 for (i = 0; i < vid_mapping_table->num_entries; i++) {
 110                         if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
 111                                 return vid_mapping_table->entries[i].vid_2bit;
 112                 }
 113
 114                 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
 115         }
 116 }
 117
 118 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
 119 {
 120 /* This bit selects who handles display phy powergating.
 121  * Clear the bit to let atom handle it.
 122  * Set it to let the driver handle it.
 123  * For now we just let atom handle it.
 124  */
 125 #if 0
 126         u32 v = RREG32(mmDOUT_SCRATCH3);
 127
 128         if (enable)
 129                 v |= 0x4;
 130         else
 131                 v &= 0xFFFFFFFB;
 132
 133         WREG32(mmDOUT_SCRATCH3, v);
 134 #endif
 135 }
 136
 137 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
 138                                                       struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
 139                                                       ATOM_AVAILABLE_SCLK_LIST *table)
 140 {
 141         u32 i;
 142         u32 n = 0;
 143         u32 prev_sclk = 0;
 144
 145         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 146                 if (table[i].ulSupportedSCLK > prev_sclk) {
 147                         sclk_voltage_mapping_table->entries[n].sclk_frequency =
 148                                 table[i].ulSupportedSCLK;
 149                         sclk_voltage_mapping_table->entries[n].vid_2bit =
 150                                 table[i].usVoltageIndex;
 151                         prev_sclk = table[i].ulSupportedSCLK;
 152                         n++;
 153                 }
 154         }
 155
 156         sclk_voltage_mapping_table->num_max_dpm_entries = n;
 157 }
 158
 159 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
 160                                              struct sumo_vid_mapping_table *vid_mapping_table,
 161                                              ATOM_AVAILABLE_SCLK_LIST *table)
 162 {
 163         u32 i, j;
 164
 165         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 166                 if (table[i].ulSupportedSCLK != 0) {
 167                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
 168                                 table[i].usVoltageID;
 169                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
 170                                 table[i].usVoltageIndex;
 171                 }
 172         }
 173
 174         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
 175                 if (vid_mapping_table->entries[i].vid_7bit == 0) {
 176                         for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
 177                                 if (vid_mapping_table->entries[j].vid_7bit != 0) {
 178                                         vid_mapping_table->entries[i] =
 179                                                 vid_mapping_table->entries[j];
 180                                         vid_mapping_table->entries[j].vid_7bit = 0;
 181                                         break;
 182                                 }
 183                         }
 184
 185                         if (j == SUMO_MAX_NUMBER_VOLTAGES)
 186                                 break;
 187                 }
 188         }
 189
 190         vid_mapping_table->num_entries = i;
 191 }
 192
 193 #if 0
 194 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
 195 {
 196         {  0,       4,        1    },
 197         {  1,       4,        1    },
 198         {  2,       5,        1    },
 199         {  3,       4,        2    },
 200         {  4,       1,        1    },
 201         {  5,       5,        2    },
 202         {  6,       6,        1    },
 203         {  7,       9,        2    },
 204         { 0xffffffff }
 205 };
 206
 207 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
 208 {
 209         {  0,       4,        1    },
 210         { 0xffffffff }
 211 };
 212
 213 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
 214 {
 215         {  0,       4,        1    },
 216         { 0xffffffff }
 217 };
 218
 219 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
 220 {
 221         {  0,       4,        1    },
 222         { 0xffffffff }
 223 };
 224
 225 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
 226 {
 227         {  0,       4,        1    },
 228         { 0xffffffff }
 229 };
 230
 231 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
 232 {
 233         {  0,       4,        1    },
 234         {  1,       4,        1    },
 235         {  2,       5,        1    },
 236         {  3,       4,        1    },
 237         {  4,       1,        1    },
 238         {  5,       5,        1    },
 239         {  6,       6,        1    },
 240         {  7,       9,        1    },
 241         {  8,       4,        1    },
 242         {  9,       2,        1    },
 243         {  10,      3,        1    },
 244         {  11,      6,        1    },
 245         {  12,      8,        2    },
 246         {  13,      1,        1    },
 247         {  14,      2,        1    },
 248         {  15,      3,        1    },
 249         {  16,      1,        1    },
 250         {  17,      4,        1    },
 251         {  18,      3,        1    },
 252         {  19,      1,        1    },
 253         {  20,      8,        1    },
 254         {  21,      5,        1    },
 255         {  22,      1,        1    },
 256         {  23,      1,        1    },
 257         {  24,      4,        1    },
 258         {  27,      6,        1    },
 259         {  28,      1,        1    },
 260         { 0xffffffff }
 261 };
 262
 263 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 264 {
 265         { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 266 };
 267
 268 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 269 {
 270         { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 271 };
 272
 273 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 274 {
 275         { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 276 };
 277
 278 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 279 {
 280         { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 281 };
 282
 283 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 284 {
 285         { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 286 };
 287
 288 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 289 {
 290         { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 291 };
 292 #endif
 293
 294 static const struct kv_pt_config_reg didt_config_kv[] =
 295 {
 296         { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 297         { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 298         { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 299         { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 300         { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 301         { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 302         { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 303         { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 304         { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 305         { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 306         { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 307         { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 308         { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 309         { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 310         { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 311         { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 312         { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 313         { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 314         { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 315         { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 316         { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 317         { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 318         { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 319         { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 320         { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 321         { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 322         { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 323         { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 324         { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 325         { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 326         { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 327         { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 328         { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 329         { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 330         { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 331         { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 332         { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 333         { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 334         { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 335         { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 336         { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 337         { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 338         { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 339         { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 340         { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 341         { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 342         { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 343         { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 344         { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 345         { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 346         { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 347         { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 348         { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 349         { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 350         { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 351         { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 352         { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 353         { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 354         { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 355         { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 356         { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 357         { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 358         { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 359         { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 360         { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 361         { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 362         { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 363         { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 364         { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 365         { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 366         { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 367         { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 368         { 0xFFFFFFFF }
 369 };
 370
 371 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
 372 {
 373         struct kv_ps *ps = rps->ps_priv;
 374
 375         return ps;
 376 }
 377
 378 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
 379 {
 380         struct kv_power_info *pi = adev->pm.dpm.priv;
 381
 382         return pi;
 383 }
 384
 385 #if 0
 386 static void kv_program_local_cac_table(struct amdgpu_device *adev,
 387                                        const struct kv_lcac_config_values *local_cac_table,
 388                                        const struct kv_lcac_config_reg *local_cac_reg)
 389 {
 390         u32 i, count, data;
 391         const struct kv_lcac_config_values *values = local_cac_table;
 392
 393         while (values->block_id != 0xffffffff) {
 394                 count = values->signal_id;
 395                 for (i = 0; i < count; i++) {
 396                         data = ((values->block_id << local_cac_reg->block_shift) &
 397                                 local_cac_reg->block_mask);
 398                         data |= ((i << local_cac_reg->signal_shift) &
 399                                  local_cac_reg->signal_mask);
 400                         data |= ((values->t << local_cac_reg->t_shift) &
 401                                  local_cac_reg->t_mask);
 402                         data |= ((1 << local_cac_reg->enable_shift) &
 403                                  local_cac_reg->enable_mask);
 404                         WREG32_SMC(local_cac_reg->cntl, data);
 405                 }
 406                 values++;
 407         }
 408 }
 409 #endif
 410
 411 static int kv_program_pt_config_registers(struct amdgpu_device *adev,
 412                                           const struct kv_pt_config_reg *cac_config_regs)
 413 {
 414         const struct kv_pt_config_reg *config_regs = cac_config_regs;
 415         u32 data;
 416         u32 cache = 0;
 417
 418         if (config_regs == NULL)
 419                 return -EINVAL;
 420
 421         while (config_regs->offset != 0xFFFFFFFF) {
 422                 if (config_regs->type == KV_CONFIGREG_CACHE) {
 423                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 424                 } else {
 425                         switch (config_regs->type) {
 426                         case KV_CONFIGREG_SMC_IND:
 427                                 data = RREG32_SMC(config_regs->offset);
 428                                 break;
 429                         case KV_CONFIGREG_DIDT_IND:
 430                                 data = RREG32_DIDT(config_regs->offset);
 431                                 break;
 432                         default:
 433                                 data = RREG32(config_regs->offset);
 434                                 break;
 435                         }
 436
 437                         data &= ~config_regs->mask;
 438                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 439                         data |= cache;
 440                         cache = 0;
 441
 442                         switch (config_regs->type) {
 443                         case KV_CONFIGREG_SMC_IND:
 444                                 WREG32_SMC(config_regs->offset, data);
 445                                 break;
 446                         case KV_CONFIGREG_DIDT_IND:
 447                                 WREG32_DIDT(config_regs->offset, data);
 448                                 break;
 449                         default:
 450                                 WREG32(config_regs->offset, data);
 451                                 break;
 452                         }
 453                 }
 454                 config_regs++;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
 461 {
 462         struct kv_power_info *pi = kv_get_pi(adev);
 463         u32 data;
 464
 465         if (pi->caps_sq_ramping) {
 466                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 467                 if (enable)
 468                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 469                 else
 470                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 471                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 472         }
 473
 474         if (pi->caps_db_ramping) {
 475                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 476                 if (enable)
 477                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 478                 else
 479                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 480                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 481         }
 482
 483         if (pi->caps_td_ramping) {
 484                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 485                 if (enable)
 486                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 487                 else
 488                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 489                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 490         }
 491
 492         if (pi->caps_tcp_ramping) {
 493                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 494                 if (enable)
 495                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 496                 else
 497                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 498                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 499         }
 500 }
 501
 502 static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
 503 {
 504         struct kv_power_info *pi = kv_get_pi(adev);
 505         int ret;
 506
 507         if (pi->caps_sq_ramping ||
 508             pi->caps_db_ramping ||
 509             pi->caps_td_ramping ||
 510             pi->caps_tcp_ramping) {
 511                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 512
 513                 if (enable) {
 514                         ret = kv_program_pt_config_registers(adev, didt_config_kv);
 515                         if (ret) {
 516                                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 517                                 return ret;
 518                         }
 519                 }
 520
 521                 kv_do_enable_didt(adev, enable);
 522
 523                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 524         }
 525
 526         return 0;
 527 }
 528
 529 #if 0
 530 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
 531 {
 532         struct kv_power_info *pi = kv_get_pi(adev);
 533
 534         if (pi->caps_cac) {
 535                 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
 536                 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
 537                 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 538
 539                 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
 540                 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
 541                 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 542
 543                 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
 544                 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
 545                 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 546
 547                 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
 548                 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
 549                 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 550
 551                 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
 552                 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
 553                 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 554
 555                 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
 556                 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
 557                 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 558         }
 559 }
 560 #endif
 561
 562 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 563 {
 564         struct kv_power_info *pi = kv_get_pi(adev);
 565         int ret = 0;
 566
 567         if (pi->caps_cac) {
 568                 if (enable) {
 569                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
 570                         if (ret)
 571                                 pi->cac_enabled = false;
 572                         else
 573                                 pi->cac_enabled = true;
 574                 } else if (pi->cac_enabled) {
 575                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
 576                         pi->cac_enabled = false;
 577                 }
 578         }
 579
 580         return ret;
 581 }
 582
 583 static int kv_process_firmware_header(struct amdgpu_device *adev)
 584 {
 585         struct kv_power_info *pi = kv_get_pi(adev);
 586         u32 tmp;
 587         int ret;
 588
 589         ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 590                                      offsetof(SMU7_Firmware_Header, DpmTable),
 591                                      &tmp, pi->sram_end);
 592
 593         if (ret == 0)
 594                 pi->dpm_table_start = tmp;
 595
 596         ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 597                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
 598                                      &tmp, pi->sram_end);
 599
 600         if (ret == 0)
 601                 pi->soft_regs_start = tmp;
 602
 603         return ret;
 604 }
 605
 606 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
 607 {
 608         struct kv_power_info *pi = kv_get_pi(adev);
 609         int ret;
 610
 611         pi->graphics_voltage_change_enable = 1;
 612
 613         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 614                                    pi->dpm_table_start +
 615                                    offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 616                                    &pi->graphics_voltage_change_enable,
 617                                    sizeof(u8), pi->sram_end);
 618
 619         return ret;
 620 }
 621
 622 static int kv_set_dpm_interval(struct amdgpu_device *adev)
 623 {
 624         struct kv_power_info *pi = kv_get_pi(adev);
 625         int ret;
 626
 627         pi->graphics_interval = 1;
 628
 629         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 630                                    pi->dpm_table_start +
 631                                    offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 632                                    &pi->graphics_interval,
 633                                    sizeof(u8), pi->sram_end);
 634
 635         return ret;
 636 }
 637
 638 static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
 639 {
 640         struct kv_power_info *pi = kv_get_pi(adev);
 641         int ret;
 642
 643         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 644                                    pi->dpm_table_start +
 645                                    offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 646                                    &pi->graphics_boot_level,
 647                                    sizeof(u8), pi->sram_end);
 648
 649         return ret;
 650 }
 651
 652 static void kv_program_vc(struct amdgpu_device *adev)
 653 {
 654         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
 655 }
 656
 657 static void kv_clear_vc(struct amdgpu_device *adev)
 658 {
 659         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
 660 }
 661
 662 static int kv_set_divider_value(struct amdgpu_device *adev,
 663                                 u32 index, u32 sclk)
 664 {
 665         struct kv_power_info *pi = kv_get_pi(adev);
 666         struct atom_clock_dividers dividers;
 667         int ret;
 668
 669         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 670                                                  sclk, false, &dividers);
 671         if (ret)
 672                 return ret;
 673
 674         pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 675         pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 676
 677         return 0;
 678 }
 679
 680 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
 681                                             u16 voltage)
 682 {
 683         return 6200 - (voltage * 25);
 684 }
 685
 686 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
 687                                             u32 vid_2bit)
 688 {
 689         struct kv_power_info *pi = kv_get_pi(adev);
 690         u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
 691                                                &pi->sys_info.vid_mapping_table,
 692                                                vid_2bit);
 693
 694         return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
 695 }
 696
 697
 698 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
 699 {
 700         struct kv_power_info *pi = kv_get_pi(adev);
 701
 702         pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 703         pi->graphics_level[index].MinVddNb =
 704                 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
 705
 706         return 0;
 707 }
 708
 709 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
 710 {
 711         struct kv_power_info *pi = kv_get_pi(adev);
 712
 713         pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 714
 715         return 0;
 716 }
 717
 718 static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
 719                                       u32 index, bool enable)
 720 {
 721         struct kv_power_info *pi = kv_get_pi(adev);
 722
 723         pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 724 }
 725
 726 static void kv_start_dpm(struct amdgpu_device *adev)
 727 {
 728         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
 729
 730         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
 731         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
 732
 733         amdgpu_kv_smc_dpm_enable(adev, true);
 734 }
 735
 736 static void kv_stop_dpm(struct amdgpu_device *adev)
 737 {
 738         amdgpu_kv_smc_dpm_enable(adev, false);
 739 }
 740
 741 static void kv_start_am(struct amdgpu_device *adev)
 742 {
 743         u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 744
 745         sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 746                         SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 747         sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
 748
 749         WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 750 }
 751
 752 static void kv_reset_am(struct amdgpu_device *adev)
 753 {
 754         u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 755
 756         sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 757                         SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 758
 759         WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 760 }
 761
 762 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
 763 {
 764         return amdgpu_kv_notify_message_to_smu(adev, freeze ?
 765                                         PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 766 }
 767
 768 static int kv_force_lowest_valid(struct amdgpu_device *adev)
 769 {
 770         return kv_force_dpm_lowest(adev);
 771 }
 772
 773 static int kv_unforce_levels(struct amdgpu_device *adev)
 774 {
 775         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
 776                 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
 777         else
 778                 return kv_set_enabled_levels(adev);
 779 }
 780
 781 static int kv_update_sclk_t(struct amdgpu_device *adev)
 782 {
 783         struct kv_power_info *pi = kv_get_pi(adev);
 784         u32 low_sclk_interrupt_t = 0;
 785         int ret = 0;
 786
 787         if (pi->caps_sclk_throttle_low_notification) {
 788                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 789
 790                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
 791                                            pi->dpm_table_start +
 792                                            offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 793                                            (u8 *)&low_sclk_interrupt_t,
 794                                            sizeof(u32), pi->sram_end);
 795         }
 796         return ret;
 797 }
 798
 799 static int kv_program_bootup_state(struct amdgpu_device *adev)
 800 {
 801         struct kv_power_info *pi = kv_get_pi(adev);
 802         u32 i;
 803         struct amdgpu_clock_voltage_dependency_table *table =
 804                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 805
 806         if (table && table->count) {
 807                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 808                         if (table->entries[i].clk == pi->boot_pl.sclk)
 809                                 break;
 810                 }
 811
 812                 pi->graphics_boot_level = (u8)i;
 813                 kv_dpm_power_level_enable(adev, i, true);
 814         } else {
 815                 struct sumo_sclk_voltage_mapping_table *table =
 816                         &pi->sys_info.sclk_voltage_mapping_table;
 817
 818                 if (table->num_max_dpm_entries == 0)
 819                         return -EINVAL;
 820
 821                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 822                         if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
 823                                 break;
 824                 }
 825
 826                 pi->graphics_boot_level = (u8)i;
 827                 kv_dpm_power_level_enable(adev, i, true);
 828         }
 829         return 0;
 830 }
 831
 832 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
 833 {
 834         struct kv_power_info *pi = kv_get_pi(adev);
 835         int ret;
 836
 837         pi->graphics_therm_throttle_enable = 1;
 838
 839         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 840                                    pi->dpm_table_start +
 841                                    offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 842                                    &pi->graphics_therm_throttle_enable,
 843                                    sizeof(u8), pi->sram_end);
 844
 845         return ret;
 846 }
 847
 848 static int kv_upload_dpm_settings(struct amdgpu_device *adev)
 849 {
 850         struct kv_power_info *pi = kv_get_pi(adev);
 851         int ret;
 852
 853         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 854                                    pi->dpm_table_start +
 855                                    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 856                                    (u8 *)&pi->graphics_level,
 857                                    sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 858                                    pi->sram_end);
 859
 860         if (ret)
 861                 return ret;
 862
 863         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 864                                    pi->dpm_table_start +
 865                                    offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 866                                    &pi->graphics_dpm_level_count,
 867                                    sizeof(u8), pi->sram_end);
 868
 869         return ret;
 870 }
 871
 872 static u32 kv_get_clock_difference(u32 a, u32 b)
 873 {
 874         return (a >= b) ? a - b : b - a;
 875 }
 876
 877 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
 878 {
 879         struct kv_power_info *pi = kv_get_pi(adev);
 880         u32 value;
 881
 882         if (pi->caps_enable_dfs_bypass) {
 883                 if (kv_get_clock_difference(clk, 40000) < 200)
 884                         value = 3;
 885                 else if (kv_get_clock_difference(clk, 30000) < 200)
 886                         value = 2;
 887                 else if (kv_get_clock_difference(clk, 20000) < 200)
 888                         value = 7;
 889                 else if (kv_get_clock_difference(clk, 15000) < 200)
 890                         value = 6;
 891                 else if (kv_get_clock_difference(clk, 10000) < 200)
 892                         value = 8;
 893                 else
 894                         value = 0;
 895         } else {
 896                 value = 0;
 897         }
 898
 899         return value;
 900 }
 901
 902 static int kv_populate_uvd_table(struct amdgpu_device *adev)
 903 {
 904         struct kv_power_info *pi = kv_get_pi(adev);
 905         struct amdgpu_uvd_clock_voltage_dependency_table *table =
 906                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 907         struct atom_clock_dividers dividers;
 908         int ret;
 909         u32 i;
 910
 911         if (table == NULL || table->count == 0)
 912                 return 0;
 913
 914         pi->uvd_level_count = 0;
 915         for (i = 0; i < table->count; i++) {
 916                 if (pi->high_voltage_t &&
 917                     (pi->high_voltage_t < table->entries[i].v))
 918                         break;
 919
 920                 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 921                 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 922                 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 923
 924                 pi->uvd_level[i].VClkBypassCntl =
 925                         (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
 926                 pi->uvd_level[i].DClkBypassCntl =
 927                         (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
 928
 929                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 930                                                          table->entries[i].vclk, false, &dividers);
 931                 if (ret)
 932                         return ret;
 933                 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 934
 935                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 936                                                          table->entries[i].dclk, false, &dividers);
 937                 if (ret)
 938                         return ret;
 939                 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 940
 941                 pi->uvd_level_count++;
 942         }
 943
 944         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 945                                    pi->dpm_table_start +
 946                                    offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 947                                    (u8 *)&pi->uvd_level_count,
 948                                    sizeof(u8), pi->sram_end);
 949         if (ret)
 950                 return ret;
 951
 952         pi->uvd_interval = 1;
 953
 954         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 955                                    pi->dpm_table_start +
 956                                    offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 957                                    &pi->uvd_interval,
 958                                    sizeof(u8), pi->sram_end);
 959         if (ret)
 960                 return ret;
 961
 962         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 963                                    pi->dpm_table_start +
 964                                    offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 965                                    (u8 *)&pi->uvd_level,
 966                                    sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 967                                    pi->sram_end);
 968
 969         return ret;
 970
 971 }
 972
 973 static int kv_populate_vce_table(struct amdgpu_device *adev)
 974 {
 975         struct kv_power_info *pi = kv_get_pi(adev);
 976         int ret;
 977         u32 i;
 978         struct amdgpu_vce_clock_voltage_dependency_table *table =
 979                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 980         struct atom_clock_dividers dividers;
 981
 982         if (table == NULL || table->count == 0)
 983                 return 0;
 984
 985         pi->vce_level_count = 0;
 986         for (i = 0; i < table->count; i++) {
 987                 if (pi->high_voltage_t &&
 988                     pi->high_voltage_t < table->entries[i].v)
 989                         break;
 990
 991                 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 992                 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 993
 994                 pi->vce_level[i].ClkBypassCntl =
 995                         (u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
 996
 997                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 998                                                          table->entries[i].evclk, false, &dividers);
 999                 if (ret)
1000                         return ret;
1001                 pi->vce_level[i].Divider = (u8)dividers.post_div;
1002
1003                 pi->vce_level_count++;
1004         }
1005
1006         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1007                                    pi->dpm_table_start +
1008                                    offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
1009                                    (u8 *)&pi->vce_level_count,
1010                                    sizeof(u8),
1011                                    pi->sram_end);
1012         if (ret)
1013                 return ret;
1014
1015         pi->vce_interval = 1;
1016
1017         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1018                                    pi->dpm_table_start +
1019                                    offsetof(SMU7_Fusion_DpmTable, VCEInterval),
1020                                    (u8 *)&pi->vce_interval,
1021                                    sizeof(u8),
1022                                    pi->sram_end);
1023         if (ret)
1024                 return ret;
1025
1026         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1027                                    pi->dpm_table_start +
1028                                    offsetof(SMU7_Fusion_DpmTable, VceLevel),
1029                                    (u8 *)&pi->vce_level,
1030                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
1031                                    pi->sram_end);
1032
1033         return ret;
1034 }
1035
1036 static int kv_populate_samu_table(struct amdgpu_device *adev)
1037 {
1038         struct kv_power_info *pi = kv_get_pi(adev);
1039         struct amdgpu_clock_voltage_dependency_table *table =
1040                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1041         struct atom_clock_dividers dividers;
1042         int ret;
1043         u32 i;
1044
1045         if (table == NULL || table->count == 0)
1046                 return 0;
1047
1048         pi->samu_level_count = 0;
1049         for (i = 0; i < table->count; i++) {
1050                 if (pi->high_voltage_t &&
1051                     pi->high_voltage_t < table->entries[i].v)
1052                         break;
1053
1054                 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1055                 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1056
1057                 pi->samu_level[i].ClkBypassCntl =
1058                         (u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1059
1060                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1061                                                          table->entries[i].clk, false, &dividers);
1062                 if (ret)
1063                         return ret;
1064                 pi->samu_level[i].Divider = (u8)dividers.post_div;
1065
1066                 pi->samu_level_count++;
1067         }
1068
1069         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1070                                    pi->dpm_table_start +
1071                                    offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
1072                                    (u8 *)&pi->samu_level_count,
1073                                    sizeof(u8),
1074                                    pi->sram_end);
1075         if (ret)
1076                 return ret;
1077
1078         pi->samu_interval = 1;
1079
1080         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1081                                    pi->dpm_table_start +
1082                                    offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
1083                                    (u8 *)&pi->samu_interval,
1084                                    sizeof(u8),
1085                                    pi->sram_end);
1086         if (ret)
1087                 return ret;
1088
1089         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1090                                    pi->dpm_table_start +
1091                                    offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1092                                    (u8 *)&pi->samu_level,
1093                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1094                                    pi->sram_end);
1095         if (ret)
1096                 return ret;
1097
1098         return ret;
1099 }
1100
1101
1102 static int kv_populate_acp_table(struct amdgpu_device *adev)
1103 {
1104         struct kv_power_info *pi = kv_get_pi(adev);
1105         struct amdgpu_clock_voltage_dependency_table *table =
1106                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1107         struct atom_clock_dividers dividers;
1108         int ret;
1109         u32 i;
1110
1111         if (table == NULL || table->count == 0)
1112                 return 0;
1113
1114         pi->acp_level_count = 0;
1115         for (i = 0; i < table->count; i++) {
1116                 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1117                 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1118
1119                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1120                                                          table->entries[i].clk, false, &dividers);
1121                 if (ret)
1122                         return ret;
1123                 pi->acp_level[i].Divider = (u8)dividers.post_div;
1124
1125                 pi->acp_level_count++;
1126         }
1127
1128         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1129                                    pi->dpm_table_start +
1130                                    offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1131                                    (u8 *)&pi->acp_level_count,
1132                                    sizeof(u8),
1133                                    pi->sram_end);
1134         if (ret)
1135                 return ret;
1136
1137         pi->acp_interval = 1;
1138
1139         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1140                                    pi->dpm_table_start +
1141                                    offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1142                                    (u8 *)&pi->acp_interval,
1143                                    sizeof(u8),
1144                                    pi->sram_end);
1145         if (ret)
1146                 return ret;
1147
1148         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1149                                    pi->dpm_table_start +
1150                                    offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1151                                    (u8 *)&pi->acp_level,
1152                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1153                                    pi->sram_end);
1154         if (ret)
1155                 return ret;
1156
1157         return ret;
1158 }
1159
1160 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
1161 {
1162         struct kv_power_info *pi = kv_get_pi(adev);
1163         u32 i;
1164         struct amdgpu_clock_voltage_dependency_table *table =
1165                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1166
1167         if (table && table->count) {
1168                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1169                         if (pi->caps_enable_dfs_bypass) {
1170                                 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1171                                         pi->graphics_level[i].ClkBypassCntl = 3;
1172                                 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1173                                         pi->graphics_level[i].ClkBypassCntl = 2;
1174                                 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1175                                         pi->graphics_level[i].ClkBypassCntl = 7;
1176                                 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1177                                         pi->graphics_level[i].ClkBypassCntl = 6;
1178                                 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1179                                         pi->graphics_level[i].ClkBypassCntl = 8;
1180                                 else
1181                                         pi->graphics_level[i].ClkBypassCntl = 0;
1182                         } else {
1183                                 pi->graphics_level[i].ClkBypassCntl = 0;
1184                         }
1185                 }
1186         } else {
1187                 struct sumo_sclk_voltage_mapping_table *table =
1188                         &pi->sys_info.sclk_voltage_mapping_table;
1189                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1190                         if (pi->caps_enable_dfs_bypass) {
1191                                 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1192                                         pi->graphics_level[i].ClkBypassCntl = 3;
1193                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1194                                         pi->graphics_level[i].ClkBypassCntl = 2;
1195                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1196                                         pi->graphics_level[i].ClkBypassCntl = 7;
1197                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1198                                         pi->graphics_level[i].ClkBypassCntl = 6;
1199                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1200                                         pi->graphics_level[i].ClkBypassCntl = 8;
1201                                 else
1202                                         pi->graphics_level[i].ClkBypassCntl = 0;
1203                         } else {
1204                                 pi->graphics_level[i].ClkBypassCntl = 0;
1205                         }
1206                 }
1207         }
1208 }
1209
1210 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
1211 {
1212         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1213                                         PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1214 }
1215
1216 static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
1217 {
1218         struct kv_power_info *pi = kv_get_pi(adev);
1219
1220         pi->acp_boot_level = 0xff;
1221 }
1222
1223 static void kv_update_current_ps(struct amdgpu_device *adev,
1224                                  struct amdgpu_ps *rps)
1225 {
1226         struct kv_ps *new_ps = kv_get_ps(rps);
1227         struct kv_power_info *pi = kv_get_pi(adev);
1228
1229         pi->current_rps = *rps;
1230         pi->current_ps = *new_ps;
1231         pi->current_rps.ps_priv = &pi->current_ps;
1232         adev->pm.dpm.current_ps = &pi->current_rps;
1233 }
1234
1235 static void kv_update_requested_ps(struct amdgpu_device *adev,
1236                                    struct amdgpu_ps *rps)
1237 {
1238         struct kv_ps *new_ps = kv_get_ps(rps);
1239         struct kv_power_info *pi = kv_get_pi(adev);
1240
1241         pi->requested_rps = *rps;
1242         pi->requested_ps = *new_ps;
1243         pi->requested_rps.ps_priv = &pi->requested_ps;
1244         adev->pm.dpm.requested_ps = &pi->requested_rps;
1245 }
1246
1247 static void kv_dpm_enable_bapm(void *handle, bool enable)
1248 {
1249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250         struct kv_power_info *pi = kv_get_pi(adev);
1251         int ret;
1252
1253         if (pi->bapm_enable) {
1254                 ret = amdgpu_kv_smc_bapm_enable(adev, enable);
1255                 if (ret)
1256                         DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1257         }
1258 }
1259
1260 static int kv_dpm_enable(struct amdgpu_device *adev)
1261 {
1262         struct kv_power_info *pi = kv_get_pi(adev);
1263         int ret;
1264
1265         ret = kv_process_firmware_header(adev);
1266         if (ret) {
1267                 DRM_ERROR("kv_process_firmware_header failed\n");
1268                 return ret;
1269         }
1270         kv_init_fps_limits(adev);
1271         kv_init_graphics_levels(adev);
1272         ret = kv_program_bootup_state(adev);
1273         if (ret) {
1274                 DRM_ERROR("kv_program_bootup_state failed\n");
1275                 return ret;
1276         }
1277         kv_calculate_dfs_bypass_settings(adev);
1278         ret = kv_upload_dpm_settings(adev);
1279         if (ret) {
1280                 DRM_ERROR("kv_upload_dpm_settings failed\n");
1281                 return ret;
1282         }
1283         ret = kv_populate_uvd_table(adev);
1284         if (ret) {
1285                 DRM_ERROR("kv_populate_uvd_table failed\n");
1286                 return ret;
1287         }
1288         ret = kv_populate_vce_table(adev);
1289         if (ret) {
1290                 DRM_ERROR("kv_populate_vce_table failed\n");
1291                 return ret;
1292         }
1293         ret = kv_populate_samu_table(adev);
1294         if (ret) {
1295                 DRM_ERROR("kv_populate_samu_table failed\n");
1296                 return ret;
1297         }
1298         ret = kv_populate_acp_table(adev);
1299         if (ret) {
1300                 DRM_ERROR("kv_populate_acp_table failed\n");
1301                 return ret;
1302         }
1303         kv_program_vc(adev);
1304 #if 0
1305         kv_initialize_hardware_cac_manager(adev);
1306 #endif
1307         kv_start_am(adev);
1308         if (pi->enable_auto_thermal_throttling) {
1309                 ret = kv_enable_auto_thermal_throttling(adev);
1310                 if (ret) {
1311                         DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1312                         return ret;
1313                 }
1314         }
1315         ret = kv_enable_dpm_voltage_scaling(adev);
1316         if (ret) {
1317                 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1318                 return ret;
1319         }
1320         ret = kv_set_dpm_interval(adev);
1321         if (ret) {
1322                 DRM_ERROR("kv_set_dpm_interval failed\n");
1323                 return ret;
1324         }
1325         ret = kv_set_dpm_boot_state(adev);
1326         if (ret) {
1327                 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1328                 return ret;
1329         }
1330         ret = kv_enable_ulv(adev, true);
1331         if (ret) {
1332                 DRM_ERROR("kv_enable_ulv failed\n");
1333                 return ret;
1334         }
1335         kv_start_dpm(adev);
1336         ret = kv_enable_didt(adev, true);
1337         if (ret) {
1338                 DRM_ERROR("kv_enable_didt failed\n");
1339                 return ret;
1340         }
1341         ret = kv_enable_smc_cac(adev, true);
1342         if (ret) {
1343                 DRM_ERROR("kv_enable_smc_cac failed\n");
1344                 return ret;
1345         }
1346
1347         kv_reset_acp_boot_level(adev);
1348
1349         ret = amdgpu_kv_smc_bapm_enable(adev, false);
1350         if (ret) {
1351                 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1352                 return ret;
1353         }
1354
1355         if (adev->irq.installed &&
1356             amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
1357                 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
1358                 if (ret) {
1359                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1360                         return ret;
1361                 }
1362                 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1363                                AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1364                 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1365                                AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1366         }
1367
1368         return ret;
1369 }
1370
1371 static void kv_dpm_disable(struct amdgpu_device *adev)
1372 {
1373         struct kv_power_info *pi = kv_get_pi(adev);
1374
1375         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1376                        AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1377         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1378                        AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1379
1380         amdgpu_kv_smc_bapm_enable(adev, false);
1381
1382         if (adev->asic_type == CHIP_MULLINS)
1383                 kv_enable_nb_dpm(adev, false);
1384
1385         /* powerup blocks */
1386         kv_dpm_powergate_acp(adev, false);
1387         kv_dpm_powergate_samu(adev, false);
1388         if (pi->caps_vce_pg) /* power on the VCE block */
1389                 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1390         if (pi->caps_uvd_pg) /* power on the UVD block */
1391                 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1392
1393         kv_enable_smc_cac(adev, false);
1394         kv_enable_didt(adev, false);
1395         kv_clear_vc(adev);
1396         kv_stop_dpm(adev);
1397         kv_enable_ulv(adev, false);
1398         kv_reset_am(adev);
1399
1400         kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1401 }
1402
1403 #if 0
1404 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1405                                       u16 reg_offset, u32 value)
1406 {
1407         struct kv_power_info *pi = kv_get_pi(adev);
1408
1409         return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1410                                     (u8 *)&value, sizeof(u16), pi->sram_end);
1411 }
1412
1413 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1414                                      u16 reg_offset, u32 *value)
1415 {
1416         struct kv_power_info *pi = kv_get_pi(adev);
1417
1418         return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1419                                       value, pi->sram_end);
1420 }
1421 #endif
1422
1423 static void kv_init_sclk_t(struct amdgpu_device *adev)
1424 {
1425         struct kv_power_info *pi = kv_get_pi(adev);
1426
1427         pi->low_sclk_interrupt_t = 0;
1428 }
1429
1430 static int kv_init_fps_limits(struct amdgpu_device *adev)
1431 {
1432         struct kv_power_info *pi = kv_get_pi(adev);
1433         int ret = 0;
1434
1435         if (pi->caps_fps) {
1436                 u16 tmp;
1437
1438                 tmp = 45;
1439                 pi->fps_high_t = cpu_to_be16(tmp);
1440                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1441                                            pi->dpm_table_start +
1442                                            offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1443                                            (u8 *)&pi->fps_high_t,
1444                                            sizeof(u16), pi->sram_end);
1445
1446                 tmp = 30;
1447                 pi->fps_low_t = cpu_to_be16(tmp);
1448
1449                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1450                                            pi->dpm_table_start +
1451                                            offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1452                                            (u8 *)&pi->fps_low_t,
1453                                            sizeof(u16), pi->sram_end);
1454
1455         }
1456         return ret;
1457 }
1458
1459 static void kv_init_powergate_state(struct amdgpu_device *adev)
1460 {
1461         struct kv_power_info *pi = kv_get_pi(adev);
1462
1463         pi->uvd_power_gated = false;
1464         pi->vce_power_gated = false;
1465         pi->samu_power_gated = false;
1466         pi->acp_power_gated = false;
1467
1468 }
1469
1470 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1471 {
1472         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1473                                         PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1474 }
1475
1476 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1477 {
1478         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1479                                         PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1480 }
1481
1482 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
1483 {
1484         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1485                                         PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1486 }
1487
1488 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
1489 {
1490         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1491                                         PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1492 }
1493
1494 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1495 {
1496         struct kv_power_info *pi = kv_get_pi(adev);
1497         struct amdgpu_uvd_clock_voltage_dependency_table *table =
1498                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1499         int ret;
1500         u32 mask;
1501
1502         if (!gate) {
1503                 if (table->count)
1504                         pi->uvd_boot_level = table->count - 1;
1505                 else
1506                         pi->uvd_boot_level = 0;
1507
1508                 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1509                         mask = 1 << pi->uvd_boot_level;
1510                 } else {
1511                         mask = 0x1f;
1512                 }
1513
1514                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1515                                            pi->dpm_table_start +
1516                                            offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1517                                            (uint8_t *)&pi->uvd_boot_level,
1518                                            sizeof(u8), pi->sram_end);
1519                 if (ret)
1520                         return ret;
1521
1522                 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1523                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
1524                                                   mask);
1525         }
1526
1527         return kv_enable_uvd_dpm(adev, !gate);
1528 }
1529
1530 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
1531 {
1532         u8 i;
1533         struct amdgpu_vce_clock_voltage_dependency_table *table =
1534                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1535
1536         for (i = 0; i < table->count; i++) {
1537                 if (table->entries[i].evclk >= evclk)
1538                         break;
1539         }
1540
1541         return i;
1542 }
1543
1544 static int kv_update_vce_dpm(struct amdgpu_device *adev,
1545                              struct amdgpu_ps *amdgpu_new_state,
1546                              struct amdgpu_ps *amdgpu_current_state)
1547 {
1548         struct kv_power_info *pi = kv_get_pi(adev);
1549         struct amdgpu_vce_clock_voltage_dependency_table *table =
1550                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1551         int ret;
1552
1553         if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1554                 if (pi->caps_stable_p_state)
1555                         pi->vce_boot_level = table->count - 1;
1556                 else
1557                         pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
1558
1559                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1560                                            pi->dpm_table_start +
1561                                            offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1562                                            (u8 *)&pi->vce_boot_level,
1563                                            sizeof(u8),
1564                                            pi->sram_end);
1565                 if (ret)
1566                         return ret;
1567
1568                 if (pi->caps_stable_p_state)
1569                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1570                                                           PPSMC_MSG_VCEDPM_SetEnabledMask,
1571                                                           (1 << pi->vce_boot_level));
1572                 kv_enable_vce_dpm(adev, true);
1573         } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1574                 kv_enable_vce_dpm(adev, false);
1575         }
1576
1577         return 0;
1578 }
1579
1580 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
1581 {
1582         struct kv_power_info *pi = kv_get_pi(adev);
1583         struct amdgpu_clock_voltage_dependency_table *table =
1584                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1585         int ret;
1586
1587         if (!gate) {
1588                 if (pi->caps_stable_p_state)
1589                         pi->samu_boot_level = table->count - 1;
1590                 else
1591                         pi->samu_boot_level = 0;
1592
1593                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1594                                            pi->dpm_table_start +
1595                                            offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1596                                            (u8 *)&pi->samu_boot_level,
1597                                            sizeof(u8),
1598                                            pi->sram_end);
1599                 if (ret)
1600                         return ret;
1601
1602                 if (pi->caps_stable_p_state)
1603                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1604                                                           PPSMC_MSG_SAMUDPM_SetEnabledMask,
1605                                                           (1 << pi->samu_boot_level));
1606         }
1607
1608         return kv_enable_samu_dpm(adev, !gate);
1609 }
1610
1611 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
1612 {
1613         return 0;
1614 }
1615
1616 static void kv_update_acp_boot_level(struct amdgpu_device *adev)
1617 {
1618         struct kv_power_info *pi = kv_get_pi(adev);
1619         u8 acp_boot_level;
1620
1621         if (!pi->caps_stable_p_state) {
1622                 acp_boot_level = kv_get_acp_boot_level(adev);
1623                 if (acp_boot_level != pi->acp_boot_level) {
1624                         pi->acp_boot_level = acp_boot_level;
1625                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1626                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1627                                                           (1 << pi->acp_boot_level));
1628                 }
1629         }
1630 }
1631
1632 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
1633 {
1634         struct kv_power_info *pi = kv_get_pi(adev);
1635         struct amdgpu_clock_voltage_dependency_table *table =
1636                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1637         int ret;
1638
1639         if (!gate) {
1640                 if (pi->caps_stable_p_state)
1641                         pi->acp_boot_level = table->count - 1;
1642                 else
1643                         pi->acp_boot_level = kv_get_acp_boot_level(adev);
1644
1645                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1646                                            pi->dpm_table_start +
1647                                            offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1648                                            (u8 *)&pi->acp_boot_level,
1649                                            sizeof(u8),
1650                                            pi->sram_end);
1651                 if (ret)
1652                         return ret;
1653
1654                 if (pi->caps_stable_p_state)
1655                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1656                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1657                                                           (1 << pi->acp_boot_level));
1658         }
1659
1660         return kv_enable_acp_dpm(adev, !gate);
1661 }
1662
1663 static void kv_dpm_powergate_uvd(void *handle, bool gate)
1664 {
1665         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1666         struct kv_power_info *pi = kv_get_pi(adev);
1667         int ret;
1668
1669         pi->uvd_power_gated = gate;
1670
1671         if (gate) {
1672                 /* stop the UVD block */
1673                 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1674                                                              AMD_PG_STATE_GATE);
1675                 kv_update_uvd_dpm(adev, gate);
1676                 if (pi->caps_uvd_pg)
1677                         /* power off the UVD block */
1678                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1679         } else {
1680                 if (pi->caps_uvd_pg)
1681                         /* power on the UVD block */
1682                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1683                         /* re-init the UVD block */
1684                 kv_update_uvd_dpm(adev, gate);
1685
1686                 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1687                                                              AMD_PG_STATE_UNGATE);
1688         }
1689 }
1690
1691 static void kv_dpm_powergate_vce(void *handle, bool gate)
1692 {
1693         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1694         struct kv_power_info *pi = kv_get_pi(adev);
1695         int ret;
1696
1697         pi->vce_power_gated = gate;
1698
1699         if (gate) {
1700                 /* stop the VCE block */
1701                 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1702                                                              AMD_PG_STATE_GATE);
1703                 kv_enable_vce_dpm(adev, false);
1704                 if (pi->caps_vce_pg) /* power off the VCE block */
1705                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1706         } else {
1707                 if (pi->caps_vce_pg) /* power on the VCE block */
1708                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1709                 kv_enable_vce_dpm(adev, true);
1710                 /* re-init the VCE block */
1711                 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1712                                                              AMD_PG_STATE_UNGATE);
1713         }
1714 }
1715
1716
1717 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
1718 {
1719         struct kv_power_info *pi = kv_get_pi(adev);
1720
1721         if (pi->samu_power_gated == gate)
1722                 return;
1723
1724         pi->samu_power_gated = gate;
1725
1726         if (gate) {
1727                 kv_update_samu_dpm(adev, true);
1728                 if (pi->caps_samu_pg)
1729                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
1730         } else {
1731                 if (pi->caps_samu_pg)
1732                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
1733                 kv_update_samu_dpm(adev, false);
1734         }
1735 }
1736
1737 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
1738 {
1739         struct kv_power_info *pi = kv_get_pi(adev);
1740
1741         if (pi->acp_power_gated == gate)
1742                 return;
1743
1744         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
1745                 return;
1746
1747         pi->acp_power_gated = gate;
1748
1749         if (gate) {
1750                 kv_update_acp_dpm(adev, true);
1751                 if (pi->caps_acp_pg)
1752                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
1753         } else {
1754                 if (pi->caps_acp_pg)
1755                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
1756                 kv_update_acp_dpm(adev, false);
1757         }
1758 }
1759
1760 static void kv_set_valid_clock_range(struct amdgpu_device *adev,
1761                                      struct amdgpu_ps *new_rps)
1762 {
1763         struct kv_ps *new_ps = kv_get_ps(new_rps);
1764         struct kv_power_info *pi = kv_get_pi(adev);
1765         u32 i;
1766         struct amdgpu_clock_voltage_dependency_table *table =
1767                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1768
1769         if (table && table->count) {
1770                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1771                         if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1772                             (i == (pi->graphics_dpm_level_count - 1))) {
1773                                 pi->lowest_valid = i;
1774                                 break;
1775                         }
1776                 }
1777
1778                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1779                         if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1780                                 break;
1781                 }
1782                 pi->highest_valid = i;
1783
1784                 if (pi->lowest_valid > pi->highest_valid) {
1785                         if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1786                             (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1787                                 pi->highest_valid = pi->lowest_valid;
1788                         else
1789                                 pi->lowest_valid =  pi->highest_valid;
1790                 }
1791         } else {
1792                 struct sumo_sclk_voltage_mapping_table *table =
1793                         &pi->sys_info.sclk_voltage_mapping_table;
1794
1795                 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1796                         if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1797                             i == (int)(pi->graphics_dpm_level_count - 1)) {
1798                                 pi->lowest_valid = i;
1799                                 break;
1800                         }
1801                 }
1802
1803                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1804                         if (table->entries[i].sclk_frequency <=
1805                             new_ps->levels[new_ps->num_levels - 1].sclk)
1806                                 break;
1807                 }
1808                 pi->highest_valid = i;
1809
1810                 if (pi->lowest_valid > pi->highest_valid) {
1811                         if ((new_ps->levels[0].sclk -
1812                              table->entries[pi->highest_valid].sclk_frequency) >
1813                             (table->entries[pi->lowest_valid].sclk_frequency -
1814                              new_ps->levels[new_ps->num_levels -1].sclk))
1815                                 pi->highest_valid = pi->lowest_valid;
1816                         else
1817                                 pi->lowest_valid =  pi->highest_valid;
1818                 }
1819         }
1820 }
1821
1822 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
1823                                          struct amdgpu_ps *new_rps)
1824 {
1825         struct kv_ps *new_ps = kv_get_ps(new_rps);
1826         struct kv_power_info *pi = kv_get_pi(adev);
1827         int ret = 0;
1828         u8 clk_bypass_cntl;
1829
1830         if (pi->caps_enable_dfs_bypass) {
1831                 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1832                         pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1833                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1834                                            (pi->dpm_table_start +
1835                                             offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1836                                             (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1837                                             offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1838                                            &clk_bypass_cntl,
1839                                            sizeof(u8), pi->sram_end);
1840         }
1841
1842         return ret;
1843 }
1844
1845 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
1846                             bool enable)
1847 {
1848         struct kv_power_info *pi = kv_get_pi(adev);
1849         int ret = 0;
1850
1851         if (enable) {
1852                 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1853                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
1854                         if (ret == 0)
1855                                 pi->nb_dpm_enabled = true;
1856                 }
1857         } else {
1858                 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1859                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
1860                         if (ret == 0)
1861                                 pi->nb_dpm_enabled = false;
1862                 }
1863         }
1864
1865         return ret;
1866 }
1867
1868 static int kv_dpm_force_performance_level(void *handle,
1869                                           enum amd_dpm_forced_level level)
1870 {
1871         int ret;
1872         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1873
1874         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
1875                 ret = kv_force_dpm_highest(adev);
1876                 if (ret)
1877                         return ret;
1878         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
1879                 ret = kv_force_dpm_lowest(adev);
1880                 if (ret)
1881                         return ret;
1882         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
1883                 ret = kv_unforce_levels(adev);
1884                 if (ret)
1885                         return ret;
1886         }
1887
1888         adev->pm.dpm.forced_level = level;
1889
1890         return 0;
1891 }
1892
1893 static int kv_dpm_pre_set_power_state(void *handle)
1894 {
1895         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1896         struct kv_power_info *pi = kv_get_pi(adev);
1897         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1898         struct amdgpu_ps *new_ps = &requested_ps;
1899
1900         kv_update_requested_ps(adev, new_ps);
1901
1902         kv_apply_state_adjust_rules(adev,
1903                                     &pi->requested_rps,
1904                                     &pi->current_rps);
1905
1906         return 0;
1907 }
1908
1909 static int kv_dpm_set_power_state(void *handle)
1910 {
1911         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1912         struct kv_power_info *pi = kv_get_pi(adev);
1913         struct amdgpu_ps *new_ps = &pi->requested_rps;
1914         struct amdgpu_ps *old_ps = &pi->current_rps;
1915         int ret;
1916
1917         if (pi->bapm_enable) {
1918                 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power);
1919                 if (ret) {
1920                         DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1921                         return ret;
1922                 }
1923         }
1924
1925         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
1926                 if (pi->enable_dpm) {
1927                         kv_set_valid_clock_range(adev, new_ps);
1928                         kv_update_dfs_bypass_settings(adev, new_ps);
1929                         ret = kv_calculate_ds_divider(adev);
1930                         if (ret) {
1931                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1932                                 return ret;
1933                         }
1934                         kv_calculate_nbps_level_settings(adev);
1935                         kv_calculate_dpm_settings(adev);
1936                         kv_force_lowest_valid(adev);
1937                         kv_enable_new_levels(adev);
1938                         kv_upload_dpm_settings(adev);
1939                         kv_program_nbps_index_settings(adev, new_ps);
1940                         kv_unforce_levels(adev);
1941                         kv_set_enabled_levels(adev);
1942                         kv_force_lowest_valid(adev);
1943                         kv_unforce_levels(adev);
1944
1945                         ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1946                         if (ret) {
1947                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1948                                 return ret;
1949                         }
1950                         kv_update_sclk_t(adev);
1951                         if (adev->asic_type == CHIP_MULLINS)
1952                                 kv_enable_nb_dpm(adev, true);
1953                 }
1954         } else {
1955                 if (pi->enable_dpm) {
1956                         kv_set_valid_clock_range(adev, new_ps);
1957                         kv_update_dfs_bypass_settings(adev, new_ps);
1958                         ret = kv_calculate_ds_divider(adev);
1959                         if (ret) {
1960                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1961                                 return ret;
1962                         }
1963                         kv_calculate_nbps_level_settings(adev);
1964                         kv_calculate_dpm_settings(adev);
1965                         kv_freeze_sclk_dpm(adev, true);
1966                         kv_upload_dpm_settings(adev);
1967                         kv_program_nbps_index_settings(adev, new_ps);
1968                         kv_freeze_sclk_dpm(adev, false);
1969                         kv_set_enabled_levels(adev);
1970                         ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1971                         if (ret) {
1972                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1973                                 return ret;
1974                         }
1975                         kv_update_acp_boot_level(adev);
1976                         kv_update_sclk_t(adev);
1977                         kv_enable_nb_dpm(adev, true);
1978                 }
1979         }
1980
1981         return 0;
1982 }
1983
1984 static void kv_dpm_post_set_power_state(void *handle)
1985 {
1986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1987         struct kv_power_info *pi = kv_get_pi(adev);
1988         struct amdgpu_ps *new_ps = &pi->requested_rps;
1989
1990         kv_update_current_ps(adev, new_ps);
1991 }
1992
1993 static void kv_dpm_setup_asic(struct amdgpu_device *adev)
1994 {
1995         sumo_take_smu_control(adev, true);
1996         kv_init_powergate_state(adev);
1997         kv_init_sclk_t(adev);
1998 }
1999
2000 #if 0
2001 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2002 {
2003         struct kv_power_info *pi = kv_get_pi(adev);
2004
2005         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2006                 kv_force_lowest_valid(adev);
2007                 kv_init_graphics_levels(adev);
2008                 kv_program_bootup_state(adev);
2009                 kv_upload_dpm_settings(adev);
2010                 kv_force_lowest_valid(adev);
2011                 kv_unforce_levels(adev);
2012         } else {
2013                 kv_init_graphics_levels(adev);
2014                 kv_program_bootup_state(adev);
2015                 kv_freeze_sclk_dpm(adev, true);
2016                 kv_upload_dpm_settings(adev);
2017                 kv_freeze_sclk_dpm(adev, false);
2018                 kv_set_enabled_level(adev, pi->graphics_boot_level);
2019         }
2020 }
2021 #endif
2022
2023 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
2024                                                 struct amdgpu_clock_and_voltage_limits *table)
2025 {
2026         struct kv_power_info *pi = kv_get_pi(adev);
2027
2028         if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
2029                 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
2030                 table->sclk =
2031                         pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
2032                 table->vddc =
2033                         kv_convert_2bit_index_to_voltage(adev,
2034                                                          pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
2035         }
2036
2037         table->mclk = pi->sys_info.nbp_memory_clock[0];
2038 }
2039
2040 static void kv_patch_voltage_values(struct amdgpu_device *adev)
2041 {
2042         int i;
2043         struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
2044                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
2045         struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
2046                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2047         struct amdgpu_clock_voltage_dependency_table *samu_table =
2048                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
2049         struct amdgpu_clock_voltage_dependency_table *acp_table =
2050                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
2051
2052         if (uvd_table->count) {
2053                 for (i = 0; i < uvd_table->count; i++)
2054                         uvd_table->entries[i].v =
2055                                 kv_convert_8bit_index_to_voltage(adev,
2056                                                                  uvd_table->entries[i].v);
2057         }
2058
2059         if (vce_table->count) {
2060                 for (i = 0; i < vce_table->count; i++)
2061                         vce_table->entries[i].v =
2062                                 kv_convert_8bit_index_to_voltage(adev,
2063                                                                  vce_table->entries[i].v);
2064         }
2065
2066         if (samu_table->count) {
2067                 for (i = 0; i < samu_table->count; i++)
2068                         samu_table->entries[i].v =
2069                                 kv_convert_8bit_index_to_voltage(adev,
2070                                                                  samu_table->entries[i].v);
2071         }
2072
2073         if (acp_table->count) {
2074                 for (i = 0; i < acp_table->count; i++)
2075                         acp_table->entries[i].v =
2076                                 kv_convert_8bit_index_to_voltage(adev,
2077                                                                  acp_table->entries[i].v);
2078         }
2079
2080 }
2081
2082 static void kv_construct_boot_state(struct amdgpu_device *adev)
2083 {
2084         struct kv_power_info *pi = kv_get_pi(adev);
2085
2086         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2087         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2088         pi->boot_pl.ds_divider_index = 0;
2089         pi->boot_pl.ss_divider_index = 0;
2090         pi->boot_pl.allow_gnb_slow = 1;
2091         pi->boot_pl.force_nbp_state = 0;
2092         pi->boot_pl.display_wm = 0;
2093         pi->boot_pl.vce_wm = 0;
2094 }
2095
2096 static int kv_force_dpm_highest(struct amdgpu_device *adev)
2097 {
2098         int ret;
2099         u32 enable_mask, i;
2100
2101         ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2102         if (ret)
2103                 return ret;
2104
2105         for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
2106                 if (enable_mask & (1 << i))
2107                         break;
2108         }
2109
2110         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2111                 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2112         else
2113                 return kv_set_enabled_level(adev, i);
2114 }
2115
2116 static int kv_force_dpm_lowest(struct amdgpu_device *adev)
2117 {
2118         int ret;
2119         u32 enable_mask, i;
2120
2121         ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2122         if (ret)
2123                 return ret;
2124
2125         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2126                 if (enable_mask & (1 << i))
2127                         break;
2128         }
2129
2130         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2131                 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2132         else
2133                 return kv_set_enabled_level(adev, i);
2134 }
2135
2136 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2137                                              u32 sclk, u32 min_sclk_in_sr)
2138 {
2139         struct kv_power_info *pi = kv_get_pi(adev);
2140         u32 i;
2141         u32 temp;
2142         u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);
2143
2144         if (sclk < min)
2145                 return 0;
2146
2147         if (!pi->caps_sclk_ds)
2148                 return 0;
2149
2150         for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2151                 temp = sclk >> i;
2152                 if (temp >= min)
2153                         break;
2154         }
2155
2156         return (u8)i;
2157 }
2158
2159 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
2160 {
2161         struct kv_power_info *pi = kv_get_pi(adev);
2162         struct amdgpu_clock_voltage_dependency_table *table =
2163                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2164         int i;
2165
2166         if (table && table->count) {
2167                 for (i = table->count - 1; i >= 0; i--) {
2168                         if (pi->high_voltage_t &&
2169                             (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
2170                              pi->high_voltage_t)) {
2171                                 *limit = i;
2172                                 return 0;
2173                         }
2174                 }
2175         } else {
2176                 struct sumo_sclk_voltage_mapping_table *table =
2177                         &pi->sys_info.sclk_voltage_mapping_table;
2178
2179                 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2180                         if (pi->high_voltage_t &&
2181                             (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
2182                              pi->high_voltage_t)) {
2183                                 *limit = i;
2184                                 return 0;
2185                         }
2186                 }
2187         }
2188
2189         *limit = 0;
2190         return 0;
2191 }
2192
2193 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
2194                                         struct amdgpu_ps *new_rps,
2195                                         struct amdgpu_ps *old_rps)
2196 {
2197         struct kv_ps *ps = kv_get_ps(new_rps);
2198         struct kv_power_info *pi = kv_get_pi(adev);
2199         u32 min_sclk = 10000; /* ??? */
2200         u32 sclk, mclk = 0;
2201         int i, limit;
2202         bool force_high;
2203         struct amdgpu_clock_voltage_dependency_table *table =
2204                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2205         u32 stable_p_state_sclk = 0;
2206         struct amdgpu_clock_and_voltage_limits *max_limits =
2207                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2208
2209         if (new_rps->vce_active) {
2210                 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
2211                 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
2212         } else {
2213                 new_rps->evclk = 0;
2214                 new_rps->ecclk = 0;
2215         }
2216
2217         mclk = max_limits->mclk;
2218         sclk = min_sclk;
2219
2220         if (pi->caps_stable_p_state) {
2221                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2222
2223                 for (i = table->count - 1; i >= 0; i--) {
2224                         if (stable_p_state_sclk >= table->entries[i].clk) {
2225                                 stable_p_state_sclk = table->entries[i].clk;
2226                                 break;
2227                         }
2228                 }
2229
2230                 if (i > 0)
2231                         stable_p_state_sclk = table->entries[0].clk;
2232
2233                 sclk = stable_p_state_sclk;
2234         }
2235
2236         if (new_rps->vce_active) {
2237                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
2238                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
2239         }
2240
2241         ps->need_dfs_bypass = true;
2242
2243         for (i = 0; i < ps->num_levels; i++) {
2244                 if (ps->levels[i].sclk < sclk)
2245                         ps->levels[i].sclk = sclk;
2246         }
2247
2248         if (table && table->count) {
2249                 for (i = 0; i < ps->num_levels; i++) {
2250                         if (pi->high_voltage_t &&
2251                             (pi->high_voltage_t <
2252                              kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2253                                 kv_get_high_voltage_limit(adev, &limit);
2254                                 ps->levels[i].sclk = table->entries[limit].clk;
2255                         }
2256                 }
2257         } else {
2258                 struct sumo_sclk_voltage_mapping_table *table =
2259                         &pi->sys_info.sclk_voltage_mapping_table;
2260
2261                 for (i = 0; i < ps->num_levels; i++) {
2262                         if (pi->high_voltage_t &&
2263                             (pi->high_voltage_t <
2264                              kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2265                                 kv_get_high_voltage_limit(adev, &limit);
2266                                 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2267                         }
2268                 }
2269         }
2270
2271         if (pi->caps_stable_p_state) {
2272                 for (i = 0; i < ps->num_levels; i++) {
2273                         ps->levels[i].sclk = stable_p_state_sclk;
2274                 }
2275         }
2276
2277         pi->video_start = new_rps->dclk || new_rps->vclk ||
2278                 new_rps->evclk || new_rps->ecclk;
2279
2280         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2281             ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2282                 pi->battery_state = true;
2283         else
2284                 pi->battery_state = false;
2285
2286         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2287                 ps->dpm0_pg_nb_ps_lo = 0x1;
2288                 ps->dpm0_pg_nb_ps_hi = 0x0;
2289                 ps->dpmx_nb_ps_lo = 0x1;
2290                 ps->dpmx_nb_ps_hi = 0x0;
2291         } else {
2292                 ps->dpm0_pg_nb_ps_lo = 0x3;
2293                 ps->dpm0_pg_nb_ps_hi = 0x0;
2294                 ps->dpmx_nb_ps_lo = 0x3;
2295                 ps->dpmx_nb_ps_hi = 0x0;
2296
2297                 if (pi->sys_info.nb_dpm_enable) {
2298                         force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2299                                 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
2300                                 pi->disable_nb_ps3_in_battery;
2301                         ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2302                         ps->dpm0_pg_nb_ps_hi = 0x2;
2303                         ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2304                         ps->dpmx_nb_ps_hi = 0x2;
2305                 }
2306         }
2307 }
2308
2309 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
2310                                                     u32 index, bool enable)
2311 {
2312         struct kv_power_info *pi = kv_get_pi(adev);
2313
2314         pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2315 }
2316
2317 static int kv_calculate_ds_divider(struct amdgpu_device *adev)
2318 {
2319         struct kv_power_info *pi = kv_get_pi(adev);
2320         u32 sclk_in_sr = 10000; /* ??? */
2321         u32 i;
2322
2323         if (pi->lowest_valid > pi->highest_valid)
2324                 return -EINVAL;
2325
2326         for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2327                 pi->graphics_level[i].DeepSleepDivId =
2328                         kv_get_sleep_divider_id_from_clock(adev,
2329                                                            be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2330                                                            sclk_in_sr);
2331         }
2332         return 0;
2333 }
2334
2335 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
2336 {
2337         struct kv_power_info *pi = kv_get_pi(adev);
2338         u32 i;
2339         bool force_high;
2340         struct amdgpu_clock_and_voltage_limits *max_limits =
2341                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2342         u32 mclk = max_limits->mclk;
2343
2344         if (pi->lowest_valid > pi->highest_valid)
2345                 return -EINVAL;
2346
2347         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2348                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2349                         pi->graphics_level[i].GnbSlow = 1;
2350                         pi->graphics_level[i].ForceNbPs1 = 0;
2351                         pi->graphics_level[i].UpH = 0;
2352                 }
2353
2354                 if (!pi->sys_info.nb_dpm_enable)
2355                         return 0;
2356
2357                 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2358                               (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2359
2360                 if (force_high) {
2361                         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2362                                 pi->graphics_level[i].GnbSlow = 0;
2363                 } else {
2364                         if (pi->battery_state)
2365                                 pi->graphics_level[0].ForceNbPs1 = 1;
2366
2367                         pi->graphics_level[1].GnbSlow = 0;
2368                         pi->graphics_level[2].GnbSlow = 0;
2369                         pi->graphics_level[3].GnbSlow = 0;
2370                         pi->graphics_level[4].GnbSlow = 0;
2371                 }
2372         } else {
2373                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2374                         pi->graphics_level[i].GnbSlow = 1;
2375                         pi->graphics_level[i].ForceNbPs1 = 0;
2376                         pi->graphics_level[i].UpH = 0;
2377                 }
2378
2379                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2380                         pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2381                         pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2382                         if (pi->lowest_valid != pi->highest_valid)
2383                                 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2384                 }
2385         }
2386         return 0;
2387 }
2388
2389 static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
2390 {
2391         struct kv_power_info *pi = kv_get_pi(adev);
2392         u32 i;
2393
2394         if (pi->lowest_valid > pi->highest_valid)
2395                 return -EINVAL;
2396
2397         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2398                 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2399
2400         return 0;
2401 }
2402
2403 static void kv_init_graphics_levels(struct amdgpu_device *adev)
2404 {
2405         struct kv_power_info *pi = kv_get_pi(adev);
2406         u32 i;
2407         struct amdgpu_clock_voltage_dependency_table *table =
2408                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2409
2410         if (table && table->count) {
2411                 u32 vid_2bit;
2412
2413                 pi->graphics_dpm_level_count = 0;
2414                 for (i = 0; i < table->count; i++) {
2415                         if (pi->high_voltage_t &&
2416                             (pi->high_voltage_t <
2417                              kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
2418                                 break;
2419
2420                         kv_set_divider_value(adev, i, table->entries[i].clk);
2421                         vid_2bit = kv_convert_vid7_to_vid2(adev,
2422                                                            &pi->sys_info.vid_mapping_table,
2423                                                            table->entries[i].v);
2424                         kv_set_vid(adev, i, vid_2bit);
2425                         kv_set_at(adev, i, pi->at[i]);
2426                         kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2427                         pi->graphics_dpm_level_count++;
2428                 }
2429         } else {
2430                 struct sumo_sclk_voltage_mapping_table *table =
2431                         &pi->sys_info.sclk_voltage_mapping_table;
2432
2433                 pi->graphics_dpm_level_count = 0;
2434                 for (i = 0; i < table->num_max_dpm_entries; i++) {
2435                         if (pi->high_voltage_t &&
2436                             pi->high_voltage_t <
2437                             kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
2438                                 break;
2439
2440                         kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
2441                         kv_set_vid(adev, i, table->entries[i].vid_2bit);
2442                         kv_set_at(adev, i, pi->at[i]);
2443                         kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2444                         pi->graphics_dpm_level_count++;
2445                 }
2446         }
2447
2448         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2449                 kv_dpm_power_level_enable(adev, i, false);
2450 }
2451
2452 static void kv_enable_new_levels(struct amdgpu_device *adev)
2453 {
2454         struct kv_power_info *pi = kv_get_pi(adev);
2455         u32 i;
2456
2457         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2458                 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2459                         kv_dpm_power_level_enable(adev, i, true);
2460         }
2461 }
2462
2463 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
2464 {
2465         u32 new_mask = (1 << level);
2466
2467         return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2468                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2469                                                  new_mask);
2470 }
2471
2472 static int kv_set_enabled_levels(struct amdgpu_device *adev)
2473 {
2474         struct kv_power_info *pi = kv_get_pi(adev);
2475         u32 i, new_mask = 0;
2476
2477         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2478                 new_mask |= (1 << i);
2479
2480         return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2481                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2482                                                  new_mask);
2483 }
2484
2485 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
2486                                            struct amdgpu_ps *new_rps)
2487 {
2488         struct kv_ps *new_ps = kv_get_ps(new_rps);
2489         struct kv_power_info *pi = kv_get_pi(adev);
2490         u32 nbdpmconfig1;
2491
2492         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2493                 return;
2494
2495         if (pi->sys_info.nb_dpm_enable) {
2496                 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2497                 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
2498                                 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
2499                                 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
2500                                 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
2501                 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
2502                                 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
2503                                 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
2504                                 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
2505                 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
2506         }
2507 }
2508
2509 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
2510                                             int min_temp, int max_temp)
2511 {
2512         int low_temp = 0 * 1000;
2513         int high_temp = 255 * 1000;
2514         u32 tmp;
2515
2516         if (low_temp < min_temp)
2517                 low_temp = min_temp;
2518         if (high_temp > max_temp)
2519                 high_temp = max_temp;
2520         if (high_temp < low_temp) {
2521                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2522                 return -EINVAL;
2523         }
2524
2525         tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2526         tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
2527                 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
2528         tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
2529                 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
2530         WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
2531
2532         adev->pm.dpm.thermal.min_temp = low_temp;
2533         adev->pm.dpm.thermal.max_temp = high_temp;
2534
2535         return 0;
2536 }
2537
2538 union igp_info {
2539         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2540         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2541         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2542         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2543         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2544         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2545 };
2546
2547 static int kv_parse_sys_info_table(struct amdgpu_device *adev)
2548 {
2549         struct kv_power_info *pi = kv_get_pi(adev);
2550         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2551         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2552         union igp_info *igp_info;
2553         u8 frev, crev;
2554         u16 data_offset;
2555         int i;
2556
2557         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2558                                    &frev, &crev, &data_offset)) {
2559                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2560                                               data_offset);
2561
2562                 if (crev != 8) {
2563                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2564                         return -EINVAL;
2565                 }
2566                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2567                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2568                 pi->sys_info.bootup_nb_voltage_index =
2569                         le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2570                 if (igp_info->info_8.ucHtcTmpLmt == 0)
2571                         pi->sys_info.htc_tmp_lmt = 203;
2572                 else
2573                         pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2574                 if (igp_info->info_8.ucHtcHystLmt == 0)
2575                         pi->sys_info.htc_hyst_lmt = 5;
2576                 else
2577                         pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2578                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2579                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2580                 }
2581
2582                 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2583                         pi->sys_info.nb_dpm_enable = true;
2584                 else
2585                         pi->sys_info.nb_dpm_enable = false;
2586
2587                 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2588                         pi->sys_info.nbp_memory_clock[i] =
2589                                 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2590                         pi->sys_info.nbp_n_clock[i] =
2591                                 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2592                 }
2593                 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2594                     SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2595                         pi->caps_enable_dfs_bypass = true;
2596
2597                 sumo_construct_sclk_voltage_mapping_table(adev,
2598                                                           &pi->sys_info.sclk_voltage_mapping_table,
2599                                                           igp_info->info_8.sAvail_SCLK);
2600
2601                 sumo_construct_vid_mapping_table(adev,
2602                                                  &pi->sys_info.vid_mapping_table,
2603                                                  igp_info->info_8.sAvail_SCLK);
2604
2605                 kv_construct_max_power_limits_table(adev,
2606                                                     &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2607         }
2608         return 0;
2609 }
2610
2611 union power_info {
2612         struct _ATOM_POWERPLAY_INFO info;
2613         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2614         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2615         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2616         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2617         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2618 };
2619
2620 union pplib_clock_info {
2621         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2622         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2623         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2624         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2625 };
2626
2627 union pplib_power_state {
2628         struct _ATOM_PPLIB_STATE v1;
2629         struct _ATOM_PPLIB_STATE_V2 v2;
2630 };
2631
2632 static void kv_patch_boot_state(struct amdgpu_device *adev,
2633                                 struct kv_ps *ps)
2634 {
2635         struct kv_power_info *pi = kv_get_pi(adev);
2636
2637         ps->num_levels = 1;
2638         ps->levels[0] = pi->boot_pl;
2639 }
2640
2641 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
2642                                           struct amdgpu_ps *rps,
2643                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2644                                           u8 table_rev)
2645 {
2646         struct kv_ps *ps = kv_get_ps(rps);
2647
2648         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2649         rps->class = le16_to_cpu(non_clock_info->usClassification);
2650         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2651
2652         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2653                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2654                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2655         } else {
2656                 rps->vclk = 0;
2657                 rps->dclk = 0;
2658         }
2659
2660         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2661                 adev->pm.dpm.boot_ps = rps;
2662                 kv_patch_boot_state(adev, ps);
2663         }
2664         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2665                 adev->pm.dpm.uvd_ps = rps;
2666 }
2667
2668 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
2669                                       struct amdgpu_ps *rps, int index,
2670                                         union pplib_clock_info *clock_info)
2671 {
2672         struct kv_power_info *pi = kv_get_pi(adev);
2673         struct kv_ps *ps = kv_get_ps(rps);
2674         struct kv_pl *pl = &ps->levels[index];
2675         u32 sclk;
2676
2677         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2678         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2679         pl->sclk = sclk;
2680         pl->vddc_index = clock_info->sumo.vddcIndex;
2681
2682         ps->num_levels = index + 1;
2683
2684         if (pi->caps_sclk_ds) {
2685                 pl->ds_divider_index = 5;
2686                 pl->ss_divider_index = 5;
2687         }
2688 }
2689
2690 static int kv_parse_power_table(struct amdgpu_device *adev)
2691 {
2692         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2693         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2694         union pplib_power_state *power_state;
2695         int i, j, k, non_clock_array_index, clock_array_index;
2696         union pplib_clock_info *clock_info;
2697         struct _StateArray *state_array;
2698         struct _ClockInfoArray *clock_info_array;
2699         struct _NonClockInfoArray *non_clock_info_array;
2700         union power_info *power_info;
2701         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2702         u16 data_offset;
2703         u8 frev, crev;
2704         u8 *power_state_offset;
2705         struct kv_ps *ps;
2706
2707         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2708                                    &frev, &crev, &data_offset))
2709                 return -EINVAL;
2710         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2711
2712         amdgpu_add_thermal_controller(adev);
2713
2714         state_array = (struct _StateArray *)
2715                 (mode_info->atom_context->bios + data_offset +
2716                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2717         clock_info_array = (struct _ClockInfoArray *)
2718                 (mode_info->atom_context->bios + data_offset +
2719                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2720         non_clock_info_array = (struct _NonClockInfoArray *)
2721                 (mode_info->atom_context->bios + data_offset +
2722                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2723
2724         adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
2725                                   sizeof(struct amdgpu_ps),
2726                                   GFP_KERNEL);
2727         if (!adev->pm.dpm.ps)
2728                 return -ENOMEM;
2729         power_state_offset = (u8 *)state_array->states;
2730         for (i = 0; i < state_array->ucNumEntries; i++) {
2731                 u8 *idx;
2732                 power_state = (union pplib_power_state *)power_state_offset;
2733                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2734                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2735                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2736                 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2737                 if (ps == NULL) {
2738                         kfree(adev->pm.dpm.ps);
2739                         return -ENOMEM;
2740                 }
2741                 adev->pm.dpm.ps[i].ps_priv = ps;
2742                 k = 0;
2743                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2744                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2745                         clock_array_index = idx[j];
2746                         if (clock_array_index >= clock_info_array->ucNumEntries)
2747                                 continue;
2748                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2749                                 break;
2750                         clock_info = (union pplib_clock_info *)
2751                                 ((u8 *)&clock_info_array->clockInfo[0] +
2752                                  (clock_array_index * clock_info_array->ucEntrySize));
2753                         kv_parse_pplib_clock_info(adev,
2754                                                   &adev->pm.dpm.ps[i], k,
2755                                                   clock_info);
2756                         k++;
2757                 }
2758                 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
2759                                               non_clock_info,
2760                                               non_clock_info_array->ucEntrySize);
2761                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2762         }
2763         adev->pm.dpm.num_ps = state_array->ucNumEntries;
2764
2765         /* fill in the vce power states */
2766         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
2767                 u32 sclk;
2768                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
2769                 clock_info = (union pplib_clock_info *)
2770                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2771                 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2772                 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2773                 adev->pm.dpm.vce_states[i].sclk = sclk;
2774                 adev->pm.dpm.vce_states[i].mclk = 0;
2775         }
2776
2777         return 0;
2778 }
2779
2780 static int kv_dpm_init(struct amdgpu_device *adev)
2781 {
2782         struct kv_power_info *pi;
2783         int ret, i;
2784
2785         pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2786         if (pi == NULL)
2787                 return -ENOMEM;
2788         adev->pm.dpm.priv = pi;
2789
2790         ret = amdgpu_get_platform_caps(adev);
2791         if (ret)
2792                 return ret;
2793
2794         ret = amdgpu_parse_extended_power_table(adev);
2795         if (ret)
2796                 return ret;
2797
2798         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2799                 pi->at[i] = TRINITY_AT_DFLT;
2800
2801         pi->sram_end = SMC_RAM_END;
2802
2803         pi->enable_nb_dpm = true;
2804
2805         pi->caps_power_containment = true;
2806         pi->caps_cac = true;
2807         pi->enable_didt = false;
2808         if (pi->enable_didt) {
2809                 pi->caps_sq_ramping = true;
2810                 pi->caps_db_ramping = true;
2811                 pi->caps_td_ramping = true;
2812                 pi->caps_tcp_ramping = true;
2813         }
2814
2815         if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
2816                 pi->caps_sclk_ds = true;
2817         else
2818                 pi->caps_sclk_ds = false;
2819
2820         pi->enable_auto_thermal_throttling = true;
2821         pi->disable_nb_ps3_in_battery = false;
2822         if (amdgpu_bapm == 0)
2823                 pi->bapm_enable = false;
2824         else
2825                 pi->bapm_enable = true;
2826         pi->voltage_drop_t = 0;
2827         pi->caps_sclk_throttle_low_notification = false;
2828         pi->caps_fps = false; /* true? */
2829         pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2830         pi->caps_uvd_dpm = true;
2831         pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2832         pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2833         pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2834         pi->caps_stable_p_state = false;
2835
2836         ret = kv_parse_sys_info_table(adev);
2837         if (ret)
2838                 return ret;
2839
2840         kv_patch_voltage_values(adev);
2841         kv_construct_boot_state(adev);
2842
2843         ret = kv_parse_power_table(adev);
2844         if (ret)
2845                 return ret;
2846
2847         pi->enable_dpm = true;
2848
2849         return 0;
2850 }
2851
2852 static void
2853 kv_dpm_debugfs_print_current_performance_level(void *handle,
2854                                                struct seq_file *m)
2855 {
2856         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2857         struct kv_power_info *pi = kv_get_pi(adev);
2858         u32 current_index =
2859                 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2860                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
2861                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
2862         u32 sclk, tmp;
2863         u16 vddc;
2864
2865         if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2866                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2867         } else {
2868                 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2869                 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2870                         SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2871                         SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
2872                 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
2873                 seq_printf(m, "uvd    %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2874                 seq_printf(m, "vce    %sabled\n", pi->vce_power_gated ? "dis" : "en");
2875                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2876                            current_index, sclk, vddc);
2877         }
2878 }
2879
2880 static void
2881 kv_dpm_print_power_state(void *handle, void *request_ps)
2882 {
2883         int i;
2884         struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
2885         struct kv_ps *ps = kv_get_ps(rps);
2886         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2887
2888         amdgpu_dpm_print_class_info(rps->class, rps->class2);
2889         amdgpu_dpm_print_cap_info(rps->caps);
2890         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2891         for (i = 0; i < ps->num_levels; i++) {
2892                 struct kv_pl *pl = &ps->levels[i];
2893                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
2894                        i, pl->sclk,
2895                        kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
2896         }
2897         amdgpu_dpm_print_ps_status(adev, rps);
2898 }
2899
2900 static void kv_dpm_fini(struct amdgpu_device *adev)
2901 {
2902         int i;
2903
2904         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2905                 kfree(adev->pm.dpm.ps[i].ps_priv);
2906         }
2907         kfree(adev->pm.dpm.ps);
2908         kfree(adev->pm.dpm.priv);
2909         amdgpu_free_extended_power_table(adev);
2910 }
2911
2912 static void kv_dpm_display_configuration_changed(void *handle)
2913 {
2914
2915 }
2916
2917 static u32 kv_dpm_get_sclk(void *handle, bool low)
2918 {
2919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2920         struct kv_power_info *pi = kv_get_pi(adev);
2921         struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2922
2923         if (low)
2924                 return requested_state->levels[0].sclk;
2925         else
2926                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2927 }
2928
2929 static u32 kv_dpm_get_mclk(void *handle, bool low)
2930 {
2931         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2932         struct kv_power_info *pi = kv_get_pi(adev);
2933
2934         return pi->sys_info.bootup_uma_clk;
2935 }
2936
2937 /* get temperature in millidegrees */
2938 static int kv_dpm_get_temp(void *handle)
2939 {
2940         u32 temp;
2941         int actual_temp = 0;
2942         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2943
2944         temp = RREG32_SMC(0xC0300E0C);
2945
2946         if (temp)
2947                 actual_temp = (temp / 8) - 49;
2948         else
2949                 actual_temp = 0;
2950
2951         actual_temp = actual_temp * 1000;
2952
2953         return actual_temp;
2954 }
2955
2956 static int kv_dpm_early_init(void *handle)
2957 {
2958         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2959
2960         adev->powerplay.pp_funcs = &kv_dpm_funcs;
2961         adev->powerplay.pp_handle = adev;
2962         kv_dpm_set_irq_funcs(adev);
2963
2964         return 0;
2965 }
2966
2967 static int kv_dpm_late_init(void *handle)
2968 {
2969         /* powerdown unused blocks for now */
2970         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2971
2972         if (!adev->pm.dpm_enabled)
2973                 return 0;
2974
2975         kv_dpm_powergate_acp(adev, true);
2976         kv_dpm_powergate_samu(adev, true);
2977
2978         return 0;
2979 }
2980
2981 static int kv_dpm_sw_init(void *handle)
2982 {
2983         int ret;
2984         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2985
2986         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
2987                                 &adev->pm.dpm.thermal.irq);
2988         if (ret)
2989                 return ret;
2990
2991         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
2992                                 &adev->pm.dpm.thermal.irq);
2993         if (ret)
2994                 return ret;
2995
2996         /* default to balanced state */
2997         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
2998         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
2999         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
3000         adev->pm.default_sclk = adev->clock.default_sclk;
3001         adev->pm.default_mclk = adev->clock.default_mclk;
3002         adev->pm.current_sclk = adev->clock.default_sclk;
3003         adev->pm.current_mclk = adev->clock.default_mclk;
3004         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
3005
3006         if (amdgpu_dpm == 0)
3007                 return 0;
3008
3009         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
3010         mutex_lock(&adev->pm.mutex);
3011         ret = kv_dpm_init(adev);
3012         if (ret)
3013                 goto dpm_failed;
3014         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3015         if (amdgpu_dpm == 1)
3016                 amdgpu_pm_print_power_states(adev);
3017         mutex_unlock(&adev->pm.mutex);
3018         DRM_INFO("amdgpu: dpm initialized\n");
3019
3020         return 0;
3021
3022 dpm_failed:
3023         kv_dpm_fini(adev);
3024         mutex_unlock(&adev->pm.mutex);
3025         DRM_ERROR("amdgpu: dpm initialization failed\n");
3026         return ret;
3027 }
3028
3029 static int kv_dpm_sw_fini(void *handle)
3030 {
3031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3032
3033         flush_work(&adev->pm.dpm.thermal.work);
3034
3035         mutex_lock(&adev->pm.mutex);
3036         kv_dpm_fini(adev);
3037         mutex_unlock(&adev->pm.mutex);
3038
3039         return 0;
3040 }
3041
3042 static int kv_dpm_hw_init(void *handle)
3043 {
3044         int ret;
3045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046
3047         if (!amdgpu_dpm)
3048                 return 0;
3049
3050         mutex_lock(&adev->pm.mutex);
3051         kv_dpm_setup_asic(adev);
3052         ret = kv_dpm_enable(adev);
3053         if (ret)
3054                 adev->pm.dpm_enabled = false;
3055         else
3056                 adev->pm.dpm_enabled = true;
3057         mutex_unlock(&adev->pm.mutex);
3058         amdgpu_pm_compute_clocks(adev);
3059         return ret;
3060 }
3061
3062 static int kv_dpm_hw_fini(void *handle)
3063 {
3064         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3065
3066         if (adev->pm.dpm_enabled) {
3067                 mutex_lock(&adev->pm.mutex);
3068                 kv_dpm_disable(adev);
3069                 mutex_unlock(&adev->pm.mutex);
3070         }
3071
3072         return 0;
3073 }
3074
3075 static int kv_dpm_suspend(void *handle)
3076 {
3077         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3078
3079         if (adev->pm.dpm_enabled) {
3080                 mutex_lock(&adev->pm.mutex);
3081                 /* disable dpm */
3082                 kv_dpm_disable(adev);
3083                 /* reset the power state */
3084                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3085                 mutex_unlock(&adev->pm.mutex);
3086         }
3087         return 0;
3088 }
3089
3090 static int kv_dpm_resume(void *handle)
3091 {
3092         int ret;
3093         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3094
3095         if (adev->pm.dpm_enabled) {
3096                 /* asic init will reset to the boot state */
3097                 mutex_lock(&adev->pm.mutex);
3098                 kv_dpm_setup_asic(adev);
3099                 ret = kv_dpm_enable(adev);
3100                 if (ret)
3101                         adev->pm.dpm_enabled = false;
3102                 else
3103                         adev->pm.dpm_enabled = true;
3104                 mutex_unlock(&adev->pm.mutex);
3105                 if (adev->pm.dpm_enabled)
3106                         amdgpu_pm_compute_clocks(adev);
3107         }
3108         return 0;
3109 }
3110
3111 static bool kv_dpm_is_idle(void *handle)
3112 {
3113         return true;
3114 }
3115
3116 static int kv_dpm_wait_for_idle(void *handle)
3117 {
3118         return 0;
3119 }
3120
3121
3122 static int kv_dpm_soft_reset(void *handle)
3123 {
3124         return 0;
3125 }
3126
3127 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
3128                                       struct amdgpu_irq_src *src,
3129                                       unsigned type,
3130                                       enum amdgpu_interrupt_state state)
3131 {
3132         u32 cg_thermal_int;
3133
3134         switch (type) {
3135         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
3136                 switch (state) {
3137                 case AMDGPU_IRQ_STATE_DISABLE:
3138                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3139                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3140                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3141                         break;
3142                 case AMDGPU_IRQ_STATE_ENABLE:
3143                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3144                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3145                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3146                         break;
3147                 default:
3148                         break;
3149                 }
3150                 break;
3151
3152         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
3153                 switch (state) {
3154                 case AMDGPU_IRQ_STATE_DISABLE:
3155                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3156                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3157                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3158                         break;
3159                 case AMDGPU_IRQ_STATE_ENABLE:
3160                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3161                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3162                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3163                         break;
3164                 default:
3165                         break;
3166                 }
3167                 break;
3168
3169         default:
3170                 break;
3171         }
3172         return 0;
3173 }
3174
3175 static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
3176                                     struct amdgpu_irq_src *source,
3177                                     struct amdgpu_iv_entry *entry)
3178 {
3179         bool queue_thermal = false;
3180
3181         if (entry == NULL)
3182                 return -EINVAL;
3183
3184         switch (entry->src_id) {
3185         case 230: /* thermal low to high */
3186                 DRM_DEBUG("IH: thermal low to high\n");
3187                 adev->pm.dpm.thermal.high_to_low = false;
3188                 queue_thermal = true;
3189                 break;
3190         case 231: /* thermal high to low */
3191                 DRM_DEBUG("IH: thermal high to low\n");
3192                 adev->pm.dpm.thermal.high_to_low = true;
3193                 queue_thermal = true;
3194                 break;
3195         default:
3196                 break;
3197         }
3198
3199         if (queue_thermal)
3200                 schedule_work(&adev->pm.dpm.thermal.work);
3201
3202         return 0;
3203 }
3204
3205 static int kv_dpm_set_clockgating_state(void *handle,
3206                                           enum amd_clockgating_state state)
3207 {
3208         return 0;
3209 }
3210
3211 static int kv_dpm_set_powergating_state(void *handle,
3212                                           enum amd_powergating_state state)
3213 {
3214         return 0;
3215 }
3216
3217 static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
3218                                                 const struct kv_pl *kv_cpl2)
3219 {
3220         return ((kv_cpl1->sclk == kv_cpl2->sclk) &&
3221                   (kv_cpl1->vddc_index == kv_cpl2->vddc_index) &&
3222                   (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) &&
3223                   (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
3224 }
3225
3226 static int kv_check_state_equal(void *handle,
3227                                 void *current_ps,
3228                                 void *request_ps,
3229                                 bool *equal)
3230 {
3231         struct kv_ps *kv_cps;
3232         struct kv_ps *kv_rps;
3233         int i;
3234         struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
3235         struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
3236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3237
3238         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
3239                 return -EINVAL;
3240
3241         kv_cps = kv_get_ps(cps);
3242         kv_rps = kv_get_ps(rps);
3243
3244         if (kv_cps == NULL) {
3245                 *equal = false;
3246                 return 0;
3247         }
3248
3249         if (kv_cps->num_levels != kv_rps->num_levels) {
3250                 *equal = false;
3251                 return 0;
3252         }
3253
3254         for (i = 0; i < kv_cps->num_levels; i++) {
3255                 if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
3256                                         &(kv_rps->levels[i]))) {
3257                         *equal = false;
3258                         return 0;
3259                 }
3260         }
3261
3262         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
3263         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
3264         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
3265
3266         return 0;
3267 }
3268
3269 static int kv_dpm_read_sensor(void *handle, int idx,
3270                               void *value, int *size)
3271 {
3272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3273         struct kv_power_info *pi = kv_get_pi(adev);
3274         uint32_t sclk;
3275         u32 pl_index =
3276                 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
3277                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
3278                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
3279
3280         /* size must be at least 4 bytes for all sensors */
3281         if (*size < 4)
3282                 return -EINVAL;
3283
3284         switch (idx) {
3285         case AMDGPU_PP_SENSOR_GFX_SCLK:
3286                 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
3287                         sclk = be32_to_cpu(
3288                                 pi->graphics_level[pl_index].SclkFrequency);
3289                         *((uint32_t *)value) = sclk;
3290                         *size = 4;
3291                         return 0;
3292                 }
3293                 return -EINVAL;
3294         case AMDGPU_PP_SENSOR_GPU_TEMP:
3295                 *((uint32_t *)value) = kv_dpm_get_temp(adev);
3296                 *size = 4;
3297                 return 0;
3298         default:
3299                 return -EINVAL;
3300         }
3301 }
3302
3303 static int kv_set_powergating_by_smu(void *handle,
3304                                 uint32_t block_type, bool gate)
3305 {
3306         switch (block_type) {
3307         case AMD_IP_BLOCK_TYPE_UVD:
3308                 kv_dpm_powergate_uvd(handle, gate);
3309                 break;
3310         case AMD_IP_BLOCK_TYPE_VCE:
3311                 kv_dpm_powergate_vce(handle, gate);
3312                 break;
3313         default:
3314                 break;
3315         }
3316         return 0;
3317 }
3318
3319 static const struct amd_ip_funcs kv_dpm_ip_funcs = {
3320         .name = "kv_dpm",
3321         .early_init = kv_dpm_early_init,
3322         .late_init = kv_dpm_late_init,
3323         .sw_init = kv_dpm_sw_init,
3324         .sw_fini = kv_dpm_sw_fini,
3325         .hw_init = kv_dpm_hw_init,
3326         .hw_fini = kv_dpm_hw_fini,
3327         .suspend = kv_dpm_suspend,
3328         .resume = kv_dpm_resume,
3329         .is_idle = kv_dpm_is_idle,
3330         .wait_for_idle = kv_dpm_wait_for_idle,
3331         .soft_reset = kv_dpm_soft_reset,
3332         .set_clockgating_state = kv_dpm_set_clockgating_state,
3333         .set_powergating_state = kv_dpm_set_powergating_state,
3334 };
3335
3336 const struct amdgpu_ip_block_version kv_smu_ip_block =
3337 {
3338         .type = AMD_IP_BLOCK_TYPE_SMC,
3339         .major = 1,
3340         .minor = 0,
3341         .rev = 0,
3342         .funcs = &kv_dpm_ip_funcs,
3343 };
3344
3345 static const struct amd_pm_funcs kv_dpm_funcs = {
3346         .pre_set_power_state = &kv_dpm_pre_set_power_state,
3347         .set_power_state = &kv_dpm_set_power_state,
3348         .post_set_power_state = &kv_dpm_post_set_power_state,
3349         .display_configuration_changed = &kv_dpm_display_configuration_changed,
3350         .get_sclk = &kv_dpm_get_sclk,
3351         .get_mclk = &kv_dpm_get_mclk,
3352         .print_power_state = &kv_dpm_print_power_state,
3353         .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
3354         .force_performance_level = &kv_dpm_force_performance_level,
3355         .set_powergating_by_smu = kv_set_powergating_by_smu,
3356         .enable_bapm = &kv_dpm_enable_bapm,
3357         .get_vce_clock_state = amdgpu_get_vce_clock_state,
3358         .check_state_equal = kv_check_state_equal,
3359         .read_sensor = &kv_dpm_read_sensor,
3360 };
3361
3362 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
3363         .set = kv_dpm_set_interrupt_state,
3364         .process = kv_dpm_process_interrupt,
3365 };
3366
3367 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
3368 {
3369         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
3370         adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
3371 }