drivers/gpu/drm/amd/amdgpu/kv_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_dpm.h"
  31 #include "kv_dpm.h"
  32 #include "gfx_v7_0.h"
  33 #include <linux/seq_file.h>
  34
  35 #include "smu/smu_7_0_0_d.h"
  36 #include "smu/smu_7_0_0_sh_mask.h"
  37
  38 #include "gca/gfx_7_2_d.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  42 #define KV_MINIMUM_ENGINE_CLOCK         800
  43 #define SMC_RAM_END                     0x40000
  44
  45 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
  46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
  47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
  48                             bool enable);
  49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
  50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
  51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
  52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
  53 static void kv_enable_new_levels(struct amdgpu_device *adev);
  54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
  55                                            struct amdgpu_ps *new_rps);
  56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
  57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
  58 static int kv_force_dpm_highest(struct amdgpu_device *adev);
  59 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
  60 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
  61                                         struct amdgpu_ps *new_rps,
  62                                         struct amdgpu_ps *old_rps);
  63 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
  64                                             int min_temp, int max_temp);
  65 static int kv_init_fps_limits(struct amdgpu_device *adev);
  66
  67 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
  68 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
  69 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
  70 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
  71
  72
  73 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
  74                                    struct sumo_vid_mapping_table *vid_mapping_table,
  75                                    u32 vid_2bit)
  76 {
  77         struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  78                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  79         u32 i;
  80
  81         if (vddc_sclk_table && vddc_sclk_table->count) {
  82                 if (vid_2bit < vddc_sclk_table->count)
  83                         return vddc_sclk_table->entries[vid_2bit].v;
  84                 else
  85                         return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
  86         } else {
  87                 for (i = 0; i < vid_mapping_table->num_entries; i++) {
  88                         if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
  89                                 return vid_mapping_table->entries[i].vid_7bit;
  90                 }
  91                 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
  92         }
  93 }
  94
  95 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
  96                                    struct sumo_vid_mapping_table *vid_mapping_table,
  97                                    u32 vid_7bit)
  98 {
  99         struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
 100                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 101         u32 i;
 102
 103         if (vddc_sclk_table && vddc_sclk_table->count) {
 104                 for (i = 0; i < vddc_sclk_table->count; i++) {
 105                         if (vddc_sclk_table->entries[i].v == vid_7bit)
 106                                 return i;
 107                 }
 108                 return vddc_sclk_table->count - 1;
 109         } else {
 110                 for (i = 0; i < vid_mapping_table->num_entries; i++) {
 111                         if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
 112                                 return vid_mapping_table->entries[i].vid_2bit;
 113                 }
 114
 115                 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
 116         }
 117 }
 118
 119 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
 120 {
 121 /* This bit selects who handles display phy powergating.
 122  * Clear the bit to let atom handle it.
 123  * Set it to let the driver handle it.
 124  * For now we just let atom handle it.
 125  */
 126 #if 0
 127         u32 v = RREG32(mmDOUT_SCRATCH3);
 128
 129         if (enable)
 130                 v |= 0x4;
 131         else
 132                 v &= 0xFFFFFFFB;
 133
 134         WREG32(mmDOUT_SCRATCH3, v);
 135 #endif
 136 }
 137
 138 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
 139                                                       struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
 140                                                       ATOM_AVAILABLE_SCLK_LIST *table)
 141 {
 142         u32 i;
 143         u32 n = 0;
 144         u32 prev_sclk = 0;
 145
 146         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 147                 if (table[i].ulSupportedSCLK > prev_sclk) {
 148                         sclk_voltage_mapping_table->entries[n].sclk_frequency =
 149                                 table[i].ulSupportedSCLK;
 150                         sclk_voltage_mapping_table->entries[n].vid_2bit =
 151                                 table[i].usVoltageIndex;
 152                         prev_sclk = table[i].ulSupportedSCLK;
 153                         n++;
 154                 }
 155         }
 156
 157         sclk_voltage_mapping_table->num_max_dpm_entries = n;
 158 }
 159
 160 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
 161                                              struct sumo_vid_mapping_table *vid_mapping_table,
 162                                              ATOM_AVAILABLE_SCLK_LIST *table)
 163 {
 164         u32 i, j;
 165
 166         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 167                 if (table[i].ulSupportedSCLK != 0) {
 168                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
 169                                 table[i].usVoltageID;
 170                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
 171                                 table[i].usVoltageIndex;
 172                 }
 173         }
 174
 175         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
 176                 if (vid_mapping_table->entries[i].vid_7bit == 0) {
 177                         for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
 178                                 if (vid_mapping_table->entries[j].vid_7bit != 0) {
 179                                         vid_mapping_table->entries[i] =
 180                                                 vid_mapping_table->entries[j];
 181                                         vid_mapping_table->entries[j].vid_7bit = 0;
 182                                         break;
 183                                 }
 184                         }
 185
 186                         if (j == SUMO_MAX_NUMBER_VOLTAGES)
 187                                 break;
 188                 }
 189         }
 190
 191         vid_mapping_table->num_entries = i;
 192 }
 193
 194 #if 0
 195 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
 196 {
 197         {  0,       4,        1    },
 198         {  1,       4,        1    },
 199         {  2,       5,        1    },
 200         {  3,       4,        2    },
 201         {  4,       1,        1    },
 202         {  5,       5,        2    },
 203         {  6,       6,        1    },
 204         {  7,       9,        2    },
 205         { 0xffffffff }
 206 };
 207
 208 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
 209 {
 210         {  0,       4,        1    },
 211         { 0xffffffff }
 212 };
 213
 214 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
 215 {
 216         {  0,       4,        1    },
 217         { 0xffffffff }
 218 };
 219
 220 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
 221 {
 222         {  0,       4,        1    },
 223         { 0xffffffff }
 224 };
 225
 226 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
 227 {
 228         {  0,       4,        1    },
 229         { 0xffffffff }
 230 };
 231
 232 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
 233 {
 234         {  0,       4,        1    },
 235         {  1,       4,        1    },
 236         {  2,       5,        1    },
 237         {  3,       4,        1    },
 238         {  4,       1,        1    },
 239         {  5,       5,        1    },
 240         {  6,       6,        1    },
 241         {  7,       9,        1    },
 242         {  8,       4,        1    },
 243         {  9,       2,        1    },
 244         {  10,      3,        1    },
 245         {  11,      6,        1    },
 246         {  12,      8,        2    },
 247         {  13,      1,        1    },
 248         {  14,      2,        1    },
 249         {  15,      3,        1    },
 250         {  16,      1,        1    },
 251         {  17,      4,        1    },
 252         {  18,      3,        1    },
 253         {  19,      1,        1    },
 254         {  20,      8,        1    },
 255         {  21,      5,        1    },
 256         {  22,      1,        1    },
 257         {  23,      1,        1    },
 258         {  24,      4,        1    },
 259         {  27,      6,        1    },
 260         {  28,      1,        1    },
 261         { 0xffffffff }
 262 };
 263
 264 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 265 {
 266         { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 267 };
 268
 269 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 270 {
 271         { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 272 };
 273
 274 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 275 {
 276         { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 277 };
 278
 279 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 280 {
 281         { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 282 };
 283
 284 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 285 {
 286         { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 287 };
 288
 289 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 290 {
 291         { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 292 };
 293 #endif
 294
 295 static const struct kv_pt_config_reg didt_config_kv[] =
 296 {
 297         { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 298         { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 299         { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 300         { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 301         { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 302         { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 303         { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 304         { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 305         { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 306         { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 307         { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 308         { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 309         { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 310         { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 311         { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 312         { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 313         { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 314         { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 315         { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 316         { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 317         { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 318         { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 319         { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 320         { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 321         { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 322         { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 323         { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 324         { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 325         { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 326         { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 327         { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 328         { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 329         { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 330         { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 331         { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 332         { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 333         { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 334         { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 335         { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 336         { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 337         { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 338         { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 339         { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 340         { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 341         { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 342         { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 343         { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 344         { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 345         { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 346         { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 347         { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 348         { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 349         { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 350         { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 351         { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 352         { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 353         { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 354         { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 355         { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 356         { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 357         { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 358         { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 359         { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 360         { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 361         { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 362         { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 363         { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 364         { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 365         { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 366         { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 367         { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 368         { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 369         { 0xFFFFFFFF }
 370 };
 371
 372 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
 373 {
 374         struct kv_ps *ps = rps->ps_priv;
 375
 376         return ps;
 377 }
 378
 379 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
 380 {
 381         struct kv_power_info *pi = adev->pm.dpm.priv;
 382
 383         return pi;
 384 }
 385
 386 #if 0
 387 static void kv_program_local_cac_table(struct amdgpu_device *adev,
 388                                        const struct kv_lcac_config_values *local_cac_table,
 389                                        const struct kv_lcac_config_reg *local_cac_reg)
 390 {
 391         u32 i, count, data;
 392         const struct kv_lcac_config_values *values = local_cac_table;
 393
 394         while (values->block_id != 0xffffffff) {
 395                 count = values->signal_id;
 396                 for (i = 0; i < count; i++) {
 397                         data = ((values->block_id << local_cac_reg->block_shift) &
 398                                 local_cac_reg->block_mask);
 399                         data |= ((i << local_cac_reg->signal_shift) &
 400                                  local_cac_reg->signal_mask);
 401                         data |= ((values->t << local_cac_reg->t_shift) &
 402                                  local_cac_reg->t_mask);
 403                         data |= ((1 << local_cac_reg->enable_shift) &
 404                                  local_cac_reg->enable_mask);
 405                         WREG32_SMC(local_cac_reg->cntl, data);
 406                 }
 407                 values++;
 408         }
 409 }
 410 #endif
 411
 412 static int kv_program_pt_config_registers(struct amdgpu_device *adev,
 413                                           const struct kv_pt_config_reg *cac_config_regs)
 414 {
 415         const struct kv_pt_config_reg *config_regs = cac_config_regs;
 416         u32 data;
 417         u32 cache = 0;
 418
 419         if (config_regs == NULL)
 420                 return -EINVAL;
 421
 422         while (config_regs->offset != 0xFFFFFFFF) {
 423                 if (config_regs->type == KV_CONFIGREG_CACHE) {
 424                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 425                 } else {
 426                         switch (config_regs->type) {
 427                         case KV_CONFIGREG_SMC_IND:
 428                                 data = RREG32_SMC(config_regs->offset);
 429                                 break;
 430                         case KV_CONFIGREG_DIDT_IND:
 431                                 data = RREG32_DIDT(config_regs->offset);
 432                                 break;
 433                         default:
 434                                 data = RREG32(config_regs->offset);
 435                                 break;
 436                         }
 437
 438                         data &= ~config_regs->mask;
 439                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 440                         data |= cache;
 441                         cache = 0;
 442
 443                         switch (config_regs->type) {
 444                         case KV_CONFIGREG_SMC_IND:
 445                                 WREG32_SMC(config_regs->offset, data);
 446                                 break;
 447                         case KV_CONFIGREG_DIDT_IND:
 448                                 WREG32_DIDT(config_regs->offset, data);
 449                                 break;
 450                         default:
 451                                 WREG32(config_regs->offset, data);
 452                                 break;
 453                         }
 454                 }
 455                 config_regs++;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
 462 {
 463         struct kv_power_info *pi = kv_get_pi(adev);
 464         u32 data;
 465
 466         if (pi->caps_sq_ramping) {
 467                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 468                 if (enable)
 469                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 470                 else
 471                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 472                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 473         }
 474
 475         if (pi->caps_db_ramping) {
 476                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 477                 if (enable)
 478                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 479                 else
 480                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 481                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 482         }
 483
 484         if (pi->caps_td_ramping) {
 485                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 486                 if (enable)
 487                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 488                 else
 489                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 490                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 491         }
 492
 493         if (pi->caps_tcp_ramping) {
 494                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 495                 if (enable)
 496                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 497                 else
 498                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 499                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 500         }
 501 }
 502
 503 static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
 504 {
 505         struct kv_power_info *pi = kv_get_pi(adev);
 506         int ret;
 507
 508         if (pi->caps_sq_ramping ||
 509             pi->caps_db_ramping ||
 510             pi->caps_td_ramping ||
 511             pi->caps_tcp_ramping) {
 512                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 513
 514                 if (enable) {
 515                         ret = kv_program_pt_config_registers(adev, didt_config_kv);
 516                         if (ret) {
 517                                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 518                                 return ret;
 519                         }
 520                 }
 521
 522                 kv_do_enable_didt(adev, enable);
 523
 524                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 525         }
 526
 527         return 0;
 528 }
 529
 530 #if 0
 531 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
 532 {
 533         struct kv_power_info *pi = kv_get_pi(adev);
 534
 535         if (pi->caps_cac) {
 536                 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
 537                 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
 538                 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 539
 540                 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
 541                 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
 542                 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 543
 544                 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
 545                 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
 546                 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 547
 548                 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
 549                 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
 550                 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 551
 552                 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
 553                 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
 554                 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 555
 556                 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
 557                 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
 558                 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 559         }
 560 }
 561 #endif
 562
 563 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 564 {
 565         struct kv_power_info *pi = kv_get_pi(adev);
 566         int ret = 0;
 567
 568         if (pi->caps_cac) {
 569                 if (enable) {
 570                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
 571                         if (ret)
 572                                 pi->cac_enabled = false;
 573                         else
 574                                 pi->cac_enabled = true;
 575                 } else if (pi->cac_enabled) {
 576                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
 577                         pi->cac_enabled = false;
 578                 }
 579         }
 580
 581         return ret;
 582 }
 583
 584 static int kv_process_firmware_header(struct amdgpu_device *adev)
 585 {
 586         struct kv_power_info *pi = kv_get_pi(adev);
 587         u32 tmp;
 588         int ret;
 589
 590         ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 591                                      offsetof(SMU7_Firmware_Header, DpmTable),
 592                                      &tmp, pi->sram_end);
 593
 594         if (ret == 0)
 595                 pi->dpm_table_start = tmp;
 596
 597         ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 598                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
 599                                      &tmp, pi->sram_end);
 600
 601         if (ret == 0)
 602                 pi->soft_regs_start = tmp;
 603
 604         return ret;
 605 }
 606
 607 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
 608 {
 609         struct kv_power_info *pi = kv_get_pi(adev);
 610         int ret;
 611
 612         pi->graphics_voltage_change_enable = 1;
 613
 614         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 615                                    pi->dpm_table_start +
 616                                    offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 617                                    &pi->graphics_voltage_change_enable,
 618                                    sizeof(u8), pi->sram_end);
 619
 620         return ret;
 621 }
 622
 623 static int kv_set_dpm_interval(struct amdgpu_device *adev)
 624 {
 625         struct kv_power_info *pi = kv_get_pi(adev);
 626         int ret;
 627
 628         pi->graphics_interval = 1;
 629
 630         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 631                                    pi->dpm_table_start +
 632                                    offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 633                                    &pi->graphics_interval,
 634                                    sizeof(u8), pi->sram_end);
 635
 636         return ret;
 637 }
 638
 639 static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
 640 {
 641         struct kv_power_info *pi = kv_get_pi(adev);
 642         int ret;
 643
 644         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 645                                    pi->dpm_table_start +
 646                                    offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 647                                    &pi->graphics_boot_level,
 648                                    sizeof(u8), pi->sram_end);
 649
 650         return ret;
 651 }
 652
 653 static void kv_program_vc(struct amdgpu_device *adev)
 654 {
 655         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
 656 }
 657
 658 static void kv_clear_vc(struct amdgpu_device *adev)
 659 {
 660         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
 661 }
 662
 663 static int kv_set_divider_value(struct amdgpu_device *adev,
 664                                 u32 index, u32 sclk)
 665 {
 666         struct kv_power_info *pi = kv_get_pi(adev);
 667         struct atom_clock_dividers dividers;
 668         int ret;
 669
 670         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 671                                                  sclk, false, &dividers);
 672         if (ret)
 673                 return ret;
 674
 675         pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 676         pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 677
 678         return 0;
 679 }
 680
 681 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
 682                                             u16 voltage)
 683 {
 684         return 6200 - (voltage * 25);
 685 }
 686
 687 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
 688                                             u32 vid_2bit)
 689 {
 690         struct kv_power_info *pi = kv_get_pi(adev);
 691         u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
 692                                                &pi->sys_info.vid_mapping_table,
 693                                                vid_2bit);
 694
 695         return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
 696 }
 697
 698
 699 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
 700 {
 701         struct kv_power_info *pi = kv_get_pi(adev);
 702
 703         pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 704         pi->graphics_level[index].MinVddNb =
 705                 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
 706
 707         return 0;
 708 }
 709
 710 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
 711 {
 712         struct kv_power_info *pi = kv_get_pi(adev);
 713
 714         pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 715
 716         return 0;
 717 }
 718
 719 static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
 720                                       u32 index, bool enable)
 721 {
 722         struct kv_power_info *pi = kv_get_pi(adev);
 723
 724         pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 725 }
 726
 727 static void kv_start_dpm(struct amdgpu_device *adev)
 728 {
 729         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
 730
 731         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
 732         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
 733
 734         amdgpu_kv_smc_dpm_enable(adev, true);
 735 }
 736
 737 static void kv_stop_dpm(struct amdgpu_device *adev)
 738 {
 739         amdgpu_kv_smc_dpm_enable(adev, false);
 740 }
 741
 742 static void kv_start_am(struct amdgpu_device *adev)
 743 {
 744         u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 745
 746         sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 747                         SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 748         sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
 749
 750         WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 751 }
 752
 753 static void kv_reset_am(struct amdgpu_device *adev)
 754 {
 755         u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 756
 757         sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 758                         SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 759
 760         WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 761 }
 762
 763 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
 764 {
 765         return amdgpu_kv_notify_message_to_smu(adev, freeze ?
 766                                         PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 767 }
 768
 769 static int kv_force_lowest_valid(struct amdgpu_device *adev)
 770 {
 771         return kv_force_dpm_lowest(adev);
 772 }
 773
 774 static int kv_unforce_levels(struct amdgpu_device *adev)
 775 {
 776         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
 777                 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
 778         else
 779                 return kv_set_enabled_levels(adev);
 780 }
 781
 782 static int kv_update_sclk_t(struct amdgpu_device *adev)
 783 {
 784         struct kv_power_info *pi = kv_get_pi(adev);
 785         u32 low_sclk_interrupt_t = 0;
 786         int ret = 0;
 787
 788         if (pi->caps_sclk_throttle_low_notification) {
 789                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 790
 791                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
 792                                            pi->dpm_table_start +
 793                                            offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 794                                            (u8 *)&low_sclk_interrupt_t,
 795                                            sizeof(u32), pi->sram_end);
 796         }
 797         return ret;
 798 }
 799
 800 static int kv_program_bootup_state(struct amdgpu_device *adev)
 801 {
 802         struct kv_power_info *pi = kv_get_pi(adev);
 803         u32 i;
 804         struct amdgpu_clock_voltage_dependency_table *table =
 805                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 806
 807         if (table && table->count) {
 808                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 809                         if (table->entries[i].clk == pi->boot_pl.sclk)
 810                                 break;
 811                 }
 812
 813                 pi->graphics_boot_level = (u8)i;
 814                 kv_dpm_power_level_enable(adev, i, true);
 815         } else {
 816                 struct sumo_sclk_voltage_mapping_table *table =
 817                         &pi->sys_info.sclk_voltage_mapping_table;
 818
 819                 if (table->num_max_dpm_entries == 0)
 820                         return -EINVAL;
 821
 822                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 823                         if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
 824                                 break;
 825                 }
 826
 827                 pi->graphics_boot_level = (u8)i;
 828                 kv_dpm_power_level_enable(adev, i, true);
 829         }
 830         return 0;
 831 }
 832
 833 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
 834 {
 835         struct kv_power_info *pi = kv_get_pi(adev);
 836         int ret;
 837
 838         pi->graphics_therm_throttle_enable = 1;
 839
 840         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 841                                    pi->dpm_table_start +
 842                                    offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 843                                    &pi->graphics_therm_throttle_enable,
 844                                    sizeof(u8), pi->sram_end);
 845
 846         return ret;
 847 }
 848
 849 static int kv_upload_dpm_settings(struct amdgpu_device *adev)
 850 {
 851         struct kv_power_info *pi = kv_get_pi(adev);
 852         int ret;
 853
 854         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 855                                    pi->dpm_table_start +
 856                                    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 857                                    (u8 *)&pi->graphics_level,
 858                                    sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 859                                    pi->sram_end);
 860
 861         if (ret)
 862                 return ret;
 863
 864         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 865                                    pi->dpm_table_start +
 866                                    offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 867                                    &pi->graphics_dpm_level_count,
 868                                    sizeof(u8), pi->sram_end);
 869
 870         return ret;
 871 }
 872
 873 static u32 kv_get_clock_difference(u32 a, u32 b)
 874 {
 875         return (a >= b) ? a - b : b - a;
 876 }
 877
 878 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
 879 {
 880         struct kv_power_info *pi = kv_get_pi(adev);
 881         u32 value;
 882
 883         if (pi->caps_enable_dfs_bypass) {
 884                 if (kv_get_clock_difference(clk, 40000) < 200)
 885                         value = 3;
 886                 else if (kv_get_clock_difference(clk, 30000) < 200)
 887                         value = 2;
 888                 else if (kv_get_clock_difference(clk, 20000) < 200)
 889                         value = 7;
 890                 else if (kv_get_clock_difference(clk, 15000) < 200)
 891                         value = 6;
 892                 else if (kv_get_clock_difference(clk, 10000) < 200)
 893                         value = 8;
 894                 else
 895                         value = 0;
 896         } else {
 897                 value = 0;
 898         }
 899
 900         return value;
 901 }
 902
 903 static int kv_populate_uvd_table(struct amdgpu_device *adev)
 904 {
 905         struct kv_power_info *pi = kv_get_pi(adev);
 906         struct amdgpu_uvd_clock_voltage_dependency_table *table =
 907                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 908         struct atom_clock_dividers dividers;
 909         int ret;
 910         u32 i;
 911
 912         if (table == NULL || table->count == 0)
 913                 return 0;
 914
 915         pi->uvd_level_count = 0;
 916         for (i = 0; i < table->count; i++) {
 917                 if (pi->high_voltage_t &&
 918                     (pi->high_voltage_t < table->entries[i].v))
 919                         break;
 920
 921                 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 922                 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 923                 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 924
 925                 pi->uvd_level[i].VClkBypassCntl =
 926                         (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
 927                 pi->uvd_level[i].DClkBypassCntl =
 928                         (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
 929
 930                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 931                                                          table->entries[i].vclk, false, &dividers);
 932                 if (ret)
 933                         return ret;
 934                 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 935
 936                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 937                                                          table->entries[i].dclk, false, &dividers);
 938                 if (ret)
 939                         return ret;
 940                 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 941
 942                 pi->uvd_level_count++;
 943         }
 944
 945         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 946                                    pi->dpm_table_start +
 947                                    offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 948                                    (u8 *)&pi->uvd_level_count,
 949                                    sizeof(u8), pi->sram_end);
 950         if (ret)
 951                 return ret;
 952
 953         pi->uvd_interval = 1;
 954
 955         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 956                                    pi->dpm_table_start +
 957                                    offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 958                                    &pi->uvd_interval,
 959                                    sizeof(u8), pi->sram_end);
 960         if (ret)
 961                 return ret;
 962
 963         ret = amdgpu_kv_copy_bytes_to_smc(adev,
 964                                    pi->dpm_table_start +
 965                                    offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 966                                    (u8 *)&pi->uvd_level,
 967                                    sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 968                                    pi->sram_end);
 969
 970         return ret;
 971
 972 }
 973
 974 static int kv_populate_vce_table(struct amdgpu_device *adev)
 975 {
 976         struct kv_power_info *pi = kv_get_pi(adev);
 977         int ret;
 978         u32 i;
 979         struct amdgpu_vce_clock_voltage_dependency_table *table =
 980                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 981         struct atom_clock_dividers dividers;
 982
 983         if (table == NULL || table->count == 0)
 984                 return 0;
 985
 986         pi->vce_level_count = 0;
 987         for (i = 0; i < table->count; i++) {
 988                 if (pi->high_voltage_t &&
 989                     pi->high_voltage_t < table->entries[i].v)
 990                         break;
 991
 992                 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 993                 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 994
 995                 pi->vce_level[i].ClkBypassCntl =
 996                         (u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
 997
 998                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 999                                                          table->entries[i].evclk, false, &dividers);
1000                 if (ret)
1001                         return ret;
1002                 pi->vce_level[i].Divider = (u8)dividers.post_div;
1003
1004                 pi->vce_level_count++;
1005         }
1006
1007         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1008                                    pi->dpm_table_start +
1009                                    offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
1010                                    (u8 *)&pi->vce_level_count,
1011                                    sizeof(u8),
1012                                    pi->sram_end);
1013         if (ret)
1014                 return ret;
1015
1016         pi->vce_interval = 1;
1017
1018         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1019                                    pi->dpm_table_start +
1020                                    offsetof(SMU7_Fusion_DpmTable, VCEInterval),
1021                                    (u8 *)&pi->vce_interval,
1022                                    sizeof(u8),
1023                                    pi->sram_end);
1024         if (ret)
1025                 return ret;
1026
1027         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1028                                    pi->dpm_table_start +
1029                                    offsetof(SMU7_Fusion_DpmTable, VceLevel),
1030                                    (u8 *)&pi->vce_level,
1031                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
1032                                    pi->sram_end);
1033
1034         return ret;
1035 }
1036
1037 static int kv_populate_samu_table(struct amdgpu_device *adev)
1038 {
1039         struct kv_power_info *pi = kv_get_pi(adev);
1040         struct amdgpu_clock_voltage_dependency_table *table =
1041                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1042         struct atom_clock_dividers dividers;
1043         int ret;
1044         u32 i;
1045
1046         if (table == NULL || table->count == 0)
1047                 return 0;
1048
1049         pi->samu_level_count = 0;
1050         for (i = 0; i < table->count; i++) {
1051                 if (pi->high_voltage_t &&
1052                     pi->high_voltage_t < table->entries[i].v)
1053                         break;
1054
1055                 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1056                 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1057
1058                 pi->samu_level[i].ClkBypassCntl =
1059                         (u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1060
1061                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1062                                                          table->entries[i].clk, false, &dividers);
1063                 if (ret)
1064                         return ret;
1065                 pi->samu_level[i].Divider = (u8)dividers.post_div;
1066
1067                 pi->samu_level_count++;
1068         }
1069
1070         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1071                                    pi->dpm_table_start +
1072                                    offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
1073                                    (u8 *)&pi->samu_level_count,
1074                                    sizeof(u8),
1075                                    pi->sram_end);
1076         if (ret)
1077                 return ret;
1078
1079         pi->samu_interval = 1;
1080
1081         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1082                                    pi->dpm_table_start +
1083                                    offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
1084                                    (u8 *)&pi->samu_interval,
1085                                    sizeof(u8),
1086                                    pi->sram_end);
1087         if (ret)
1088                 return ret;
1089
1090         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1091                                    pi->dpm_table_start +
1092                                    offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1093                                    (u8 *)&pi->samu_level,
1094                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1095                                    pi->sram_end);
1096         if (ret)
1097                 return ret;
1098
1099         return ret;
1100 }
1101
1102
1103 static int kv_populate_acp_table(struct amdgpu_device *adev)
1104 {
1105         struct kv_power_info *pi = kv_get_pi(adev);
1106         struct amdgpu_clock_voltage_dependency_table *table =
1107                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1108         struct atom_clock_dividers dividers;
1109         int ret;
1110         u32 i;
1111
1112         if (table == NULL || table->count == 0)
1113                 return 0;
1114
1115         pi->acp_level_count = 0;
1116         for (i = 0; i < table->count; i++) {
1117                 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1118                 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1119
1120                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1121                                                          table->entries[i].clk, false, &dividers);
1122                 if (ret)
1123                         return ret;
1124                 pi->acp_level[i].Divider = (u8)dividers.post_div;
1125
1126                 pi->acp_level_count++;
1127         }
1128
1129         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1130                                    pi->dpm_table_start +
1131                                    offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1132                                    (u8 *)&pi->acp_level_count,
1133                                    sizeof(u8),
1134                                    pi->sram_end);
1135         if (ret)
1136                 return ret;
1137
1138         pi->acp_interval = 1;
1139
1140         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1141                                    pi->dpm_table_start +
1142                                    offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1143                                    (u8 *)&pi->acp_interval,
1144                                    sizeof(u8),
1145                                    pi->sram_end);
1146         if (ret)
1147                 return ret;
1148
1149         ret = amdgpu_kv_copy_bytes_to_smc(adev,
1150                                    pi->dpm_table_start +
1151                                    offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1152                                    (u8 *)&pi->acp_level,
1153                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1154                                    pi->sram_end);
1155         if (ret)
1156                 return ret;
1157
1158         return ret;
1159 }
1160
1161 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
1162 {
1163         struct kv_power_info *pi = kv_get_pi(adev);
1164         u32 i;
1165         struct amdgpu_clock_voltage_dependency_table *table =
1166                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1167
1168         if (table && table->count) {
1169                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1170                         if (pi->caps_enable_dfs_bypass) {
1171                                 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1172                                         pi->graphics_level[i].ClkBypassCntl = 3;
1173                                 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1174                                         pi->graphics_level[i].ClkBypassCntl = 2;
1175                                 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1176                                         pi->graphics_level[i].ClkBypassCntl = 7;
1177                                 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1178                                         pi->graphics_level[i].ClkBypassCntl = 6;
1179                                 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1180                                         pi->graphics_level[i].ClkBypassCntl = 8;
1181                                 else
1182                                         pi->graphics_level[i].ClkBypassCntl = 0;
1183                         } else {
1184                                 pi->graphics_level[i].ClkBypassCntl = 0;
1185                         }
1186                 }
1187         } else {
1188                 struct sumo_sclk_voltage_mapping_table *table =
1189                         &pi->sys_info.sclk_voltage_mapping_table;
1190                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1191                         if (pi->caps_enable_dfs_bypass) {
1192                                 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1193                                         pi->graphics_level[i].ClkBypassCntl = 3;
1194                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1195                                         pi->graphics_level[i].ClkBypassCntl = 2;
1196                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1197                                         pi->graphics_level[i].ClkBypassCntl = 7;
1198                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1199                                         pi->graphics_level[i].ClkBypassCntl = 6;
1200                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1201                                         pi->graphics_level[i].ClkBypassCntl = 8;
1202                                 else
1203                                         pi->graphics_level[i].ClkBypassCntl = 0;
1204                         } else {
1205                                 pi->graphics_level[i].ClkBypassCntl = 0;
1206                         }
1207                 }
1208         }
1209 }
1210
1211 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
1212 {
1213         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1214                                         PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1215 }
1216
1217 static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
1218 {
1219         struct kv_power_info *pi = kv_get_pi(adev);
1220
1221         pi->acp_boot_level = 0xff;
1222 }
1223
1224 static void kv_update_current_ps(struct amdgpu_device *adev,
1225                                  struct amdgpu_ps *rps)
1226 {
1227         struct kv_ps *new_ps = kv_get_ps(rps);
1228         struct kv_power_info *pi = kv_get_pi(adev);
1229
1230         pi->current_rps = *rps;
1231         pi->current_ps = *new_ps;
1232         pi->current_rps.ps_priv = &pi->current_ps;
1233         adev->pm.dpm.current_ps = &pi->current_rps;
1234 }
1235
1236 static void kv_update_requested_ps(struct amdgpu_device *adev,
1237                                    struct amdgpu_ps *rps)
1238 {
1239         struct kv_ps *new_ps = kv_get_ps(rps);
1240         struct kv_power_info *pi = kv_get_pi(adev);
1241
1242         pi->requested_rps = *rps;
1243         pi->requested_ps = *new_ps;
1244         pi->requested_rps.ps_priv = &pi->requested_ps;
1245         adev->pm.dpm.requested_ps = &pi->requested_rps;
1246 }
1247
1248 static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
1249 {
1250         struct kv_power_info *pi = kv_get_pi(adev);
1251         int ret;
1252
1253         if (pi->bapm_enable) {
1254                 ret = amdgpu_kv_smc_bapm_enable(adev, enable);
1255                 if (ret)
1256                         DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1257         }
1258 }
1259
1260 static int kv_dpm_enable(struct amdgpu_device *adev)
1261 {
1262         struct kv_power_info *pi = kv_get_pi(adev);
1263         int ret;
1264
1265         ret = kv_process_firmware_header(adev);
1266         if (ret) {
1267                 DRM_ERROR("kv_process_firmware_header failed\n");
1268                 return ret;
1269         }
1270         kv_init_fps_limits(adev);
1271         kv_init_graphics_levels(adev);
1272         ret = kv_program_bootup_state(adev);
1273         if (ret) {
1274                 DRM_ERROR("kv_program_bootup_state failed\n");
1275                 return ret;
1276         }
1277         kv_calculate_dfs_bypass_settings(adev);
1278         ret = kv_upload_dpm_settings(adev);
1279         if (ret) {
1280                 DRM_ERROR("kv_upload_dpm_settings failed\n");
1281                 return ret;
1282         }
1283         ret = kv_populate_uvd_table(adev);
1284         if (ret) {
1285                 DRM_ERROR("kv_populate_uvd_table failed\n");
1286                 return ret;
1287         }
1288         ret = kv_populate_vce_table(adev);
1289         if (ret) {
1290                 DRM_ERROR("kv_populate_vce_table failed\n");
1291                 return ret;
1292         }
1293         ret = kv_populate_samu_table(adev);
1294         if (ret) {
1295                 DRM_ERROR("kv_populate_samu_table failed\n");
1296                 return ret;
1297         }
1298         ret = kv_populate_acp_table(adev);
1299         if (ret) {
1300                 DRM_ERROR("kv_populate_acp_table failed\n");
1301                 return ret;
1302         }
1303         kv_program_vc(adev);
1304 #if 0
1305         kv_initialize_hardware_cac_manager(adev);
1306 #endif
1307         kv_start_am(adev);
1308         if (pi->enable_auto_thermal_throttling) {
1309                 ret = kv_enable_auto_thermal_throttling(adev);
1310                 if (ret) {
1311                         DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1312                         return ret;
1313                 }
1314         }
1315         ret = kv_enable_dpm_voltage_scaling(adev);
1316         if (ret) {
1317                 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1318                 return ret;
1319         }
1320         ret = kv_set_dpm_interval(adev);
1321         if (ret) {
1322                 DRM_ERROR("kv_set_dpm_interval failed\n");
1323                 return ret;
1324         }
1325         ret = kv_set_dpm_boot_state(adev);
1326         if (ret) {
1327                 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1328                 return ret;
1329         }
1330         ret = kv_enable_ulv(adev, true);
1331         if (ret) {
1332                 DRM_ERROR("kv_enable_ulv failed\n");
1333                 return ret;
1334         }
1335         kv_start_dpm(adev);
1336         ret = kv_enable_didt(adev, true);
1337         if (ret) {
1338                 DRM_ERROR("kv_enable_didt failed\n");
1339                 return ret;
1340         }
1341         ret = kv_enable_smc_cac(adev, true);
1342         if (ret) {
1343                 DRM_ERROR("kv_enable_smc_cac failed\n");
1344                 return ret;
1345         }
1346
1347         kv_reset_acp_boot_level(adev);
1348
1349         ret = amdgpu_kv_smc_bapm_enable(adev, false);
1350         if (ret) {
1351                 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1352                 return ret;
1353         }
1354
1355         if (adev->irq.installed &&
1356             amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
1357                 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
1358                 if (ret) {
1359                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1360                         return ret;
1361                 }
1362                 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1363                                AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1364                 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1365                                AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1366         }
1367
1368         return ret;
1369 }
1370
1371 static void kv_dpm_disable(struct amdgpu_device *adev)
1372 {
1373         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1374                        AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1375         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1376                        AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1377
1378         amdgpu_kv_smc_bapm_enable(adev, false);
1379
1380         if (adev->asic_type == CHIP_MULLINS)
1381                 kv_enable_nb_dpm(adev, false);
1382
1383         /* powerup blocks */
1384         kv_dpm_powergate_acp(adev, false);
1385         kv_dpm_powergate_samu(adev, false);
1386         kv_dpm_powergate_vce(adev, false);
1387         kv_dpm_powergate_uvd(adev, false);
1388
1389         kv_enable_smc_cac(adev, false);
1390         kv_enable_didt(adev, false);
1391         kv_clear_vc(adev);
1392         kv_stop_dpm(adev);
1393         kv_enable_ulv(adev, false);
1394         kv_reset_am(adev);
1395
1396         kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1397 }
1398
1399 #if 0
1400 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1401                                       u16 reg_offset, u32 value)
1402 {
1403         struct kv_power_info *pi = kv_get_pi(adev);
1404
1405         return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1406                                     (u8 *)&value, sizeof(u16), pi->sram_end);
1407 }
1408
1409 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1410                                      u16 reg_offset, u32 *value)
1411 {
1412         struct kv_power_info *pi = kv_get_pi(adev);
1413
1414         return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1415                                       value, pi->sram_end);
1416 }
1417 #endif
1418
1419 static void kv_init_sclk_t(struct amdgpu_device *adev)
1420 {
1421         struct kv_power_info *pi = kv_get_pi(adev);
1422
1423         pi->low_sclk_interrupt_t = 0;
1424 }
1425
1426 static int kv_init_fps_limits(struct amdgpu_device *adev)
1427 {
1428         struct kv_power_info *pi = kv_get_pi(adev);
1429         int ret = 0;
1430
1431         if (pi->caps_fps) {
1432                 u16 tmp;
1433
1434                 tmp = 45;
1435                 pi->fps_high_t = cpu_to_be16(tmp);
1436                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1437                                            pi->dpm_table_start +
1438                                            offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1439                                            (u8 *)&pi->fps_high_t,
1440                                            sizeof(u16), pi->sram_end);
1441
1442                 tmp = 30;
1443                 pi->fps_low_t = cpu_to_be16(tmp);
1444
1445                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1446                                            pi->dpm_table_start +
1447                                            offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1448                                            (u8 *)&pi->fps_low_t,
1449                                            sizeof(u16), pi->sram_end);
1450
1451         }
1452         return ret;
1453 }
1454
1455 static void kv_init_powergate_state(struct amdgpu_device *adev)
1456 {
1457         struct kv_power_info *pi = kv_get_pi(adev);
1458
1459         pi->uvd_power_gated = false;
1460         pi->vce_power_gated = false;
1461         pi->samu_power_gated = false;
1462         pi->acp_power_gated = false;
1463
1464 }
1465
1466 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1467 {
1468         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1469                                         PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1470 }
1471
1472 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1473 {
1474         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1475                                         PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1476 }
1477
1478 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
1479 {
1480         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1481                                         PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1482 }
1483
1484 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
1485 {
1486         return amdgpu_kv_notify_message_to_smu(adev, enable ?
1487                                         PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1488 }
1489
1490 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1491 {
1492         struct kv_power_info *pi = kv_get_pi(adev);
1493         struct amdgpu_uvd_clock_voltage_dependency_table *table =
1494                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1495         int ret;
1496         u32 mask;
1497
1498         if (!gate) {
1499                 if (table->count)
1500                         pi->uvd_boot_level = table->count - 1;
1501                 else
1502                         pi->uvd_boot_level = 0;
1503
1504                 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1505                         mask = 1 << pi->uvd_boot_level;
1506                 } else {
1507                         mask = 0x1f;
1508                 }
1509
1510                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1511                                            pi->dpm_table_start +
1512                                            offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1513                                            (uint8_t *)&pi->uvd_boot_level,
1514                                            sizeof(u8), pi->sram_end);
1515                 if (ret)
1516                         return ret;
1517
1518                 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1519                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
1520                                                   mask);
1521         }
1522
1523         return kv_enable_uvd_dpm(adev, !gate);
1524 }
1525
1526 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
1527 {
1528         u8 i;
1529         struct amdgpu_vce_clock_voltage_dependency_table *table =
1530                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1531
1532         for (i = 0; i < table->count; i++) {
1533                 if (table->entries[i].evclk >= evclk)
1534                         break;
1535         }
1536
1537         return i;
1538 }
1539
1540 static int kv_update_vce_dpm(struct amdgpu_device *adev,
1541                              struct amdgpu_ps *amdgpu_new_state,
1542                              struct amdgpu_ps *amdgpu_current_state)
1543 {
1544         struct kv_power_info *pi = kv_get_pi(adev);
1545         struct amdgpu_vce_clock_voltage_dependency_table *table =
1546                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1547         int ret;
1548
1549         if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1550                 kv_dpm_powergate_vce(adev, false);
1551                 if (pi->caps_stable_p_state)
1552                         pi->vce_boot_level = table->count - 1;
1553                 else
1554                         pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
1555
1556                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1557                                            pi->dpm_table_start +
1558                                            offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1559                                            (u8 *)&pi->vce_boot_level,
1560                                            sizeof(u8),
1561                                            pi->sram_end);
1562                 if (ret)
1563                         return ret;
1564
1565                 if (pi->caps_stable_p_state)
1566                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1567                                                           PPSMC_MSG_VCEDPM_SetEnabledMask,
1568                                                           (1 << pi->vce_boot_level));
1569                 kv_enable_vce_dpm(adev, true);
1570         } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1571                 kv_enable_vce_dpm(adev, false);
1572                 kv_dpm_powergate_vce(adev, true);
1573         }
1574
1575         return 0;
1576 }
1577
1578 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
1579 {
1580         struct kv_power_info *pi = kv_get_pi(adev);
1581         struct amdgpu_clock_voltage_dependency_table *table =
1582                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1583         int ret;
1584
1585         if (!gate) {
1586                 if (pi->caps_stable_p_state)
1587                         pi->samu_boot_level = table->count - 1;
1588                 else
1589                         pi->samu_boot_level = 0;
1590
1591                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1592                                            pi->dpm_table_start +
1593                                            offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1594                                            (u8 *)&pi->samu_boot_level,
1595                                            sizeof(u8),
1596                                            pi->sram_end);
1597                 if (ret)
1598                         return ret;
1599
1600                 if (pi->caps_stable_p_state)
1601                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1602                                                           PPSMC_MSG_SAMUDPM_SetEnabledMask,
1603                                                           (1 << pi->samu_boot_level));
1604         }
1605
1606         return kv_enable_samu_dpm(adev, !gate);
1607 }
1608
1609 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
1610 {
1611         return 0;
1612 }
1613
1614 static void kv_update_acp_boot_level(struct amdgpu_device *adev)
1615 {
1616         struct kv_power_info *pi = kv_get_pi(adev);
1617         u8 acp_boot_level;
1618
1619         if (!pi->caps_stable_p_state) {
1620                 acp_boot_level = kv_get_acp_boot_level(adev);
1621                 if (acp_boot_level != pi->acp_boot_level) {
1622                         pi->acp_boot_level = acp_boot_level;
1623                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1624                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1625                                                           (1 << pi->acp_boot_level));
1626                 }
1627         }
1628 }
1629
1630 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
1631 {
1632         struct kv_power_info *pi = kv_get_pi(adev);
1633         struct amdgpu_clock_voltage_dependency_table *table =
1634                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1635         int ret;
1636
1637         if (!gate) {
1638                 if (pi->caps_stable_p_state)
1639                         pi->acp_boot_level = table->count - 1;
1640                 else
1641                         pi->acp_boot_level = kv_get_acp_boot_level(adev);
1642
1643                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1644                                            pi->dpm_table_start +
1645                                            offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1646                                            (u8 *)&pi->acp_boot_level,
1647                                            sizeof(u8),
1648                                            pi->sram_end);
1649                 if (ret)
1650                         return ret;
1651
1652                 if (pi->caps_stable_p_state)
1653                         amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1654                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1655                                                           (1 << pi->acp_boot_level));
1656         }
1657
1658         return kv_enable_acp_dpm(adev, !gate);
1659 }
1660
1661 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1662 {
1663         struct kv_power_info *pi = kv_get_pi(adev);
1664         int ret;
1665
1666         pi->uvd_power_gated = gate;
1667
1668         if (gate) {
1669                 /* stop the UVD block */
1670                 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1671                                                         AMD_PG_STATE_GATE);
1672                 kv_update_uvd_dpm(adev, gate);
1673                 if (pi->caps_uvd_pg)
1674                         /* power off the UVD block */
1675                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1676         } else {
1677                 if (pi->caps_uvd_pg)
1678                         /* power on the UVD block */
1679                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1680                         /* re-init the UVD block */
1681                 kv_update_uvd_dpm(adev, gate);
1682
1683                 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1684                                                         AMD_PG_STATE_UNGATE);
1685         }
1686 }
1687
1688 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1689 {
1690         struct kv_power_info *pi = kv_get_pi(adev);
1691
1692         if (pi->vce_power_gated == gate)
1693                 return;
1694
1695         pi->vce_power_gated = gate;
1696
1697         if (!pi->caps_vce_pg)
1698                 return;
1699
1700         if (gate)
1701                 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1702         else
1703                 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1704 }
1705
1706 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
1707 {
1708         struct kv_power_info *pi = kv_get_pi(adev);
1709
1710         if (pi->samu_power_gated == gate)
1711                 return;
1712
1713         pi->samu_power_gated = gate;
1714
1715         if (gate) {
1716                 kv_update_samu_dpm(adev, true);
1717                 if (pi->caps_samu_pg)
1718                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
1719         } else {
1720                 if (pi->caps_samu_pg)
1721                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
1722                 kv_update_samu_dpm(adev, false);
1723         }
1724 }
1725
1726 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
1727 {
1728         struct kv_power_info *pi = kv_get_pi(adev);
1729
1730         if (pi->acp_power_gated == gate)
1731                 return;
1732
1733         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
1734                 return;
1735
1736         pi->acp_power_gated = gate;
1737
1738         if (gate) {
1739                 kv_update_acp_dpm(adev, true);
1740                 if (pi->caps_acp_pg)
1741                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
1742         } else {
1743                 if (pi->caps_acp_pg)
1744                         amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
1745                 kv_update_acp_dpm(adev, false);
1746         }
1747 }
1748
1749 static void kv_set_valid_clock_range(struct amdgpu_device *adev,
1750                                      struct amdgpu_ps *new_rps)
1751 {
1752         struct kv_ps *new_ps = kv_get_ps(new_rps);
1753         struct kv_power_info *pi = kv_get_pi(adev);
1754         u32 i;
1755         struct amdgpu_clock_voltage_dependency_table *table =
1756                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1757
1758         if (table && table->count) {
1759                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1760                         if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1761                             (i == (pi->graphics_dpm_level_count - 1))) {
1762                                 pi->lowest_valid = i;
1763                                 break;
1764                         }
1765                 }
1766
1767                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1768                         if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1769                                 break;
1770                 }
1771                 pi->highest_valid = i;
1772
1773                 if (pi->lowest_valid > pi->highest_valid) {
1774                         if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1775                             (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1776                                 pi->highest_valid = pi->lowest_valid;
1777                         else
1778                                 pi->lowest_valid =  pi->highest_valid;
1779                 }
1780         } else {
1781                 struct sumo_sclk_voltage_mapping_table *table =
1782                         &pi->sys_info.sclk_voltage_mapping_table;
1783
1784                 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1785                         if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1786                             i == (int)(pi->graphics_dpm_level_count - 1)) {
1787                                 pi->lowest_valid = i;
1788                                 break;
1789                         }
1790                 }
1791
1792                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1793                         if (table->entries[i].sclk_frequency <=
1794                             new_ps->levels[new_ps->num_levels - 1].sclk)
1795                                 break;
1796                 }
1797                 pi->highest_valid = i;
1798
1799                 if (pi->lowest_valid > pi->highest_valid) {
1800                         if ((new_ps->levels[0].sclk -
1801                              table->entries[pi->highest_valid].sclk_frequency) >
1802                             (table->entries[pi->lowest_valid].sclk_frequency -
1803                              new_ps->levels[new_ps->num_levels -1].sclk))
1804                                 pi->highest_valid = pi->lowest_valid;
1805                         else
1806                                 pi->lowest_valid =  pi->highest_valid;
1807                 }
1808         }
1809 }
1810
1811 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
1812                                          struct amdgpu_ps *new_rps)
1813 {
1814         struct kv_ps *new_ps = kv_get_ps(new_rps);
1815         struct kv_power_info *pi = kv_get_pi(adev);
1816         int ret = 0;
1817         u8 clk_bypass_cntl;
1818
1819         if (pi->caps_enable_dfs_bypass) {
1820                 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1821                         pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1822                 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1823                                            (pi->dpm_table_start +
1824                                             offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1825                                             (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1826                                             offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1827                                            &clk_bypass_cntl,
1828                                            sizeof(u8), pi->sram_end);
1829         }
1830
1831         return ret;
1832 }
1833
1834 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
1835                             bool enable)
1836 {
1837         struct kv_power_info *pi = kv_get_pi(adev);
1838         int ret = 0;
1839
1840         if (enable) {
1841                 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1842                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
1843                         if (ret == 0)
1844                                 pi->nb_dpm_enabled = true;
1845                 }
1846         } else {
1847                 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1848                         ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
1849                         if (ret == 0)
1850                                 pi->nb_dpm_enabled = false;
1851                 }
1852         }
1853
1854         return ret;
1855 }
1856
1857 static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
1858                                           enum amd_dpm_forced_level level)
1859 {
1860         int ret;
1861
1862         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
1863                 ret = kv_force_dpm_highest(adev);
1864                 if (ret)
1865                         return ret;
1866         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
1867                 ret = kv_force_dpm_lowest(adev);
1868                 if (ret)
1869                         return ret;
1870         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
1871                 ret = kv_unforce_levels(adev);
1872                 if (ret)
1873                         return ret;
1874         }
1875
1876         adev->pm.dpm.forced_level = level;
1877
1878         return 0;
1879 }
1880
1881 static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
1882 {
1883         struct kv_power_info *pi = kv_get_pi(adev);
1884         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1885         struct amdgpu_ps *new_ps = &requested_ps;
1886
1887         kv_update_requested_ps(adev, new_ps);
1888
1889         kv_apply_state_adjust_rules(adev,
1890                                     &pi->requested_rps,
1891                                     &pi->current_rps);
1892
1893         return 0;
1894 }
1895
1896 static int kv_dpm_set_power_state(struct amdgpu_device *adev)
1897 {
1898         struct kv_power_info *pi = kv_get_pi(adev);
1899         struct amdgpu_ps *new_ps = &pi->requested_rps;
1900         struct amdgpu_ps *old_ps = &pi->current_rps;
1901         int ret;
1902
1903         if (pi->bapm_enable) {
1904                 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power);
1905                 if (ret) {
1906                         DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1907                         return ret;
1908                 }
1909         }
1910
1911         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
1912                 if (pi->enable_dpm) {
1913                         kv_set_valid_clock_range(adev, new_ps);
1914                         kv_update_dfs_bypass_settings(adev, new_ps);
1915                         ret = kv_calculate_ds_divider(adev);
1916                         if (ret) {
1917                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1918                                 return ret;
1919                         }
1920                         kv_calculate_nbps_level_settings(adev);
1921                         kv_calculate_dpm_settings(adev);
1922                         kv_force_lowest_valid(adev);
1923                         kv_enable_new_levels(adev);
1924                         kv_upload_dpm_settings(adev);
1925                         kv_program_nbps_index_settings(adev, new_ps);
1926                         kv_unforce_levels(adev);
1927                         kv_set_enabled_levels(adev);
1928                         kv_force_lowest_valid(adev);
1929                         kv_unforce_levels(adev);
1930
1931                         ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1932                         if (ret) {
1933                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1934                                 return ret;
1935                         }
1936                         kv_update_sclk_t(adev);
1937                         if (adev->asic_type == CHIP_MULLINS)
1938                                 kv_enable_nb_dpm(adev, true);
1939                 }
1940         } else {
1941                 if (pi->enable_dpm) {
1942                         kv_set_valid_clock_range(adev, new_ps);
1943                         kv_update_dfs_bypass_settings(adev, new_ps);
1944                         ret = kv_calculate_ds_divider(adev);
1945                         if (ret) {
1946                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1947                                 return ret;
1948                         }
1949                         kv_calculate_nbps_level_settings(adev);
1950                         kv_calculate_dpm_settings(adev);
1951                         kv_freeze_sclk_dpm(adev, true);
1952                         kv_upload_dpm_settings(adev);
1953                         kv_program_nbps_index_settings(adev, new_ps);
1954                         kv_freeze_sclk_dpm(adev, false);
1955                         kv_set_enabled_levels(adev);
1956                         ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1957                         if (ret) {
1958                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1959                                 return ret;
1960                         }
1961                         kv_update_acp_boot_level(adev);
1962                         kv_update_sclk_t(adev);
1963                         kv_enable_nb_dpm(adev, true);
1964                 }
1965         }
1966
1967         return 0;
1968 }
1969
1970 static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)
1971 {
1972         struct kv_power_info *pi = kv_get_pi(adev);
1973         struct amdgpu_ps *new_ps = &pi->requested_rps;
1974
1975         kv_update_current_ps(adev, new_ps);
1976 }
1977
1978 static void kv_dpm_setup_asic(struct amdgpu_device *adev)
1979 {
1980         sumo_take_smu_control(adev, true);
1981         kv_init_powergate_state(adev);
1982         kv_init_sclk_t(adev);
1983 }
1984
1985 #if 0
1986 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
1987 {
1988         struct kv_power_info *pi = kv_get_pi(adev);
1989
1990         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
1991                 kv_force_lowest_valid(adev);
1992                 kv_init_graphics_levels(adev);
1993                 kv_program_bootup_state(adev);
1994                 kv_upload_dpm_settings(adev);
1995                 kv_force_lowest_valid(adev);
1996                 kv_unforce_levels(adev);
1997         } else {
1998                 kv_init_graphics_levels(adev);
1999                 kv_program_bootup_state(adev);
2000                 kv_freeze_sclk_dpm(adev, true);
2001                 kv_upload_dpm_settings(adev);
2002                 kv_freeze_sclk_dpm(adev, false);
2003                 kv_set_enabled_level(adev, pi->graphics_boot_level);
2004         }
2005 }
2006 #endif
2007
2008 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
2009                                                 struct amdgpu_clock_and_voltage_limits *table)
2010 {
2011         struct kv_power_info *pi = kv_get_pi(adev);
2012
2013         if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
2014                 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
2015                 table->sclk =
2016                         pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
2017                 table->vddc =
2018                         kv_convert_2bit_index_to_voltage(adev,
2019                                                          pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
2020         }
2021
2022         table->mclk = pi->sys_info.nbp_memory_clock[0];
2023 }
2024
2025 static void kv_patch_voltage_values(struct amdgpu_device *adev)
2026 {
2027         int i;
2028         struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
2029                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
2030         struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
2031                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2032         struct amdgpu_clock_voltage_dependency_table *samu_table =
2033                 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
2034         struct amdgpu_clock_voltage_dependency_table *acp_table =
2035                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
2036
2037         if (uvd_table->count) {
2038                 for (i = 0; i < uvd_table->count; i++)
2039                         uvd_table->entries[i].v =
2040                                 kv_convert_8bit_index_to_voltage(adev,
2041                                                                  uvd_table->entries[i].v);
2042         }
2043
2044         if (vce_table->count) {
2045                 for (i = 0; i < vce_table->count; i++)
2046                         vce_table->entries[i].v =
2047                                 kv_convert_8bit_index_to_voltage(adev,
2048                                                                  vce_table->entries[i].v);
2049         }
2050
2051         if (samu_table->count) {
2052                 for (i = 0; i < samu_table->count; i++)
2053                         samu_table->entries[i].v =
2054                                 kv_convert_8bit_index_to_voltage(adev,
2055                                                                  samu_table->entries[i].v);
2056         }
2057
2058         if (acp_table->count) {
2059                 for (i = 0; i < acp_table->count; i++)
2060                         acp_table->entries[i].v =
2061                                 kv_convert_8bit_index_to_voltage(adev,
2062                                                                  acp_table->entries[i].v);
2063         }
2064
2065 }
2066
2067 static void kv_construct_boot_state(struct amdgpu_device *adev)
2068 {
2069         struct kv_power_info *pi = kv_get_pi(adev);
2070
2071         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2072         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2073         pi->boot_pl.ds_divider_index = 0;
2074         pi->boot_pl.ss_divider_index = 0;
2075         pi->boot_pl.allow_gnb_slow = 1;
2076         pi->boot_pl.force_nbp_state = 0;
2077         pi->boot_pl.display_wm = 0;
2078         pi->boot_pl.vce_wm = 0;
2079 }
2080
2081 static int kv_force_dpm_highest(struct amdgpu_device *adev)
2082 {
2083         int ret;
2084         u32 enable_mask, i;
2085
2086         ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2087         if (ret)
2088                 return ret;
2089
2090         for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
2091                 if (enable_mask & (1 << i))
2092                         break;
2093         }
2094
2095         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2096                 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2097         else
2098                 return kv_set_enabled_level(adev, i);
2099 }
2100
2101 static int kv_force_dpm_lowest(struct amdgpu_device *adev)
2102 {
2103         int ret;
2104         u32 enable_mask, i;
2105
2106         ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2107         if (ret)
2108                 return ret;
2109
2110         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2111                 if (enable_mask & (1 << i))
2112                         break;
2113         }
2114
2115         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2116                 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2117         else
2118                 return kv_set_enabled_level(adev, i);
2119 }
2120
2121 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2122                                              u32 sclk, u32 min_sclk_in_sr)
2123 {
2124         struct kv_power_info *pi = kv_get_pi(adev);
2125         u32 i;
2126         u32 temp;
2127         u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);
2128
2129         if (sclk < min)
2130                 return 0;
2131
2132         if (!pi->caps_sclk_ds)
2133                 return 0;
2134
2135         for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2136                 temp = sclk >> i;
2137                 if (temp >= min)
2138                         break;
2139         }
2140
2141         return (u8)i;
2142 }
2143
2144 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
2145 {
2146         struct kv_power_info *pi = kv_get_pi(adev);
2147         struct amdgpu_clock_voltage_dependency_table *table =
2148                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2149         int i;
2150
2151         if (table && table->count) {
2152                 for (i = table->count - 1; i >= 0; i--) {
2153                         if (pi->high_voltage_t &&
2154                             (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
2155                              pi->high_voltage_t)) {
2156                                 *limit = i;
2157                                 return 0;
2158                         }
2159                 }
2160         } else {
2161                 struct sumo_sclk_voltage_mapping_table *table =
2162                         &pi->sys_info.sclk_voltage_mapping_table;
2163
2164                 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2165                         if (pi->high_voltage_t &&
2166                             (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
2167                              pi->high_voltage_t)) {
2168                                 *limit = i;
2169                                 return 0;
2170                         }
2171                 }
2172         }
2173
2174         *limit = 0;
2175         return 0;
2176 }
2177
2178 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
2179                                         struct amdgpu_ps *new_rps,
2180                                         struct amdgpu_ps *old_rps)
2181 {
2182         struct kv_ps *ps = kv_get_ps(new_rps);
2183         struct kv_power_info *pi = kv_get_pi(adev);
2184         u32 min_sclk = 10000; /* ??? */
2185         u32 sclk, mclk = 0;
2186         int i, limit;
2187         bool force_high;
2188         struct amdgpu_clock_voltage_dependency_table *table =
2189                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2190         u32 stable_p_state_sclk = 0;
2191         struct amdgpu_clock_and_voltage_limits *max_limits =
2192                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2193
2194         if (new_rps->vce_active) {
2195                 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
2196                 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
2197         } else {
2198                 new_rps->evclk = 0;
2199                 new_rps->ecclk = 0;
2200         }
2201
2202         mclk = max_limits->mclk;
2203         sclk = min_sclk;
2204
2205         if (pi->caps_stable_p_state) {
2206                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2207
2208                 for (i = table->count - 1; i >= 0; i--) {
2209                         if (stable_p_state_sclk >= table->entries[i].clk) {
2210                                 stable_p_state_sclk = table->entries[i].clk;
2211                                 break;
2212                         }
2213                 }
2214
2215                 if (i > 0)
2216                         stable_p_state_sclk = table->entries[0].clk;
2217
2218                 sclk = stable_p_state_sclk;
2219         }
2220
2221         if (new_rps->vce_active) {
2222                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
2223                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
2224         }
2225
2226         ps->need_dfs_bypass = true;
2227
2228         for (i = 0; i < ps->num_levels; i++) {
2229                 if (ps->levels[i].sclk < sclk)
2230                         ps->levels[i].sclk = sclk;
2231         }
2232
2233         if (table && table->count) {
2234                 for (i = 0; i < ps->num_levels; i++) {
2235                         if (pi->high_voltage_t &&
2236                             (pi->high_voltage_t <
2237                              kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2238                                 kv_get_high_voltage_limit(adev, &limit);
2239                                 ps->levels[i].sclk = table->entries[limit].clk;
2240                         }
2241                 }
2242         } else {
2243                 struct sumo_sclk_voltage_mapping_table *table =
2244                         &pi->sys_info.sclk_voltage_mapping_table;
2245
2246                 for (i = 0; i < ps->num_levels; i++) {
2247                         if (pi->high_voltage_t &&
2248                             (pi->high_voltage_t <
2249                              kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2250                                 kv_get_high_voltage_limit(adev, &limit);
2251                                 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2252                         }
2253                 }
2254         }
2255
2256         if (pi->caps_stable_p_state) {
2257                 for (i = 0; i < ps->num_levels; i++) {
2258                         ps->levels[i].sclk = stable_p_state_sclk;
2259                 }
2260         }
2261
2262         pi->video_start = new_rps->dclk || new_rps->vclk ||
2263                 new_rps->evclk || new_rps->ecclk;
2264
2265         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2266             ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2267                 pi->battery_state = true;
2268         else
2269                 pi->battery_state = false;
2270
2271         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2272                 ps->dpm0_pg_nb_ps_lo = 0x1;
2273                 ps->dpm0_pg_nb_ps_hi = 0x0;
2274                 ps->dpmx_nb_ps_lo = 0x1;
2275                 ps->dpmx_nb_ps_hi = 0x0;
2276         } else {
2277                 ps->dpm0_pg_nb_ps_lo = 0x3;
2278                 ps->dpm0_pg_nb_ps_hi = 0x0;
2279                 ps->dpmx_nb_ps_lo = 0x3;
2280                 ps->dpmx_nb_ps_hi = 0x0;
2281
2282                 if (pi->sys_info.nb_dpm_enable) {
2283                         force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2284                                 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
2285                                 pi->disable_nb_ps3_in_battery;
2286                         ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2287                         ps->dpm0_pg_nb_ps_hi = 0x2;
2288                         ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2289                         ps->dpmx_nb_ps_hi = 0x2;
2290                 }
2291         }
2292 }
2293
2294 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
2295                                                     u32 index, bool enable)
2296 {
2297         struct kv_power_info *pi = kv_get_pi(adev);
2298
2299         pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2300 }
2301
2302 static int kv_calculate_ds_divider(struct amdgpu_device *adev)
2303 {
2304         struct kv_power_info *pi = kv_get_pi(adev);
2305         u32 sclk_in_sr = 10000; /* ??? */
2306         u32 i;
2307
2308         if (pi->lowest_valid > pi->highest_valid)
2309                 return -EINVAL;
2310
2311         for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2312                 pi->graphics_level[i].DeepSleepDivId =
2313                         kv_get_sleep_divider_id_from_clock(adev,
2314                                                            be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2315                                                            sclk_in_sr);
2316         }
2317         return 0;
2318 }
2319
2320 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
2321 {
2322         struct kv_power_info *pi = kv_get_pi(adev);
2323         u32 i;
2324         bool force_high;
2325         struct amdgpu_clock_and_voltage_limits *max_limits =
2326                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2327         u32 mclk = max_limits->mclk;
2328
2329         if (pi->lowest_valid > pi->highest_valid)
2330                 return -EINVAL;
2331
2332         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2333                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2334                         pi->graphics_level[i].GnbSlow = 1;
2335                         pi->graphics_level[i].ForceNbPs1 = 0;
2336                         pi->graphics_level[i].UpH = 0;
2337                 }
2338
2339                 if (!pi->sys_info.nb_dpm_enable)
2340                         return 0;
2341
2342                 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2343                               (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2344
2345                 if (force_high) {
2346                         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2347                                 pi->graphics_level[i].GnbSlow = 0;
2348                 } else {
2349                         if (pi->battery_state)
2350                                 pi->graphics_level[0].ForceNbPs1 = 1;
2351
2352                         pi->graphics_level[1].GnbSlow = 0;
2353                         pi->graphics_level[2].GnbSlow = 0;
2354                         pi->graphics_level[3].GnbSlow = 0;
2355                         pi->graphics_level[4].GnbSlow = 0;
2356                 }
2357         } else {
2358                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2359                         pi->graphics_level[i].GnbSlow = 1;
2360                         pi->graphics_level[i].ForceNbPs1 = 0;
2361                         pi->graphics_level[i].UpH = 0;
2362                 }
2363
2364                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2365                         pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2366                         pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2367                         if (pi->lowest_valid != pi->highest_valid)
2368                                 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2369                 }
2370         }
2371         return 0;
2372 }
2373
2374 static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
2375 {
2376         struct kv_power_info *pi = kv_get_pi(adev);
2377         u32 i;
2378
2379         if (pi->lowest_valid > pi->highest_valid)
2380                 return -EINVAL;
2381
2382         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2383                 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2384
2385         return 0;
2386 }
2387
2388 static void kv_init_graphics_levels(struct amdgpu_device *adev)
2389 {
2390         struct kv_power_info *pi = kv_get_pi(adev);
2391         u32 i;
2392         struct amdgpu_clock_voltage_dependency_table *table =
2393                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2394
2395         if (table && table->count) {
2396                 u32 vid_2bit;
2397
2398                 pi->graphics_dpm_level_count = 0;
2399                 for (i = 0; i < table->count; i++) {
2400                         if (pi->high_voltage_t &&
2401                             (pi->high_voltage_t <
2402                              kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
2403                                 break;
2404
2405                         kv_set_divider_value(adev, i, table->entries[i].clk);
2406                         vid_2bit = kv_convert_vid7_to_vid2(adev,
2407                                                            &pi->sys_info.vid_mapping_table,
2408                                                            table->entries[i].v);
2409                         kv_set_vid(adev, i, vid_2bit);
2410                         kv_set_at(adev, i, pi->at[i]);
2411                         kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2412                         pi->graphics_dpm_level_count++;
2413                 }
2414         } else {
2415                 struct sumo_sclk_voltage_mapping_table *table =
2416                         &pi->sys_info.sclk_voltage_mapping_table;
2417
2418                 pi->graphics_dpm_level_count = 0;
2419                 for (i = 0; i < table->num_max_dpm_entries; i++) {
2420                         if (pi->high_voltage_t &&
2421                             pi->high_voltage_t <
2422                             kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
2423                                 break;
2424
2425                         kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
2426                         kv_set_vid(adev, i, table->entries[i].vid_2bit);
2427                         kv_set_at(adev, i, pi->at[i]);
2428                         kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2429                         pi->graphics_dpm_level_count++;
2430                 }
2431         }
2432
2433         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2434                 kv_dpm_power_level_enable(adev, i, false);
2435 }
2436
2437 static void kv_enable_new_levels(struct amdgpu_device *adev)
2438 {
2439         struct kv_power_info *pi = kv_get_pi(adev);
2440         u32 i;
2441
2442         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2443                 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2444                         kv_dpm_power_level_enable(adev, i, true);
2445         }
2446 }
2447
2448 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
2449 {
2450         u32 new_mask = (1 << level);
2451
2452         return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2453                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2454                                                  new_mask);
2455 }
2456
2457 static int kv_set_enabled_levels(struct amdgpu_device *adev)
2458 {
2459         struct kv_power_info *pi = kv_get_pi(adev);
2460         u32 i, new_mask = 0;
2461
2462         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2463                 new_mask |= (1 << i);
2464
2465         return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2466                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2467                                                  new_mask);
2468 }
2469
2470 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
2471                                            struct amdgpu_ps *new_rps)
2472 {
2473         struct kv_ps *new_ps = kv_get_ps(new_rps);
2474         struct kv_power_info *pi = kv_get_pi(adev);
2475         u32 nbdpmconfig1;
2476
2477         if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2478                 return;
2479
2480         if (pi->sys_info.nb_dpm_enable) {
2481                 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2482                 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
2483                                 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
2484                                 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
2485                                 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
2486                 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
2487                                 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
2488                                 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
2489                                 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
2490                 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
2491         }
2492 }
2493
2494 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
2495                                             int min_temp, int max_temp)
2496 {
2497         int low_temp = 0 * 1000;
2498         int high_temp = 255 * 1000;
2499         u32 tmp;
2500
2501         if (low_temp < min_temp)
2502                 low_temp = min_temp;
2503         if (high_temp > max_temp)
2504                 high_temp = max_temp;
2505         if (high_temp < low_temp) {
2506                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2507                 return -EINVAL;
2508         }
2509
2510         tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2511         tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
2512                 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
2513         tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
2514                 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
2515         WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
2516
2517         adev->pm.dpm.thermal.min_temp = low_temp;
2518         adev->pm.dpm.thermal.max_temp = high_temp;
2519
2520         return 0;
2521 }
2522
2523 union igp_info {
2524         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2525         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2526         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2527         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2528         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2529         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2530 };
2531
2532 static int kv_parse_sys_info_table(struct amdgpu_device *adev)
2533 {
2534         struct kv_power_info *pi = kv_get_pi(adev);
2535         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2536         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2537         union igp_info *igp_info;
2538         u8 frev, crev;
2539         u16 data_offset;
2540         int i;
2541
2542         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2543                                    &frev, &crev, &data_offset)) {
2544                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2545                                               data_offset);
2546
2547                 if (crev != 8) {
2548                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2549                         return -EINVAL;
2550                 }
2551                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2552                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2553                 pi->sys_info.bootup_nb_voltage_index =
2554                         le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2555                 if (igp_info->info_8.ucHtcTmpLmt == 0)
2556                         pi->sys_info.htc_tmp_lmt = 203;
2557                 else
2558                         pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2559                 if (igp_info->info_8.ucHtcHystLmt == 0)
2560                         pi->sys_info.htc_hyst_lmt = 5;
2561                 else
2562                         pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2563                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2564                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2565                 }
2566
2567                 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2568                         pi->sys_info.nb_dpm_enable = true;
2569                 else
2570                         pi->sys_info.nb_dpm_enable = false;
2571
2572                 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2573                         pi->sys_info.nbp_memory_clock[i] =
2574                                 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2575                         pi->sys_info.nbp_n_clock[i] =
2576                                 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2577                 }
2578                 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2579                     SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2580                         pi->caps_enable_dfs_bypass = true;
2581
2582                 sumo_construct_sclk_voltage_mapping_table(adev,
2583                                                           &pi->sys_info.sclk_voltage_mapping_table,
2584                                                           igp_info->info_8.sAvail_SCLK);
2585
2586                 sumo_construct_vid_mapping_table(adev,
2587                                                  &pi->sys_info.vid_mapping_table,
2588                                                  igp_info->info_8.sAvail_SCLK);
2589
2590                 kv_construct_max_power_limits_table(adev,
2591                                                     &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2592         }
2593         return 0;
2594 }
2595
2596 union power_info {
2597         struct _ATOM_POWERPLAY_INFO info;
2598         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2599         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2600         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2601         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2602         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2603 };
2604
2605 union pplib_clock_info {
2606         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2607         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2608         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2609         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2610 };
2611
2612 union pplib_power_state {
2613         struct _ATOM_PPLIB_STATE v1;
2614         struct _ATOM_PPLIB_STATE_V2 v2;
2615 };
2616
2617 static void kv_patch_boot_state(struct amdgpu_device *adev,
2618                                 struct kv_ps *ps)
2619 {
2620         struct kv_power_info *pi = kv_get_pi(adev);
2621
2622         ps->num_levels = 1;
2623         ps->levels[0] = pi->boot_pl;
2624 }
2625
2626 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
2627                                           struct amdgpu_ps *rps,
2628                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2629                                           u8 table_rev)
2630 {
2631         struct kv_ps *ps = kv_get_ps(rps);
2632
2633         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2634         rps->class = le16_to_cpu(non_clock_info->usClassification);
2635         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2636
2637         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2638                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2639                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2640         } else {
2641                 rps->vclk = 0;
2642                 rps->dclk = 0;
2643         }
2644
2645         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2646                 adev->pm.dpm.boot_ps = rps;
2647                 kv_patch_boot_state(adev, ps);
2648         }
2649         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2650                 adev->pm.dpm.uvd_ps = rps;
2651 }
2652
2653 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
2654                                       struct amdgpu_ps *rps, int index,
2655                                         union pplib_clock_info *clock_info)
2656 {
2657         struct kv_power_info *pi = kv_get_pi(adev);
2658         struct kv_ps *ps = kv_get_ps(rps);
2659         struct kv_pl *pl = &ps->levels[index];
2660         u32 sclk;
2661
2662         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2663         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2664         pl->sclk = sclk;
2665         pl->vddc_index = clock_info->sumo.vddcIndex;
2666
2667         ps->num_levels = index + 1;
2668
2669         if (pi->caps_sclk_ds) {
2670                 pl->ds_divider_index = 5;
2671                 pl->ss_divider_index = 5;
2672         }
2673 }
2674
2675 static int kv_parse_power_table(struct amdgpu_device *adev)
2676 {
2677         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2678         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2679         union pplib_power_state *power_state;
2680         int i, j, k, non_clock_array_index, clock_array_index;
2681         union pplib_clock_info *clock_info;
2682         struct _StateArray *state_array;
2683         struct _ClockInfoArray *clock_info_array;
2684         struct _NonClockInfoArray *non_clock_info_array;
2685         union power_info *power_info;
2686         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2687         u16 data_offset;
2688         u8 frev, crev;
2689         u8 *power_state_offset;
2690         struct kv_ps *ps;
2691
2692         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2693                                    &frev, &crev, &data_offset))
2694                 return -EINVAL;
2695         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2696
2697         amdgpu_add_thermal_controller(adev);
2698
2699         state_array = (struct _StateArray *)
2700                 (mode_info->atom_context->bios + data_offset +
2701                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2702         clock_info_array = (struct _ClockInfoArray *)
2703                 (mode_info->atom_context->bios + data_offset +
2704                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2705         non_clock_info_array = (struct _NonClockInfoArray *)
2706                 (mode_info->atom_context->bios + data_offset +
2707                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2708
2709         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
2710                                   state_array->ucNumEntries, GFP_KERNEL);
2711         if (!adev->pm.dpm.ps)
2712                 return -ENOMEM;
2713         power_state_offset = (u8 *)state_array->states;
2714         for (i = 0; i < state_array->ucNumEntries; i++) {
2715                 u8 *idx;
2716                 power_state = (union pplib_power_state *)power_state_offset;
2717                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2718                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2719                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2720                 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2721                 if (ps == NULL) {
2722                         kfree(adev->pm.dpm.ps);
2723                         return -ENOMEM;
2724                 }
2725                 adev->pm.dpm.ps[i].ps_priv = ps;
2726                 k = 0;
2727                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2728                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2729                         clock_array_index = idx[j];
2730                         if (clock_array_index >= clock_info_array->ucNumEntries)
2731                                 continue;
2732                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2733                                 break;
2734                         clock_info = (union pplib_clock_info *)
2735                                 ((u8 *)&clock_info_array->clockInfo[0] +
2736                                  (clock_array_index * clock_info_array->ucEntrySize));
2737                         kv_parse_pplib_clock_info(adev,
2738                                                   &adev->pm.dpm.ps[i], k,
2739                                                   clock_info);
2740                         k++;
2741                 }
2742                 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
2743                                               non_clock_info,
2744                                               non_clock_info_array->ucEntrySize);
2745                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2746         }
2747         adev->pm.dpm.num_ps = state_array->ucNumEntries;
2748
2749         /* fill in the vce power states */
2750         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
2751                 u32 sclk;
2752                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
2753                 clock_info = (union pplib_clock_info *)
2754                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2755                 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2756                 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2757                 adev->pm.dpm.vce_states[i].sclk = sclk;
2758                 adev->pm.dpm.vce_states[i].mclk = 0;
2759         }
2760
2761         return 0;
2762 }
2763
2764 static int kv_dpm_init(struct amdgpu_device *adev)
2765 {
2766         struct kv_power_info *pi;
2767         int ret, i;
2768
2769         pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2770         if (pi == NULL)
2771                 return -ENOMEM;
2772         adev->pm.dpm.priv = pi;
2773
2774         ret = amdgpu_get_platform_caps(adev);
2775         if (ret)
2776                 return ret;
2777
2778         ret = amdgpu_parse_extended_power_table(adev);
2779         if (ret)
2780                 return ret;
2781
2782         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2783                 pi->at[i] = TRINITY_AT_DFLT;
2784
2785         pi->sram_end = SMC_RAM_END;
2786
2787         pi->enable_nb_dpm = true;
2788
2789         pi->caps_power_containment = true;
2790         pi->caps_cac = true;
2791         pi->enable_didt = false;
2792         if (pi->enable_didt) {
2793                 pi->caps_sq_ramping = true;
2794                 pi->caps_db_ramping = true;
2795                 pi->caps_td_ramping = true;
2796                 pi->caps_tcp_ramping = true;
2797         }
2798
2799         if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
2800                 pi->caps_sclk_ds = true;
2801         else
2802                 pi->caps_sclk_ds = false;
2803
2804         pi->enable_auto_thermal_throttling = true;
2805         pi->disable_nb_ps3_in_battery = false;
2806         if (amdgpu_bapm == 0)
2807                 pi->bapm_enable = false;
2808         else
2809                 pi->bapm_enable = true;
2810         pi->voltage_drop_t = 0;
2811         pi->caps_sclk_throttle_low_notification = false;
2812         pi->caps_fps = false; /* true? */
2813         pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2814         pi->caps_uvd_dpm = true;
2815         pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2816         pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2817         pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2818         pi->caps_stable_p_state = false;
2819
2820         ret = kv_parse_sys_info_table(adev);
2821         if (ret)
2822                 return ret;
2823
2824         kv_patch_voltage_values(adev);
2825         kv_construct_boot_state(adev);
2826
2827         ret = kv_parse_power_table(adev);
2828         if (ret)
2829                 return ret;
2830
2831         pi->enable_dpm = true;
2832
2833         return 0;
2834 }
2835
2836 static void
2837 kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
2838                                                struct seq_file *m)
2839 {
2840         struct kv_power_info *pi = kv_get_pi(adev);
2841         u32 current_index =
2842                 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2843                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
2844                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
2845         u32 sclk, tmp;
2846         u16 vddc;
2847
2848         if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2849                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2850         } else {
2851                 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2852                 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2853                         SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2854                         SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
2855                 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
2856                 seq_printf(m, "uvd    %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2857                 seq_printf(m, "vce    %sabled\n", pi->vce_power_gated ? "dis" : "en");
2858                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2859                            current_index, sclk, vddc);
2860         }
2861 }
2862
2863 static void
2864 kv_dpm_print_power_state(struct amdgpu_device *adev,
2865                          struct amdgpu_ps *rps)
2866 {
2867         int i;
2868         struct kv_ps *ps = kv_get_ps(rps);
2869
2870         amdgpu_dpm_print_class_info(rps->class, rps->class2);
2871         amdgpu_dpm_print_cap_info(rps->caps);
2872         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2873         for (i = 0; i < ps->num_levels; i++) {
2874                 struct kv_pl *pl = &ps->levels[i];
2875                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
2876                        i, pl->sclk,
2877                        kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
2878         }
2879         amdgpu_dpm_print_ps_status(adev, rps);
2880 }
2881
2882 static void kv_dpm_fini(struct amdgpu_device *adev)
2883 {
2884         int i;
2885
2886         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2887                 kfree(adev->pm.dpm.ps[i].ps_priv);
2888         }
2889         kfree(adev->pm.dpm.ps);
2890         kfree(adev->pm.dpm.priv);
2891         amdgpu_free_extended_power_table(adev);
2892 }
2893
2894 static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev)
2895 {
2896
2897 }
2898
2899 static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
2900 {
2901         struct kv_power_info *pi = kv_get_pi(adev);
2902         struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2903
2904         if (low)
2905                 return requested_state->levels[0].sclk;
2906         else
2907                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2908 }
2909
2910 static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low)
2911 {
2912         struct kv_power_info *pi = kv_get_pi(adev);
2913
2914         return pi->sys_info.bootup_uma_clk;
2915 }
2916
2917 /* get temperature in millidegrees */
2918 static int kv_dpm_get_temp(struct amdgpu_device *adev)
2919 {
2920         u32 temp;
2921         int actual_temp = 0;
2922
2923         temp = RREG32_SMC(0xC0300E0C);
2924
2925         if (temp)
2926                 actual_temp = (temp / 8) - 49;
2927         else
2928                 actual_temp = 0;
2929
2930         actual_temp = actual_temp * 1000;
2931
2932         return actual_temp;
2933 }
2934
2935 static int kv_dpm_early_init(void *handle)
2936 {
2937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2938
2939         kv_dpm_set_dpm_funcs(adev);
2940         kv_dpm_set_irq_funcs(adev);
2941
2942         return 0;
2943 }
2944
2945 static int kv_dpm_late_init(void *handle)
2946 {
2947         /* powerdown unused blocks for now */
2948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2949         int ret;
2950
2951         if (!amdgpu_dpm)
2952                 return 0;
2953
2954         /* init the sysfs and debugfs files late */
2955         ret = amdgpu_pm_sysfs_init(adev);
2956         if (ret)
2957                 return ret;
2958
2959         kv_dpm_powergate_acp(adev, true);
2960         kv_dpm_powergate_samu(adev, true);
2961
2962         return 0;
2963 }
2964
2965 static int kv_dpm_sw_init(void *handle)
2966 {
2967         int ret;
2968         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2969
2970         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
2971                                 &adev->pm.dpm.thermal.irq);
2972         if (ret)
2973                 return ret;
2974
2975         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
2976                                 &adev->pm.dpm.thermal.irq);
2977         if (ret)
2978                 return ret;
2979
2980         /* default to balanced state */
2981         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
2982         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
2983         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
2984         adev->pm.default_sclk = adev->clock.default_sclk;
2985         adev->pm.default_mclk = adev->clock.default_mclk;
2986         adev->pm.current_sclk = adev->clock.default_sclk;
2987         adev->pm.current_mclk = adev->clock.default_mclk;
2988         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
2989
2990         if (amdgpu_dpm == 0)
2991                 return 0;
2992
2993         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
2994         mutex_lock(&adev->pm.mutex);
2995         ret = kv_dpm_init(adev);
2996         if (ret)
2997                 goto dpm_failed;
2998         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
2999         if (amdgpu_dpm == 1)
3000                 amdgpu_pm_print_power_states(adev);
3001         mutex_unlock(&adev->pm.mutex);
3002         DRM_INFO("amdgpu: dpm initialized\n");
3003
3004         return 0;
3005
3006 dpm_failed:
3007         kv_dpm_fini(adev);
3008         mutex_unlock(&adev->pm.mutex);
3009         DRM_ERROR("amdgpu: dpm initialization failed\n");
3010         return ret;
3011 }
3012
3013 static int kv_dpm_sw_fini(void *handle)
3014 {
3015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3016
3017         flush_work(&adev->pm.dpm.thermal.work);
3018
3019         mutex_lock(&adev->pm.mutex);
3020         amdgpu_pm_sysfs_fini(adev);
3021         kv_dpm_fini(adev);
3022         mutex_unlock(&adev->pm.mutex);
3023
3024         return 0;
3025 }
3026
3027 static int kv_dpm_hw_init(void *handle)
3028 {
3029         int ret;
3030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3031
3032         if (!amdgpu_dpm)
3033                 return 0;
3034
3035         mutex_lock(&adev->pm.mutex);
3036         kv_dpm_setup_asic(adev);
3037         ret = kv_dpm_enable(adev);
3038         if (ret)
3039                 adev->pm.dpm_enabled = false;
3040         else
3041                 adev->pm.dpm_enabled = true;
3042         mutex_unlock(&adev->pm.mutex);
3043         amdgpu_pm_compute_clocks(adev);
3044         return ret;
3045 }
3046
3047 static int kv_dpm_hw_fini(void *handle)
3048 {
3049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3050
3051         if (adev->pm.dpm_enabled) {
3052                 mutex_lock(&adev->pm.mutex);
3053                 kv_dpm_disable(adev);
3054                 mutex_unlock(&adev->pm.mutex);
3055         }
3056
3057         return 0;
3058 }
3059
3060 static int kv_dpm_suspend(void *handle)
3061 {
3062         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3063
3064         if (adev->pm.dpm_enabled) {
3065                 mutex_lock(&adev->pm.mutex);
3066                 /* disable dpm */
3067                 kv_dpm_disable(adev);
3068                 /* reset the power state */
3069                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3070                 mutex_unlock(&adev->pm.mutex);
3071         }
3072         return 0;
3073 }
3074
3075 static int kv_dpm_resume(void *handle)
3076 {
3077         int ret;
3078         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3079
3080         if (adev->pm.dpm_enabled) {
3081                 /* asic init will reset to the boot state */
3082                 mutex_lock(&adev->pm.mutex);
3083                 kv_dpm_setup_asic(adev);
3084                 ret = kv_dpm_enable(adev);
3085                 if (ret)
3086                         adev->pm.dpm_enabled = false;
3087                 else
3088                         adev->pm.dpm_enabled = true;
3089                 mutex_unlock(&adev->pm.mutex);
3090                 if (adev->pm.dpm_enabled)
3091                         amdgpu_pm_compute_clocks(adev);
3092         }
3093         return 0;
3094 }
3095
3096 static bool kv_dpm_is_idle(void *handle)
3097 {
3098         return true;
3099 }
3100
3101 static int kv_dpm_wait_for_idle(void *handle)
3102 {
3103         return 0;
3104 }
3105
3106
3107 static int kv_dpm_soft_reset(void *handle)
3108 {
3109         return 0;
3110 }
3111
3112 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
3113                                       struct amdgpu_irq_src *src,
3114                                       unsigned type,
3115                                       enum amdgpu_interrupt_state state)
3116 {
3117         u32 cg_thermal_int;
3118
3119         switch (type) {
3120         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
3121                 switch (state) {
3122                 case AMDGPU_IRQ_STATE_DISABLE:
3123                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3124                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3125                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3126                         break;
3127                 case AMDGPU_IRQ_STATE_ENABLE:
3128                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3129                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3130                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3131                         break;
3132                 default:
3133                         break;
3134                 }
3135                 break;
3136
3137         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
3138                 switch (state) {
3139                 case AMDGPU_IRQ_STATE_DISABLE:
3140                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3141                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3142                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3143                         break;
3144                 case AMDGPU_IRQ_STATE_ENABLE:
3145                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3146                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3147                         WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3148                         break;
3149                 default:
3150                         break;
3151                 }
3152                 break;
3153
3154         default:
3155                 break;
3156         }
3157         return 0;
3158 }
3159
3160 static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
3161                                     struct amdgpu_irq_src *source,
3162                                     struct amdgpu_iv_entry *entry)
3163 {
3164         bool queue_thermal = false;
3165
3166         if (entry == NULL)
3167                 return -EINVAL;
3168
3169         switch (entry->src_id) {
3170         case 230: /* thermal low to high */
3171                 DRM_DEBUG("IH: thermal low to high\n");
3172                 adev->pm.dpm.thermal.high_to_low = false;
3173                 queue_thermal = true;
3174                 break;
3175         case 231: /* thermal high to low */
3176                 DRM_DEBUG("IH: thermal high to low\n");
3177                 adev->pm.dpm.thermal.high_to_low = true;
3178                 queue_thermal = true;
3179                 break;
3180         default:
3181                 break;
3182         }
3183
3184         if (queue_thermal)
3185                 schedule_work(&adev->pm.dpm.thermal.work);
3186
3187         return 0;
3188 }
3189
3190 static int kv_dpm_set_clockgating_state(void *handle,
3191                                           enum amd_clockgating_state state)
3192 {
3193         return 0;
3194 }
3195
3196 static int kv_dpm_set_powergating_state(void *handle,
3197                                           enum amd_powergating_state state)
3198 {
3199         return 0;
3200 }
3201
3202 static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
3203                                                 const struct kv_pl *kv_cpl2)
3204 {
3205         return ((kv_cpl1->sclk == kv_cpl2->sclk) &&
3206                   (kv_cpl1->vddc_index == kv_cpl2->vddc_index) &&
3207                   (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) &&
3208                   (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
3209 }
3210
3211 static int kv_check_state_equal(struct amdgpu_device *adev,
3212                                 struct amdgpu_ps *cps,
3213                                 struct amdgpu_ps *rps,
3214                                 bool *equal)
3215 {
3216         struct kv_ps *kv_cps;
3217         struct kv_ps *kv_rps;
3218         int i;
3219
3220         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
3221                 return -EINVAL;
3222
3223         kv_cps = kv_get_ps(cps);
3224         kv_rps = kv_get_ps(rps);
3225
3226         if (kv_cps == NULL) {
3227                 *equal = false;
3228                 return 0;
3229         }
3230
3231         if (kv_cps->num_levels != kv_rps->num_levels) {
3232                 *equal = false;
3233                 return 0;
3234         }
3235
3236         for (i = 0; i < kv_cps->num_levels; i++) {
3237                 if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
3238                                         &(kv_rps->levels[i]))) {
3239                         *equal = false;
3240                         return 0;
3241                 }
3242         }
3243
3244         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
3245         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
3246         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
3247
3248         return 0;
3249 }
3250
3251 static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx,
3252                               void *value, int *size)
3253 {
3254         struct kv_power_info *pi = kv_get_pi(adev);
3255         uint32_t sclk;
3256         u32 pl_index =
3257                 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
3258                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
3259                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
3260
3261         /* size must be at least 4 bytes for all sensors */
3262         if (*size < 4)
3263                 return -EINVAL;
3264
3265         switch (idx) {
3266         case AMDGPU_PP_SENSOR_GFX_SCLK:
3267                 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
3268                         sclk = be32_to_cpu(
3269                                 pi->graphics_level[pl_index].SclkFrequency);
3270                         *((uint32_t *)value) = sclk;
3271                         *size = 4;
3272                         return 0;
3273                 }
3274                 return -EINVAL;
3275         case AMDGPU_PP_SENSOR_GPU_TEMP:
3276                 *((uint32_t *)value) = kv_dpm_get_temp(adev);
3277                 *size = 4;
3278                 return 0;
3279         default:
3280                 return -EINVAL;
3281         }
3282 }
3283
3284 const struct amd_ip_funcs kv_dpm_ip_funcs = {
3285         .name = "kv_dpm",
3286         .early_init = kv_dpm_early_init,
3287         .late_init = kv_dpm_late_init,
3288         .sw_init = kv_dpm_sw_init,
3289         .sw_fini = kv_dpm_sw_fini,
3290         .hw_init = kv_dpm_hw_init,
3291         .hw_fini = kv_dpm_hw_fini,
3292         .suspend = kv_dpm_suspend,
3293         .resume = kv_dpm_resume,
3294         .is_idle = kv_dpm_is_idle,
3295         .wait_for_idle = kv_dpm_wait_for_idle,
3296         .soft_reset = kv_dpm_soft_reset,
3297         .set_clockgating_state = kv_dpm_set_clockgating_state,
3298         .set_powergating_state = kv_dpm_set_powergating_state,
3299 };
3300
3301 static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
3302         .get_temperature = &kv_dpm_get_temp,
3303         .pre_set_power_state = &kv_dpm_pre_set_power_state,
3304         .set_power_state = &kv_dpm_set_power_state,
3305         .post_set_power_state = &kv_dpm_post_set_power_state,
3306         .display_configuration_changed = &kv_dpm_display_configuration_changed,
3307         .get_sclk = &kv_dpm_get_sclk,
3308         .get_mclk = &kv_dpm_get_mclk,
3309         .print_power_state = &kv_dpm_print_power_state,
3310         .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
3311         .force_performance_level = &kv_dpm_force_performance_level,
3312         .powergate_uvd = &kv_dpm_powergate_uvd,
3313         .enable_bapm = &kv_dpm_enable_bapm,
3314         .get_vce_clock_state = amdgpu_get_vce_clock_state,
3315         .check_state_equal = kv_check_state_equal,
3316         .read_sensor = &kv_dpm_read_sensor,
3317 };
3318
3319 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
3320 {
3321         if (adev->pm.funcs == NULL)
3322                 adev->pm.funcs = &kv_dpm_funcs;
3323 }
3324
3325 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
3326         .set = kv_dpm_set_interrupt_state,
3327         .process = kv_dpm_process_interrupt,
3328 };
3329
3330 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
3331 {
3332         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
3333         adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
3334 }