drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_0.h"
  26
  27 #include "nbio/nbio_7_0_default.h"
  28 #include "nbio/nbio_7_0_offset.h"
  29 #include "nbio/nbio_7_0_sh_mask.h"
  30 #include "vega10_enum.h"
  31
  32 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c
  33
  34 #define smnCPM_CONTROL                                                                                  0x11180460
  35 #define smnPCIE_CNTL2                                                                                   0x11180070
  36
  37 /* vega20 */
  38 #define mmRCC_DEV0_EPF0_STRAP0_VG20                                                                         0x0011
  39 #define mmRCC_DEV0_EPF0_STRAP0_VG20_BASE_IDX                                                                2
  40
  41 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
  42 {
  43         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  44
  45         if (adev->asic_type == CHIP_VEGA20)
  46                 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_VG20);
  47         else
  48                 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  49
  50         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  51         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  52
  53         return tmp;
  54 }
  55
  56 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
  57 {
  58         if (enable)
  59                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  60                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  61         else
  62                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  63 }
  64
  65 static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
  66                                 struct amdgpu_ring *ring)
  67 {
  68         if (!ring || !ring->funcs->emit_wreg)
  69                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
  70         else
  71                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  72                         NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
  73 }
  74
  75 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
  76 {
  77         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  78 }
  79
  80 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  81                                           bool use_doorbell, int doorbell_index)
  82 {
  83         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  84                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  85
  86         u32 doorbell_range = RREG32(reg);
  87         u32 range = 2;
  88
  89         if (adev->asic_type == CHIP_VEGA20)
  90                 range = 8;
  91
  92         if (use_doorbell) {
  93                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
  94                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range);
  95         } else
  96                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
  97
  98         WREG32(reg, doorbell_range);
  99 }
 100
 101 static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
 102                                                bool enable)
 103 {
 104         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 105 }
 106
 107 static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 108                                                         bool enable)
 109 {
 110
 111 }
 112
 113 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
 114                                         bool use_doorbell, int doorbell_index)
 115 {
 116         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 117
 118         if (use_doorbell) {
 119                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 120                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 121         } else
 122                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 123
 124         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 125 }
 126
 127 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
 128 {
 129         uint32_t data;
 130
 131         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 132         data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
 133
 134         return data;
 135 }
 136
 137 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
 138                                        uint32_t data)
 139 {
 140         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 141         WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
 142 }
 143
 144 static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 145                                                        bool enable)
 146 {
 147         uint32_t def, data;
 148
 149         if (adev->asic_type == CHIP_VEGA20)
 150                 return;
 151
 152         /* NBIF_MGCG_CTRL_LCLK */
 153         def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
 154
 155         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 156                 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 157         else
 158                 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 159
 160         if (def != data)
 161                 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
 162
 163         /* SYSHUB_MGCG_CTRL_SOCCLK */
 164         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
 165
 166         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 167                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 168         else
 169                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 170
 171         if (def != data)
 172                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
 173
 174         /* SYSHUB_MGCG_CTRL_SHUBCLK */
 175         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
 176
 177         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 178                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 179         else
 180                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 181
 182         if (def != data)
 183                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
 184 }
 185
 186 static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 187                                                       bool enable)
 188 {
 189         uint32_t def, data;
 190
 191         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 192         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 193                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 194                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 195                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 196         } else {
 197                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 198                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 199                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 200         }
 201
 202         if (def != data)
 203                 WREG32_PCIE(smnPCIE_CNTL2, data);
 204 }
 205
 206 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
 207                                             u32 *flags)
 208 {
 209         int data;
 210
 211         /* AMD_CG_SUPPORT_BIF_MGCG */
 212         data = RREG32_PCIE(smnCPM_CONTROL);
 213         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 214                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 215
 216         /* AMD_CG_SUPPORT_BIF_LS */
 217         data = RREG32_PCIE(smnPCIE_CNTL2);
 218         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 219                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 220 }
 221
 222 static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
 223 {
 224         u32 interrupt_cntl;
 225
 226         /* setup interrupt control */
 227         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 228         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 229         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 230          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 231          */
 232         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 233         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 234         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 235         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 236 }
 237
 238 static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 239 {
 240         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 241 }
 242
 243 static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 244 {
 245         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 246 }
 247
 248 static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
 249 {
 250         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 251 }
 252
 253 static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
 254 {
 255         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 256 }
 257
 258 const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
 259         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 260         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 261         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 262         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 263         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 264         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 265         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 266         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 267         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 268         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 269         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 270         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 271 };
 272
 273 static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
 274 {
 275         if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 276                 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 277 }
 278
 279 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
 280 {
 281
 282 }
 283
 284 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 285         .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
 286         .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
 287         .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
 288         .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
 289         .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
 290         .get_rev_id = nbio_v7_0_get_rev_id,
 291         .mc_access_enable = nbio_v7_0_mc_access_enable,
 292         .hdp_flush = nbio_v7_0_hdp_flush,
 293         .get_memsize = nbio_v7_0_get_memsize,
 294         .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
 295         .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
 296         .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
 297         .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
 298         .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
 299         .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
 300         .get_clockgating_state = nbio_v7_0_get_clockgating_state,
 301         .ih_control = nbio_v7_0_ih_control,
 302         .init_registers = nbio_v7_0_init_registers,
 303         .detect_hw_virt = nbio_v7_0_detect_hw_virt,
 304 };