drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 /*(DEBLOBBED)*/
  53
  54 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  55 {
  56         SDMA0_REGISTER_OFFSET,
  57         SDMA1_REGISTER_OFFSET
  58 };
  59
  60 static const u32 golden_settings_iceland_a11[] =
  61 {
  62         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  63         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  64         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  65         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  66 };
  67
  68 static const u32 iceland_mgcg_cgcg_init[] =
  69 {
  70         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  71         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  72 };
  73
  74 /*
  75  * sDMA - System DMA
  76  * Starting with CIK, the GPU has new asynchronous
  77  * DMA engines.  These engines are used for compute
  78  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  79  * and each one supports 1 ring buffer used for gfx
  80  * and 2 queues used for compute.
  81  *
  82  * The programming model is very similar to the CP
  83  * (ring buffer, IBs, etc.), but sDMA has it's own
  84  * packet format that is different from the PM4 format
  85  * used by the CP. sDMA supports copying data, writing
  86  * embedded data, solid fills, and a number of other
  87  * things.  It also has support for tiling/detiling of
  88  * buffers.
  89  */
  90
  91 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  92 {
  93         switch (adev->asic_type) {
  94         case CHIP_TOPAZ:
  95                 amdgpu_program_register_sequence(adev,
  96                                                  iceland_mgcg_cgcg_init,
  97                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  98                 amdgpu_program_register_sequence(adev,
  99                                                  golden_settings_iceland_a11,
 100                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 101                 break;
 102         default:
 103                 break;
 104         }
 105 }
 106
 107 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 108 {
 109         int i;
 110         for (i = 0; i < adev->sdma.num_instances; i++) {
 111                 release_firmware(adev->sdma.instance[i].fw);
 112                 adev->sdma.instance[i].fw = NULL;
 113         }
 114 }
 115
 116 /**
 117  * sdma_v2_4_init_microcode - load ucode images from disk
 118  *
 119  * @adev: amdgpu_device pointer
 120  *
 121  * Use the firmware interface to load the ucode images into
 122  * the driver (not loaded into hw).
 123  * Returns 0 on success, error on failure.
 124  */
 125 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 126 {
 127         const char *chip_name;
 128         char fw_name[30];
 129         int err = 0, i;
 130         struct amdgpu_firmware_info *info = NULL;
 131         const struct common_firmware_header *header = NULL;
 132         const struct sdma_firmware_header_v1_0 *hdr;
 133
 134         DRM_DEBUG("\n");
 135
 136         switch (adev->asic_type) {
 137         case CHIP_TOPAZ:
 138                 chip_name = "topaz";
 139                 break;
 140         default: BUG();
 141         }
 142
 143         for (i = 0; i < adev->sdma.num_instances; i++) {
 144                 if (i == 0)
 145                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 146                 else
 147                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 148                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 149                 if (err)
 150                         goto out;
 151                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 152                 if (err)
 153                         goto out;
 154                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 155                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 156                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 157                 if (adev->sdma.instance[i].feature_version >= 20)
 158                         adev->sdma.instance[i].burst_nop = true;
 159
 160                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
 161                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 162                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 163                         info->fw = adev->sdma.instance[i].fw;
 164                         header = (const struct common_firmware_header *)info->fw->data;
 165                         adev->firmware.fw_size +=
 166                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 167                 }
 168         }
 169
 170 out:
 171         if (err) {
 172                 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
 173                 for (i = 0; i < adev->sdma.num_instances; i++) {
 174                         release_firmware(adev->sdma.instance[i].fw);
 175                         adev->sdma.instance[i].fw = NULL;
 176                 }
 177         }
 178         return err;
 179 }
 180
 181 /**
 182  * sdma_v2_4_ring_get_rptr - get the current read pointer
 183  *
 184  * @ring: amdgpu ring pointer
 185  *
 186  * Get the current rptr from the hardware (VI+).
 187  */
 188 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 189 {
 190         /* XXX check if swapping is necessary on BE */
 191         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 192 }
 193
 194 /**
 195  * sdma_v2_4_ring_get_wptr - get the current write pointer
 196  *
 197  * @ring: amdgpu ring pointer
 198  *
 199  * Get the current wptr from the hardware (VI+).
 200  */
 201 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 202 {
 203         struct amdgpu_device *adev = ring->adev;
 204         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 205         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 206
 207         return wptr;
 208 }
 209
 210 /**
 211  * sdma_v2_4_ring_set_wptr - commit the write pointer
 212  *
 213  * @ring: amdgpu ring pointer
 214  *
 215  * Write the wptr back to the hardware (VI+).
 216  */
 217 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 218 {
 219         struct amdgpu_device *adev = ring->adev;
 220         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 221
 222         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
 223 }
 224
 225 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 226 {
 227         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 228         int i;
 229
 230         for (i = 0; i < count; i++)
 231                 if (sdma && sdma->burst_nop && (i == 0))
 232                         amdgpu_ring_write(ring, ring->funcs->nop |
 233                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 234                 else
 235                         amdgpu_ring_write(ring, ring->funcs->nop);
 236 }
 237
 238 /**
 239  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 240  *
 241  * @ring: amdgpu ring pointer
 242  * @ib: IB object to schedule
 243  *
 244  * Schedule an IB in the DMA ring (VI).
 245  */
 246 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 247                                    struct amdgpu_ib *ib,
 248                                    unsigned vm_id, bool ctx_switch)
 249 {
 250         u32 vmid = vm_id & 0xf;
 251
 252         /* IB packet must end on a 8 DW boundary */
 253         sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 254
 255         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 256                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 257         /* base must be 32 byte aligned */
 258         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 259         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 260         amdgpu_ring_write(ring, ib->length_dw);
 261         amdgpu_ring_write(ring, 0);
 262         amdgpu_ring_write(ring, 0);
 263
 264 }
 265
 266 /**
 267  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 268  *
 269  * @ring: amdgpu ring pointer
 270  *
 271  * Emit an hdp flush packet on the requested DMA ring.
 272  */
 273 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 274 {
 275         u32 ref_and_mask = 0;
 276
 277         if (ring == &ring->adev->sdma.instance[0].ring)
 278                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 279         else
 280                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 281
 282         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 283                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 284                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 285         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 286         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 287         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 288         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 289         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 290                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 291 }
 292
 293 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 294 {
 295         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 296                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 297         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 298         amdgpu_ring_write(ring, 1);
 299 }
 300 /**
 301  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 302  *
 303  * @ring: amdgpu ring pointer
 304  * @fence: amdgpu fence object
 305  *
 306  * Add a DMA fence packet to the ring to write
 307  * the fence seq number and DMA trap packet to generate
 308  * an interrupt if needed (VI).
 309  */
 310 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 311                                       unsigned flags)
 312 {
 313         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 314         /* write the fence */
 315         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 316         amdgpu_ring_write(ring, lower_32_bits(addr));
 317         amdgpu_ring_write(ring, upper_32_bits(addr));
 318         amdgpu_ring_write(ring, lower_32_bits(seq));
 319
 320         /* optionally write high bits as well */
 321         if (write64bit) {
 322                 addr += 4;
 323                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 324                 amdgpu_ring_write(ring, lower_32_bits(addr));
 325                 amdgpu_ring_write(ring, upper_32_bits(addr));
 326                 amdgpu_ring_write(ring, upper_32_bits(seq));
 327         }
 328
 329         /* generate an interrupt */
 330         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 331         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 332 }
 333
 334 /**
 335  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 336  *
 337  * @adev: amdgpu_device pointer
 338  *
 339  * Stop the gfx async dma ring buffers (VI).
 340  */
 341 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 342 {
 343         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 344         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 345         u32 rb_cntl, ib_cntl;
 346         int i;
 347
 348         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 349             (adev->mman.buffer_funcs_ring == sdma1))
 350                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 351
 352         for (i = 0; i < adev->sdma.num_instances; i++) {
 353                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 354                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 355                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 356                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 357                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 358                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 359         }
 360         sdma0->ready = false;
 361         sdma1->ready = false;
 362 }
 363
 364 /**
 365  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 366  *
 367  * @adev: amdgpu_device pointer
 368  *
 369  * Stop the compute async dma queues (VI).
 370  */
 371 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 372 {
 373         /* XXX todo */
 374 }
 375
 376 /**
 377  * sdma_v2_4_enable - stop the async dma engines
 378  *
 379  * @adev: amdgpu_device pointer
 380  * @enable: enable/disable the DMA MEs.
 381  *
 382  * Halt or unhalt the async dma engines (VI).
 383  */
 384 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 385 {
 386         u32 f32_cntl;
 387         int i;
 388
 389         if (!enable) {
 390                 sdma_v2_4_gfx_stop(adev);
 391                 sdma_v2_4_rlc_stop(adev);
 392         }
 393
 394         for (i = 0; i < adev->sdma.num_instances; i++) {
 395                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 396                 if (enable)
 397                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 398                 else
 399                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 400                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 401         }
 402 }
 403
 404 /**
 405  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 406  *
 407  * @adev: amdgpu_device pointer
 408  *
 409  * Set up the gfx DMA ring buffers and enable them (VI).
 410  * Returns 0 for success, error for failure.
 411  */
 412 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 413 {
 414         struct amdgpu_ring *ring;
 415         u32 rb_cntl, ib_cntl;
 416         u32 rb_bufsz;
 417         u32 wb_offset;
 418         int i, j, r;
 419
 420         for (i = 0; i < adev->sdma.num_instances; i++) {
 421                 ring = &adev->sdma.instance[i].ring;
 422                 wb_offset = (ring->rptr_offs * 4);
 423
 424                 mutex_lock(&adev->srbm_mutex);
 425                 for (j = 0; j < 16; j++) {
 426                         vi_srbm_select(adev, 0, 0, 0, j);
 427                         /* SDMA GFX */
 428                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 429                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 430                 }
 431                 vi_srbm_select(adev, 0, 0, 0, 0);
 432                 mutex_unlock(&adev->srbm_mutex);
 433
 434                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 435                        adev->gfx.config.gb_addr_config & 0x70);
 436
 437                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 438
 439                 /* Set ring buffer size in dwords */
 440                 rb_bufsz = order_base_2(ring->ring_size / 4);
 441                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 442                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 443 #ifdef __BIG_ENDIAN
 444                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 445                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 446                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 447 #endif
 448                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 449
 450                 /* Initialize the ring buffer's read and write pointers */
 451                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 452                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 453                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 454                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 455
 456                 /* set the wb address whether it's enabled or not */
 457                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 458                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 459                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 460                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 461
 462                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 463
 464                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 465                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 466
 467                 ring->wptr = 0;
 468                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 469
 470                 /* enable DMA RB */
 471                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 472                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 473
 474                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 475                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 476 #ifdef __BIG_ENDIAN
 477                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 478 #endif
 479                 /* enable DMA IBs */
 480                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 481
 482                 ring->ready = true;
 483         }
 484
 485         sdma_v2_4_enable(adev, true);
 486         for (i = 0; i < adev->sdma.num_instances; i++) {
 487                 ring = &adev->sdma.instance[i].ring;
 488                 r = amdgpu_ring_test_ring(ring);
 489                 if (r) {
 490                         ring->ready = false;
 491                         return r;
 492                 }
 493
 494                 if (adev->mman.buffer_funcs_ring == ring)
 495                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 496         }
 497
 498         return 0;
 499 }
 500
 501 /**
 502  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 503  *
 504  * @adev: amdgpu_device pointer
 505  *
 506  * Set up the compute DMA queues and enable them (VI).
 507  * Returns 0 for success, error for failure.
 508  */
 509 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 510 {
 511         /* XXX todo */
 512         return 0;
 513 }
 514
 515 /**
 516  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 517  *
 518  * @adev: amdgpu_device pointer
 519  *
 520  * Loads the sDMA0/1 ucode.
 521  * Returns 0 for success, -EINVAL if the ucode is not available.
 522  */
 523 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 524 {
 525         const struct sdma_firmware_header_v1_0 *hdr;
 526         const __le32 *fw_data;
 527         u32 fw_size;
 528         int i, j;
 529
 530         /* halt the MEs */
 531         sdma_v2_4_enable(adev, false);
 532
 533         for (i = 0; i < adev->sdma.num_instances; i++) {
 534                 if (!adev->sdma.instance[i].fw)
 535                         return -EINVAL;
 536                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 537                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 538                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 539                 fw_data = (const __le32 *)
 540                         (adev->sdma.instance[i].fw->data +
 541                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 542                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 543                 for (j = 0; j < fw_size; j++)
 544                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 545                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 546         }
 547
 548         return 0;
 549 }
 550
 551 /**
 552  * sdma_v2_4_start - setup and start the async dma engines
 553  *
 554  * @adev: amdgpu_device pointer
 555  *
 556  * Set up the DMA engines and enable them (VI).
 557  * Returns 0 for success, error for failure.
 558  */
 559 static int sdma_v2_4_start(struct amdgpu_device *adev)
 560 {
 561         int r;
 562
 563         if (!adev->pp_enabled) {
 564                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
 565                         r = sdma_v2_4_load_microcode(adev);
 566                         if (r)
 567                                 return r;
 568                 } else {
 569                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 570                                                         AMDGPU_UCODE_ID_SDMA0);
 571                         if (r)
 572                                 return -EINVAL;
 573                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 574                                                         AMDGPU_UCODE_ID_SDMA1);
 575                         if (r)
 576                                 return -EINVAL;
 577                 }
 578         }
 579
 580         /* halt the engine before programing */
 581         sdma_v2_4_enable(adev, false);
 582
 583         /* start the gfx rings and rlc compute queues */
 584         r = sdma_v2_4_gfx_resume(adev);
 585         if (r)
 586                 return r;
 587         r = sdma_v2_4_rlc_resume(adev);
 588         if (r)
 589                 return r;
 590
 591         return 0;
 592 }
 593
 594 /**
 595  * sdma_v2_4_ring_test_ring - simple async dma engine test
 596  *
 597  * @ring: amdgpu_ring structure holding ring information
 598  *
 599  * Test the DMA engine by writing using it to write an
 600  * value to memory. (VI).
 601  * Returns 0 for success, error for failure.
 602  */
 603 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 604 {
 605         struct amdgpu_device *adev = ring->adev;
 606         unsigned i;
 607         unsigned index;
 608         int r;
 609         u32 tmp;
 610         u64 gpu_addr;
 611
 612         r = amdgpu_wb_get(adev, &index);
 613         if (r) {
 614                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 615                 return r;
 616         }
 617
 618         gpu_addr = adev->wb.gpu_addr + (index * 4);
 619         tmp = 0xCAFEDEAD;
 620         adev->wb.wb[index] = cpu_to_le32(tmp);
 621
 622         r = amdgpu_ring_alloc(ring, 5);
 623         if (r) {
 624                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 625                 amdgpu_wb_free(adev, index);
 626                 return r;
 627         }
 628
 629         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 630                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 631         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 632         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 633         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 634         amdgpu_ring_write(ring, 0xDEADBEEF);
 635         amdgpu_ring_commit(ring);
 636
 637         for (i = 0; i < adev->usec_timeout; i++) {
 638                 tmp = le32_to_cpu(adev->wb.wb[index]);
 639                 if (tmp == 0xDEADBEEF)
 640                         break;
 641                 DRM_UDELAY(1);
 642         }
 643
 644         if (i < adev->usec_timeout) {
 645                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 646         } else {
 647                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 648                           ring->idx, tmp);
 649                 r = -EINVAL;
 650         }
 651         amdgpu_wb_free(adev, index);
 652
 653         return r;
 654 }
 655
 656 /**
 657  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 658  *
 659  * @ring: amdgpu_ring structure holding ring information
 660  *
 661  * Test a simple IB in the DMA ring (VI).
 662  * Returns 0 on success, error on failure.
 663  */
 664 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 665 {
 666         struct amdgpu_device *adev = ring->adev;
 667         struct amdgpu_ib ib;
 668         struct dma_fence *f = NULL;
 669         unsigned index;
 670         u32 tmp = 0;
 671         u64 gpu_addr;
 672         long r;
 673
 674         r = amdgpu_wb_get(adev, &index);
 675         if (r) {
 676                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 677                 return r;
 678         }
 679
 680         gpu_addr = adev->wb.gpu_addr + (index * 4);
 681         tmp = 0xCAFEDEAD;
 682         adev->wb.wb[index] = cpu_to_le32(tmp);
 683         memset(&ib, 0, sizeof(ib));
 684         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 685         if (r) {
 686                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 687                 goto err0;
 688         }
 689
 690         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 691                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 692         ib.ptr[1] = lower_32_bits(gpu_addr);
 693         ib.ptr[2] = upper_32_bits(gpu_addr);
 694         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 695         ib.ptr[4] = 0xDEADBEEF;
 696         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 697         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 698         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 699         ib.length_dw = 8;
 700
 701         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 702         if (r)
 703                 goto err1;
 704
 705         r = dma_fence_wait_timeout(f, false, timeout);
 706         if (r == 0) {
 707                 DRM_ERROR("amdgpu: IB test timed out\n");
 708                 r = -ETIMEDOUT;
 709                 goto err1;
 710         } else if (r < 0) {
 711                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 712                 goto err1;
 713         }
 714         tmp = le32_to_cpu(adev->wb.wb[index]);
 715         if (tmp == 0xDEADBEEF) {
 716                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 717                 r = 0;
 718         } else {
 719                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 720                 r = -EINVAL;
 721         }
 722
 723 err1:
 724         amdgpu_ib_free(adev, &ib, NULL);
 725         dma_fence_put(f);
 726 err0:
 727         amdgpu_wb_free(adev, index);
 728         return r;
 729 }
 730
 731 /**
 732  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 733  *
 734  * @ib: indirect buffer to fill with commands
 735  * @pe: addr of the page entry
 736  * @src: src addr to copy from
 737  * @count: number of page entries to update
 738  *
 739  * Update PTEs by copying them from the GART using sDMA (CIK).
 740  */
 741 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 742                                   uint64_t pe, uint64_t src,
 743                                   unsigned count)
 744 {
 745         unsigned bytes = count * 8;
 746
 747         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 748                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 749         ib->ptr[ib->length_dw++] = bytes;
 750         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 751         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 752         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 753         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 754         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 755 }
 756
 757 /**
 758  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 759  *
 760  * @ib: indirect buffer to fill with commands
 761  * @pe: addr of the page entry
 762  * @value: dst addr to write into pe
 763  * @count: number of page entries to update
 764  * @incr: increase next addr by incr bytes
 765  *
 766  * Update PTEs by writing them manually using sDMA (CIK).
 767  */
 768 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 769                                    uint64_t value, unsigned count,
 770                                    uint32_t incr)
 771 {
 772         unsigned ndw = count * 2;
 773
 774         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 775                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 776         ib->ptr[ib->length_dw++] = pe;
 777         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 778         ib->ptr[ib->length_dw++] = ndw;
 779         for (; ndw > 0; ndw -= 2) {
 780                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 781                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 782                 value += incr;
 783         }
 784 }
 785
 786 /**
 787  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 788  *
 789  * @ib: indirect buffer to fill with commands
 790  * @pe: addr of the page entry
 791  * @addr: dst addr to write into pe
 792  * @count: number of page entries to update
 793  * @incr: increase next addr by incr bytes
 794  * @flags: access flags
 795  *
 796  * Update the page tables using sDMA (CIK).
 797  */
 798 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 799                                      uint64_t addr, unsigned count,
 800                                      uint32_t incr, uint64_t flags)
 801 {
 802         /* for physically contiguous pages (vram) */
 803         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 804         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 805         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 806         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 807         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 808         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 809         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 810         ib->ptr[ib->length_dw++] = incr; /* increment size */
 811         ib->ptr[ib->length_dw++] = 0;
 812         ib->ptr[ib->length_dw++] = count; /* number of entries */
 813 }
 814
 815 /**
 816  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 817  *
 818  * @ib: indirect buffer to fill with padding
 819  *
 820  */
 821 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 822 {
 823         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 824         u32 pad_count;
 825         int i;
 826
 827         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 828         for (i = 0; i < pad_count; i++)
 829                 if (sdma && sdma->burst_nop && (i == 0))
 830                         ib->ptr[ib->length_dw++] =
 831                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 832                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 833                 else
 834                         ib->ptr[ib->length_dw++] =
 835                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 836 }
 837
 838 /**
 839  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 840  *
 841  * @ring: amdgpu_ring pointer
 842  *
 843  * Make sure all previous operations are completed (CIK).
 844  */
 845 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 846 {
 847         uint32_t seq = ring->fence_drv.sync_seq;
 848         uint64_t addr = ring->fence_drv.gpu_addr;
 849
 850         /* wait for idle */
 851         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 852                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 853                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 854                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 855         amdgpu_ring_write(ring, addr & 0xfffffffc);
 856         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 857         amdgpu_ring_write(ring, seq); /* reference */
 858         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 859         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 860                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 861 }
 862
 863 /**
 864  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 865  *
 866  * @ring: amdgpu_ring pointer
 867  * @vm: amdgpu_vm pointer
 868  *
 869  * Update the page table base and flush the VM TLB
 870  * using sDMA (VI).
 871  */
 872 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 873                                          unsigned vm_id, uint64_t pd_addr)
 874 {
 875         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 876                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 877         if (vm_id < 8) {
 878                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 879         } else {
 880                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 881         }
 882         amdgpu_ring_write(ring, pd_addr >> 12);
 883
 884         /* flush TLB */
 885         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 886                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 887         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 888         amdgpu_ring_write(ring, 1 << vm_id);
 889
 890         /* wait for flush */
 891         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 892                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 893                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 894         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 895         amdgpu_ring_write(ring, 0);
 896         amdgpu_ring_write(ring, 0); /* reference */
 897         amdgpu_ring_write(ring, 0); /* mask */
 898         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 899                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 900 }
 901
 902 static int sdma_v2_4_early_init(void *handle)
 903 {
 904         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 905
 906         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 907
 908         sdma_v2_4_set_ring_funcs(adev);
 909         sdma_v2_4_set_buffer_funcs(adev);
 910         sdma_v2_4_set_vm_pte_funcs(adev);
 911         sdma_v2_4_set_irq_funcs(adev);
 912
 913         return 0;
 914 }
 915
 916 static int sdma_v2_4_sw_init(void *handle)
 917 {
 918         struct amdgpu_ring *ring;
 919         int r, i;
 920         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 921
 922         /* SDMA trap event */
 923         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
 924                               &adev->sdma.trap_irq);
 925         if (r)
 926                 return r;
 927
 928         /* SDMA Privileged inst */
 929         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
 930                               &adev->sdma.illegal_inst_irq);
 931         if (r)
 932                 return r;
 933
 934         /* SDMA Privileged inst */
 935         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
 936                               &adev->sdma.illegal_inst_irq);
 937         if (r)
 938                 return r;
 939
 940         r = sdma_v2_4_init_microcode(adev);
 941         if (r) {
 942                 DRM_ERROR("Failed to load sdma firmware!\n");
 943                 return r;
 944         }
 945
 946         for (i = 0; i < adev->sdma.num_instances; i++) {
 947                 ring = &adev->sdma.instance[i].ring;
 948                 ring->ring_obj = NULL;
 949                 ring->use_doorbell = false;
 950                 sprintf(ring->name, "sdma%d", i);
 951                 r = amdgpu_ring_init(adev, ring, 1024,
 952                                      &adev->sdma.trap_irq,
 953                                      (i == 0) ?
 954                                      AMDGPU_SDMA_IRQ_TRAP0 :
 955                                      AMDGPU_SDMA_IRQ_TRAP1);
 956                 if (r)
 957                         return r;
 958         }
 959
 960         return r;
 961 }
 962
 963 static int sdma_v2_4_sw_fini(void *handle)
 964 {
 965         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 966         int i;
 967
 968         for (i = 0; i < adev->sdma.num_instances; i++)
 969                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 970
 971         sdma_v2_4_free_microcode(adev);
 972         return 0;
 973 }
 974
 975 static int sdma_v2_4_hw_init(void *handle)
 976 {
 977         int r;
 978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 979
 980         sdma_v2_4_init_golden_registers(adev);
 981
 982         r = sdma_v2_4_start(adev);
 983         if (r)
 984                 return r;
 985
 986         return r;
 987 }
 988
 989 static int sdma_v2_4_hw_fini(void *handle)
 990 {
 991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 992
 993         sdma_v2_4_enable(adev, false);
 994
 995         return 0;
 996 }
 997
 998 static int sdma_v2_4_suspend(void *handle)
 999 {
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         return sdma_v2_4_hw_fini(adev);
1003 }
1004
1005 static int sdma_v2_4_resume(void *handle)
1006 {
1007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008
1009         return sdma_v2_4_hw_init(adev);
1010 }
1011
1012 static bool sdma_v2_4_is_idle(void *handle)
1013 {
1014         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1015         u32 tmp = RREG32(mmSRBM_STATUS2);
1016
1017         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1018                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1019             return false;
1020
1021         return true;
1022 }
1023
1024 static int sdma_v2_4_wait_for_idle(void *handle)
1025 {
1026         unsigned i;
1027         u32 tmp;
1028         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029
1030         for (i = 0; i < adev->usec_timeout; i++) {
1031                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1032                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1033
1034                 if (!tmp)
1035                         return 0;
1036                 udelay(1);
1037         }
1038         return -ETIMEDOUT;
1039 }
1040
1041 static int sdma_v2_4_soft_reset(void *handle)
1042 {
1043         u32 srbm_soft_reset = 0;
1044         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045         u32 tmp = RREG32(mmSRBM_STATUS2);
1046
1047         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1048                 /* sdma0 */
1049                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1050                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1051                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1052                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1053         }
1054         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1055                 /* sdma1 */
1056                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1057                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1058                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1059                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1060         }
1061
1062         if (srbm_soft_reset) {
1063                 tmp = RREG32(mmSRBM_SOFT_RESET);
1064                 tmp |= srbm_soft_reset;
1065                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1066                 WREG32(mmSRBM_SOFT_RESET, tmp);
1067                 tmp = RREG32(mmSRBM_SOFT_RESET);
1068
1069                 udelay(50);
1070
1071                 tmp &= ~srbm_soft_reset;
1072                 WREG32(mmSRBM_SOFT_RESET, tmp);
1073                 tmp = RREG32(mmSRBM_SOFT_RESET);
1074
1075                 /* Wait a little for things to settle down */
1076                 udelay(50);
1077         }
1078
1079         return 0;
1080 }
1081
1082 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1083                                         struct amdgpu_irq_src *src,
1084                                         unsigned type,
1085                                         enum amdgpu_interrupt_state state)
1086 {
1087         u32 sdma_cntl;
1088
1089         switch (type) {
1090         case AMDGPU_SDMA_IRQ_TRAP0:
1091                 switch (state) {
1092                 case AMDGPU_IRQ_STATE_DISABLE:
1093                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1094                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1095                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1096                         break;
1097                 case AMDGPU_IRQ_STATE_ENABLE:
1098                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1099                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1100                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1101                         break;
1102                 default:
1103                         break;
1104                 }
1105                 break;
1106         case AMDGPU_SDMA_IRQ_TRAP1:
1107                 switch (state) {
1108                 case AMDGPU_IRQ_STATE_DISABLE:
1109                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1110                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1111                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1112                         break;
1113                 case AMDGPU_IRQ_STATE_ENABLE:
1114                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1115                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1116                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1117                         break;
1118                 default:
1119                         break;
1120                 }
1121                 break;
1122         default:
1123                 break;
1124         }
1125         return 0;
1126 }
1127
1128 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1129                                       struct amdgpu_irq_src *source,
1130                                       struct amdgpu_iv_entry *entry)
1131 {
1132         u8 instance_id, queue_id;
1133
1134         instance_id = (entry->ring_id & 0x3) >> 0;
1135         queue_id = (entry->ring_id & 0xc) >> 2;
1136         DRM_DEBUG("IH: SDMA trap\n");
1137         switch (instance_id) {
1138         case 0:
1139                 switch (queue_id) {
1140                 case 0:
1141                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1142                         break;
1143                 case 1:
1144                         /* XXX compute */
1145                         break;
1146                 case 2:
1147                         /* XXX compute */
1148                         break;
1149                 }
1150                 break;
1151         case 1:
1152                 switch (queue_id) {
1153                 case 0:
1154                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1155                         break;
1156                 case 1:
1157                         /* XXX compute */
1158                         break;
1159                 case 2:
1160                         /* XXX compute */
1161                         break;
1162                 }
1163                 break;
1164         }
1165         return 0;
1166 }
1167
1168 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1169                                               struct amdgpu_irq_src *source,
1170                                               struct amdgpu_iv_entry *entry)
1171 {
1172         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1173         schedule_work(&adev->reset_work);
1174         return 0;
1175 }
1176
1177 static int sdma_v2_4_set_clockgating_state(void *handle,
1178                                           enum amd_clockgating_state state)
1179 {
1180         /* XXX handled via the smc on VI */
1181         return 0;
1182 }
1183
1184 static int sdma_v2_4_set_powergating_state(void *handle,
1185                                           enum amd_powergating_state state)
1186 {
1187         return 0;
1188 }
1189
1190 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1191         .name = "sdma_v2_4",
1192         .early_init = sdma_v2_4_early_init,
1193         .late_init = NULL,
1194         .sw_init = sdma_v2_4_sw_init,
1195         .sw_fini = sdma_v2_4_sw_fini,
1196         .hw_init = sdma_v2_4_hw_init,
1197         .hw_fini = sdma_v2_4_hw_fini,
1198         .suspend = sdma_v2_4_suspend,
1199         .resume = sdma_v2_4_resume,
1200         .is_idle = sdma_v2_4_is_idle,
1201         .wait_for_idle = sdma_v2_4_wait_for_idle,
1202         .soft_reset = sdma_v2_4_soft_reset,
1203         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1204         .set_powergating_state = sdma_v2_4_set_powergating_state,
1205 };
1206
1207 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1208         .type = AMDGPU_RING_TYPE_SDMA,
1209         .align_mask = 0xf,
1210         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1211         .support_64bit_ptrs = false,
1212         .get_rptr = sdma_v2_4_ring_get_rptr,
1213         .get_wptr = sdma_v2_4_ring_get_wptr,
1214         .set_wptr = sdma_v2_4_ring_set_wptr,
1215         .emit_frame_size =
1216                 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1217                 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
1218                 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1219                 12 + /* sdma_v2_4_ring_emit_vm_flush */
1220                 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1221         .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1222         .emit_ib = sdma_v2_4_ring_emit_ib,
1223         .emit_fence = sdma_v2_4_ring_emit_fence,
1224         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1225         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1226         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1227         .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1228         .test_ring = sdma_v2_4_ring_test_ring,
1229         .test_ib = sdma_v2_4_ring_test_ib,
1230         .insert_nop = sdma_v2_4_ring_insert_nop,
1231         .pad_ib = sdma_v2_4_ring_pad_ib,
1232 };
1233
1234 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1235 {
1236         int i;
1237
1238         for (i = 0; i < adev->sdma.num_instances; i++)
1239                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1240 }
1241
1242 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1243         .set = sdma_v2_4_set_trap_irq_state,
1244         .process = sdma_v2_4_process_trap_irq,
1245 };
1246
1247 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1248         .process = sdma_v2_4_process_illegal_inst_irq,
1249 };
1250
1251 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1252 {
1253         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1254         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1255         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1256 }
1257
1258 /**
1259  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1260  *
1261  * @ring: amdgpu_ring structure holding ring information
1262  * @src_offset: src GPU address
1263  * @dst_offset: dst GPU address
1264  * @byte_count: number of bytes to xfer
1265  *
1266  * Copy GPU buffers using the DMA engine (VI).
1267  * Used by the amdgpu ttm implementation to move pages if
1268  * registered as the asic copy callback.
1269  */
1270 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1271                                        uint64_t src_offset,
1272                                        uint64_t dst_offset,
1273                                        uint32_t byte_count)
1274 {
1275         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1276                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1277         ib->ptr[ib->length_dw++] = byte_count;
1278         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1279         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1280         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1281         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1282         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1283 }
1284
1285 /**
1286  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1287  *
1288  * @ring: amdgpu_ring structure holding ring information
1289  * @src_data: value to write to buffer
1290  * @dst_offset: dst GPU address
1291  * @byte_count: number of bytes to xfer
1292  *
1293  * Fill GPU buffers using the DMA engine (VI).
1294  */
1295 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1296                                        uint32_t src_data,
1297                                        uint64_t dst_offset,
1298                                        uint32_t byte_count)
1299 {
1300         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1301         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1302         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1303         ib->ptr[ib->length_dw++] = src_data;
1304         ib->ptr[ib->length_dw++] = byte_count;
1305 }
1306
1307 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1308         .copy_max_bytes = 0x1fffff,
1309         .copy_num_dw = 7,
1310         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1311
1312         .fill_max_bytes = 0x1fffff,
1313         .fill_num_dw = 7,
1314         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1315 };
1316
1317 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1318 {
1319         if (adev->mman.buffer_funcs == NULL) {
1320                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1321                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1322         }
1323 }
1324
1325 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1326         .copy_pte = sdma_v2_4_vm_copy_pte,
1327         .write_pte = sdma_v2_4_vm_write_pte,
1328         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1329 };
1330
1331 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1332 {
1333         unsigned i;
1334
1335         if (adev->vm_manager.vm_pte_funcs == NULL) {
1336                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1337                 for (i = 0; i < adev->sdma.num_instances; i++)
1338                         adev->vm_manager.vm_pte_rings[i] =
1339                                 &adev->sdma.instance[i].ring;
1340
1341                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1342         }
1343 }
1344
1345 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1346 {
1347         .type = AMD_IP_BLOCK_TYPE_SDMA,
1348         .major = 2,
1349         .minor = 4,
1350         .rev = 0,
1351         .funcs = &sdma_v2_4_ip_funcs,
1352 };