drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 /*(DEBLOBBED)*/
  53
  54 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  55 {
  56         SDMA0_REGISTER_OFFSET,
  57         SDMA1_REGISTER_OFFSET
  58 };
  59
  60 static const u32 golden_settings_iceland_a11[] =
  61 {
  62         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  63         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  64         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  65         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  66 };
  67
  68 static const u32 iceland_mgcg_cgcg_init[] =
  69 {
  70         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  71         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  72 };
  73
  74 /*
  75  * sDMA - System DMA
  76  * Starting with CIK, the GPU has new asynchronous
  77  * DMA engines.  These engines are used for compute
  78  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  79  * and each one supports 1 ring buffer used for gfx
  80  * and 2 queues used for compute.
  81  *
  82  * The programming model is very similar to the CP
  83  * (ring buffer, IBs, etc.), but sDMA has it's own
  84  * packet format that is different from the PM4 format
  85  * used by the CP. sDMA supports copying data, writing
  86  * embedded data, solid fills, and a number of other
  87  * things.  It also has support for tiling/detiling of
  88  * buffers.
  89  */
  90
  91 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  92 {
  93         switch (adev->asic_type) {
  94         case CHIP_TOPAZ:
  95                 amdgpu_program_register_sequence(adev,
  96                                                  iceland_mgcg_cgcg_init,
  97                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  98                 amdgpu_program_register_sequence(adev,
  99                                                  golden_settings_iceland_a11,
 100                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 101                 break;
 102         default:
 103                 break;
 104         }
 105 }
 106
 107 /**
 108  * sdma_v2_4_init_microcode - load ucode images from disk
 109  *
 110  * @adev: amdgpu_device pointer
 111  *
 112  * Use the firmware interface to load the ucode images into
 113  * the driver (not loaded into hw).
 114  * Returns 0 on success, error on failure.
 115  */
 116 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 117 {
 118         const char *chip_name;
 119         char fw_name[30];
 120         int err = 0, i;
 121         struct amdgpu_firmware_info *info = NULL;
 122         const struct common_firmware_header *header = NULL;
 123         const struct sdma_firmware_header_v1_0 *hdr;
 124
 125         DRM_DEBUG("\n");
 126
 127         switch (adev->asic_type) {
 128         case CHIP_TOPAZ:
 129                 chip_name = "topaz";
 130                 break;
 131         default: BUG();
 132         }
 133
 134         for (i = 0; i < adev->sdma.num_instances; i++) {
 135                 if (i == 0)
 136                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 137                 else
 138                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 139                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 140                 if (err)
 141                         goto out;
 142                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 143                 if (err)
 144                         goto out;
 145                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 146                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 147                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 148                 if (adev->sdma.instance[i].feature_version >= 20)
 149                         adev->sdma.instance[i].burst_nop = true;
 150
 151                 if (adev->firmware.smu_load) {
 152                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 153                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 154                         info->fw = adev->sdma.instance[i].fw;
 155                         header = (const struct common_firmware_header *)info->fw->data;
 156                         adev->firmware.fw_size +=
 157                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 158                 }
 159         }
 160
 161 out:
 162         if (err) {
 163                 printk(KERN_ERR
 164                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 165                        fw_name);
 166                 for (i = 0; i < adev->sdma.num_instances; i++) {
 167                         release_firmware(adev->sdma.instance[i].fw);
 168                         adev->sdma.instance[i].fw = NULL;
 169                 }
 170         }
 171         return err;
 172 }
 173
 174 /**
 175  * sdma_v2_4_ring_get_rptr - get the current read pointer
 176  *
 177  * @ring: amdgpu ring pointer
 178  *
 179  * Get the current rptr from the hardware (VI+).
 180  */
 181 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 182 {
 183         u32 rptr;
 184
 185         /* XXX check if swapping is necessary on BE */
 186         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 187
 188         return rptr;
 189 }
 190
 191 /**
 192  * sdma_v2_4_ring_get_wptr - get the current write pointer
 193  *
 194  * @ring: amdgpu ring pointer
 195  *
 196  * Get the current wptr from the hardware (VI+).
 197  */
 198 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 199 {
 200         struct amdgpu_device *adev = ring->adev;
 201         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 202         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 203
 204         return wptr;
 205 }
 206
 207 /**
 208  * sdma_v2_4_ring_set_wptr - commit the write pointer
 209  *
 210  * @ring: amdgpu ring pointer
 211  *
 212  * Write the wptr back to the hardware (VI+).
 213  */
 214 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 215 {
 216         struct amdgpu_device *adev = ring->adev;
 217         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 218
 219         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 220 }
 221
 222 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 223 {
 224         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 225         int i;
 226
 227         for (i = 0; i < count; i++)
 228                 if (sdma && sdma->burst_nop && (i == 0))
 229                         amdgpu_ring_write(ring, ring->nop |
 230                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 231                 else
 232                         amdgpu_ring_write(ring, ring->nop);
 233 }
 234
 235 /**
 236  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 237  *
 238  * @ring: amdgpu ring pointer
 239  * @ib: IB object to schedule
 240  *
 241  * Schedule an IB in the DMA ring (VI).
 242  */
 243 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 244                                    struct amdgpu_ib *ib)
 245 {
 246         u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 247         u32 next_rptr = ring->wptr + 5;
 248
 249         while ((next_rptr & 7) != 2)
 250                 next_rptr++;
 251
 252         next_rptr += 6;
 253
 254         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 255                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 256         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 257         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 258         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 259         amdgpu_ring_write(ring, next_rptr);
 260
 261         /* IB packet must end on a 8 DW boundary */
 262         sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 263
 264         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 265                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 266         /* base must be 32 byte aligned */
 267         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 268         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 269         amdgpu_ring_write(ring, ib->length_dw);
 270         amdgpu_ring_write(ring, 0);
 271         amdgpu_ring_write(ring, 0);
 272
 273 }
 274
 275 /**
 276  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 277  *
 278  * @ring: amdgpu ring pointer
 279  *
 280  * Emit an hdp flush packet on the requested DMA ring.
 281  */
 282 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 283 {
 284         u32 ref_and_mask = 0;
 285
 286         if (ring == &ring->adev->sdma.instance[0].ring)
 287                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 288         else
 289                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 290
 291         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 292                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 293                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 294         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 295         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 296         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 297         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 298         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 299                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 300 }
 301
 302 /**
 303  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 304  *
 305  * @ring: amdgpu ring pointer
 306  * @fence: amdgpu fence object
 307  *
 308  * Add a DMA fence packet to the ring to write
 309  * the fence seq number and DMA trap packet to generate
 310  * an interrupt if needed (VI).
 311  */
 312 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 313                                       unsigned flags)
 314 {
 315         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 316         /* write the fence */
 317         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 318         amdgpu_ring_write(ring, lower_32_bits(addr));
 319         amdgpu_ring_write(ring, upper_32_bits(addr));
 320         amdgpu_ring_write(ring, lower_32_bits(seq));
 321
 322         /* optionally write high bits as well */
 323         if (write64bit) {
 324                 addr += 4;
 325                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 326                 amdgpu_ring_write(ring, lower_32_bits(addr));
 327                 amdgpu_ring_write(ring, upper_32_bits(addr));
 328                 amdgpu_ring_write(ring, upper_32_bits(seq));
 329         }
 330
 331         /* generate an interrupt */
 332         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 333         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 334 }
 335
 336 /**
 337  * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
 338  *
 339  * @ring: amdgpu_ring structure holding ring information
 340  * @semaphore: amdgpu semaphore object
 341  * @emit_wait: wait or signal semaphore
 342  *
 343  * Add a DMA semaphore packet to the ring wait on or signal
 344  * other rings (VI).
 345  */
 346 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
 347                                           struct amdgpu_semaphore *semaphore,
 348                                           bool emit_wait)
 349 {
 350         u64 addr = semaphore->gpu_addr;
 351         u32 sig = emit_wait ? 0 : 1;
 352
 353         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
 354                           SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
 355         amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
 356         amdgpu_ring_write(ring, upper_32_bits(addr));
 357
 358         return true;
 359 }
 360
 361 /**
 362  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 363  *
 364  * @adev: amdgpu_device pointer
 365  *
 366  * Stop the gfx async dma ring buffers (VI).
 367  */
 368 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 369 {
 370         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 371         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 372         u32 rb_cntl, ib_cntl;
 373         int i;
 374
 375         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 376             (adev->mman.buffer_funcs_ring == sdma1))
 377                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 378
 379         for (i = 0; i < adev->sdma.num_instances; i++) {
 380                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 381                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 382                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 383                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 384                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 385                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 386         }
 387         sdma0->ready = false;
 388         sdma1->ready = false;
 389 }
 390
 391 /**
 392  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 393  *
 394  * @adev: amdgpu_device pointer
 395  *
 396  * Stop the compute async dma queues (VI).
 397  */
 398 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 399 {
 400         /* XXX todo */
 401 }
 402
 403 /**
 404  * sdma_v2_4_enable - stop the async dma engines
 405  *
 406  * @adev: amdgpu_device pointer
 407  * @enable: enable/disable the DMA MEs.
 408  *
 409  * Halt or unhalt the async dma engines (VI).
 410  */
 411 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 412 {
 413         u32 f32_cntl;
 414         int i;
 415
 416         if (enable == false) {
 417                 sdma_v2_4_gfx_stop(adev);
 418                 sdma_v2_4_rlc_stop(adev);
 419         }
 420
 421         for (i = 0; i < adev->sdma.num_instances; i++) {
 422                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 423                 if (enable)
 424                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 425                 else
 426                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 427                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 428         }
 429 }
 430
 431 /**
 432  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 433  *
 434  * @adev: amdgpu_device pointer
 435  *
 436  * Set up the gfx DMA ring buffers and enable them (VI).
 437  * Returns 0 for success, error for failure.
 438  */
 439 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 440 {
 441         struct amdgpu_ring *ring;
 442         u32 rb_cntl, ib_cntl;
 443         u32 rb_bufsz;
 444         u32 wb_offset;
 445         int i, j, r;
 446
 447         for (i = 0; i < adev->sdma.num_instances; i++) {
 448                 ring = &adev->sdma.instance[i].ring;
 449                 wb_offset = (ring->rptr_offs * 4);
 450
 451                 mutex_lock(&adev->srbm_mutex);
 452                 for (j = 0; j < 16; j++) {
 453                         vi_srbm_select(adev, 0, 0, 0, j);
 454                         /* SDMA GFX */
 455                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 456                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 457                 }
 458                 vi_srbm_select(adev, 0, 0, 0, 0);
 459                 mutex_unlock(&adev->srbm_mutex);
 460
 461                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 462
 463                 /* Set ring buffer size in dwords */
 464                 rb_bufsz = order_base_2(ring->ring_size / 4);
 465                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 466                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 467 #ifdef __BIG_ENDIAN
 468                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 469                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 470                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 471 #endif
 472                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 473
 474                 /* Initialize the ring buffer's read and write pointers */
 475                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 476                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 477
 478                 /* set the wb address whether it's enabled or not */
 479                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 480                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 481                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 482                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 483
 484                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 485
 486                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 487                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 488
 489                 ring->wptr = 0;
 490                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 491
 492                 /* enable DMA RB */
 493                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 494                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 495
 496                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 497                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 498 #ifdef __BIG_ENDIAN
 499                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 500 #endif
 501                 /* enable DMA IBs */
 502                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 503
 504                 ring->ready = true;
 505
 506                 r = amdgpu_ring_test_ring(ring);
 507                 if (r) {
 508                         ring->ready = false;
 509                         return r;
 510                 }
 511
 512                 if (adev->mman.buffer_funcs_ring == ring)
 513                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 514         }
 515
 516         return 0;
 517 }
 518
 519 /**
 520  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 521  *
 522  * @adev: amdgpu_device pointer
 523  *
 524  * Set up the compute DMA queues and enable them (VI).
 525  * Returns 0 for success, error for failure.
 526  */
 527 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 528 {
 529         /* XXX todo */
 530         return 0;
 531 }
 532
 533 /**
 534  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 535  *
 536  * @adev: amdgpu_device pointer
 537  *
 538  * Loads the sDMA0/1 ucode.
 539  * Returns 0 for success, -EINVAL if the ucode is not available.
 540  */
 541 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 542 {
 543         const struct sdma_firmware_header_v1_0 *hdr;
 544         const __le32 *fw_data;
 545         u32 fw_size;
 546         int i, j;
 547
 548         /* halt the MEs */
 549         sdma_v2_4_enable(adev, false);
 550
 551         for (i = 0; i < adev->sdma.num_instances; i++) {
 552                 if (!adev->sdma.instance[i].fw)
 553                         return -EINVAL;
 554                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 555                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 556                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 557                 fw_data = (const __le32 *)
 558                         (adev->sdma.instance[i].fw->data +
 559                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 560                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 561                 for (j = 0; j < fw_size; j++)
 562                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 563                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 564         }
 565
 566         return 0;
 567 }
 568
 569 /**
 570  * sdma_v2_4_start - setup and start the async dma engines
 571  *
 572  * @adev: amdgpu_device pointer
 573  *
 574  * Set up the DMA engines and enable them (VI).
 575  * Returns 0 for success, error for failure.
 576  */
 577 static int sdma_v2_4_start(struct amdgpu_device *adev)
 578 {
 579         int r;
 580
 581         if (!adev->firmware.smu_load) {
 582                 r = sdma_v2_4_load_microcode(adev);
 583                 if (r)
 584                         return r;
 585         } else {
 586                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 587                                                 AMDGPU_UCODE_ID_SDMA0);
 588                 if (r)
 589                         return -EINVAL;
 590                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 591                                                 AMDGPU_UCODE_ID_SDMA1);
 592                 if (r)
 593                         return -EINVAL;
 594         }
 595
 596         /* unhalt the MEs */
 597         sdma_v2_4_enable(adev, true);
 598
 599         /* start the gfx rings and rlc compute queues */
 600         r = sdma_v2_4_gfx_resume(adev);
 601         if (r)
 602                 return r;
 603         r = sdma_v2_4_rlc_resume(adev);
 604         if (r)
 605                 return r;
 606
 607         return 0;
 608 }
 609
 610 /**
 611  * sdma_v2_4_ring_test_ring - simple async dma engine test
 612  *
 613  * @ring: amdgpu_ring structure holding ring information
 614  *
 615  * Test the DMA engine by writing using it to write an
 616  * value to memory. (VI).
 617  * Returns 0 for success, error for failure.
 618  */
 619 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 620 {
 621         struct amdgpu_device *adev = ring->adev;
 622         unsigned i;
 623         unsigned index;
 624         int r;
 625         u32 tmp;
 626         u64 gpu_addr;
 627
 628         r = amdgpu_wb_get(adev, &index);
 629         if (r) {
 630                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 631                 return r;
 632         }
 633
 634         gpu_addr = adev->wb.gpu_addr + (index * 4);
 635         tmp = 0xCAFEDEAD;
 636         adev->wb.wb[index] = cpu_to_le32(tmp);
 637
 638         r = amdgpu_ring_lock(ring, 5);
 639         if (r) {
 640                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 641                 amdgpu_wb_free(adev, index);
 642                 return r;
 643         }
 644
 645         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 646                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 647         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 648         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 649         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 650         amdgpu_ring_write(ring, 0xDEADBEEF);
 651         amdgpu_ring_unlock_commit(ring);
 652
 653         for (i = 0; i < adev->usec_timeout; i++) {
 654                 tmp = le32_to_cpu(adev->wb.wb[index]);
 655                 if (tmp == 0xDEADBEEF)
 656                         break;
 657                 DRM_UDELAY(1);
 658         }
 659
 660         if (i < adev->usec_timeout) {
 661                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 662         } else {
 663                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 664                           ring->idx, tmp);
 665                 r = -EINVAL;
 666         }
 667         amdgpu_wb_free(adev, index);
 668
 669         return r;
 670 }
 671
 672 /**
 673  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 674  *
 675  * @ring: amdgpu_ring structure holding ring information
 676  *
 677  * Test a simple IB in the DMA ring (VI).
 678  * Returns 0 on success, error on failure.
 679  */
 680 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
 681 {
 682         struct amdgpu_device *adev = ring->adev;
 683         struct amdgpu_ib ib;
 684         struct fence *f = NULL;
 685         unsigned i;
 686         unsigned index;
 687         int r;
 688         u32 tmp = 0;
 689         u64 gpu_addr;
 690
 691         r = amdgpu_wb_get(adev, &index);
 692         if (r) {
 693                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 694                 return r;
 695         }
 696
 697         gpu_addr = adev->wb.gpu_addr + (index * 4);
 698         tmp = 0xCAFEDEAD;
 699         adev->wb.wb[index] = cpu_to_le32(tmp);
 700         memset(&ib, 0, sizeof(ib));
 701         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 702         if (r) {
 703                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 704                 goto err0;
 705         }
 706
 707         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 708                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 709         ib.ptr[1] = lower_32_bits(gpu_addr);
 710         ib.ptr[2] = upper_32_bits(gpu_addr);
 711         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 712         ib.ptr[4] = 0xDEADBEEF;
 713         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 714         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 715         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 716         ib.length_dw = 8;
 717
 718         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 719                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 720                                                  &f);
 721         if (r)
 722                 goto err1;
 723
 724         r = fence_wait(f, false);
 725         if (r) {
 726                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 727                 goto err1;
 728         }
 729         for (i = 0; i < adev->usec_timeout; i++) {
 730                 tmp = le32_to_cpu(adev->wb.wb[index]);
 731                 if (tmp == 0xDEADBEEF)
 732                         break;
 733                 DRM_UDELAY(1);
 734         }
 735         if (i < adev->usec_timeout) {
 736                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 737                          ring->idx, i);
 738                 goto err1;
 739         } else {
 740                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 741                 r = -EINVAL;
 742         }
 743
 744 err1:
 745         fence_put(f);
 746         amdgpu_ib_free(adev, &ib);
 747 err0:
 748         amdgpu_wb_free(adev, index);
 749         return r;
 750 }
 751
 752 /**
 753  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 754  *
 755  * @ib: indirect buffer to fill with commands
 756  * @pe: addr of the page entry
 757  * @src: src addr to copy from
 758  * @count: number of page entries to update
 759  *
 760  * Update PTEs by copying them from the GART using sDMA (CIK).
 761  */
 762 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 763                                   uint64_t pe, uint64_t src,
 764                                   unsigned count)
 765 {
 766         while (count) {
 767                 unsigned bytes = count * 8;
 768                 if (bytes > 0x1FFFF8)
 769                         bytes = 0x1FFFF8;
 770
 771                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 772                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 773                 ib->ptr[ib->length_dw++] = bytes;
 774                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 775                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 776                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 777                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 778                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 779
 780                 pe += bytes;
 781                 src += bytes;
 782                 count -= bytes / 8;
 783         }
 784 }
 785
 786 /**
 787  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 788  *
 789  * @ib: indirect buffer to fill with commands
 790  * @pe: addr of the page entry
 791  * @addr: dst addr to write into pe
 792  * @count: number of page entries to update
 793  * @incr: increase next addr by incr bytes
 794  * @flags: access flags
 795  *
 796  * Update PTEs by writing them manually using sDMA (CIK).
 797  */
 798 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
 799                                    uint64_t pe,
 800                                    uint64_t addr, unsigned count,
 801                                    uint32_t incr, uint32_t flags)
 802 {
 803         uint64_t value;
 804         unsigned ndw;
 805
 806         while (count) {
 807                 ndw = count * 2;
 808                 if (ndw > 0xFFFFE)
 809                         ndw = 0xFFFFE;
 810
 811                 /* for non-physically contiguous pages (system) */
 812                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 813                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 814                 ib->ptr[ib->length_dw++] = pe;
 815                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 816                 ib->ptr[ib->length_dw++] = ndw;
 817                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 818                         if (flags & AMDGPU_PTE_SYSTEM) {
 819                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 820                                 value &= 0xFFFFFFFFFFFFF000ULL;
 821                         } else if (flags & AMDGPU_PTE_VALID) {
 822                                 value = addr;
 823                         } else {
 824                                 value = 0;
 825                         }
 826                         addr += incr;
 827                         value |= flags;
 828                         ib->ptr[ib->length_dw++] = value;
 829                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 830                 }
 831         }
 832 }
 833
 834 /**
 835  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 836  *
 837  * @ib: indirect buffer to fill with commands
 838  * @pe: addr of the page entry
 839  * @addr: dst addr to write into pe
 840  * @count: number of page entries to update
 841  * @incr: increase next addr by incr bytes
 842  * @flags: access flags
 843  *
 844  * Update the page tables using sDMA (CIK).
 845  */
 846 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
 847                                      uint64_t pe,
 848                                      uint64_t addr, unsigned count,
 849                                      uint32_t incr, uint32_t flags)
 850 {
 851         uint64_t value;
 852         unsigned ndw;
 853
 854         while (count) {
 855                 ndw = count;
 856                 if (ndw > 0x7FFFF)
 857                         ndw = 0x7FFFF;
 858
 859                 if (flags & AMDGPU_PTE_VALID)
 860                         value = addr;
 861                 else
 862                         value = 0;
 863
 864                 /* for physically contiguous pages (vram) */
 865                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 866                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 867                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 868                 ib->ptr[ib->length_dw++] = flags; /* mask */
 869                 ib->ptr[ib->length_dw++] = 0;
 870                 ib->ptr[ib->length_dw++] = value; /* value */
 871                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 872                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 873                 ib->ptr[ib->length_dw++] = 0;
 874                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 875
 876                 pe += ndw * 8;
 877                 addr += ndw * incr;
 878                 count -= ndw;
 879         }
 880 }
 881
 882 /**
 883  * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
 884  *
 885  * @ib: indirect buffer to fill with padding
 886  *
 887  */
 888 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
 889 {
 890         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
 891         u32 pad_count;
 892         int i;
 893
 894         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 895         for (i = 0; i < pad_count; i++)
 896                 if (sdma && sdma->burst_nop && (i == 0))
 897                         ib->ptr[ib->length_dw++] =
 898                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 899                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 900                 else
 901                         ib->ptr[ib->length_dw++] =
 902                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 903 }
 904
 905 /**
 906  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 907  *
 908  * @ring: amdgpu_ring pointer
 909  * @vm: amdgpu_vm pointer
 910  *
 911  * Update the page table base and flush the VM TLB
 912  * using sDMA (VI).
 913  */
 914 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 915                                          unsigned vm_id, uint64_t pd_addr)
 916 {
 917         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 918                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 919         if (vm_id < 8) {
 920                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 921         } else {
 922                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 923         }
 924         amdgpu_ring_write(ring, pd_addr >> 12);
 925
 926         /* flush TLB */
 927         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 928                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 929         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 930         amdgpu_ring_write(ring, 1 << vm_id);
 931
 932         /* wait for flush */
 933         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 934                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 935                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 936         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 937         amdgpu_ring_write(ring, 0);
 938         amdgpu_ring_write(ring, 0); /* reference */
 939         amdgpu_ring_write(ring, 0); /* mask */
 940         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 941                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 942 }
 943
 944 static int sdma_v2_4_early_init(void *handle)
 945 {
 946         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 947
 948         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 949
 950         sdma_v2_4_set_ring_funcs(adev);
 951         sdma_v2_4_set_buffer_funcs(adev);
 952         sdma_v2_4_set_vm_pte_funcs(adev);
 953         sdma_v2_4_set_irq_funcs(adev);
 954
 955         return 0;
 956 }
 957
 958 static int sdma_v2_4_sw_init(void *handle)
 959 {
 960         struct amdgpu_ring *ring;
 961         int r, i;
 962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 963
 964         /* SDMA trap event */
 965         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 966         if (r)
 967                 return r;
 968
 969         /* SDMA Privileged inst */
 970         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 971         if (r)
 972                 return r;
 973
 974         /* SDMA Privileged inst */
 975         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 976         if (r)
 977                 return r;
 978
 979         r = sdma_v2_4_init_microcode(adev);
 980         if (r) {
 981                 DRM_ERROR("Failed to load sdma firmware!\n");
 982                 return r;
 983         }
 984
 985         for (i = 0; i < adev->sdma.num_instances; i++) {
 986                 ring = &adev->sdma.instance[i].ring;
 987                 ring->ring_obj = NULL;
 988                 ring->use_doorbell = false;
 989                 sprintf(ring->name, "sdma%d", i);
 990                 r = amdgpu_ring_init(adev, ring, 256 * 1024,
 991                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
 992                                      &adev->sdma.trap_irq,
 993                                      (i == 0) ?
 994                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 995                                      AMDGPU_RING_TYPE_SDMA);
 996                 if (r)
 997                         return r;
 998         }
 999
1000         return r;
1001 }
1002
1003 static int sdma_v2_4_sw_fini(void *handle)
1004 {
1005         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006         int i;
1007
1008         for (i = 0; i < adev->sdma.num_instances; i++)
1009                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1010
1011         return 0;
1012 }
1013
1014 static int sdma_v2_4_hw_init(void *handle)
1015 {
1016         int r;
1017         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019         sdma_v2_4_init_golden_registers(adev);
1020
1021         r = sdma_v2_4_start(adev);
1022         if (r)
1023                 return r;
1024
1025         return r;
1026 }
1027
1028 static int sdma_v2_4_hw_fini(void *handle)
1029 {
1030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031
1032         sdma_v2_4_enable(adev, false);
1033
1034         return 0;
1035 }
1036
1037 static int sdma_v2_4_suspend(void *handle)
1038 {
1039         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1040
1041         return sdma_v2_4_hw_fini(adev);
1042 }
1043
1044 static int sdma_v2_4_resume(void *handle)
1045 {
1046         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1047
1048         return sdma_v2_4_hw_init(adev);
1049 }
1050
1051 static bool sdma_v2_4_is_idle(void *handle)
1052 {
1053         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054         u32 tmp = RREG32(mmSRBM_STATUS2);
1055
1056         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1057                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1058             return false;
1059
1060         return true;
1061 }
1062
1063 static int sdma_v2_4_wait_for_idle(void *handle)
1064 {
1065         unsigned i;
1066         u32 tmp;
1067         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068
1069         for (i = 0; i < adev->usec_timeout; i++) {
1070                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1071                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1072
1073                 if (!tmp)
1074                         return 0;
1075                 udelay(1);
1076         }
1077         return -ETIMEDOUT;
1078 }
1079
1080 static void sdma_v2_4_print_status(void *handle)
1081 {
1082         int i, j;
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
1085         dev_info(adev->dev, "VI SDMA registers\n");
1086         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1087                  RREG32(mmSRBM_STATUS2));
1088         for (i = 0; i < adev->sdma.num_instances; i++) {
1089                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1090                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1091                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
1092                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1093                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1094                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1095                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1096                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1097                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1098                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1099                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1100                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1101                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1102                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1103                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1104                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1105                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1106                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1107                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1108                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1109                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1110                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1111                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1112                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1113                 mutex_lock(&adev->srbm_mutex);
1114                 for (j = 0; j < 16; j++) {
1115                         vi_srbm_select(adev, 0, 0, 0, j);
1116                         dev_info(adev->dev, "  VM %d:\n", j);
1117                         dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1118                                  i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1119                         dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1120                                  i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1121                 }
1122                 vi_srbm_select(adev, 0, 0, 0, 0);
1123                 mutex_unlock(&adev->srbm_mutex);
1124         }
1125 }
1126
1127 static int sdma_v2_4_soft_reset(void *handle)
1128 {
1129         u32 srbm_soft_reset = 0;
1130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1131         u32 tmp = RREG32(mmSRBM_STATUS2);
1132
1133         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1134                 /* sdma0 */
1135                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1136                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1137                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1138                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1139         }
1140         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1141                 /* sdma1 */
1142                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1143                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1144                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1145                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1146         }
1147
1148         if (srbm_soft_reset) {
1149                 sdma_v2_4_print_status((void *)adev);
1150
1151                 tmp = RREG32(mmSRBM_SOFT_RESET);
1152                 tmp |= srbm_soft_reset;
1153                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1154                 WREG32(mmSRBM_SOFT_RESET, tmp);
1155                 tmp = RREG32(mmSRBM_SOFT_RESET);
1156
1157                 udelay(50);
1158
1159                 tmp &= ~srbm_soft_reset;
1160                 WREG32(mmSRBM_SOFT_RESET, tmp);
1161                 tmp = RREG32(mmSRBM_SOFT_RESET);
1162
1163                 /* Wait a little for things to settle down */
1164                 udelay(50);
1165
1166                 sdma_v2_4_print_status((void *)adev);
1167         }
1168
1169         return 0;
1170 }
1171
1172 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1173                                         struct amdgpu_irq_src *src,
1174                                         unsigned type,
1175                                         enum amdgpu_interrupt_state state)
1176 {
1177         u32 sdma_cntl;
1178
1179         switch (type) {
1180         case AMDGPU_SDMA_IRQ_TRAP0:
1181                 switch (state) {
1182                 case AMDGPU_IRQ_STATE_DISABLE:
1183                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1184                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1185                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1186                         break;
1187                 case AMDGPU_IRQ_STATE_ENABLE:
1188                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1189                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1190                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1191                         break;
1192                 default:
1193                         break;
1194                 }
1195                 break;
1196         case AMDGPU_SDMA_IRQ_TRAP1:
1197                 switch (state) {
1198                 case AMDGPU_IRQ_STATE_DISABLE:
1199                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1200                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1201                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1202                         break;
1203                 case AMDGPU_IRQ_STATE_ENABLE:
1204                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1205                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1206                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1207                         break;
1208                 default:
1209                         break;
1210                 }
1211                 break;
1212         default:
1213                 break;
1214         }
1215         return 0;
1216 }
1217
1218 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1219                                       struct amdgpu_irq_src *source,
1220                                       struct amdgpu_iv_entry *entry)
1221 {
1222         u8 instance_id, queue_id;
1223
1224         instance_id = (entry->ring_id & 0x3) >> 0;
1225         queue_id = (entry->ring_id & 0xc) >> 2;
1226         DRM_DEBUG("IH: SDMA trap\n");
1227         switch (instance_id) {
1228         case 0:
1229                 switch (queue_id) {
1230                 case 0:
1231                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1232                         break;
1233                 case 1:
1234                         /* XXX compute */
1235                         break;
1236                 case 2:
1237                         /* XXX compute */
1238                         break;
1239                 }
1240                 break;
1241         case 1:
1242                 switch (queue_id) {
1243                 case 0:
1244                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1245                         break;
1246                 case 1:
1247                         /* XXX compute */
1248                         break;
1249                 case 2:
1250                         /* XXX compute */
1251                         break;
1252                 }
1253                 break;
1254         }
1255         return 0;
1256 }
1257
1258 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1259                                               struct amdgpu_irq_src *source,
1260                                               struct amdgpu_iv_entry *entry)
1261 {
1262         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1263         schedule_work(&adev->reset_work);
1264         return 0;
1265 }
1266
1267 static int sdma_v2_4_set_clockgating_state(void *handle,
1268                                           enum amd_clockgating_state state)
1269 {
1270         /* XXX handled via the smc on VI */
1271         return 0;
1272 }
1273
1274 static int sdma_v2_4_set_powergating_state(void *handle,
1275                                           enum amd_powergating_state state)
1276 {
1277         return 0;
1278 }
1279
1280 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1281         .early_init = sdma_v2_4_early_init,
1282         .late_init = NULL,
1283         .sw_init = sdma_v2_4_sw_init,
1284         .sw_fini = sdma_v2_4_sw_fini,
1285         .hw_init = sdma_v2_4_hw_init,
1286         .hw_fini = sdma_v2_4_hw_fini,
1287         .suspend = sdma_v2_4_suspend,
1288         .resume = sdma_v2_4_resume,
1289         .is_idle = sdma_v2_4_is_idle,
1290         .wait_for_idle = sdma_v2_4_wait_for_idle,
1291         .soft_reset = sdma_v2_4_soft_reset,
1292         .print_status = sdma_v2_4_print_status,
1293         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1294         .set_powergating_state = sdma_v2_4_set_powergating_state,
1295 };
1296
1297 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1298         .get_rptr = sdma_v2_4_ring_get_rptr,
1299         .get_wptr = sdma_v2_4_ring_get_wptr,
1300         .set_wptr = sdma_v2_4_ring_set_wptr,
1301         .parse_cs = NULL,
1302         .emit_ib = sdma_v2_4_ring_emit_ib,
1303         .emit_fence = sdma_v2_4_ring_emit_fence,
1304         .emit_semaphore = sdma_v2_4_ring_emit_semaphore,
1305         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1306         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1307         .test_ring = sdma_v2_4_ring_test_ring,
1308         .test_ib = sdma_v2_4_ring_test_ib,
1309         .insert_nop = sdma_v2_4_ring_insert_nop,
1310 };
1311
1312 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1313 {
1314         int i;
1315
1316         for (i = 0; i < adev->sdma.num_instances; i++)
1317                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1318 }
1319
1320 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1321         .set = sdma_v2_4_set_trap_irq_state,
1322         .process = sdma_v2_4_process_trap_irq,
1323 };
1324
1325 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1326         .process = sdma_v2_4_process_illegal_inst_irq,
1327 };
1328
1329 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1330 {
1331         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1332         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1333         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1334 }
1335
1336 /**
1337  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1338  *
1339  * @ring: amdgpu_ring structure holding ring information
1340  * @src_offset: src GPU address
1341  * @dst_offset: dst GPU address
1342  * @byte_count: number of bytes to xfer
1343  *
1344  * Copy GPU buffers using the DMA engine (VI).
1345  * Used by the amdgpu ttm implementation to move pages if
1346  * registered as the asic copy callback.
1347  */
1348 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1349                                        uint64_t src_offset,
1350                                        uint64_t dst_offset,
1351                                        uint32_t byte_count)
1352 {
1353         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1354                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1355         ib->ptr[ib->length_dw++] = byte_count;
1356         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1357         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1358         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1359         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1360         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1361 }
1362
1363 /**
1364  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1365  *
1366  * @ring: amdgpu_ring structure holding ring information
1367  * @src_data: value to write to buffer
1368  * @dst_offset: dst GPU address
1369  * @byte_count: number of bytes to xfer
1370  *
1371  * Fill GPU buffers using the DMA engine (VI).
1372  */
1373 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1374                                        uint32_t src_data,
1375                                        uint64_t dst_offset,
1376                                        uint32_t byte_count)
1377 {
1378         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1379         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1380         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1381         ib->ptr[ib->length_dw++] = src_data;
1382         ib->ptr[ib->length_dw++] = byte_count;
1383 }
1384
1385 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1386         .copy_max_bytes = 0x1fffff,
1387         .copy_num_dw = 7,
1388         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1389
1390         .fill_max_bytes = 0x1fffff,
1391         .fill_num_dw = 7,
1392         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1393 };
1394
1395 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1396 {
1397         if (adev->mman.buffer_funcs == NULL) {
1398                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1399                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1400         }
1401 }
1402
1403 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1404         .copy_pte = sdma_v2_4_vm_copy_pte,
1405         .write_pte = sdma_v2_4_vm_write_pte,
1406         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1407         .pad_ib = sdma_v2_4_vm_pad_ib,
1408 };
1409
1410 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1411 {
1412         if (adev->vm_manager.vm_pte_funcs == NULL) {
1413                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1414                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1415                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1416         }
1417 }