drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amd_pcie.h"
  30 #include "sid.h"
  31 #include "r600_dpm.h"
  32 #include "si_dpm.h"
  33 #include "atom.h"
  34 #include "../include/pptable.h"
  35 #include <linux/math64.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/firmware.h>
  38
  39 #define MC_CG_ARB_FREQ_F0           0x0a
  40 #define MC_CG_ARB_FREQ_F1           0x0b
  41 #define MC_CG_ARB_FREQ_F2           0x0c
  42 #define MC_CG_ARB_FREQ_F3           0x0d
  43
  44 #define SMC_RAM_END                 0x20000
  45
  46 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  47
  48
  49 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  55 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  56
  57 #define BIOS_SCRATCH_4                                    0x5cd
  58
  59 /*(DEBLOBBED)*/
  60
  61 static const struct amd_pm_funcs si_dpm_funcs;
  62
  63 union power_info {
  64         struct _ATOM_POWERPLAY_INFO info;
  65         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  66         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  67         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  68         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  69         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  70         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  71         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  72 };
  73
  74 union fan_info {
  75         struct _ATOM_PPLIB_FANTABLE fan;
  76         struct _ATOM_PPLIB_FANTABLE2 fan2;
  77         struct _ATOM_PPLIB_FANTABLE3 fan3;
  78 };
  79
  80 union pplib_clock_info {
  81         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  82         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  83         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  84         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  85         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  86 };
  87
  88 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  89 {
  90         R600_UTC_DFLT_00,
  91         R600_UTC_DFLT_01,
  92         R600_UTC_DFLT_02,
  93         R600_UTC_DFLT_03,
  94         R600_UTC_DFLT_04,
  95         R600_UTC_DFLT_05,
  96         R600_UTC_DFLT_06,
  97         R600_UTC_DFLT_07,
  98         R600_UTC_DFLT_08,
  99         R600_UTC_DFLT_09,
 100         R600_UTC_DFLT_10,
 101         R600_UTC_DFLT_11,
 102         R600_UTC_DFLT_12,
 103         R600_UTC_DFLT_13,
 104         R600_UTC_DFLT_14,
 105 };
 106
 107 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 108 {
 109         R600_DTC_DFLT_00,
 110         R600_DTC_DFLT_01,
 111         R600_DTC_DFLT_02,
 112         R600_DTC_DFLT_03,
 113         R600_DTC_DFLT_04,
 114         R600_DTC_DFLT_05,
 115         R600_DTC_DFLT_06,
 116         R600_DTC_DFLT_07,
 117         R600_DTC_DFLT_08,
 118         R600_DTC_DFLT_09,
 119         R600_DTC_DFLT_10,
 120         R600_DTC_DFLT_11,
 121         R600_DTC_DFLT_12,
 122         R600_DTC_DFLT_13,
 123         R600_DTC_DFLT_14,
 124 };
 125
 126 static const struct si_cac_config_reg cac_weights_tahiti[] =
 127 {
 128         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 129         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 130         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 131         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 132         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 133         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 134         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 135         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 136         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 137         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 138         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 139         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 140         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 141         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 143         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 144         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 145         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 146         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 147         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 148         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 149         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 150         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 151         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 152         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 153         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 154         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 155         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 156         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 157         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 160         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 161         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 163         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 164         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 165         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 166         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 168         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 169         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 170         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 172         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 173         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 174         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 186         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 187         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 188         { 0xFFFFFFFF }
 189 };
 190
 191 static const struct si_cac_config_reg lcac_tahiti[] =
 192 {
 193         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 194         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 195         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 196         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 197         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 198         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 199         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 200         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 201         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 202         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 203         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 204         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 205         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 206         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 207         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 208         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 209         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 210         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 211         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 212         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 213         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 214         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 215         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 216         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 217         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 218         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 219         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 220         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 221         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 222         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 223         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 224         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 225         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 226         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 227         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 228         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 229         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 230         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 231         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 232         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 233         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 234         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 235         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 236         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 237         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 238         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 239         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 240         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 241         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 242         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 243         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 244         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 245         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 246         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 247         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 248         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 249         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 250         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 251         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 252         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 253         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 254         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 255         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 256         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 257         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 258         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 259         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 260         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 261         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 262         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 263         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 264         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 265         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 266         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 267         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 268         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 269         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 270         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 271         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 272         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 273         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 274         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 275         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 276         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 277         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 278         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 279         { 0xFFFFFFFF }
 280
 281 };
 282
 283 static const struct si_cac_config_reg cac_override_tahiti[] =
 284 {
 285         { 0xFFFFFFFF }
 286 };
 287
 288 static const struct si_powertune_data powertune_data_tahiti =
 289 {
 290         ((1 << 16) | 27027),
 291         6,
 292         0,
 293         4,
 294         95,
 295         {
 296                 0UL,
 297                 0UL,
 298                 4521550UL,
 299                 309631529UL,
 300                 -1270850L,
 301                 4513710L,
 302                 40
 303         },
 304         595000000UL,
 305         12,
 306         {
 307                 0,
 308                 0,
 309                 0,
 310                 0,
 311                 0,
 312                 0,
 313                 0,
 314                 0
 315         },
 316         true
 317 };
 318
 319 static const struct si_dte_data dte_data_tahiti =
 320 {
 321         { 1159409, 0, 0, 0, 0 },
 322         { 777, 0, 0, 0, 0 },
 323         2,
 324         54000,
 325         127000,
 326         25,
 327         2,
 328         10,
 329         13,
 330         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 331         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 332         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 333         85,
 334         false
 335 };
 336
 337 #if 0
 338 static const struct si_dte_data dte_data_tahiti_le =
 339 {
 340         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 341         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 342         0x5,
 343         0xAFC8,
 344         0x64,
 345         0x32,
 346         1,
 347         0,
 348         0x10,
 349         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 350         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 351         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 352         85,
 353         true
 354 };
 355 #endif
 356
 357 static const struct si_dte_data dte_data_tahiti_pro =
 358 {
 359         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 360         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 361         5,
 362         45000,
 363         100,
 364         0xA,
 365         1,
 366         0,
 367         0x10,
 368         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 369         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 370         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 371         90,
 372         true
 373 };
 374
 375 static const struct si_dte_data dte_data_new_zealand =
 376 {
 377         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 378         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 379         0x5,
 380         0xAFC8,
 381         0x69,
 382         0x32,
 383         1,
 384         0,
 385         0x10,
 386         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 387         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 388         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 389         85,
 390         true
 391 };
 392
 393 static const struct si_dte_data dte_data_aruba_pro =
 394 {
 395         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 396         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 397         5,
 398         45000,
 399         100,
 400         0xA,
 401         1,
 402         0,
 403         0x10,
 404         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 405         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 406         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 407         90,
 408         true
 409 };
 410
 411 static const struct si_dte_data dte_data_malta =
 412 {
 413         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 414         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 415         5,
 416         45000,
 417         100,
 418         0xA,
 419         1,
 420         0,
 421         0x10,
 422         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 423         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 424         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 425         90,
 426         true
 427 };
 428
 429 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 430 {
 431         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 432         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 433         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 434         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 435         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 436         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 437         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 438         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 439         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 440         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 441         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 442         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 443         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 444         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 445         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 446         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 447         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 448         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 449         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 450         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 451         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 452         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 453         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 454         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 455         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 456         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 457         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 458         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 459         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 460         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 463         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 464         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 465         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 466         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 467         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 468         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 469         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 470         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 472         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 473         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 474         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 475         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 476         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 488         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 489         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 490         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 491         { 0xFFFFFFFF }
 492 };
 493
 494 static const struct si_cac_config_reg lcac_pitcairn[] =
 495 {
 496         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 497         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 498         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 499         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 500         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 501         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 502         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 503         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 504         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 505         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 506         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 507         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 508         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 509         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 510         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 511         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 512         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 513         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 514         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 515         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 516         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 517         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 518         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 519         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 520         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 521         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 522         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 523         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 524         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 525         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 526         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 527         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 528         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 529         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 530         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 531         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 532         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 533         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 534         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 535         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 536         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 537         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 538         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 539         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 540         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 541         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 542         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 543         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 544         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 545         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 546         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 547         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 548         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 549         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 550         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 551         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 552         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 553         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 554         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 555         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 556         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 557         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 558         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 559         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 560         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 561         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 562         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 563         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 564         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 565         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 566         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 567         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 568         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 569         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 570         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 571         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 572         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 573         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 574         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 575         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 576         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 577         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 578         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 579         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 580         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 581         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 582         { 0xFFFFFFFF }
 583 };
 584
 585 static const struct si_cac_config_reg cac_override_pitcairn[] =
 586 {
 587     { 0xFFFFFFFF }
 588 };
 589
 590 static const struct si_powertune_data powertune_data_pitcairn =
 591 {
 592         ((1 << 16) | 27027),
 593         5,
 594         0,
 595         6,
 596         100,
 597         {
 598                 51600000UL,
 599                 1800000UL,
 600                 7194395UL,
 601                 309631529UL,
 602                 -1270850L,
 603                 4513710L,
 604                 100
 605         },
 606         117830498UL,
 607         12,
 608         {
 609                 0,
 610                 0,
 611                 0,
 612                 0,
 613                 0,
 614                 0,
 615                 0,
 616                 0
 617         },
 618         true
 619 };
 620
 621 static const struct si_dte_data dte_data_pitcairn =
 622 {
 623         { 0, 0, 0, 0, 0 },
 624         { 0, 0, 0, 0, 0 },
 625         0,
 626         0,
 627         0,
 628         0,
 629         0,
 630         0,
 631         0,
 632         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 633         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 634         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 635         0,
 636         false
 637 };
 638
 639 static const struct si_dte_data dte_data_curacao_xt =
 640 {
 641         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 642         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 643         5,
 644         45000,
 645         100,
 646         0xA,
 647         1,
 648         0,
 649         0x10,
 650         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 651         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 652         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 653         90,
 654         true
 655 };
 656
 657 static const struct si_dte_data dte_data_curacao_pro =
 658 {
 659         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 660         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 661         5,
 662         45000,
 663         100,
 664         0xA,
 665         1,
 666         0,
 667         0x10,
 668         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 669         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 670         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 671         90,
 672         true
 673 };
 674
 675 static const struct si_dte_data dte_data_neptune_xt =
 676 {
 677         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 678         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 679         5,
 680         45000,
 681         100,
 682         0xA,
 683         1,
 684         0,
 685         0x10,
 686         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 687         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 688         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 689         90,
 690         true
 691 };
 692
 693 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 694 {
 695         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 696         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 697         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 698         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 699         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 700         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 701         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 702         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 703         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 704         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 705         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 706         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 707         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 708         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 709         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 710         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 711         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 712         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 713         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 714         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 715         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 716         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 717         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 718         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 719         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 720         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 721         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 722         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 724         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 725         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 726         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 727         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 728         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 729         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 730         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 731         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 733         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 735         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 736         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 737         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 738         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 739         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 740         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 741         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 752         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 753         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 754         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 755         { 0xFFFFFFFF }
 756 };
 757
 758 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 759 {
 760         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 761         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 762         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 763         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 764         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 765         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 766         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 767         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 768         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 769         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 770         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 771         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 772         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 773         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 774         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 775         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 776         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 777         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 778         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 779         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 780         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 781         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 782         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 783         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 784         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 785         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 786         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 787         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 789         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 790         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 791         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 792         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 793         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 794         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 795         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 796         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 798         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 800         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 801         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 802         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 803         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 804         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 805         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 806         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 817         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 818         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 819         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 820         { 0xFFFFFFFF }
 821 };
 822
 823 static const struct si_cac_config_reg cac_weights_heathrow[] =
 824 {
 825         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 826         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 827         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 828         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 829         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 830         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 831         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 832         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 833         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 834         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 835         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 836         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 837         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 838         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 839         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 840         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 841         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 842         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 843         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 844         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 845         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 846         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 847         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 848         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 849         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 850         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 851         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 852         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 854         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 855         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 856         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 857         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 858         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 859         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 860         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 861         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 863         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 865         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 866         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 867         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 868         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 869         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 870         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 871         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 882         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 883         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 884         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 885         { 0xFFFFFFFF }
 886 };
 887
 888 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 889 {
 890         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 891         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 892         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 893         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 894         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 895         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 896         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 897         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 898         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 899         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 900         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 901         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 902         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 903         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 904         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 905         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 906         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 907         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 908         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 909         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 910         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 911         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 912         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 913         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 914         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 915         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 916         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 917         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 919         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 920         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 921         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 922         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 923         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 924         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 925         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 926         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 928         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 930         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 931         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 932         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 933         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 934         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 935         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 936         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 937         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 947         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 948         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 949         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 950         { 0xFFFFFFFF }
 951 };
 952
 953 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 954 {
 955         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 956         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 957         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 958         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 959         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 960         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 961         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 962         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 963         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 964         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 965         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 966         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 967         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 968         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 969         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 970         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 971         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 972         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 973         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 974         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 975         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 976         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 977         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 978         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 979         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 980         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 981         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 982         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 983         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 986         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 987         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 988         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 989         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 990         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 991         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 992         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 993         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 994         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 995         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 996         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 997         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 998         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 999         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1001         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1002         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1015         { 0xFFFFFFFF }
1016 };
1017
1018 static const struct si_cac_config_reg lcac_cape_verde[] =
1019 {
1020         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1021         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1022         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1023         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1024         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1025         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1026         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1027         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1029         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1031         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1033         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1035         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1037         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1039         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1041         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1043         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1045         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1047         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1049         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1063         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1067         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1071         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074         { 0xFFFFFFFF }
1075 };
1076
1077 static const struct si_cac_config_reg cac_override_cape_verde[] =
1078 {
1079     { 0xFFFFFFFF }
1080 };
1081
1082 static const struct si_powertune_data powertune_data_cape_verde =
1083 {
1084         ((1 << 16) | 0x6993),
1085         5,
1086         0,
1087         7,
1088         105,
1089         {
1090                 0UL,
1091                 0UL,
1092                 7194395UL,
1093                 309631529UL,
1094                 -1270850L,
1095                 4513710L,
1096                 100
1097         },
1098         117830498UL,
1099         12,
1100         {
1101                 0,
1102                 0,
1103                 0,
1104                 0,
1105                 0,
1106                 0,
1107                 0,
1108                 0
1109         },
1110         true
1111 };
1112
1113 static const struct si_dte_data dte_data_cape_verde =
1114 {
1115         { 0, 0, 0, 0, 0 },
1116         { 0, 0, 0, 0, 0 },
1117         0,
1118         0,
1119         0,
1120         0,
1121         0,
1122         0,
1123         0,
1124         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1125         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1126         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1127         0,
1128         false
1129 };
1130
1131 static const struct si_dte_data dte_data_venus_xtx =
1132 {
1133         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1134         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1135         5,
1136         55000,
1137         0x69,
1138         0xA,
1139         1,
1140         0,
1141         0x3,
1142         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1143         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1144         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1145         90,
1146         true
1147 };
1148
1149 static const struct si_dte_data dte_data_venus_xt =
1150 {
1151         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1152         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1153         5,
1154         55000,
1155         0x69,
1156         0xA,
1157         1,
1158         0,
1159         0x3,
1160         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1161         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1162         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1163         90,
1164         true
1165 };
1166
1167 static const struct si_dte_data dte_data_venus_pro =
1168 {
1169         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1170         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1171         5,
1172         55000,
1173         0x69,
1174         0xA,
1175         1,
1176         0,
1177         0x3,
1178         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1179         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1180         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1181         90,
1182         true
1183 };
1184
1185 static const struct si_cac_config_reg cac_weights_oland[] =
1186 {
1187         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1188         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1189         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1190         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1191         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1192         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1193         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1194         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1195         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1196         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1197         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1198         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1199         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1200         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1201         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1202         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1203         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1204         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1205         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1206         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1207         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1208         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1209         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1210         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1211         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1212         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1213         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1214         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1215         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1216         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1217         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1218         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1219         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1220         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1221         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1222         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1223         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1225         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1227         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1228         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1229         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1231         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1233         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1247         { 0xFFFFFFFF }
1248 };
1249
1250 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1251 {
1252         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1253         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1254         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1255         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1256         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1257         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1258         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1259         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1260         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1261         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1262         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1263         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1264         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1265         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1266         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1267         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1268         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1269         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1270         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1271         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1272         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1273         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1274         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1275         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1276         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1277         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1278         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1279         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1280         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1281         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1282         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1283         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1284         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1285         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1286         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1287         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1288         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1290         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1292         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1293         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1294         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1296         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1298         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1303         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1304         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1308         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1309         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1310         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1311         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1312         { 0xFFFFFFFF }
1313 };
1314
1315 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1316 {
1317         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1318         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1319         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1320         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1321         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1322         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1323         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1324         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1325         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1326         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1327         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1328         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1329         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1330         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1331         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1332         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1333         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1334         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1335         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1336         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1337         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1338         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1339         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1340         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1341         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1342         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1343         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1344         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1345         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1346         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1347         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1348         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1349         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1350         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1351         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1352         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1353         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1355         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1357         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1358         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1359         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1361         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1363         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1368         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1369         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1373         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1374         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1375         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1376         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1377         { 0xFFFFFFFF }
1378 };
1379
1380 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1381 {
1382         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1383         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1384         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1385         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1386         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1387         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1388         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1389         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1390         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1391         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1392         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1393         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1394         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1395         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1396         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1397         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1398         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1399         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1400         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1401         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1402         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1403         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1404         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1405         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1406         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1407         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1408         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1409         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1410         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1411         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1412         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1413         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1414         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1415         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1416         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1417         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1418         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1420         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1422         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1423         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1424         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1426         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1428         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1429         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1430         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1433         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1434         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1437         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1438         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1439         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1440         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1441         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1442         { 0xFFFFFFFF }
1443 };
1444
1445 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1446 {
1447         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1448         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1449         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1450         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1451         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1452         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1453         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1454         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1455         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1456         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1457         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1458         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1459         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1460         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1461         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1462         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1463         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1464         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1465         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1466         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1467         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1468         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1469         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1470         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1471         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1472         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1473         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1474         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1475         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1477         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1478         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1479         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1480         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1481         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1482         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1483         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1484         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1485         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1486         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1487         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1488         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1489         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1491         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1493         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1494         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1495         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1498         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1499         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1502         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1503         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1504         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1505         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1506         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1507         { 0xFFFFFFFF }
1508 };
1509
1510 static const struct si_cac_config_reg lcac_oland[] =
1511 {
1512         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1513         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1515         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1517         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1518         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1519         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1521         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1523         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1525         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1527         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1529         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1531         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1533         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1541         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1547         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554         { 0xFFFFFFFF }
1555 };
1556
1557 static const struct si_cac_config_reg lcac_mars_pro[] =
1558 {
1559         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1560         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1561         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1562         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1563         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1564         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1565         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1566         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1568         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1570         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1572         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1574         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1576         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1578         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1580         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1588         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1594         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601         { 0xFFFFFFFF }
1602 };
1603
1604 static const struct si_cac_config_reg cac_override_oland[] =
1605 {
1606         { 0xFFFFFFFF }
1607 };
1608
1609 static const struct si_powertune_data powertune_data_oland =
1610 {
1611         ((1 << 16) | 0x6993),
1612         5,
1613         0,
1614         7,
1615         105,
1616         {
1617                 0UL,
1618                 0UL,
1619                 7194395UL,
1620                 309631529UL,
1621                 -1270850L,
1622                 4513710L,
1623                 100
1624         },
1625         117830498UL,
1626         12,
1627         {
1628                 0,
1629                 0,
1630                 0,
1631                 0,
1632                 0,
1633                 0,
1634                 0,
1635                 0
1636         },
1637         true
1638 };
1639
1640 static const struct si_powertune_data powertune_data_mars_pro =
1641 {
1642         ((1 << 16) | 0x6993),
1643         5,
1644         0,
1645         7,
1646         105,
1647         {
1648                 0UL,
1649                 0UL,
1650                 7194395UL,
1651                 309631529UL,
1652                 -1270850L,
1653                 4513710L,
1654                 100
1655         },
1656         117830498UL,
1657         12,
1658         {
1659                 0,
1660                 0,
1661                 0,
1662                 0,
1663                 0,
1664                 0,
1665                 0,
1666                 0
1667         },
1668         true
1669 };
1670
1671 static const struct si_dte_data dte_data_oland =
1672 {
1673         { 0, 0, 0, 0, 0 },
1674         { 0, 0, 0, 0, 0 },
1675         0,
1676         0,
1677         0,
1678         0,
1679         0,
1680         0,
1681         0,
1682         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1683         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1684         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1685         0,
1686         false
1687 };
1688
1689 static const struct si_dte_data dte_data_mars_pro =
1690 {
1691         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1692         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1693         5,
1694         55000,
1695         105,
1696         0xA,
1697         1,
1698         0,
1699         0x10,
1700         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1701         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1702         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1703         90,
1704         true
1705 };
1706
1707 static const struct si_dte_data dte_data_sun_xt =
1708 {
1709         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1710         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1711         5,
1712         55000,
1713         105,
1714         0xA,
1715         1,
1716         0,
1717         0x10,
1718         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1719         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1720         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1721         90,
1722         true
1723 };
1724
1725
1726 static const struct si_cac_config_reg cac_weights_hainan[] =
1727 {
1728         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1729         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1730         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1731         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1732         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1733         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1734         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1735         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1736         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1737         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1738         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1739         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1740         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1741         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1743         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1744         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1745         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1746         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1747         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1748         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1749         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1750         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1751         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1752         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1753         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1754         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1755         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1756         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1757         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1758         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1759         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1760         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1761         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1762         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1763         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1764         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1765         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1768         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1769         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1770         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1771         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1774         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1775         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1776         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1788         { 0xFFFFFFFF }
1789 };
1790
1791 static const struct si_powertune_data powertune_data_hainan =
1792 {
1793         ((1 << 16) | 0x6993),
1794         5,
1795         0,
1796         9,
1797         105,
1798         {
1799                 0UL,
1800                 0UL,
1801                 7194395UL,
1802                 309631529UL,
1803                 -1270850L,
1804                 4513710L,
1805                 100
1806         },
1807         117830498UL,
1808         12,
1809         {
1810                 0,
1811                 0,
1812                 0,
1813                 0,
1814                 0,
1815                 0,
1816                 0,
1817                 0
1818         },
1819         true
1820 };
1821
1822 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1823 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1824 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1825 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1826
1827 static int si_populate_voltage_value(struct amdgpu_device *adev,
1828                                      const struct atom_voltage_table *table,
1829                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1830 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1831                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1832                                     u16 *std_voltage);
1833 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1834                                       u16 reg_offset, u32 value);
1835 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1836                                          struct rv7xx_pl *pl,
1837                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1838 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1839                                     u32 engine_clock,
1840                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1841
1842 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1843 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1844 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1845
1846 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1847 {
1848         struct si_power_info *pi = adev->pm.dpm.priv;
1849         return pi;
1850 }
1851
1852 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1853                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1854 {
1855         s64 kt, kv, leakage_w, i_leakage, vddc;
1856         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1857         s64 tmp;
1858
1859         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1860         vddc = div64_s64(drm_int2fixp(v), 1000);
1861         temperature = div64_s64(drm_int2fixp(t), 1000);
1862
1863         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1864         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1865         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1866         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1867         t_ref = drm_int2fixp(coeff->t_ref);
1868
1869         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1870         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1871         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1872         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1873
1874         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1875
1876         *leakage = drm_fixp2int(leakage_w * 1000);
1877 }
1878
1879 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1880                                              const struct ni_leakage_coeffients *coeff,
1881                                              u16 v,
1882                                              s32 t,
1883                                              u32 i_leakage,
1884                                              u32 *leakage)
1885 {
1886         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1887 }
1888
1889 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1890                                                const u32 fixed_kt, u16 v,
1891                                                u32 ileakage, u32 *leakage)
1892 {
1893         s64 kt, kv, leakage_w, i_leakage, vddc;
1894
1895         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1896         vddc = div64_s64(drm_int2fixp(v), 1000);
1897
1898         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1899         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1900                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1901
1902         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1903
1904         *leakage = drm_fixp2int(leakage_w * 1000);
1905 }
1906
1907 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1908                                        const struct ni_leakage_coeffients *coeff,
1909                                        const u32 fixed_kt,
1910                                        u16 v,
1911                                        u32 i_leakage,
1912                                        u32 *leakage)
1913 {
1914         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1915 }
1916
1917
1918 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1919                                    struct si_dte_data *dte_data)
1920 {
1921         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1922         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1923         u32 k = dte_data->k;
1924         u32 t_max = dte_data->max_t;
1925         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1926         u32 t_0 = dte_data->t0;
1927         u32 i;
1928
1929         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1930                 dte_data->tdep_count = 3;
1931
1932                 for (i = 0; i < k; i++) {
1933                         dte_data->r[i] =
1934                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1935                                 (p_limit2  * (u32)100);
1936                 }
1937
1938                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1939
1940                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1941                         dte_data->tdep_r[i] = dte_data->r[4];
1942                 }
1943         } else {
1944                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1945         }
1946 }
1947
1948 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1949 {
1950         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1951
1952         return pi;
1953 }
1954
1955 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1956 {
1957         struct ni_power_info *pi = adev->pm.dpm.priv;
1958
1959         return pi;
1960 }
1961
1962 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1963 {
1964         struct  si_ps *ps = aps->ps_priv;
1965
1966         return ps;
1967 }
1968
1969 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1970 {
1971         struct ni_power_info *ni_pi = ni_get_pi(adev);
1972         struct si_power_info *si_pi = si_get_pi(adev);
1973         bool update_dte_from_pl2 = false;
1974
1975         if (adev->asic_type == CHIP_TAHITI) {
1976                 si_pi->cac_weights = cac_weights_tahiti;
1977                 si_pi->lcac_config = lcac_tahiti;
1978                 si_pi->cac_override = cac_override_tahiti;
1979                 si_pi->powertune_data = &powertune_data_tahiti;
1980                 si_pi->dte_data = dte_data_tahiti;
1981
1982                 switch (adev->pdev->device) {
1983                 case 0x6798:
1984                         si_pi->dte_data.enable_dte_by_default = true;
1985                         break;
1986                 case 0x6799:
1987                         si_pi->dte_data = dte_data_new_zealand;
1988                         break;
1989                 case 0x6790:
1990                 case 0x6791:
1991                 case 0x6792:
1992                 case 0x679E:
1993                         si_pi->dte_data = dte_data_aruba_pro;
1994                         update_dte_from_pl2 = true;
1995                         break;
1996                 case 0x679B:
1997                         si_pi->dte_data = dte_data_malta;
1998                         update_dte_from_pl2 = true;
1999                         break;
2000                 case 0x679A:
2001                         si_pi->dte_data = dte_data_tahiti_pro;
2002                         update_dte_from_pl2 = true;
2003                         break;
2004                 default:
2005                         if (si_pi->dte_data.enable_dte_by_default == true)
2006                                 DRM_ERROR("DTE is not enabled!\n");
2007                         break;
2008                 }
2009         } else if (adev->asic_type == CHIP_PITCAIRN) {
2010                 si_pi->cac_weights = cac_weights_pitcairn;
2011                 si_pi->lcac_config = lcac_pitcairn;
2012                 si_pi->cac_override = cac_override_pitcairn;
2013                 si_pi->powertune_data = &powertune_data_pitcairn;
2014
2015                 switch (adev->pdev->device) {
2016                 case 0x6810:
2017                 case 0x6818:
2018                         si_pi->dte_data = dte_data_curacao_xt;
2019                         update_dte_from_pl2 = true;
2020                         break;
2021                 case 0x6819:
2022                 case 0x6811:
2023                         si_pi->dte_data = dte_data_curacao_pro;
2024                         update_dte_from_pl2 = true;
2025                         break;
2026                 case 0x6800:
2027                 case 0x6806:
2028                         si_pi->dte_data = dte_data_neptune_xt;
2029                         update_dte_from_pl2 = true;
2030                         break;
2031                 default:
2032                         si_pi->dte_data = dte_data_pitcairn;
2033                         break;
2034                 }
2035         } else if (adev->asic_type == CHIP_VERDE) {
2036                 si_pi->lcac_config = lcac_cape_verde;
2037                 si_pi->cac_override = cac_override_cape_verde;
2038                 si_pi->powertune_data = &powertune_data_cape_verde;
2039
2040                 switch (adev->pdev->device) {
2041                 case 0x683B:
2042                 case 0x683F:
2043                 case 0x6829:
2044                 case 0x6835:
2045                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2046                         si_pi->dte_data = dte_data_cape_verde;
2047                         break;
2048                 case 0x682C:
2049                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2050                         si_pi->dte_data = dte_data_sun_xt;
2051                         update_dte_from_pl2 = true;
2052                         break;
2053                 case 0x6825:
2054                 case 0x6827:
2055                         si_pi->cac_weights = cac_weights_heathrow;
2056                         si_pi->dte_data = dte_data_cape_verde;
2057                         break;
2058                 case 0x6824:
2059                 case 0x682D:
2060                         si_pi->cac_weights = cac_weights_chelsea_xt;
2061                         si_pi->dte_data = dte_data_cape_verde;
2062                         break;
2063                 case 0x682F:
2064                         si_pi->cac_weights = cac_weights_chelsea_pro;
2065                         si_pi->dte_data = dte_data_cape_verde;
2066                         break;
2067                 case 0x6820:
2068                         si_pi->cac_weights = cac_weights_heathrow;
2069                         si_pi->dte_data = dte_data_venus_xtx;
2070                         break;
2071                 case 0x6821:
2072                         si_pi->cac_weights = cac_weights_heathrow;
2073                         si_pi->dte_data = dte_data_venus_xt;
2074                         break;
2075                 case 0x6823:
2076                 case 0x682B:
2077                 case 0x6822:
2078                 case 0x682A:
2079                         si_pi->cac_weights = cac_weights_chelsea_pro;
2080                         si_pi->dte_data = dte_data_venus_pro;
2081                         break;
2082                 default:
2083                         si_pi->cac_weights = cac_weights_cape_verde;
2084                         si_pi->dte_data = dte_data_cape_verde;
2085                         break;
2086                 }
2087         } else if (adev->asic_type == CHIP_OLAND) {
2088                 si_pi->lcac_config = lcac_mars_pro;
2089                 si_pi->cac_override = cac_override_oland;
2090                 si_pi->powertune_data = &powertune_data_mars_pro;
2091                 si_pi->dte_data = dte_data_mars_pro;
2092
2093                 switch (adev->pdev->device) {
2094                 case 0x6601:
2095                 case 0x6621:
2096                 case 0x6603:
2097                 case 0x6605:
2098                         si_pi->cac_weights = cac_weights_mars_pro;
2099                         update_dte_from_pl2 = true;
2100                         break;
2101                 case 0x6600:
2102                 case 0x6606:
2103                 case 0x6620:
2104                 case 0x6604:
2105                         si_pi->cac_weights = cac_weights_mars_xt;
2106                         update_dte_from_pl2 = true;
2107                         break;
2108                 case 0x6611:
2109                 case 0x6613:
2110                 case 0x6608:
2111                         si_pi->cac_weights = cac_weights_oland_pro;
2112                         update_dte_from_pl2 = true;
2113                         break;
2114                 case 0x6610:
2115                         si_pi->cac_weights = cac_weights_oland_xt;
2116                         update_dte_from_pl2 = true;
2117                         break;
2118                 default:
2119                         si_pi->cac_weights = cac_weights_oland;
2120                         si_pi->lcac_config = lcac_oland;
2121                         si_pi->cac_override = cac_override_oland;
2122                         si_pi->powertune_data = &powertune_data_oland;
2123                         si_pi->dte_data = dte_data_oland;
2124                         break;
2125                 }
2126         } else if (adev->asic_type == CHIP_HAINAN) {
2127                 si_pi->cac_weights = cac_weights_hainan;
2128                 si_pi->lcac_config = lcac_oland;
2129                 si_pi->cac_override = cac_override_oland;
2130                 si_pi->powertune_data = &powertune_data_hainan;
2131                 si_pi->dte_data = dte_data_sun_xt;
2132                 update_dte_from_pl2 = true;
2133         } else {
2134                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2135                 return;
2136         }
2137
2138         ni_pi->enable_power_containment = false;
2139         ni_pi->enable_cac = false;
2140         ni_pi->enable_sq_ramping = false;
2141         si_pi->enable_dte = false;
2142
2143         if (si_pi->powertune_data->enable_powertune_by_default) {
2144                 ni_pi->enable_power_containment = true;
2145                 ni_pi->enable_cac = true;
2146                 if (si_pi->dte_data.enable_dte_by_default) {
2147                         si_pi->enable_dte = true;
2148                         if (update_dte_from_pl2)
2149                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2150
2151                 }
2152                 ni_pi->enable_sq_ramping = true;
2153         }
2154
2155         ni_pi->driver_calculate_cac_leakage = true;
2156         ni_pi->cac_configuration_required = true;
2157
2158         if (ni_pi->cac_configuration_required) {
2159                 ni_pi->support_cac_long_term_average = true;
2160                 si_pi->dyn_powertune_data.l2_lta_window_size =
2161                         si_pi->powertune_data->l2_lta_window_size_default;
2162                 si_pi->dyn_powertune_data.lts_truncate =
2163                         si_pi->powertune_data->lts_truncate_default;
2164         } else {
2165                 ni_pi->support_cac_long_term_average = false;
2166                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2167                 si_pi->dyn_powertune_data.lts_truncate = 0;
2168         }
2169
2170         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2171 }
2172
2173 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2174 {
2175         return 1;
2176 }
2177
2178 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2179 {
2180         u32 xclk;
2181         u32 wintime;
2182         u32 cac_window;
2183         u32 cac_window_size;
2184
2185         xclk = amdgpu_asic_get_xclk(adev);
2186
2187         if (xclk == 0)
2188                 return 0;
2189
2190         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2191         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2192
2193         wintime = (cac_window_size * 100) / xclk;
2194
2195         return wintime;
2196 }
2197
2198 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2199 {
2200         return power_in_watts;
2201 }
2202
2203 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2204                                             bool adjust_polarity,
2205                                             u32 tdp_adjustment,
2206                                             u32 *tdp_limit,
2207                                             u32 *near_tdp_limit)
2208 {
2209         u32 adjustment_delta, max_tdp_limit;
2210
2211         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2212                 return -EINVAL;
2213
2214         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2215
2216         if (adjust_polarity) {
2217                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2218                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2219         } else {
2220                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2221                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2222                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2223                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2224                 else
2225                         *near_tdp_limit = 0;
2226         }
2227
2228         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2229                 return -EINVAL;
2230         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2231                 return -EINVAL;
2232
2233         return 0;
2234 }
2235
2236 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2237                                       struct amdgpu_ps *amdgpu_state)
2238 {
2239         struct ni_power_info *ni_pi = ni_get_pi(adev);
2240         struct si_power_info *si_pi = si_get_pi(adev);
2241
2242         if (ni_pi->enable_power_containment) {
2243                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2244                 PP_SIslands_PAPMParameters *papm_parm;
2245                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2246                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2247                 u32 tdp_limit;
2248                 u32 near_tdp_limit;
2249                 int ret;
2250
2251                 if (scaling_factor == 0)
2252                         return -EINVAL;
2253
2254                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2255
2256                 ret = si_calculate_adjusted_tdp_limits(adev,
2257                                                        false, /* ??? */
2258                                                        adev->pm.dpm.tdp_adjustment,
2259                                                        &tdp_limit,
2260                                                        &near_tdp_limit);
2261                 if (ret)
2262                         return ret;
2263
2264                 smc_table->dpm2Params.TDPLimit =
2265                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2266                 smc_table->dpm2Params.NearTDPLimit =
2267                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2268                 smc_table->dpm2Params.SafePowerLimit =
2269                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2270
2271                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2272                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2273                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2274                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2275                                                   sizeof(u32) * 3,
2276                                                   si_pi->sram_end);
2277                 if (ret)
2278                         return ret;
2279
2280                 if (si_pi->enable_ppm) {
2281                         papm_parm = &si_pi->papm_parm;
2282                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2283                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2284                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2285                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2286                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2287                         papm_parm->PlatformPowerLimit = 0xffffffff;
2288                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2289
2290                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2291                                                           (u8 *)papm_parm,
2292                                                           sizeof(PP_SIslands_PAPMParameters),
2293                                                           si_pi->sram_end);
2294                         if (ret)
2295                                 return ret;
2296                 }
2297         }
2298         return 0;
2299 }
2300
2301 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2302                                         struct amdgpu_ps *amdgpu_state)
2303 {
2304         struct ni_power_info *ni_pi = ni_get_pi(adev);
2305         struct si_power_info *si_pi = si_get_pi(adev);
2306
2307         if (ni_pi->enable_power_containment) {
2308                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2309                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2310                 int ret;
2311
2312                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2313
2314                 smc_table->dpm2Params.NearTDPLimit =
2315                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2316                 smc_table->dpm2Params.SafePowerLimit =
2317                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2318
2319                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2320                                                   (si_pi->state_table_start +
2321                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2322                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2323                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2324                                                   sizeof(u32) * 2,
2325                                                   si_pi->sram_end);
2326                 if (ret)
2327                         return ret;
2328         }
2329
2330         return 0;
2331 }
2332
2333 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2334                                                const u16 prev_std_vddc,
2335                                                const u16 curr_std_vddc)
2336 {
2337         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2338         u64 prev_vddc = (u64)prev_std_vddc;
2339         u64 curr_vddc = (u64)curr_std_vddc;
2340         u64 pwr_efficiency_ratio, n, d;
2341
2342         if ((prev_vddc == 0) || (curr_vddc == 0))
2343                 return 0;
2344
2345         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2346         d = prev_vddc * prev_vddc;
2347         pwr_efficiency_ratio = div64_u64(n, d);
2348
2349         if (pwr_efficiency_ratio > (u64)0xFFFF)
2350                 return 0;
2351
2352         return (u16)pwr_efficiency_ratio;
2353 }
2354
2355 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2356                                             struct amdgpu_ps *amdgpu_state)
2357 {
2358         struct si_power_info *si_pi = si_get_pi(adev);
2359
2360         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2361             amdgpu_state->vclk && amdgpu_state->dclk)
2362                 return true;
2363
2364         return false;
2365 }
2366
2367 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2368 {
2369         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2370
2371         return pi;
2372 }
2373
2374 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2375                                                 struct amdgpu_ps *amdgpu_state,
2376                                                 SISLANDS_SMC_SWSTATE *smc_state)
2377 {
2378         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2379         struct ni_power_info *ni_pi = ni_get_pi(adev);
2380         struct  si_ps *state = si_get_ps(amdgpu_state);
2381         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2382         u32 prev_sclk;
2383         u32 max_sclk;
2384         u32 min_sclk;
2385         u16 prev_std_vddc;
2386         u16 curr_std_vddc;
2387         int i;
2388         u16 pwr_efficiency_ratio;
2389         u8 max_ps_percent;
2390         bool disable_uvd_power_tune;
2391         int ret;
2392
2393         if (ni_pi->enable_power_containment == false)
2394                 return 0;
2395
2396         if (state->performance_level_count == 0)
2397                 return -EINVAL;
2398
2399         if (smc_state->levelCount != state->performance_level_count)
2400                 return -EINVAL;
2401
2402         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2403
2404         smc_state->levels[0].dpm2.MaxPS = 0;
2405         smc_state->levels[0].dpm2.NearTDPDec = 0;
2406         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2407         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2408         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2409
2410         for (i = 1; i < state->performance_level_count; i++) {
2411                 prev_sclk = state->performance_levels[i-1].sclk;
2412                 max_sclk  = state->performance_levels[i].sclk;
2413                 if (i == 1)
2414                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2415                 else
2416                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2417
2418                 if (prev_sclk > max_sclk)
2419                         return -EINVAL;
2420
2421                 if ((max_ps_percent == 0) ||
2422                     (prev_sclk == max_sclk) ||
2423                     disable_uvd_power_tune)
2424                         min_sclk = max_sclk;
2425                 else if (i == 1)
2426                         min_sclk = prev_sclk;
2427                 else
2428                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2429
2430                 if (min_sclk < state->performance_levels[0].sclk)
2431                         min_sclk = state->performance_levels[0].sclk;
2432
2433                 if (min_sclk == 0)
2434                         return -EINVAL;
2435
2436                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2437                                                 state->performance_levels[i-1].vddc, &vddc);
2438                 if (ret)
2439                         return ret;
2440
2441                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2442                 if (ret)
2443                         return ret;
2444
2445                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2446                                                 state->performance_levels[i].vddc, &vddc);
2447                 if (ret)
2448                         return ret;
2449
2450                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2451                 if (ret)
2452                         return ret;
2453
2454                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2455                                                                            prev_std_vddc, curr_std_vddc);
2456
2457                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2458                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2459                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2460                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2461                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2462         }
2463
2464         return 0;
2465 }
2466
2467 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2468                                          struct amdgpu_ps *amdgpu_state,
2469                                          SISLANDS_SMC_SWSTATE *smc_state)
2470 {
2471         struct ni_power_info *ni_pi = ni_get_pi(adev);
2472         struct  si_ps *state = si_get_ps(amdgpu_state);
2473         u32 sq_power_throttle, sq_power_throttle2;
2474         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2475         int i;
2476
2477         if (state->performance_level_count == 0)
2478                 return -EINVAL;
2479
2480         if (smc_state->levelCount != state->performance_level_count)
2481                 return -EINVAL;
2482
2483         if (adev->pm.dpm.sq_ramping_threshold == 0)
2484                 return -EINVAL;
2485
2486         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2487                 enable_sq_ramping = false;
2488
2489         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2490                 enable_sq_ramping = false;
2491
2492         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2493                 enable_sq_ramping = false;
2494
2495         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2496                 enable_sq_ramping = false;
2497
2498         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2499                 enable_sq_ramping = false;
2500
2501         for (i = 0; i < state->performance_level_count; i++) {
2502                 sq_power_throttle = 0;
2503                 sq_power_throttle2 = 0;
2504
2505                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2506                     enable_sq_ramping) {
2507                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2508                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2509                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2510                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2511                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2512                 } else {
2513                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2514                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2515                 }
2516
2517                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2518                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2519         }
2520
2521         return 0;
2522 }
2523
2524 static int si_enable_power_containment(struct amdgpu_device *adev,
2525                                        struct amdgpu_ps *amdgpu_new_state,
2526                                        bool enable)
2527 {
2528         struct ni_power_info *ni_pi = ni_get_pi(adev);
2529         PPSMC_Result smc_result;
2530         int ret = 0;
2531
2532         if (ni_pi->enable_power_containment) {
2533                 if (enable) {
2534                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2535                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2536                                 if (smc_result != PPSMC_Result_OK) {
2537                                         ret = -EINVAL;
2538                                         ni_pi->pc_enabled = false;
2539                                 } else {
2540                                         ni_pi->pc_enabled = true;
2541                                 }
2542                         }
2543                 } else {
2544                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2545                         if (smc_result != PPSMC_Result_OK)
2546                                 ret = -EINVAL;
2547                         ni_pi->pc_enabled = false;
2548                 }
2549         }
2550
2551         return ret;
2552 }
2553
2554 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2555 {
2556         struct si_power_info *si_pi = si_get_pi(adev);
2557         int ret = 0;
2558         struct si_dte_data *dte_data = &si_pi->dte_data;
2559         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2560         u32 table_size;
2561         u8 tdep_count;
2562         u32 i;
2563
2564         if (dte_data == NULL)
2565                 si_pi->enable_dte = false;
2566
2567         if (si_pi->enable_dte == false)
2568                 return 0;
2569
2570         if (dte_data->k <= 0)
2571                 return -EINVAL;
2572
2573         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2574         if (dte_tables == NULL) {
2575                 si_pi->enable_dte = false;
2576                 return -ENOMEM;
2577         }
2578
2579         table_size = dte_data->k;
2580
2581         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2582                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2583
2584         tdep_count = dte_data->tdep_count;
2585         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2586                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2587
2588         dte_tables->K = cpu_to_be32(table_size);
2589         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2590         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2591         dte_tables->WindowSize = dte_data->window_size;
2592         dte_tables->temp_select = dte_data->temp_select;
2593         dte_tables->DTE_mode = dte_data->dte_mode;
2594         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2595
2596         if (tdep_count > 0)
2597                 table_size--;
2598
2599         for (i = 0; i < table_size; i++) {
2600                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2601                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2602         }
2603
2604         dte_tables->Tdep_count = tdep_count;
2605
2606         for (i = 0; i < (u32)tdep_count; i++) {
2607                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2608                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2609                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2610         }
2611
2612         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2613                                           (u8 *)dte_tables,
2614                                           sizeof(Smc_SIslands_DTE_Configuration),
2615                                           si_pi->sram_end);
2616         kfree(dte_tables);
2617
2618         return ret;
2619 }
2620
2621 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2622                                           u16 *max, u16 *min)
2623 {
2624         struct si_power_info *si_pi = si_get_pi(adev);
2625         struct amdgpu_cac_leakage_table *table =
2626                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2627         u32 i;
2628         u32 v0_loadline;
2629
2630         if (table == NULL)
2631                 return -EINVAL;
2632
2633         *max = 0;
2634         *min = 0xFFFF;
2635
2636         for (i = 0; i < table->count; i++) {
2637                 if (table->entries[i].vddc > *max)
2638                         *max = table->entries[i].vddc;
2639                 if (table->entries[i].vddc < *min)
2640                         *min = table->entries[i].vddc;
2641         }
2642
2643         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2644                 return -EINVAL;
2645
2646         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2647
2648         if (v0_loadline > 0xFFFFUL)
2649                 return -EINVAL;
2650
2651         *min = (u16)v0_loadline;
2652
2653         if ((*min > *max) || (*max == 0) || (*min == 0))
2654                 return -EINVAL;
2655
2656         return 0;
2657 }
2658
2659 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2660 {
2661         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2662                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2663 }
2664
2665 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2666                                      PP_SIslands_CacConfig *cac_tables,
2667                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2668                                      u16 t0, u16 t_step)
2669 {
2670         struct si_power_info *si_pi = si_get_pi(adev);
2671         u32 leakage;
2672         unsigned int i, j;
2673         s32 t;
2674         u32 smc_leakage;
2675         u32 scaling_factor;
2676         u16 voltage;
2677
2678         scaling_factor = si_get_smc_power_scaling_factor(adev);
2679
2680         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2681                 t = (1000 * (i * t_step + t0));
2682
2683                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2684                         voltage = vddc_max - (vddc_step * j);
2685
2686                         si_calculate_leakage_for_v_and_t(adev,
2687                                                          &si_pi->powertune_data->leakage_coefficients,
2688                                                          voltage,
2689                                                          t,
2690                                                          si_pi->dyn_powertune_data.cac_leakage,
2691                                                          &leakage);
2692
2693                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2694
2695                         if (smc_leakage > 0xFFFF)
2696                                 smc_leakage = 0xFFFF;
2697
2698                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2699                                 cpu_to_be16((u16)smc_leakage);
2700                 }
2701         }
2702         return 0;
2703 }
2704
2705 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2706                                             PP_SIslands_CacConfig *cac_tables,
2707                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2708 {
2709         struct si_power_info *si_pi = si_get_pi(adev);
2710         u32 leakage;
2711         unsigned int i, j;
2712         u32 smc_leakage;
2713         u32 scaling_factor;
2714         u16 voltage;
2715
2716         scaling_factor = si_get_smc_power_scaling_factor(adev);
2717
2718         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2719                 voltage = vddc_max - (vddc_step * j);
2720
2721                 si_calculate_leakage_for_v(adev,
2722                                            &si_pi->powertune_data->leakage_coefficients,
2723                                            si_pi->powertune_data->fixed_kt,
2724                                            voltage,
2725                                            si_pi->dyn_powertune_data.cac_leakage,
2726                                            &leakage);
2727
2728                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2729
2730                 if (smc_leakage > 0xFFFF)
2731                         smc_leakage = 0xFFFF;
2732
2733                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2734                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2735                                 cpu_to_be16((u16)smc_leakage);
2736         }
2737         return 0;
2738 }
2739
2740 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2741 {
2742         struct ni_power_info *ni_pi = ni_get_pi(adev);
2743         struct si_power_info *si_pi = si_get_pi(adev);
2744         PP_SIslands_CacConfig *cac_tables = NULL;
2745         u16 vddc_max, vddc_min, vddc_step;
2746         u16 t0, t_step;
2747         u32 load_line_slope, reg;
2748         int ret = 0;
2749         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2750
2751         if (ni_pi->enable_cac == false)
2752                 return 0;
2753
2754         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2755         if (!cac_tables)
2756                 return -ENOMEM;
2757
2758         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2759         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2760         WREG32(CG_CAC_CTRL, reg);
2761
2762         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2763         si_pi->dyn_powertune_data.dc_pwr_value =
2764                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2765         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2766         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2767
2768         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2769
2770         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2771         if (ret)
2772                 goto done_free;
2773
2774         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2775         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2776         t_step = 4;
2777         t0 = 60;
2778
2779         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2780                 ret = si_init_dte_leakage_table(adev, cac_tables,
2781                                                 vddc_max, vddc_min, vddc_step,
2782                                                 t0, t_step);
2783         else
2784                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2785                                                        vddc_max, vddc_min, vddc_step);
2786         if (ret)
2787                 goto done_free;
2788
2789         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2790
2791         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2792         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2793         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2794         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2795         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2796         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2797         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2798         cac_tables->calculation_repeats = cpu_to_be32(2);
2799         cac_tables->dc_cac = cpu_to_be32(0);
2800         cac_tables->log2_PG_LKG_SCALE = 12;
2801         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2802         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2803         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2804
2805         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2806                                           (u8 *)cac_tables,
2807                                           sizeof(PP_SIslands_CacConfig),
2808                                           si_pi->sram_end);
2809
2810         if (ret)
2811                 goto done_free;
2812
2813         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2814
2815 done_free:
2816         if (ret) {
2817                 ni_pi->enable_cac = false;
2818                 ni_pi->enable_power_containment = false;
2819         }
2820
2821         kfree(cac_tables);
2822
2823         return ret;
2824 }
2825
2826 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2827                                            const struct si_cac_config_reg *cac_config_regs)
2828 {
2829         const struct si_cac_config_reg *config_regs = cac_config_regs;
2830         u32 data = 0, offset;
2831
2832         if (!config_regs)
2833                 return -EINVAL;
2834
2835         while (config_regs->offset != 0xFFFFFFFF) {
2836                 switch (config_regs->type) {
2837                 case SISLANDS_CACCONFIG_CGIND:
2838                         offset = SMC_CG_IND_START + config_regs->offset;
2839                         if (offset < SMC_CG_IND_END)
2840                                 data = RREG32_SMC(offset);
2841                         break;
2842                 default:
2843                         data = RREG32(config_regs->offset);
2844                         break;
2845                 }
2846
2847                 data &= ~config_regs->mask;
2848                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2849
2850                 switch (config_regs->type) {
2851                 case SISLANDS_CACCONFIG_CGIND:
2852                         offset = SMC_CG_IND_START + config_regs->offset;
2853                         if (offset < SMC_CG_IND_END)
2854                                 WREG32_SMC(offset, data);
2855                         break;
2856                 default:
2857                         WREG32(config_regs->offset, data);
2858                         break;
2859                 }
2860                 config_regs++;
2861         }
2862         return 0;
2863 }
2864
2865 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2866 {
2867         struct ni_power_info *ni_pi = ni_get_pi(adev);
2868         struct si_power_info *si_pi = si_get_pi(adev);
2869         int ret;
2870
2871         if ((ni_pi->enable_cac == false) ||
2872             (ni_pi->cac_configuration_required == false))
2873                 return 0;
2874
2875         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2876         if (ret)
2877                 return ret;
2878         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2879         if (ret)
2880                 return ret;
2881         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2882         if (ret)
2883                 return ret;
2884
2885         return 0;
2886 }
2887
2888 static int si_enable_smc_cac(struct amdgpu_device *adev,
2889                              struct amdgpu_ps *amdgpu_new_state,
2890                              bool enable)
2891 {
2892         struct ni_power_info *ni_pi = ni_get_pi(adev);
2893         struct si_power_info *si_pi = si_get_pi(adev);
2894         PPSMC_Result smc_result;
2895         int ret = 0;
2896
2897         if (ni_pi->enable_cac) {
2898                 if (enable) {
2899                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2900                                 if (ni_pi->support_cac_long_term_average) {
2901                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2902                                         if (smc_result != PPSMC_Result_OK)
2903                                                 ni_pi->support_cac_long_term_average = false;
2904                                 }
2905
2906                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2907                                 if (smc_result != PPSMC_Result_OK) {
2908                                         ret = -EINVAL;
2909                                         ni_pi->cac_enabled = false;
2910                                 } else {
2911                                         ni_pi->cac_enabled = true;
2912                                 }
2913
2914                                 if (si_pi->enable_dte) {
2915                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2916                                         if (smc_result != PPSMC_Result_OK)
2917                                                 ret = -EINVAL;
2918                                 }
2919                         }
2920                 } else if (ni_pi->cac_enabled) {
2921                         if (si_pi->enable_dte)
2922                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2923
2924                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2925
2926                         ni_pi->cac_enabled = false;
2927
2928                         if (ni_pi->support_cac_long_term_average)
2929                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2930                 }
2931         }
2932         return ret;
2933 }
2934
2935 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2936 {
2937         struct ni_power_info *ni_pi = ni_get_pi(adev);
2938         struct si_power_info *si_pi = si_get_pi(adev);
2939         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2940         SISLANDS_SMC_SCLK_VALUE sclk_params;
2941         u32 fb_div, p_div;
2942         u32 clk_s, clk_v;
2943         u32 sclk = 0;
2944         int ret = 0;
2945         u32 tmp;
2946         int i;
2947
2948         if (si_pi->spll_table_start == 0)
2949                 return -EINVAL;
2950
2951         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2952         if (spll_table == NULL)
2953                 return -ENOMEM;
2954
2955         for (i = 0; i < 256; i++) {
2956                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2957                 if (ret)
2958                         break;
2959                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2960                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2961                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2962                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2963
2964                 fb_div &= ~0x00001FFF;
2965                 fb_div >>= 1;
2966                 clk_v >>= 6;
2967
2968                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2969                         ret = -EINVAL;
2970                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2971                         ret = -EINVAL;
2972                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2973                         ret = -EINVAL;
2974                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2975                         ret = -EINVAL;
2976
2977                 if (ret)
2978                         break;
2979
2980                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2981                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2982                 spll_table->freq[i] = cpu_to_be32(tmp);
2983
2984                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2985                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2986                 spll_table->ss[i] = cpu_to_be32(tmp);
2987
2988                 sclk += 512;
2989         }
2990
2991
2992         if (!ret)
2993                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2994                                                   (u8 *)spll_table,
2995                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2996                                                   si_pi->sram_end);
2997
2998         if (ret)
2999                 ni_pi->enable_power_containment = false;
3000
3001         kfree(spll_table);
3002
3003         return ret;
3004 }
3005
3006 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3007                                                    u16 vce_voltage)
3008 {
3009         u16 highest_leakage = 0;
3010         struct si_power_info *si_pi = si_get_pi(adev);
3011         int i;
3012
3013         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3014                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3015                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3016         }
3017
3018         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3019                 return highest_leakage;
3020
3021         return vce_voltage;
3022 }
3023
3024 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3025                                     u32 evclk, u32 ecclk, u16 *voltage)
3026 {
3027         u32 i;
3028         int ret = -EINVAL;
3029         struct amdgpu_vce_clock_voltage_dependency_table *table =
3030                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3031
3032         if (((evclk == 0) && (ecclk == 0)) ||
3033             (table && (table->count == 0))) {
3034                 *voltage = 0;
3035                 return 0;
3036         }
3037
3038         for (i = 0; i < table->count; i++) {
3039                 if ((evclk <= table->entries[i].evclk) &&
3040                     (ecclk <= table->entries[i].ecclk)) {
3041                         *voltage = table->entries[i].v;
3042                         ret = 0;
3043                         break;
3044                 }
3045         }
3046
3047         /* if no match return the highest voltage */
3048         if (ret)
3049                 *voltage = table->entries[table->count - 1].v;
3050
3051         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3052
3053         return ret;
3054 }
3055
3056 static bool si_dpm_vblank_too_short(void *handle)
3057 {
3058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3059         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3060         /* we never hit the non-gddr5 limit so disable it */
3061         u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3062
3063         if (vblank_time < switch_limit)
3064                 return true;
3065         else
3066                 return false;
3067
3068 }
3069
3070 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3071                                 u32 arb_freq_src, u32 arb_freq_dest)
3072 {
3073         u32 mc_arb_dram_timing;
3074         u32 mc_arb_dram_timing2;
3075         u32 burst_time;
3076         u32 mc_cg_config;
3077
3078         switch (arb_freq_src) {
3079         case MC_CG_ARB_FREQ_F0:
3080                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3081                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3082                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3083                 break;
3084         case MC_CG_ARB_FREQ_F1:
3085                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3086                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3087                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3088                 break;
3089         case MC_CG_ARB_FREQ_F2:
3090                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3091                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3092                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3093                 break;
3094         case MC_CG_ARB_FREQ_F3:
3095                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3096                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3097                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3098                 break;
3099         default:
3100                 return -EINVAL;
3101         }
3102
3103         switch (arb_freq_dest) {
3104         case MC_CG_ARB_FREQ_F0:
3105                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3106                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3107                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3108                 break;
3109         case MC_CG_ARB_FREQ_F1:
3110                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3111                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3112                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3113                 break;
3114         case MC_CG_ARB_FREQ_F2:
3115                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3116                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3117                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3118                 break;
3119         case MC_CG_ARB_FREQ_F3:
3120                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3121                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3122                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3123                 break;
3124         default:
3125                 return -EINVAL;
3126         }
3127
3128         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3129         WREG32(MC_CG_CONFIG, mc_cg_config);
3130         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3131
3132         return 0;
3133 }
3134
3135 static void ni_update_current_ps(struct amdgpu_device *adev,
3136                           struct amdgpu_ps *rps)
3137 {
3138         struct si_ps *new_ps = si_get_ps(rps);
3139         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3140         struct ni_power_info *ni_pi = ni_get_pi(adev);
3141
3142         eg_pi->current_rps = *rps;
3143         ni_pi->current_ps = *new_ps;
3144         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3145         adev->pm.dpm.current_ps = &eg_pi->current_rps;
3146 }
3147
3148 static void ni_update_requested_ps(struct amdgpu_device *adev,
3149                             struct amdgpu_ps *rps)
3150 {
3151         struct si_ps *new_ps = si_get_ps(rps);
3152         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3153         struct ni_power_info *ni_pi = ni_get_pi(adev);
3154
3155         eg_pi->requested_rps = *rps;
3156         ni_pi->requested_ps = *new_ps;
3157         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3158         adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3159 }
3160
3161 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3162                                            struct amdgpu_ps *new_ps,
3163                                            struct amdgpu_ps *old_ps)
3164 {
3165         struct si_ps *new_state = si_get_ps(new_ps);
3166         struct si_ps *current_state = si_get_ps(old_ps);
3167
3168         if ((new_ps->vclk == old_ps->vclk) &&
3169             (new_ps->dclk == old_ps->dclk))
3170                 return;
3171
3172         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3173             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3174                 return;
3175
3176         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3177 }
3178
3179 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3180                                           struct amdgpu_ps *new_ps,
3181                                           struct amdgpu_ps *old_ps)
3182 {
3183         struct si_ps *new_state = si_get_ps(new_ps);
3184         struct si_ps *current_state = si_get_ps(old_ps);
3185
3186         if ((new_ps->vclk == old_ps->vclk) &&
3187             (new_ps->dclk == old_ps->dclk))
3188                 return;
3189
3190         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3191             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3192                 return;
3193
3194         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3195 }
3196
3197 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3198 {
3199         unsigned int i;
3200
3201         for (i = 0; i < table->count; i++)
3202                 if (voltage <= table->entries[i].value)
3203                         return table->entries[i].value;
3204
3205         return table->entries[table->count - 1].value;
3206 }
3207
3208 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3209                                 u32 max_clock, u32 requested_clock)
3210 {
3211         unsigned int i;
3212
3213         if ((clocks == NULL) || (clocks->count == 0))
3214                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3215
3216         for (i = 0; i < clocks->count; i++) {
3217                 if (clocks->values[i] >= requested_clock)
3218                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3219         }
3220
3221         return (clocks->values[clocks->count - 1] < max_clock) ?
3222                 clocks->values[clocks->count - 1] : max_clock;
3223 }
3224
3225 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3226                               u32 max_mclk, u32 requested_mclk)
3227 {
3228         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3229                                     max_mclk, requested_mclk);
3230 }
3231
3232 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3233                               u32 max_sclk, u32 requested_sclk)
3234 {
3235         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3236                                     max_sclk, requested_sclk);
3237 }
3238
3239 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3240                                                             u32 *max_clock)
3241 {
3242         u32 i, clock = 0;
3243
3244         if ((table == NULL) || (table->count == 0)) {
3245                 *max_clock = clock;
3246                 return;
3247         }
3248
3249         for (i = 0; i < table->count; i++) {
3250                 if (clock < table->entries[i].clk)
3251                         clock = table->entries[i].clk;
3252         }
3253         *max_clock = clock;
3254 }
3255
3256 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3257                                                u32 clock, u16 max_voltage, u16 *voltage)
3258 {
3259         u32 i;
3260
3261         if ((table == NULL) || (table->count == 0))
3262                 return;
3263
3264         for (i= 0; i < table->count; i++) {
3265                 if (clock <= table->entries[i].clk) {
3266                         if (*voltage < table->entries[i].v)
3267                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3268                                            table->entries[i].v : max_voltage);
3269                         return;
3270                 }
3271         }
3272
3273         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3274 }
3275
3276 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3277                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3278                                           struct rv7xx_pl *pl)
3279 {
3280
3281         if ((pl->mclk == 0) || (pl->sclk == 0))
3282                 return;
3283
3284         if (pl->mclk == pl->sclk)
3285                 return;
3286
3287         if (pl->mclk > pl->sclk) {
3288                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3289                         pl->sclk = btc_get_valid_sclk(adev,
3290                                                       max_limits->sclk,
3291                                                       (pl->mclk +
3292                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3293                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3294         } else {
3295                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3296                         pl->mclk = btc_get_valid_mclk(adev,
3297                                                       max_limits->mclk,
3298                                                       pl->sclk -
3299                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3300         }
3301 }
3302
3303 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3304                                           u16 max_vddc, u16 max_vddci,
3305                                           u16 *vddc, u16 *vddci)
3306 {
3307         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3308         u16 new_voltage;
3309
3310         if ((0 == *vddc) || (0 == *vddci))
3311                 return;
3312
3313         if (*vddc > *vddci) {
3314                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3315                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3316                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3317                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3318                 }
3319         } else {
3320                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3321                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3322                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3323                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3324                 }
3325         }
3326 }
3327
3328 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3329                             u32 *p, u32 *u)
3330 {
3331         u32 b_c = 0;
3332         u32 i_c;
3333         u32 tmp;
3334
3335         i_c = (i * r_c) / 100;
3336         tmp = i_c >> p_b;
3337
3338         while (tmp) {
3339                 b_c++;
3340                 tmp >>= 1;
3341         }
3342
3343         *u = (b_c + 1) / 2;
3344         *p = i_c / (1 << (2 * (*u)));
3345 }
3346
3347 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3348 {
3349         u32 k, a, ah, al;
3350         u32 t1;
3351
3352         if ((fl == 0) || (fh == 0) || (fl > fh))
3353                 return -EINVAL;
3354
3355         k = (100 * fh) / fl;
3356         t1 = (t * (k - 100));
3357         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3358         a = (a + 5) / 10;
3359         ah = ((a * t) + 5000) / 10000;
3360         al = a - ah;
3361
3362         *th = t - ah;
3363         *tl = t + al;
3364
3365         return 0;
3366 }
3367
3368 static bool r600_is_uvd_state(u32 class, u32 class2)
3369 {
3370         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3371                 return true;
3372         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3373                 return true;
3374         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3375                 return true;
3376         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3377                 return true;
3378         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3379                 return true;
3380         return false;
3381 }
3382
3383 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3384 {
3385         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3386 }
3387
3388 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3389 {
3390         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3391         u16 vddc;
3392
3393         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3394                 pi->max_vddc = 0;
3395         else
3396                 pi->max_vddc = vddc;
3397 }
3398
3399 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3400 {
3401         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3402         struct amdgpu_atom_ss ss;
3403
3404         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3405                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3406         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3407                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3408
3409         if (pi->sclk_ss || pi->mclk_ss)
3410                 pi->dynamic_ss = true;
3411         else
3412                 pi->dynamic_ss = false;
3413 }
3414
3415
3416 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3417                                         struct amdgpu_ps *rps)
3418 {
3419         struct  si_ps *ps = si_get_ps(rps);
3420         struct amdgpu_clock_and_voltage_limits *max_limits;
3421         bool disable_mclk_switching = false;
3422         bool disable_sclk_switching = false;
3423         u32 mclk, sclk;
3424         u16 vddc, vddci, min_vce_voltage = 0;
3425         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3426         u32 max_sclk = 0, max_mclk = 0;
3427         int i;
3428
3429         if (adev->asic_type == CHIP_HAINAN) {
3430                 if ((adev->pdev->revision == 0x81) ||
3431                     (adev->pdev->revision == 0x83) ||
3432                     (adev->pdev->revision == 0xC3) ||
3433                     (adev->pdev->device == 0x6664) ||
3434                     (adev->pdev->device == 0x6665) ||
3435                     (adev->pdev->device == 0x6667)) {
3436                         max_sclk = 75000;
3437                 }
3438                 if ((adev->pdev->revision == 0xC3) ||
3439                     (adev->pdev->device == 0x6665)) {
3440                         max_sclk = 60000;
3441                         max_mclk = 80000;
3442                 }
3443         } else if (adev->asic_type == CHIP_OLAND) {
3444                 if ((adev->pdev->revision == 0xC7) ||
3445                     (adev->pdev->revision == 0x80) ||
3446                     (adev->pdev->revision == 0x81) ||
3447                     (adev->pdev->revision == 0x83) ||
3448                     (adev->pdev->revision == 0x87) ||
3449                     (adev->pdev->device == 0x6604) ||
3450                     (adev->pdev->device == 0x6605)) {
3451                         max_sclk = 75000;
3452                 }
3453         }
3454
3455         if (rps->vce_active) {
3456                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3457                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3458                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3459                                          &min_vce_voltage);
3460         } else {
3461                 rps->evclk = 0;
3462                 rps->ecclk = 0;
3463         }
3464
3465         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3466             si_dpm_vblank_too_short(adev))
3467                 disable_mclk_switching = true;
3468
3469         if (rps->vclk || rps->dclk) {
3470                 disable_mclk_switching = true;
3471                 disable_sclk_switching = true;
3472         }
3473
3474         if (adev->pm.ac_power)
3475                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3476         else
3477                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3478
3479         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3480                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3481                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3482         }
3483         if (adev->pm.ac_power == false) {
3484                 for (i = 0; i < ps->performance_level_count; i++) {
3485                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3486                                 ps->performance_levels[i].mclk = max_limits->mclk;
3487                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3488                                 ps->performance_levels[i].sclk = max_limits->sclk;
3489                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3490                                 ps->performance_levels[i].vddc = max_limits->vddc;
3491                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3492                                 ps->performance_levels[i].vddci = max_limits->vddci;
3493                 }
3494         }
3495
3496         /* limit clocks to max supported clocks based on voltage dependency tables */
3497         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3498                                                         &max_sclk_vddc);
3499         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3500                                                         &max_mclk_vddci);
3501         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3502                                                         &max_mclk_vddc);
3503
3504         for (i = 0; i < ps->performance_level_count; i++) {
3505                 if (max_sclk_vddc) {
3506                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3507                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3508                 }
3509                 if (max_mclk_vddci) {
3510                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3511                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3512                 }
3513                 if (max_mclk_vddc) {
3514                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3515                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3516                 }
3517                 if (max_mclk) {
3518                         if (ps->performance_levels[i].mclk > max_mclk)
3519                                 ps->performance_levels[i].mclk = max_mclk;
3520                 }
3521                 if (max_sclk) {
3522                         if (ps->performance_levels[i].sclk > max_sclk)
3523                                 ps->performance_levels[i].sclk = max_sclk;
3524                 }
3525         }
3526
3527         /* XXX validate the min clocks required for display */
3528
3529         if (disable_mclk_switching) {
3530                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3531                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3532         } else {
3533                 mclk = ps->performance_levels[0].mclk;
3534                 vddci = ps->performance_levels[0].vddci;
3535         }
3536
3537         if (disable_sclk_switching) {
3538                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3539                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3540         } else {
3541                 sclk = ps->performance_levels[0].sclk;
3542                 vddc = ps->performance_levels[0].vddc;
3543         }
3544
3545         if (rps->vce_active) {
3546                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3547                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3548                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3549                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3550         }
3551
3552         /* adjusted low state */
3553         ps->performance_levels[0].sclk = sclk;
3554         ps->performance_levels[0].mclk = mclk;
3555         ps->performance_levels[0].vddc = vddc;
3556         ps->performance_levels[0].vddci = vddci;
3557
3558         if (disable_sclk_switching) {
3559                 sclk = ps->performance_levels[0].sclk;
3560                 for (i = 1; i < ps->performance_level_count; i++) {
3561                         if (sclk < ps->performance_levels[i].sclk)
3562                                 sclk = ps->performance_levels[i].sclk;
3563                 }
3564                 for (i = 0; i < ps->performance_level_count; i++) {
3565                         ps->performance_levels[i].sclk = sclk;
3566                         ps->performance_levels[i].vddc = vddc;
3567                 }
3568         } else {
3569                 for (i = 1; i < ps->performance_level_count; i++) {
3570                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3571                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3572                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3573                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3574                 }
3575         }
3576
3577         if (disable_mclk_switching) {
3578                 mclk = ps->performance_levels[0].mclk;
3579                 for (i = 1; i < ps->performance_level_count; i++) {
3580                         if (mclk < ps->performance_levels[i].mclk)
3581                                 mclk = ps->performance_levels[i].mclk;
3582                 }
3583                 for (i = 0; i < ps->performance_level_count; i++) {
3584                         ps->performance_levels[i].mclk = mclk;
3585                         ps->performance_levels[i].vddci = vddci;
3586                 }
3587         } else {
3588                 for (i = 1; i < ps->performance_level_count; i++) {
3589                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3590                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3591                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3592                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3593                 }
3594         }
3595
3596         for (i = 0; i < ps->performance_level_count; i++)
3597                 btc_adjust_clock_combinations(adev, max_limits,
3598                                               &ps->performance_levels[i]);
3599
3600         for (i = 0; i < ps->performance_level_count; i++) {
3601                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3602                         ps->performance_levels[i].vddc = min_vce_voltage;
3603                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3604                                                    ps->performance_levels[i].sclk,
3605                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3606                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3607                                                    ps->performance_levels[i].mclk,
3608                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3609                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3610                                                    ps->performance_levels[i].mclk,
3611                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3612                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3613                                                    adev->clock.current_dispclk,
3614                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3615         }
3616
3617         for (i = 0; i < ps->performance_level_count; i++) {
3618                 btc_apply_voltage_delta_rules(adev,
3619                                               max_limits->vddc, max_limits->vddci,
3620                                               &ps->performance_levels[i].vddc,
3621                                               &ps->performance_levels[i].vddci);
3622         }
3623
3624         ps->dc_compatible = true;
3625         for (i = 0; i < ps->performance_level_count; i++) {
3626                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3627                         ps->dc_compatible = false;
3628         }
3629 }
3630
3631 #if 0
3632 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3633                                      u16 reg_offset, u32 *value)
3634 {
3635         struct si_power_info *si_pi = si_get_pi(adev);
3636
3637         return amdgpu_si_read_smc_sram_dword(adev,
3638                                              si_pi->soft_regs_start + reg_offset, value,
3639                                              si_pi->sram_end);
3640 }
3641 #endif
3642
3643 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3644                                       u16 reg_offset, u32 value)
3645 {
3646         struct si_power_info *si_pi = si_get_pi(adev);
3647
3648         return amdgpu_si_write_smc_sram_dword(adev,
3649                                               si_pi->soft_regs_start + reg_offset,
3650                                               value, si_pi->sram_end);
3651 }
3652
3653 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3654 {
3655         bool ret = false;
3656         u32 tmp, width, row, column, bank, density;
3657         bool is_memory_gddr5, is_special;
3658
3659         tmp = RREG32(MC_SEQ_MISC0);
3660         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3661         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3662                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3663
3664         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3665         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3666
3667         tmp = RREG32(MC_ARB_RAMCFG);
3668         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3669         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3670         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3671
3672         density = (1 << (row + column - 20 + bank)) * width;
3673
3674         if ((adev->pdev->device == 0x6819) &&
3675             is_memory_gddr5 && is_special && (density == 0x400))
3676                 ret = true;
3677
3678         return ret;
3679 }
3680
3681 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3682 {
3683         struct si_power_info *si_pi = si_get_pi(adev);
3684         u16 vddc, count = 0;
3685         int i, ret;
3686
3687         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3688                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3689
3690                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3691                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3692                         si_pi->leakage_voltage.entries[count].leakage_index =
3693                                 SISLANDS_LEAKAGE_INDEX0 + i;
3694                         count++;
3695                 }
3696         }
3697         si_pi->leakage_voltage.count = count;
3698 }
3699
3700 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3701                                                      u32 index, u16 *leakage_voltage)
3702 {
3703         struct si_power_info *si_pi = si_get_pi(adev);
3704         int i;
3705
3706         if (leakage_voltage == NULL)
3707                 return -EINVAL;
3708
3709         if ((index & 0xff00) != 0xff00)
3710                 return -EINVAL;
3711
3712         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3713                 return -EINVAL;
3714
3715         if (index < SISLANDS_LEAKAGE_INDEX0)
3716                 return -EINVAL;
3717
3718         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3719                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3720                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3721                         return 0;
3722                 }
3723         }
3724         return -EAGAIN;
3725 }
3726
3727 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3728 {
3729         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3730         bool want_thermal_protection;
3731         enum amdgpu_dpm_event_src dpm_event_src;
3732
3733         switch (sources) {
3734         case 0:
3735         default:
3736                 want_thermal_protection = false;
3737                 break;
3738         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3739                 want_thermal_protection = true;
3740                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3741                 break;
3742         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3743                 want_thermal_protection = true;
3744                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3745                 break;
3746         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3747               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3748                 want_thermal_protection = true;
3749                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3750                 break;
3751         }
3752
3753         if (want_thermal_protection) {
3754                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3755                 if (pi->thermal_protection)
3756                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3757         } else {
3758                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3759         }
3760 }
3761
3762 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3763                                            enum amdgpu_dpm_auto_throttle_src source,
3764                                            bool enable)
3765 {
3766         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3767
3768         if (enable) {
3769                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3770                         pi->active_auto_throttle_sources |= 1 << source;
3771                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3772                 }
3773         } else {
3774                 if (pi->active_auto_throttle_sources & (1 << source)) {
3775                         pi->active_auto_throttle_sources &= ~(1 << source);
3776                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3777                 }
3778         }
3779 }
3780
3781 static void si_start_dpm(struct amdgpu_device *adev)
3782 {
3783         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3784 }
3785
3786 static void si_stop_dpm(struct amdgpu_device *adev)
3787 {
3788         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3789 }
3790
3791 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3792 {
3793         if (enable)
3794                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3795         else
3796                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3797
3798 }
3799
3800 #if 0
3801 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3802                                                u32 thermal_level)
3803 {
3804         PPSMC_Result ret;
3805
3806         if (thermal_level == 0) {
3807                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3808                 if (ret == PPSMC_Result_OK)
3809                         return 0;
3810                 else
3811                         return -EINVAL;
3812         }
3813         return 0;
3814 }
3815
3816 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3817 {
3818         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3819 }
3820 #endif
3821
3822 #if 0
3823 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3824 {
3825         if (ac_power)
3826                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3827                         0 : -EINVAL;
3828
3829         return 0;
3830 }
3831 #endif
3832
3833 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3834                                                       PPSMC_Msg msg, u32 parameter)
3835 {
3836         WREG32(SMC_SCRATCH0, parameter);
3837         return amdgpu_si_send_msg_to_smc(adev, msg);
3838 }
3839
3840 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3841 {
3842         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3843                 return -EINVAL;
3844
3845         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3846                 0 : -EINVAL;
3847 }
3848
3849 static int si_dpm_force_performance_level(void *handle,
3850                                    enum amd_dpm_forced_level level)
3851 {
3852         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3853         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3854         struct  si_ps *ps = si_get_ps(rps);
3855         u32 levels = ps->performance_level_count;
3856
3857         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3858                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3859                         return -EINVAL;
3860
3861                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3862                         return -EINVAL;
3863         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3864                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3865                         return -EINVAL;
3866
3867                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3868                         return -EINVAL;
3869         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3870                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3871                         return -EINVAL;
3872
3873                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3874                         return -EINVAL;
3875         }
3876
3877         adev->pm.dpm.forced_level = level;
3878
3879         return 0;
3880 }
3881
3882 #if 0
3883 static int si_set_boot_state(struct amdgpu_device *adev)
3884 {
3885         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3886                 0 : -EINVAL;
3887 }
3888 #endif
3889
3890 static int si_set_sw_state(struct amdgpu_device *adev)
3891 {
3892         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3893                 0 : -EINVAL;
3894 }
3895
3896 static int si_halt_smc(struct amdgpu_device *adev)
3897 {
3898         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3899                 return -EINVAL;
3900
3901         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3902                 0 : -EINVAL;
3903 }
3904
3905 static int si_resume_smc(struct amdgpu_device *adev)
3906 {
3907         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3908                 return -EINVAL;
3909
3910         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3911                 0 : -EINVAL;
3912 }
3913
3914 static void si_dpm_start_smc(struct amdgpu_device *adev)
3915 {
3916         amdgpu_si_program_jump_on_start(adev);
3917         amdgpu_si_start_smc(adev);
3918         amdgpu_si_smc_clock(adev, true);
3919 }
3920
3921 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3922 {
3923         amdgpu_si_reset_smc(adev);
3924         amdgpu_si_smc_clock(adev, false);
3925 }
3926
3927 static int si_process_firmware_header(struct amdgpu_device *adev)
3928 {
3929         struct si_power_info *si_pi = si_get_pi(adev);
3930         u32 tmp;
3931         int ret;
3932
3933         ret = amdgpu_si_read_smc_sram_dword(adev,
3934                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3935                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3936                                             &tmp, si_pi->sram_end);
3937         if (ret)
3938                 return ret;
3939
3940         si_pi->state_table_start = tmp;
3941
3942         ret = amdgpu_si_read_smc_sram_dword(adev,
3943                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3944                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3945                                             &tmp, si_pi->sram_end);
3946         if (ret)
3947                 return ret;
3948
3949         si_pi->soft_regs_start = tmp;
3950
3951         ret = amdgpu_si_read_smc_sram_dword(adev,
3952                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3953                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3954                                             &tmp, si_pi->sram_end);
3955         if (ret)
3956                 return ret;
3957
3958         si_pi->mc_reg_table_start = tmp;
3959
3960         ret = amdgpu_si_read_smc_sram_dword(adev,
3961                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3962                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3963                                             &tmp, si_pi->sram_end);
3964         if (ret)
3965                 return ret;
3966
3967         si_pi->fan_table_start = tmp;
3968
3969         ret = amdgpu_si_read_smc_sram_dword(adev,
3970                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3971                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3972                                             &tmp, si_pi->sram_end);
3973         if (ret)
3974                 return ret;
3975
3976         si_pi->arb_table_start = tmp;
3977
3978         ret = amdgpu_si_read_smc_sram_dword(adev,
3979                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3980                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3981                                             &tmp, si_pi->sram_end);
3982         if (ret)
3983                 return ret;
3984
3985         si_pi->cac_table_start = tmp;
3986
3987         ret = amdgpu_si_read_smc_sram_dword(adev,
3988                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3989                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3990                                             &tmp, si_pi->sram_end);
3991         if (ret)
3992                 return ret;
3993
3994         si_pi->dte_table_start = tmp;
3995
3996         ret = amdgpu_si_read_smc_sram_dword(adev,
3997                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3998                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3999                                             &tmp, si_pi->sram_end);
4000         if (ret)
4001                 return ret;
4002
4003         si_pi->spll_table_start = tmp;
4004
4005         ret = amdgpu_si_read_smc_sram_dword(adev,
4006                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4007                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4008                                             &tmp, si_pi->sram_end);
4009         if (ret)
4010                 return ret;
4011
4012         si_pi->papm_cfg_table_start = tmp;
4013
4014         return ret;
4015 }
4016
4017 static void si_read_clock_registers(struct amdgpu_device *adev)
4018 {
4019         struct si_power_info *si_pi = si_get_pi(adev);
4020
4021         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4022         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4023         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4024         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4025         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4026         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4027         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4028         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4029         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4030         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4031         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4032         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4033         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4034         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4035         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4036 }
4037
4038 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4039                                           bool enable)
4040 {
4041         if (enable)
4042                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4043         else
4044                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4045 }
4046
4047 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4048 {
4049         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4050 }
4051
4052 #if 0
4053 static int si_enter_ulp_state(struct amdgpu_device *adev)
4054 {
4055         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4056
4057         udelay(25000);
4058
4059         return 0;
4060 }
4061
4062 static int si_exit_ulp_state(struct amdgpu_device *adev)
4063 {
4064         int i;
4065
4066         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4067
4068         udelay(7000);
4069
4070         for (i = 0; i < adev->usec_timeout; i++) {
4071                 if (RREG32(SMC_RESP_0) == 1)
4072                         break;
4073                 udelay(1000);
4074         }
4075
4076         return 0;
4077 }
4078 #endif
4079
4080 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4081                                      bool has_display)
4082 {
4083         PPSMC_Msg msg = has_display ?
4084                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4085
4086         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4087                 0 : -EINVAL;
4088 }
4089
4090 static void si_program_response_times(struct amdgpu_device *adev)
4091 {
4092         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4093         u32 vddc_dly, acpi_dly, vbi_dly;
4094         u32 reference_clock;
4095
4096         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4097
4098         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4099         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4100
4101         if (voltage_response_time == 0)
4102                 voltage_response_time = 1000;
4103
4104         acpi_delay_time = 15000;
4105         vbi_time_out = 100000;
4106
4107         reference_clock = amdgpu_asic_get_xclk(adev);
4108
4109         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4110         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4111         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4112
4113         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4114         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4115         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4116         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4117 }
4118
4119 static void si_program_ds_registers(struct amdgpu_device *adev)
4120 {
4121         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4122         u32 tmp;
4123
4124         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4125         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4126                 tmp = 0x10;
4127         else
4128                 tmp = 0x1;
4129
4130         if (eg_pi->sclk_deep_sleep) {
4131                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4132                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4133                          ~AUTOSCALE_ON_SS_CLEAR);
4134         }
4135 }
4136
4137 static void si_program_display_gap(struct amdgpu_device *adev)
4138 {
4139         u32 tmp, pipe;
4140         int i;
4141
4142         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4143         if (adev->pm.dpm.new_active_crtc_count > 0)
4144                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4145         else
4146                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4147
4148         if (adev->pm.dpm.new_active_crtc_count > 1)
4149                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4150         else
4151                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4152
4153         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4154
4155         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4156         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4157
4158         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4159             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4160                 /* find the first active crtc */
4161                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4162                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4163                                 break;
4164                 }
4165                 if (i == adev->mode_info.num_crtc)
4166                         pipe = 0;
4167                 else
4168                         pipe = i;
4169
4170                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4171                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4172                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4173         }
4174
4175         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4176          * This can be a problem on PowerXpress systems or if you want to use the card
4177          * for offscreen rendering or compute if there are no crtcs enabled.
4178          */
4179         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4180 }
4181
4182 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4183 {
4184         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4185
4186         if (enable) {
4187                 if (pi->sclk_ss)
4188                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4189         } else {
4190                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4191                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4192         }
4193 }
4194
4195 static void si_setup_bsp(struct amdgpu_device *adev)
4196 {
4197         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4198         u32 xclk = amdgpu_asic_get_xclk(adev);
4199
4200         r600_calculate_u_and_p(pi->asi,
4201                                xclk,
4202                                16,
4203                                &pi->bsp,
4204                                &pi->bsu);
4205
4206         r600_calculate_u_and_p(pi->pasi,
4207                                xclk,
4208                                16,
4209                                &pi->pbsp,
4210                                &pi->pbsu);
4211
4212
4213         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4214         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4215
4216         WREG32(CG_BSP, pi->dsp);
4217 }
4218
4219 static void si_program_git(struct amdgpu_device *adev)
4220 {
4221         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4222 }
4223
4224 static void si_program_tp(struct amdgpu_device *adev)
4225 {
4226         int i;
4227         enum r600_td td = R600_TD_DFLT;
4228
4229         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4230                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4231
4232         if (td == R600_TD_AUTO)
4233                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4234         else
4235                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4236
4237         if (td == R600_TD_UP)
4238                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4239
4240         if (td == R600_TD_DOWN)
4241                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4242 }
4243
4244 static void si_program_tpp(struct amdgpu_device *adev)
4245 {
4246         WREG32(CG_TPC, R600_TPC_DFLT);
4247 }
4248
4249 static void si_program_sstp(struct amdgpu_device *adev)
4250 {
4251         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4252 }
4253
4254 static void si_enable_display_gap(struct amdgpu_device *adev)
4255 {
4256         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4257
4258         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4259         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4260                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4261
4262         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4263         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4264                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4265         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4266 }
4267
4268 static void si_program_vc(struct amdgpu_device *adev)
4269 {
4270         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4271
4272         WREG32(CG_FTV, pi->vrc);
4273 }
4274
4275 static void si_clear_vc(struct amdgpu_device *adev)
4276 {
4277         WREG32(CG_FTV, 0);
4278 }
4279
4280 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4281 {
4282         u8 mc_para_index;
4283
4284         if (memory_clock < 10000)
4285                 mc_para_index = 0;
4286         else if (memory_clock >= 80000)
4287                 mc_para_index = 0x0f;
4288         else
4289                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4290         return mc_para_index;
4291 }
4292
4293 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4294 {
4295         u8 mc_para_index;
4296
4297         if (strobe_mode) {
4298                 if (memory_clock < 12500)
4299                         mc_para_index = 0x00;
4300                 else if (memory_clock > 47500)
4301                         mc_para_index = 0x0f;
4302                 else
4303                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4304         } else {
4305                 if (memory_clock < 65000)
4306                         mc_para_index = 0x00;
4307                 else if (memory_clock > 135000)
4308                         mc_para_index = 0x0f;
4309                 else
4310                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4311         }
4312         return mc_para_index;
4313 }
4314
4315 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4316 {
4317         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4318         bool strobe_mode = false;
4319         u8 result = 0;
4320
4321         if (mclk <= pi->mclk_strobe_mode_threshold)
4322                 strobe_mode = true;
4323
4324         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4325                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4326         else
4327                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4328
4329         if (strobe_mode)
4330                 result |= SISLANDS_SMC_STROBE_ENABLE;
4331
4332         return result;
4333 }
4334
4335 static int si_upload_firmware(struct amdgpu_device *adev)
4336 {
4337         struct si_power_info *si_pi = si_get_pi(adev);
4338
4339         amdgpu_si_reset_smc(adev);
4340         amdgpu_si_smc_clock(adev, false);
4341
4342         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4343 }
4344
4345 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4346                                               const struct atom_voltage_table *table,
4347                                               const struct amdgpu_phase_shedding_limits_table *limits)
4348 {
4349         u32 data, num_bits, num_levels;
4350
4351         if ((table == NULL) || (limits == NULL))
4352                 return false;
4353
4354         data = table->mask_low;
4355
4356         num_bits = hweight32(data);
4357
4358         if (num_bits == 0)
4359                 return false;
4360
4361         num_levels = (1 << num_bits);
4362
4363         if (table->count != num_levels)
4364                 return false;
4365
4366         if (limits->count != (num_levels - 1))
4367                 return false;
4368
4369         return true;
4370 }
4371
4372 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4373                                               u32 max_voltage_steps,
4374                                               struct atom_voltage_table *voltage_table)
4375 {
4376         unsigned int i, diff;
4377
4378         if (voltage_table->count <= max_voltage_steps)
4379                 return;
4380
4381         diff = voltage_table->count - max_voltage_steps;
4382
4383         for (i= 0; i < max_voltage_steps; i++)
4384                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4385
4386         voltage_table->count = max_voltage_steps;
4387 }
4388
4389 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4390                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4391                                      struct atom_voltage_table *voltage_table)
4392 {
4393         u32 i;
4394
4395         if (voltage_dependency_table == NULL)
4396                 return -EINVAL;
4397
4398         voltage_table->mask_low = 0;
4399         voltage_table->phase_delay = 0;
4400
4401         voltage_table->count = voltage_dependency_table->count;
4402         for (i = 0; i < voltage_table->count; i++) {
4403                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4404                 voltage_table->entries[i].smio_low = 0;
4405         }
4406
4407         return 0;
4408 }
4409
4410 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4411 {
4412         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4413         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4414         struct si_power_info *si_pi = si_get_pi(adev);
4415         int ret;
4416
4417         if (pi->voltage_control) {
4418                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4419                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4420                 if (ret)
4421                         return ret;
4422
4423                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4424                         si_trim_voltage_table_to_fit_state_table(adev,
4425                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4426                                                                  &eg_pi->vddc_voltage_table);
4427         } else if (si_pi->voltage_control_svi2) {
4428                 ret = si_get_svi2_voltage_table(adev,
4429                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4430                                                 &eg_pi->vddc_voltage_table);
4431                 if (ret)
4432                         return ret;
4433         } else {
4434                 return -EINVAL;
4435         }
4436
4437         if (eg_pi->vddci_control) {
4438                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4439                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4440                 if (ret)
4441                         return ret;
4442
4443                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4444                         si_trim_voltage_table_to_fit_state_table(adev,
4445                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4446                                                                  &eg_pi->vddci_voltage_table);
4447         }
4448         if (si_pi->vddci_control_svi2) {
4449                 ret = si_get_svi2_voltage_table(adev,
4450                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4451                                                 &eg_pi->vddci_voltage_table);
4452                 if (ret)
4453                         return ret;
4454         }
4455
4456         if (pi->mvdd_control) {
4457                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4458                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4459
4460                 if (ret) {
4461                         pi->mvdd_control = false;
4462                         return ret;
4463                 }
4464
4465                 if (si_pi->mvdd_voltage_table.count == 0) {
4466                         pi->mvdd_control = false;
4467                         return -EINVAL;
4468                 }
4469
4470                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4471                         si_trim_voltage_table_to_fit_state_table(adev,
4472                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4473                                                                  &si_pi->mvdd_voltage_table);
4474         }
4475
4476         if (si_pi->vddc_phase_shed_control) {
4477                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4478                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4479                 if (ret)
4480                         si_pi->vddc_phase_shed_control = false;
4481
4482                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4483                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4484                         si_pi->vddc_phase_shed_control = false;
4485         }
4486
4487         return 0;
4488 }
4489
4490 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4491                                           const struct atom_voltage_table *voltage_table,
4492                                           SISLANDS_SMC_STATETABLE *table)
4493 {
4494         unsigned int i;
4495
4496         for (i = 0; i < voltage_table->count; i++)
4497                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4498 }
4499
4500 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4501                                           SISLANDS_SMC_STATETABLE *table)
4502 {
4503         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4504         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4505         struct si_power_info *si_pi = si_get_pi(adev);
4506         u8 i;
4507
4508         if (si_pi->voltage_control_svi2) {
4509                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4510                         si_pi->svc_gpio_id);
4511                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4512                         si_pi->svd_gpio_id);
4513                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4514                                            2);
4515         } else {
4516                 if (eg_pi->vddc_voltage_table.count) {
4517                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4518                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4519                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4520
4521                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4522                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4523                                         table->maxVDDCIndexInPPTable = i;
4524                                         break;
4525                                 }
4526                         }
4527                 }
4528
4529                 if (eg_pi->vddci_voltage_table.count) {
4530                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4531
4532                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4533                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4534                 }
4535
4536
4537                 if (si_pi->mvdd_voltage_table.count) {
4538                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4539
4540                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4541                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4542                 }
4543
4544                 if (si_pi->vddc_phase_shed_control) {
4545                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4546                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4547                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4548
4549                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4550                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4551
4552                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4553                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4554                         } else {
4555                                 si_pi->vddc_phase_shed_control = false;
4556                         }
4557                 }
4558         }
4559
4560         return 0;
4561 }
4562
4563 static int si_populate_voltage_value(struct amdgpu_device *adev,
4564                                      const struct atom_voltage_table *table,
4565                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4566 {
4567         unsigned int i;
4568
4569         for (i = 0; i < table->count; i++) {
4570                 if (value <= table->entries[i].value) {
4571                         voltage->index = (u8)i;
4572                         voltage->value = cpu_to_be16(table->entries[i].value);
4573                         break;
4574                 }
4575         }
4576
4577         if (i >= table->count)
4578                 return -EINVAL;
4579
4580         return 0;
4581 }
4582
4583 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4584                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4585 {
4586         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4587         struct si_power_info *si_pi = si_get_pi(adev);
4588
4589         if (pi->mvdd_control) {
4590                 if (mclk <= pi->mvdd_split_frequency)
4591                         voltage->index = 0;
4592                 else
4593                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4594
4595                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4596         }
4597         return 0;
4598 }
4599
4600 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4601                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4602                                     u16 *std_voltage)
4603 {
4604         u16 v_index;
4605         bool voltage_found = false;
4606         *std_voltage = be16_to_cpu(voltage->value);
4607
4608         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4609                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4610                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4611                                 return -EINVAL;
4612
4613                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4614                                 if (be16_to_cpu(voltage->value) ==
4615                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4616                                         voltage_found = true;
4617                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4618                                                 *std_voltage =
4619                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4620                                         else
4621                                                 *std_voltage =
4622                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4623                                         break;
4624                                 }
4625                         }
4626
4627                         if (!voltage_found) {
4628                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4629                                         if (be16_to_cpu(voltage->value) <=
4630                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4631                                                 voltage_found = true;
4632                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4633                                                         *std_voltage =
4634                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4635                                                 else
4636                                                         *std_voltage =
4637                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4638                                                 break;
4639                                         }
4640                                 }
4641                         }
4642                 } else {
4643                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4644                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4645                 }
4646         }
4647
4648         return 0;
4649 }
4650
4651 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4652                                          u16 value, u8 index,
4653                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4654 {
4655         voltage->index = index;
4656         voltage->value = cpu_to_be16(value);
4657
4658         return 0;
4659 }
4660
4661 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4662                                             const struct amdgpu_phase_shedding_limits_table *limits,
4663                                             u16 voltage, u32 sclk, u32 mclk,
4664                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4665 {
4666         unsigned int i;
4667
4668         for (i = 0; i < limits->count; i++) {
4669                 if ((voltage <= limits->entries[i].voltage) &&
4670                     (sclk <= limits->entries[i].sclk) &&
4671                     (mclk <= limits->entries[i].mclk))
4672                         break;
4673         }
4674
4675         smc_voltage->phase_settings = (u8)i;
4676
4677         return 0;
4678 }
4679
4680 static int si_init_arb_table_index(struct amdgpu_device *adev)
4681 {
4682         struct si_power_info *si_pi = si_get_pi(adev);
4683         u32 tmp;
4684         int ret;
4685
4686         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4687                                             &tmp, si_pi->sram_end);
4688         if (ret)
4689                 return ret;
4690
4691         tmp &= 0x00FFFFFF;
4692         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4693
4694         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4695                                               tmp, si_pi->sram_end);
4696 }
4697
4698 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4699 {
4700         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4701 }
4702
4703 static int si_reset_to_default(struct amdgpu_device *adev)
4704 {
4705         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4706                 0 : -EINVAL;
4707 }
4708
4709 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4710 {
4711         struct si_power_info *si_pi = si_get_pi(adev);
4712         u32 tmp;
4713         int ret;
4714
4715         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4716                                             &tmp, si_pi->sram_end);
4717         if (ret)
4718                 return ret;
4719
4720         tmp = (tmp >> 24) & 0xff;
4721
4722         if (tmp == MC_CG_ARB_FREQ_F0)
4723                 return 0;
4724
4725         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4726 }
4727
4728 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4729                                             u32 engine_clock)
4730 {
4731         u32 dram_rows;
4732         u32 dram_refresh_rate;
4733         u32 mc_arb_rfsh_rate;
4734         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4735
4736         if (tmp >= 4)
4737                 dram_rows = 16384;
4738         else
4739                 dram_rows = 1 << (tmp + 10);
4740
4741         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4742         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4743
4744         return mc_arb_rfsh_rate;
4745 }
4746
4747 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4748                                                 struct rv7xx_pl *pl,
4749                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4750 {
4751         u32 dram_timing;
4752         u32 dram_timing2;
4753         u32 burst_time;
4754
4755         arb_regs->mc_arb_rfsh_rate =
4756                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4757
4758         amdgpu_atombios_set_engine_dram_timings(adev,
4759                                             pl->sclk,
4760                                             pl->mclk);
4761
4762         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4763         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4764         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4765
4766         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4767         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4768         arb_regs->mc_arb_burst_time = (u8)burst_time;
4769
4770         return 0;
4771 }
4772
4773 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4774                                                   struct amdgpu_ps *amdgpu_state,
4775                                                   unsigned int first_arb_set)
4776 {
4777         struct si_power_info *si_pi = si_get_pi(adev);
4778         struct  si_ps *state = si_get_ps(amdgpu_state);
4779         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4780         int i, ret = 0;
4781
4782         for (i = 0; i < state->performance_level_count; i++) {
4783                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4784                 if (ret)
4785                         break;
4786                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4787                                                   si_pi->arb_table_start +
4788                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4789                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4790                                                   (u8 *)&arb_regs,
4791                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4792                                                   si_pi->sram_end);
4793                 if (ret)
4794                         break;
4795         }
4796
4797         return ret;
4798 }
4799
4800 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4801                                                struct amdgpu_ps *amdgpu_new_state)
4802 {
4803         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4804                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4805 }
4806
4807 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4808                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4809 {
4810         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4811         struct si_power_info *si_pi = si_get_pi(adev);
4812
4813         if (pi->mvdd_control)
4814                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4815                                                  si_pi->mvdd_bootup_value, voltage);
4816
4817         return 0;
4818 }
4819
4820 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4821                                          struct amdgpu_ps *amdgpu_initial_state,
4822                                          SISLANDS_SMC_STATETABLE *table)
4823 {
4824         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4825         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4826         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4827         struct si_power_info *si_pi = si_get_pi(adev);
4828         u32 reg;
4829         int ret;
4830
4831         table->initialState.levels[0].mclk.vDLL_CNTL =
4832                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4833         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4834                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4835         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4836                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4837         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4838                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4839         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4840                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4841         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4842                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4843         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4844                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4845         table->initialState.levels[0].mclk.vMPLL_SS =
4846                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4847         table->initialState.levels[0].mclk.vMPLL_SS2 =
4848                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4849
4850         table->initialState.levels[0].mclk.mclk_value =
4851                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4852
4853         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4854                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4855         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4856                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4857         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4858                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4859         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4860                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4861         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4862                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4863         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4864                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4865
4866         table->initialState.levels[0].sclk.sclk_value =
4867                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4868
4869         table->initialState.levels[0].arbRefreshState =
4870                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4871
4872         table->initialState.levels[0].ACIndex = 0;
4873
4874         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4875                                         initial_state->performance_levels[0].vddc,
4876                                         &table->initialState.levels[0].vddc);
4877
4878         if (!ret) {
4879                 u16 std_vddc;
4880
4881                 ret = si_get_std_voltage_value(adev,
4882                                                &table->initialState.levels[0].vddc,
4883                                                &std_vddc);
4884                 if (!ret)
4885                         si_populate_std_voltage_value(adev, std_vddc,
4886                                                       table->initialState.levels[0].vddc.index,
4887                                                       &table->initialState.levels[0].std_vddc);
4888         }
4889
4890         if (eg_pi->vddci_control)
4891                 si_populate_voltage_value(adev,
4892                                           &eg_pi->vddci_voltage_table,
4893                                           initial_state->performance_levels[0].vddci,
4894                                           &table->initialState.levels[0].vddci);
4895
4896         if (si_pi->vddc_phase_shed_control)
4897                 si_populate_phase_shedding_value(adev,
4898                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4899                                                  initial_state->performance_levels[0].vddc,
4900                                                  initial_state->performance_levels[0].sclk,
4901                                                  initial_state->performance_levels[0].mclk,
4902                                                  &table->initialState.levels[0].vddc);
4903
4904         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4905
4906         reg = CG_R(0xffff) | CG_L(0);
4907         table->initialState.levels[0].aT = cpu_to_be32(reg);
4908         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4909         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4910
4911         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4912                 table->initialState.levels[0].strobeMode =
4913                         si_get_strobe_mode_settings(adev,
4914                                                     initial_state->performance_levels[0].mclk);
4915
4916                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4917                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4918                 else
4919                         table->initialState.levels[0].mcFlags =  0;
4920         }
4921
4922         table->initialState.levelCount = 1;
4923
4924         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4925
4926         table->initialState.levels[0].dpm2.MaxPS = 0;
4927         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4928         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4929         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4930         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4931
4932         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4933         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4934
4935         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4936         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4937
4938         return 0;
4939 }
4940
4941 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4942                                       SISLANDS_SMC_STATETABLE *table)
4943 {
4944         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4945         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4946         struct si_power_info *si_pi = si_get_pi(adev);
4947         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4948         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4949         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4950         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4951         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4952         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4953         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4954         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4955         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4956         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4957         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4958         u32 reg;
4959         int ret;
4960
4961         table->ACPIState = table->initialState;
4962
4963         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4964
4965         if (pi->acpi_vddc) {
4966                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4967                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4968                 if (!ret) {
4969                         u16 std_vddc;
4970
4971                         ret = si_get_std_voltage_value(adev,
4972                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4973                         if (!ret)
4974                                 si_populate_std_voltage_value(adev, std_vddc,
4975                                                               table->ACPIState.levels[0].vddc.index,
4976                                                               &table->ACPIState.levels[0].std_vddc);
4977                 }
4978                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4979
4980                 if (si_pi->vddc_phase_shed_control) {
4981                         si_populate_phase_shedding_value(adev,
4982                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4983                                                          pi->acpi_vddc,
4984                                                          0,
4985                                                          0,
4986                                                          &table->ACPIState.levels[0].vddc);
4987                 }
4988         } else {
4989                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4990                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4991                 if (!ret) {
4992                         u16 std_vddc;
4993
4994                         ret = si_get_std_voltage_value(adev,
4995                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4996
4997                         if (!ret)
4998                                 si_populate_std_voltage_value(adev, std_vddc,
4999                                                               table->ACPIState.levels[0].vddc.index,
5000                                                               &table->ACPIState.levels[0].std_vddc);
5001                 }
5002                 table->ACPIState.levels[0].gen2PCIE =
5003                         (u8)amdgpu_get_pcie_gen_support(adev,
5004                                                         si_pi->sys_pcie_mask,
5005                                                         si_pi->boot_pcie_gen,
5006                                                         AMDGPU_PCIE_GEN1);
5007
5008                 if (si_pi->vddc_phase_shed_control)
5009                         si_populate_phase_shedding_value(adev,
5010                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5011                                                          pi->min_vddc_in_table,
5012                                                          0,
5013                                                          0,
5014                                                          &table->ACPIState.levels[0].vddc);
5015         }
5016
5017         if (pi->acpi_vddc) {
5018                 if (eg_pi->acpi_vddci)
5019                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5020                                                   eg_pi->acpi_vddci,
5021                                                   &table->ACPIState.levels[0].vddci);
5022         }
5023
5024         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5025         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5026
5027         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5028
5029         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5030         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5031
5032         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5033                 cpu_to_be32(dll_cntl);
5034         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5035                 cpu_to_be32(mclk_pwrmgt_cntl);
5036         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5037                 cpu_to_be32(mpll_ad_func_cntl);
5038         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5039                 cpu_to_be32(mpll_dq_func_cntl);
5040         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5041                 cpu_to_be32(mpll_func_cntl);
5042         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5043                 cpu_to_be32(mpll_func_cntl_1);
5044         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5045                 cpu_to_be32(mpll_func_cntl_2);
5046         table->ACPIState.levels[0].mclk.vMPLL_SS =
5047                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5048         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5049                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5050
5051         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5052                 cpu_to_be32(spll_func_cntl);
5053         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5054                 cpu_to_be32(spll_func_cntl_2);
5055         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5056                 cpu_to_be32(spll_func_cntl_3);
5057         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5058                 cpu_to_be32(spll_func_cntl_4);
5059
5060         table->ACPIState.levels[0].mclk.mclk_value = 0;
5061         table->ACPIState.levels[0].sclk.sclk_value = 0;
5062
5063         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5064
5065         if (eg_pi->dynamic_ac_timing)
5066                 table->ACPIState.levels[0].ACIndex = 0;
5067
5068         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5069         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5070         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5071         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5072         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5073
5074         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5075         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5076
5077         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5078         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5079
5080         return 0;
5081 }
5082
5083 static int si_populate_ulv_state(struct amdgpu_device *adev,
5084                                  SISLANDS_SMC_SWSTATE *state)
5085 {
5086         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5087         struct si_power_info *si_pi = si_get_pi(adev);
5088         struct si_ulv_param *ulv = &si_pi->ulv;
5089         u32 sclk_in_sr = 1350; /* ??? */
5090         int ret;
5091
5092         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5093                                             &state->levels[0]);
5094         if (!ret) {
5095                 if (eg_pi->sclk_deep_sleep) {
5096                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5097                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5098                         else
5099                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5100                 }
5101                 if (ulv->one_pcie_lane_in_ulv)
5102                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5103                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5104                 state->levels[0].ACIndex = 1;
5105                 state->levels[0].std_vddc = state->levels[0].vddc;
5106                 state->levelCount = 1;
5107
5108                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5109         }
5110
5111         return ret;
5112 }
5113
5114 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5115 {
5116         struct si_power_info *si_pi = si_get_pi(adev);
5117         struct si_ulv_param *ulv = &si_pi->ulv;
5118         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5119         int ret;
5120
5121         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5122                                                    &arb_regs);
5123         if (ret)
5124                 return ret;
5125
5126         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5127                                    ulv->volt_change_delay);
5128
5129         ret = amdgpu_si_copy_bytes_to_smc(adev,
5130                                           si_pi->arb_table_start +
5131                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5132                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5133                                           (u8 *)&arb_regs,
5134                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5135                                           si_pi->sram_end);
5136
5137         return ret;
5138 }
5139
5140 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5141 {
5142         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5143
5144         pi->mvdd_split_frequency = 30000;
5145 }
5146
5147 static int si_init_smc_table(struct amdgpu_device *adev)
5148 {
5149         struct si_power_info *si_pi = si_get_pi(adev);
5150         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5151         const struct si_ulv_param *ulv = &si_pi->ulv;
5152         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5153         int ret;
5154         u32 lane_width;
5155         u32 vr_hot_gpio;
5156
5157         si_populate_smc_voltage_tables(adev, table);
5158
5159         switch (adev->pm.int_thermal_type) {
5160         case THERMAL_TYPE_SI:
5161         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5162                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5163                 break;
5164         case THERMAL_TYPE_NONE:
5165                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5166                 break;
5167         default:
5168                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5169                 break;
5170         }
5171
5172         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5173                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5174
5175         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5176                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5177                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5178         }
5179
5180         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5181                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5182
5183         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5184                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5185
5186         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5187                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5188
5189         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5190                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5191                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5192                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5193                                            vr_hot_gpio);
5194         }
5195
5196         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5197         if (ret)
5198                 return ret;
5199
5200         ret = si_populate_smc_acpi_state(adev, table);
5201         if (ret)
5202                 return ret;
5203
5204         table->driverState = table->initialState;
5205
5206         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5207                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5208         if (ret)
5209                 return ret;
5210
5211         if (ulv->supported && ulv->pl.vddc) {
5212                 ret = si_populate_ulv_state(adev, &table->ULVState);
5213                 if (ret)
5214                         return ret;
5215
5216                 ret = si_program_ulv_memory_timing_parameters(adev);
5217                 if (ret)
5218                         return ret;
5219
5220                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5221                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5222
5223                 lane_width = amdgpu_get_pcie_lanes(adev);
5224                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5225         } else {
5226                 table->ULVState = table->initialState;
5227         }
5228
5229         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5230                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5231                                            si_pi->sram_end);
5232 }
5233
5234 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5235                                     u32 engine_clock,
5236                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5237 {
5238         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5239         struct si_power_info *si_pi = si_get_pi(adev);
5240         struct atom_clock_dividers dividers;
5241         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5242         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5243         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5244         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5245         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5246         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5247         u64 tmp;
5248         u32 reference_clock = adev->clock.spll.reference_freq;
5249         u32 reference_divider;
5250         u32 fbdiv;
5251         int ret;
5252
5253         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5254                                              engine_clock, false, &dividers);
5255         if (ret)
5256                 return ret;
5257
5258         reference_divider = 1 + dividers.ref_div;
5259
5260         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5261         do_div(tmp, reference_clock);
5262         fbdiv = (u32) tmp;
5263
5264         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5265         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5266         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5267
5268         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5269         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5270
5271         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5272         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5273         spll_func_cntl_3 |= SPLL_DITHEN;
5274
5275         if (pi->sclk_ss) {
5276                 struct amdgpu_atom_ss ss;
5277                 u32 vco_freq = engine_clock * dividers.post_div;
5278
5279                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5280                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5281                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5282                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5283
5284                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5285                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5286                         cg_spll_spread_spectrum |= SSEN;
5287
5288                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5289                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5290                 }
5291         }
5292
5293         sclk->sclk_value = engine_clock;
5294         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5295         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5296         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5297         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5298         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5299         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5300
5301         return 0;
5302 }
5303
5304 static int si_populate_sclk_value(struct amdgpu_device *adev,
5305                                   u32 engine_clock,
5306                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5307 {
5308         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5309         int ret;
5310
5311         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5312         if (!ret) {
5313                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5314                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5315                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5316                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5317                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5318                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5319                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5320         }
5321
5322         return ret;
5323 }
5324
5325 static int si_populate_mclk_value(struct amdgpu_device *adev,
5326                                   u32 engine_clock,
5327                                   u32 memory_clock,
5328                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5329                                   bool strobe_mode,
5330                                   bool dll_state_on)
5331 {
5332         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5333         struct si_power_info *si_pi = si_get_pi(adev);
5334         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5335         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5336         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5337         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5338         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5339         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5340         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5341         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5342         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5343         struct atom_mpll_param mpll_param;
5344         int ret;
5345
5346         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5347         if (ret)
5348                 return ret;
5349
5350         mpll_func_cntl &= ~BWCTRL_MASK;
5351         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5352
5353         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5354         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5355                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5356
5357         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5358         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5359
5360         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5361                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5362                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5363                         YCLK_POST_DIV(mpll_param.post_div);
5364         }
5365
5366         if (pi->mclk_ss) {
5367                 struct amdgpu_atom_ss ss;
5368                 u32 freq_nom;
5369                 u32 tmp;
5370                 u32 reference_clock = adev->clock.mpll.reference_freq;
5371
5372                 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5373                         freq_nom = memory_clock * 4;
5374                 else
5375                         freq_nom = memory_clock * 2;
5376
5377                 tmp = freq_nom / reference_clock;
5378                 tmp = tmp * tmp;
5379                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5380                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5381                         u32 clks = reference_clock * 5 / ss.rate;
5382                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5383
5384                         mpll_ss1 &= ~CLKV_MASK;
5385                         mpll_ss1 |= CLKV(clkv);
5386
5387                         mpll_ss2 &= ~CLKS_MASK;
5388                         mpll_ss2 |= CLKS(clks);
5389                 }
5390         }
5391
5392         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5393         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5394
5395         if (dll_state_on)
5396                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5397         else
5398                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5399
5400         mclk->mclk_value = cpu_to_be32(memory_clock);
5401         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5402         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5403         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5404         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5405         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5406         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5407         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5408         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5409         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5410
5411         return 0;
5412 }
5413
5414 static void si_populate_smc_sp(struct amdgpu_device *adev,
5415                                struct amdgpu_ps *amdgpu_state,
5416                                SISLANDS_SMC_SWSTATE *smc_state)
5417 {
5418         struct  si_ps *ps = si_get_ps(amdgpu_state);
5419         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5420         int i;
5421
5422         for (i = 0; i < ps->performance_level_count - 1; i++)
5423                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5424
5425         smc_state->levels[ps->performance_level_count - 1].bSP =
5426                 cpu_to_be32(pi->psp);
5427 }
5428
5429 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5430                                          struct rv7xx_pl *pl,
5431                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5432 {
5433         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5434         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5435         struct si_power_info *si_pi = si_get_pi(adev);
5436         int ret;
5437         bool dll_state_on;
5438         u16 std_vddc;
5439         bool gmc_pg = false;
5440
5441         if (eg_pi->pcie_performance_request &&
5442             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5443                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5444         else
5445                 level->gen2PCIE = (u8)pl->pcie_gen;
5446
5447         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5448         if (ret)
5449                 return ret;
5450
5451         level->mcFlags =  0;
5452
5453         if (pi->mclk_stutter_mode_threshold &&
5454             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5455             !eg_pi->uvd_enabled &&
5456             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5457             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5458                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5459
5460                 if (gmc_pg)
5461                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5462         }
5463
5464         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5465                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5466                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5467
5468                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5469                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5470
5471                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5472
5473                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5474                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5475                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5476                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5477                         else
5478                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5479                 } else {
5480                         dll_state_on = false;
5481                 }
5482         } else {
5483                 level->strobeMode = si_get_strobe_mode_settings(adev,
5484                                                                 pl->mclk);
5485
5486                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5487         }
5488
5489         ret = si_populate_mclk_value(adev,
5490                                      pl->sclk,
5491                                      pl->mclk,
5492                                      &level->mclk,
5493                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5494         if (ret)
5495                 return ret;
5496
5497         ret = si_populate_voltage_value(adev,
5498                                         &eg_pi->vddc_voltage_table,
5499                                         pl->vddc, &level->vddc);
5500         if (ret)
5501                 return ret;
5502
5503
5504         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5505         if (ret)
5506                 return ret;
5507
5508         ret = si_populate_std_voltage_value(adev, std_vddc,
5509                                             level->vddc.index, &level->std_vddc);
5510         if (ret)
5511                 return ret;
5512
5513         if (eg_pi->vddci_control) {
5514                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5515                                                 pl->vddci, &level->vddci);
5516                 if (ret)
5517                         return ret;
5518         }
5519
5520         if (si_pi->vddc_phase_shed_control) {
5521                 ret = si_populate_phase_shedding_value(adev,
5522                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5523                                                        pl->vddc,
5524                                                        pl->sclk,
5525                                                        pl->mclk,
5526                                                        &level->vddc);
5527                 if (ret)
5528                         return ret;
5529         }
5530
5531         level->MaxPoweredUpCU = si_pi->max_cu;
5532
5533         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5534
5535         return ret;
5536 }
5537
5538 static int si_populate_smc_t(struct amdgpu_device *adev,
5539                              struct amdgpu_ps *amdgpu_state,
5540                              SISLANDS_SMC_SWSTATE *smc_state)
5541 {
5542         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5543         struct  si_ps *state = si_get_ps(amdgpu_state);
5544         u32 a_t;
5545         u32 t_l, t_h;
5546         u32 high_bsp;
5547         int i, ret;
5548
5549         if (state->performance_level_count >= 9)
5550                 return -EINVAL;
5551
5552         if (state->performance_level_count < 2) {
5553                 a_t = CG_R(0xffff) | CG_L(0);
5554                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5555                 return 0;
5556         }
5557
5558         smc_state->levels[0].aT = cpu_to_be32(0);
5559
5560         for (i = 0; i <= state->performance_level_count - 2; i++) {
5561                 ret = r600_calculate_at(
5562                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5563                         100 * R600_AH_DFLT,
5564                         state->performance_levels[i + 1].sclk,
5565                         state->performance_levels[i].sclk,
5566                         &t_l,
5567                         &t_h);
5568
5569                 if (ret) {
5570                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5571                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5572                 }
5573
5574                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5575                 a_t |= CG_R(t_l * pi->bsp / 20000);
5576                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5577
5578                 high_bsp = (i == state->performance_level_count - 2) ?
5579                         pi->pbsp : pi->bsp;
5580                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5581                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5582         }
5583
5584         return 0;
5585 }
5586
5587 static int si_disable_ulv(struct amdgpu_device *adev)
5588 {
5589         struct si_power_info *si_pi = si_get_pi(adev);
5590         struct si_ulv_param *ulv = &si_pi->ulv;
5591
5592         if (ulv->supported)
5593                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5594                         0 : -EINVAL;
5595
5596         return 0;
5597 }
5598
5599 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5600                                        struct amdgpu_ps *amdgpu_state)
5601 {
5602         const struct si_power_info *si_pi = si_get_pi(adev);
5603         const struct si_ulv_param *ulv = &si_pi->ulv;
5604         const struct  si_ps *state = si_get_ps(amdgpu_state);
5605         int i;
5606
5607         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5608                 return false;
5609
5610         /* XXX validate against display requirements! */
5611
5612         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5613                 if (adev->clock.current_dispclk <=
5614                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5615                         if (ulv->pl.vddc <
5616                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5617                                 return false;
5618                 }
5619         }
5620
5621         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5622                 return false;
5623
5624         return true;
5625 }
5626
5627 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5628                                                        struct amdgpu_ps *amdgpu_new_state)
5629 {
5630         const struct si_power_info *si_pi = si_get_pi(adev);
5631         const struct si_ulv_param *ulv = &si_pi->ulv;
5632
5633         if (ulv->supported) {
5634                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5635                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5636                                 0 : -EINVAL;
5637         }
5638         return 0;
5639 }
5640
5641 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5642                                          struct amdgpu_ps *amdgpu_state,
5643                                          SISLANDS_SMC_SWSTATE *smc_state)
5644 {
5645         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5646         struct ni_power_info *ni_pi = ni_get_pi(adev);
5647         struct si_power_info *si_pi = si_get_pi(adev);
5648         struct  si_ps *state = si_get_ps(amdgpu_state);
5649         int i, ret;
5650         u32 threshold;
5651         u32 sclk_in_sr = 1350; /* ??? */
5652
5653         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5654                 return -EINVAL;
5655
5656         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5657
5658         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5659                 eg_pi->uvd_enabled = true;
5660                 if (eg_pi->smu_uvd_hs)
5661                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5662         } else {
5663                 eg_pi->uvd_enabled = false;
5664         }
5665
5666         if (state->dc_compatible)
5667                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5668
5669         smc_state->levelCount = 0;
5670         for (i = 0; i < state->performance_level_count; i++) {
5671                 if (eg_pi->sclk_deep_sleep) {
5672                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5673                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5674                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5675                                 else
5676                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5677                         }
5678                 }
5679
5680                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5681                                                     &smc_state->levels[i]);
5682                 smc_state->levels[i].arbRefreshState =
5683                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5684
5685                 if (ret)
5686                         return ret;
5687
5688                 if (ni_pi->enable_power_containment)
5689                         smc_state->levels[i].displayWatermark =
5690                                 (state->performance_levels[i].sclk < threshold) ?
5691                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5692                 else
5693                         smc_state->levels[i].displayWatermark = (i < 2) ?
5694                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5695
5696                 if (eg_pi->dynamic_ac_timing)
5697                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5698                 else
5699                         smc_state->levels[i].ACIndex = 0;
5700
5701                 smc_state->levelCount++;
5702         }
5703
5704         si_write_smc_soft_register(adev,
5705                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5706                                    threshold / 512);
5707
5708         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5709
5710         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5711         if (ret)
5712                 ni_pi->enable_power_containment = false;
5713
5714         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5715         if (ret)
5716                 ni_pi->enable_sq_ramping = false;
5717
5718         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5719 }
5720
5721 static int si_upload_sw_state(struct amdgpu_device *adev,
5722                               struct amdgpu_ps *amdgpu_new_state)
5723 {
5724         struct si_power_info *si_pi = si_get_pi(adev);
5725         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5726         int ret;
5727         u32 address = si_pi->state_table_start +
5728                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5729         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5730                 ((new_state->performance_level_count - 1) *
5731                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5732         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5733
5734         memset(smc_state, 0, state_size);
5735
5736         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5737         if (ret)
5738                 return ret;
5739
5740         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5741                                            state_size, si_pi->sram_end);
5742 }
5743
5744 static int si_upload_ulv_state(struct amdgpu_device *adev)
5745 {
5746         struct si_power_info *si_pi = si_get_pi(adev);
5747         struct si_ulv_param *ulv = &si_pi->ulv;
5748         int ret = 0;
5749
5750         if (ulv->supported && ulv->pl.vddc) {
5751                 u32 address = si_pi->state_table_start +
5752                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5753                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5754                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5755
5756                 memset(smc_state, 0, state_size);
5757
5758                 ret = si_populate_ulv_state(adev, smc_state);
5759                 if (!ret)
5760                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5761                                                           state_size, si_pi->sram_end);
5762         }
5763
5764         return ret;
5765 }
5766
5767 static int si_upload_smc_data(struct amdgpu_device *adev)
5768 {
5769         struct amdgpu_crtc *amdgpu_crtc = NULL;
5770         int i;
5771
5772         if (adev->pm.dpm.new_active_crtc_count == 0)
5773                 return 0;
5774
5775         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5776                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5777                         amdgpu_crtc = adev->mode_info.crtcs[i];
5778                         break;
5779                 }
5780         }
5781
5782         if (amdgpu_crtc == NULL)
5783                 return 0;
5784
5785         if (amdgpu_crtc->line_time <= 0)
5786                 return 0;
5787
5788         if (si_write_smc_soft_register(adev,
5789                                        SI_SMC_SOFT_REGISTER_crtc_index,
5790                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5791                 return 0;
5792
5793         if (si_write_smc_soft_register(adev,
5794                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5795                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5796                 return 0;
5797
5798         if (si_write_smc_soft_register(adev,
5799                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5800                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5801                 return 0;
5802
5803         return 0;
5804 }
5805
5806 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5807                                        struct si_mc_reg_table *table)
5808 {
5809         u8 i, j, k;
5810         u32 temp_reg;
5811
5812         for (i = 0, j = table->last; i < table->last; i++) {
5813                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5814                         return -EINVAL;
5815                 switch (table->mc_reg_address[i].s1) {
5816                 case MC_SEQ_MISC1:
5817                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5818                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5819                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5820                         for (k = 0; k < table->num_entries; k++)
5821                                 table->mc_reg_table_entry[k].mc_data[j] =
5822                                         ((temp_reg & 0xffff0000)) |
5823                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5824                         j++;
5825
5826                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5827                                 return -EINVAL;
5828                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5829                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5830                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5831                         for (k = 0; k < table->num_entries; k++) {
5832                                 table->mc_reg_table_entry[k].mc_data[j] =
5833                                         (temp_reg & 0xffff0000) |
5834                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5835                                 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5836                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5837                         }
5838                         j++;
5839
5840                         if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5841                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5842                                         return -EINVAL;
5843                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5844                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5845                                 for (k = 0; k < table->num_entries; k++)
5846                                         table->mc_reg_table_entry[k].mc_data[j] =
5847                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5848                                 j++;
5849                         }
5850                         break;
5851                 case MC_SEQ_RESERVE_M:
5852                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5853                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5854                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5855                         for(k = 0; k < table->num_entries; k++)
5856                                 table->mc_reg_table_entry[k].mc_data[j] =
5857                                         (temp_reg & 0xffff0000) |
5858                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5859                         j++;
5860                         break;
5861                 default:
5862                         break;
5863                 }
5864         }
5865
5866         table->last = j;
5867
5868         return 0;
5869 }
5870
5871 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5872 {
5873         bool result = true;
5874         switch (in_reg) {
5875         case  MC_SEQ_RAS_TIMING:
5876                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5877                 break;
5878         case MC_SEQ_CAS_TIMING:
5879                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5880                 break;
5881         case MC_SEQ_MISC_TIMING:
5882                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5883                 break;
5884         case MC_SEQ_MISC_TIMING2:
5885                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5886                 break;
5887         case MC_SEQ_RD_CTL_D0:
5888                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5889                 break;
5890         case MC_SEQ_RD_CTL_D1:
5891                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5892                 break;
5893         case MC_SEQ_WR_CTL_D0:
5894                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5895                 break;
5896         case MC_SEQ_WR_CTL_D1:
5897                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5898                 break;
5899         case MC_PMG_CMD_EMRS:
5900                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5901                 break;
5902         case MC_PMG_CMD_MRS:
5903                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5904                 break;
5905         case MC_PMG_CMD_MRS1:
5906                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5907                 break;
5908         case MC_SEQ_PMG_TIMING:
5909                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5910                 break;
5911         case MC_PMG_CMD_MRS2:
5912                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5913                 break;
5914         case MC_SEQ_WR_CTL_2:
5915                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5916                 break;
5917         default:
5918                 result = false;
5919                 break;
5920         }
5921
5922         return result;
5923 }
5924
5925 static void si_set_valid_flag(struct si_mc_reg_table *table)
5926 {
5927         u8 i, j;
5928
5929         for (i = 0; i < table->last; i++) {
5930                 for (j = 1; j < table->num_entries; j++) {
5931                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5932                                 table->valid_flag |= 1 << i;
5933                                 break;
5934                         }
5935                 }
5936         }
5937 }
5938
5939 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5940 {
5941         u32 i;
5942         u16 address;
5943
5944         for (i = 0; i < table->last; i++)
5945                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5946                         address : table->mc_reg_address[i].s1;
5947
5948 }
5949
5950 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5951                                       struct si_mc_reg_table *si_table)
5952 {
5953         u8 i, j;
5954
5955         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5956                 return -EINVAL;
5957         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5958                 return -EINVAL;
5959
5960         for (i = 0; i < table->last; i++)
5961                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5962         si_table->last = table->last;
5963
5964         for (i = 0; i < table->num_entries; i++) {
5965                 si_table->mc_reg_table_entry[i].mclk_max =
5966                         table->mc_reg_table_entry[i].mclk_max;
5967                 for (j = 0; j < table->last; j++) {
5968                         si_table->mc_reg_table_entry[i].mc_data[j] =
5969                                 table->mc_reg_table_entry[i].mc_data[j];
5970                 }
5971         }
5972         si_table->num_entries = table->num_entries;
5973
5974         return 0;
5975 }
5976
5977 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
5978 {
5979         struct si_power_info *si_pi = si_get_pi(adev);
5980         struct atom_mc_reg_table *table;
5981         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5982         u8 module_index = rv770_get_memory_module_index(adev);
5983         int ret;
5984
5985         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5986         if (!table)
5987                 return -ENOMEM;
5988
5989         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5990         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5991         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5992         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5993         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5994         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5995         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5996         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5997         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5998         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5999         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6000         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6001         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6002         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6003
6004         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6005         if (ret)
6006                 goto init_mc_done;
6007
6008         ret = si_copy_vbios_mc_reg_table(table, si_table);
6009         if (ret)
6010                 goto init_mc_done;
6011
6012         si_set_s0_mc_reg_index(si_table);
6013
6014         ret = si_set_mc_special_registers(adev, si_table);
6015         if (ret)
6016                 goto init_mc_done;
6017
6018         si_set_valid_flag(si_table);
6019
6020 init_mc_done:
6021         kfree(table);
6022
6023         return ret;
6024
6025 }
6026
6027 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6028                                          SMC_SIslands_MCRegisters *mc_reg_table)
6029 {
6030         struct si_power_info *si_pi = si_get_pi(adev);
6031         u32 i, j;
6032
6033         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6034                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6035                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6036                                 break;
6037                         mc_reg_table->address[i].s0 =
6038                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6039                         mc_reg_table->address[i].s1 =
6040                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6041                         i++;
6042                 }
6043         }
6044         mc_reg_table->last = (u8)i;
6045 }
6046
6047 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6048                                     SMC_SIslands_MCRegisterSet *data,
6049                                     u32 num_entries, u32 valid_flag)
6050 {
6051         u32 i, j;
6052
6053         for(i = 0, j = 0; j < num_entries; j++) {
6054                 if (valid_flag & (1 << j)) {
6055                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6056                         i++;
6057                 }
6058         }
6059 }
6060
6061 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6062                                                  struct rv7xx_pl *pl,
6063                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6064 {
6065         struct si_power_info *si_pi = si_get_pi(adev);
6066         u32 i = 0;
6067
6068         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6069                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6070                         break;
6071         }
6072
6073         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6074                 --i;
6075
6076         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6077                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6078                                 si_pi->mc_reg_table.valid_flag);
6079 }
6080
6081 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6082                                            struct amdgpu_ps *amdgpu_state,
6083                                            SMC_SIslands_MCRegisters *mc_reg_table)
6084 {
6085         struct si_ps *state = si_get_ps(amdgpu_state);
6086         int i;
6087
6088         for (i = 0; i < state->performance_level_count; i++) {
6089                 si_convert_mc_reg_table_entry_to_smc(adev,
6090                                                      &state->performance_levels[i],
6091                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6092         }
6093 }
6094
6095 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6096                                     struct amdgpu_ps *amdgpu_boot_state)
6097 {
6098         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6099         struct si_power_info *si_pi = si_get_pi(adev);
6100         struct si_ulv_param *ulv = &si_pi->ulv;
6101         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6102
6103         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6104
6105         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6106
6107         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6108
6109         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6110                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6111
6112         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6113                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6114                                 si_pi->mc_reg_table.last,
6115                                 si_pi->mc_reg_table.valid_flag);
6116
6117         if (ulv->supported && ulv->pl.vddc != 0)
6118                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6119                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6120         else
6121                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6122                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6123                                         si_pi->mc_reg_table.last,
6124                                         si_pi->mc_reg_table.valid_flag);
6125
6126         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6127
6128         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6129                                            (u8 *)smc_mc_reg_table,
6130                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6131 }
6132
6133 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6134                                   struct amdgpu_ps *amdgpu_new_state)
6135 {
6136         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6137         struct si_power_info *si_pi = si_get_pi(adev);
6138         u32 address = si_pi->mc_reg_table_start +
6139                 offsetof(SMC_SIslands_MCRegisters,
6140                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6141         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6142
6143         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6144
6145         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6146
6147         return amdgpu_si_copy_bytes_to_smc(adev, address,
6148                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6149                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6150                                            si_pi->sram_end);
6151 }
6152
6153 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6154 {
6155         if (enable)
6156                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6157         else
6158                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6159 }
6160
6161 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6162                                                       struct amdgpu_ps *amdgpu_state)
6163 {
6164         struct si_ps *state = si_get_ps(amdgpu_state);
6165         int i;
6166         u16 pcie_speed, max_speed = 0;
6167
6168         for (i = 0; i < state->performance_level_count; i++) {
6169                 pcie_speed = state->performance_levels[i].pcie_gen;
6170                 if (max_speed < pcie_speed)
6171                         max_speed = pcie_speed;
6172         }
6173         return max_speed;
6174 }
6175
6176 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6177 {
6178         u32 speed_cntl;
6179
6180         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6181         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6182
6183         return (u16)speed_cntl;
6184 }
6185
6186 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6187                                                              struct amdgpu_ps *amdgpu_new_state,
6188                                                              struct amdgpu_ps *amdgpu_current_state)
6189 {
6190         struct si_power_info *si_pi = si_get_pi(adev);
6191         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6192         enum amdgpu_pcie_gen current_link_speed;
6193
6194         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6195                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6196         else
6197                 current_link_speed = si_pi->force_pcie_gen;
6198
6199         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6200         si_pi->pspp_notify_required = false;
6201         if (target_link_speed > current_link_speed) {
6202                 switch (target_link_speed) {
6203 #if defined(CONFIG_ACPI)
6204                 case AMDGPU_PCIE_GEN3:
6205                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6206                                 break;
6207                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6208                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6209                                 break;
6210                 case AMDGPU_PCIE_GEN2:
6211                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6212                                 break;
6213 #endif
6214                 default:
6215                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6216                         break;
6217                 }
6218         } else {
6219                 if (target_link_speed < current_link_speed)
6220                         si_pi->pspp_notify_required = true;
6221         }
6222 }
6223
6224 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6225                                                            struct amdgpu_ps *amdgpu_new_state,
6226                                                            struct amdgpu_ps *amdgpu_current_state)
6227 {
6228         struct si_power_info *si_pi = si_get_pi(adev);
6229         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6230         u8 request;
6231
6232         if (si_pi->pspp_notify_required) {
6233                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6234                         request = PCIE_PERF_REQ_PECI_GEN3;
6235                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6236                         request = PCIE_PERF_REQ_PECI_GEN2;
6237                 else
6238                         request = PCIE_PERF_REQ_PECI_GEN1;
6239
6240                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6241                     (si_get_current_pcie_speed(adev) > 0))
6242                         return;
6243
6244 #if defined(CONFIG_ACPI)
6245                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6246 #endif
6247         }
6248 }
6249
6250 #if 0
6251 static int si_ds_request(struct amdgpu_device *adev,
6252                          bool ds_status_on, u32 count_write)
6253 {
6254         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6255
6256         if (eg_pi->sclk_deep_sleep) {
6257                 if (ds_status_on)
6258                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6259                                 PPSMC_Result_OK) ?
6260                                 0 : -EINVAL;
6261                 else
6262                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6263                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6264         }
6265         return 0;
6266 }
6267 #endif
6268
6269 static void si_set_max_cu_value(struct amdgpu_device *adev)
6270 {
6271         struct si_power_info *si_pi = si_get_pi(adev);
6272
6273         if (adev->asic_type == CHIP_VERDE) {
6274                 switch (adev->pdev->device) {
6275                 case 0x6820:
6276                 case 0x6825:
6277                 case 0x6821:
6278                 case 0x6823:
6279                 case 0x6827:
6280                         si_pi->max_cu = 10;
6281                         break;
6282                 case 0x682D:
6283                 case 0x6824:
6284                 case 0x682F:
6285                 case 0x6826:
6286                         si_pi->max_cu = 8;
6287                         break;
6288                 case 0x6828:
6289                 case 0x6830:
6290                 case 0x6831:
6291                 case 0x6838:
6292                 case 0x6839:
6293                 case 0x683D:
6294                         si_pi->max_cu = 10;
6295                         break;
6296                 case 0x683B:
6297                 case 0x683F:
6298                 case 0x6829:
6299                         si_pi->max_cu = 8;
6300                         break;
6301                 default:
6302                         si_pi->max_cu = 0;
6303                         break;
6304                 }
6305         } else {
6306                 si_pi->max_cu = 0;
6307         }
6308 }
6309
6310 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6311                                                              struct amdgpu_clock_voltage_dependency_table *table)
6312 {
6313         u32 i;
6314         int j;
6315         u16 leakage_voltage;
6316
6317         if (table) {
6318                 for (i = 0; i < table->count; i++) {
6319                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6320                                                                           table->entries[i].v,
6321                                                                           &leakage_voltage)) {
6322                         case 0:
6323                                 table->entries[i].v = leakage_voltage;
6324                                 break;
6325                         case -EAGAIN:
6326                                 return -EINVAL;
6327                         case -EINVAL:
6328                         default:
6329                                 break;
6330                         }
6331                 }
6332
6333                 for (j = (table->count - 2); j >= 0; j--) {
6334                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6335                                 table->entries[j].v : table->entries[j + 1].v;
6336                 }
6337         }
6338         return 0;
6339 }
6340
6341 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6342 {
6343         int ret = 0;
6344
6345         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6346                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6347         if (ret)
6348                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6349         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6350                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6351         if (ret)
6352                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6353         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6354                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6355         if (ret)
6356                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6357         return ret;
6358 }
6359
6360 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6361                                           struct amdgpu_ps *amdgpu_new_state,
6362                                           struct amdgpu_ps *amdgpu_current_state)
6363 {
6364         u32 lane_width;
6365         u32 new_lane_width =
6366                 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6367         u32 current_lane_width =
6368                 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6369
6370         if (new_lane_width != current_lane_width) {
6371                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6372                 lane_width = amdgpu_get_pcie_lanes(adev);
6373                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6374         }
6375 }
6376
6377 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6378 {
6379         si_read_clock_registers(adev);
6380         si_enable_acpi_power_management(adev);
6381 }
6382
6383 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6384                                    bool enable)
6385 {
6386         u32 thermal_int = RREG32(CG_THERMAL_INT);
6387
6388         if (enable) {
6389                 PPSMC_Result result;
6390
6391                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6392                 WREG32(CG_THERMAL_INT, thermal_int);
6393                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6394                 if (result != PPSMC_Result_OK) {
6395                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6396                         return -EINVAL;
6397                 }
6398         } else {
6399                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6400                 WREG32(CG_THERMAL_INT, thermal_int);
6401         }
6402
6403         return 0;
6404 }
6405
6406 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6407                                             int min_temp, int max_temp)
6408 {
6409         int low_temp = 0 * 1000;
6410         int high_temp = 255 * 1000;
6411
6412         if (low_temp < min_temp)
6413                 low_temp = min_temp;
6414         if (high_temp > max_temp)
6415                 high_temp = max_temp;
6416         if (high_temp < low_temp) {
6417                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6418                 return -EINVAL;
6419         }
6420
6421         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6422         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6423         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6424
6425         adev->pm.dpm.thermal.min_temp = low_temp;
6426         adev->pm.dpm.thermal.max_temp = high_temp;
6427
6428         return 0;
6429 }
6430
6431 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6432 {
6433         struct si_power_info *si_pi = si_get_pi(adev);
6434         u32 tmp;
6435
6436         if (si_pi->fan_ctrl_is_in_default_mode) {
6437                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6438                 si_pi->fan_ctrl_default_mode = tmp;
6439                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6440                 si_pi->t_min = tmp;
6441                 si_pi->fan_ctrl_is_in_default_mode = false;
6442         }
6443
6444         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6445         tmp |= TMIN(0);
6446         WREG32(CG_FDO_CTRL2, tmp);
6447
6448         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6449         tmp |= FDO_PWM_MODE(mode);
6450         WREG32(CG_FDO_CTRL2, tmp);
6451 }
6452
6453 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6454 {
6455         struct si_power_info *si_pi = si_get_pi(adev);
6456         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6457         u32 duty100;
6458         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6459         u16 fdo_min, slope1, slope2;
6460         u32 reference_clock, tmp;
6461         int ret;
6462         u64 tmp64;
6463
6464         if (!si_pi->fan_table_start) {
6465                 adev->pm.dpm.fan.ucode_fan_control = false;
6466                 return 0;
6467         }
6468
6469         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6470
6471         if (duty100 == 0) {
6472                 adev->pm.dpm.fan.ucode_fan_control = false;
6473                 return 0;
6474         }
6475
6476         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6477         do_div(tmp64, 10000);
6478         fdo_min = (u16)tmp64;
6479
6480         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6481         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6482
6483         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6484         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6485
6486         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6487         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6488
6489         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6490         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6491         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6492         fan_table.slope1 = cpu_to_be16(slope1);
6493         fan_table.slope2 = cpu_to_be16(slope2);
6494         fan_table.fdo_min = cpu_to_be16(fdo_min);
6495         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6496         fan_table.hys_up = cpu_to_be16(1);
6497         fan_table.hys_slope = cpu_to_be16(1);
6498         fan_table.temp_resp_lim = cpu_to_be16(5);
6499         reference_clock = amdgpu_asic_get_xclk(adev);
6500
6501         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6502                                                 reference_clock) / 1600);
6503         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6504
6505         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6506         fan_table.temp_src = (uint8_t)tmp;
6507
6508         ret = amdgpu_si_copy_bytes_to_smc(adev,
6509                                           si_pi->fan_table_start,
6510                                           (u8 *)(&fan_table),
6511                                           sizeof(fan_table),
6512                                           si_pi->sram_end);
6513
6514         if (ret) {
6515                 DRM_ERROR("Failed to load fan table to the SMC.");
6516                 adev->pm.dpm.fan.ucode_fan_control = false;
6517         }
6518
6519         return ret;
6520 }
6521
6522 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6523 {
6524         struct si_power_info *si_pi = si_get_pi(adev);
6525         PPSMC_Result ret;
6526
6527         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6528         if (ret == PPSMC_Result_OK) {
6529                 si_pi->fan_is_controlled_by_smc = true;
6530                 return 0;
6531         } else {
6532                 return -EINVAL;
6533         }
6534 }
6535
6536 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6537 {
6538         struct si_power_info *si_pi = si_get_pi(adev);
6539         PPSMC_Result ret;
6540
6541         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6542
6543         if (ret == PPSMC_Result_OK) {
6544                 si_pi->fan_is_controlled_by_smc = false;
6545                 return 0;
6546         } else {
6547                 return -EINVAL;
6548         }
6549 }
6550
6551 static int si_dpm_get_fan_speed_percent(void *handle,
6552                                       u32 *speed)
6553 {
6554         u32 duty, duty100;
6555         u64 tmp64;
6556         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6557
6558         if (adev->pm.no_fan)
6559                 return -ENOENT;
6560
6561         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6562         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6563
6564         if (duty100 == 0)
6565                 return -EINVAL;
6566
6567         tmp64 = (u64)duty * 100;
6568         do_div(tmp64, duty100);
6569         *speed = (u32)tmp64;
6570
6571         if (*speed > 100)
6572                 *speed = 100;
6573
6574         return 0;
6575 }
6576
6577 static int si_dpm_set_fan_speed_percent(void *handle,
6578                                       u32 speed)
6579 {
6580         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6581         struct si_power_info *si_pi = si_get_pi(adev);
6582         u32 tmp;
6583         u32 duty, duty100;
6584         u64 tmp64;
6585
6586         if (adev->pm.no_fan)
6587                 return -ENOENT;
6588
6589         if (si_pi->fan_is_controlled_by_smc)
6590                 return -EINVAL;
6591
6592         if (speed > 100)
6593                 return -EINVAL;
6594
6595         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6596
6597         if (duty100 == 0)
6598                 return -EINVAL;
6599
6600         tmp64 = (u64)speed * duty100;
6601         do_div(tmp64, 100);
6602         duty = (u32)tmp64;
6603
6604         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6605         tmp |= FDO_STATIC_DUTY(duty);
6606         WREG32(CG_FDO_CTRL0, tmp);
6607
6608         return 0;
6609 }
6610
6611 static void si_dpm_set_fan_control_mode(void *handle, u32 mode)
6612 {
6613         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6614
6615         if (mode) {
6616                 /* stop auto-manage */
6617                 if (adev->pm.dpm.fan.ucode_fan_control)
6618                         si_fan_ctrl_stop_smc_fan_control(adev);
6619                 si_fan_ctrl_set_static_mode(adev, mode);
6620         } else {
6621                 /* restart auto-manage */
6622                 if (adev->pm.dpm.fan.ucode_fan_control)
6623                         si_thermal_start_smc_fan_control(adev);
6624                 else
6625                         si_fan_ctrl_set_default_mode(adev);
6626         }
6627 }
6628
6629 static u32 si_dpm_get_fan_control_mode(void *handle)
6630 {
6631         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6632         struct si_power_info *si_pi = si_get_pi(adev);
6633         u32 tmp;
6634
6635         if (si_pi->fan_is_controlled_by_smc)
6636                 return 0;
6637
6638         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6639         return (tmp >> FDO_PWM_MODE_SHIFT);
6640 }
6641
6642 #if 0
6643 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6644                                          u32 *speed)
6645 {
6646         u32 tach_period;
6647         u32 xclk = amdgpu_asic_get_xclk(adev);
6648
6649         if (adev->pm.no_fan)
6650                 return -ENOENT;
6651
6652         if (adev->pm.fan_pulses_per_revolution == 0)
6653                 return -ENOENT;
6654
6655         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6656         if (tach_period == 0)
6657                 return -ENOENT;
6658
6659         *speed = 60 * xclk * 10000 / tach_period;
6660
6661         return 0;
6662 }
6663
6664 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6665                                          u32 speed)
6666 {
6667         u32 tach_period, tmp;
6668         u32 xclk = amdgpu_asic_get_xclk(adev);
6669
6670         if (adev->pm.no_fan)
6671                 return -ENOENT;
6672
6673         if (adev->pm.fan_pulses_per_revolution == 0)
6674                 return -ENOENT;
6675
6676         if ((speed < adev->pm.fan_min_rpm) ||
6677             (speed > adev->pm.fan_max_rpm))
6678                 return -EINVAL;
6679
6680         if (adev->pm.dpm.fan.ucode_fan_control)
6681                 si_fan_ctrl_stop_smc_fan_control(adev);
6682
6683         tach_period = 60 * xclk * 10000 / (8 * speed);
6684         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6685         tmp |= TARGET_PERIOD(tach_period);
6686         WREG32(CG_TACH_CTRL, tmp);
6687
6688         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6689
6690         return 0;
6691 }
6692 #endif
6693
6694 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6695 {
6696         struct si_power_info *si_pi = si_get_pi(adev);
6697         u32 tmp;
6698
6699         if (!si_pi->fan_ctrl_is_in_default_mode) {
6700                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6701                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6702                 WREG32(CG_FDO_CTRL2, tmp);
6703
6704                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6705                 tmp |= TMIN(si_pi->t_min);
6706                 WREG32(CG_FDO_CTRL2, tmp);
6707                 si_pi->fan_ctrl_is_in_default_mode = true;
6708         }
6709 }
6710
6711 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6712 {
6713         if (adev->pm.dpm.fan.ucode_fan_control) {
6714                 si_fan_ctrl_start_smc_fan_control(adev);
6715                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6716         }
6717 }
6718
6719 static void si_thermal_initialize(struct amdgpu_device *adev)
6720 {
6721         u32 tmp;
6722
6723         if (adev->pm.fan_pulses_per_revolution) {
6724                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6725                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6726                 WREG32(CG_TACH_CTRL, tmp);
6727         }
6728
6729         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6730         tmp |= TACH_PWM_RESP_RATE(0x28);
6731         WREG32(CG_FDO_CTRL2, tmp);
6732 }
6733
6734 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6735 {
6736         int ret;
6737
6738         si_thermal_initialize(adev);
6739         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6740         if (ret)
6741                 return ret;
6742         ret = si_thermal_enable_alert(adev, true);
6743         if (ret)
6744                 return ret;
6745         if (adev->pm.dpm.fan.ucode_fan_control) {
6746                 ret = si_halt_smc(adev);
6747                 if (ret)
6748                         return ret;
6749                 ret = si_thermal_setup_fan_table(adev);
6750                 if (ret)
6751                         return ret;
6752                 ret = si_resume_smc(adev);
6753                 if (ret)
6754                         return ret;
6755                 si_thermal_start_smc_fan_control(adev);
6756         }
6757
6758         return 0;
6759 }
6760
6761 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6762 {
6763         if (!adev->pm.no_fan) {
6764                 si_fan_ctrl_set_default_mode(adev);
6765                 si_fan_ctrl_stop_smc_fan_control(adev);
6766         }
6767 }
6768
6769 static int si_dpm_enable(struct amdgpu_device *adev)
6770 {
6771         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6772         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6773         struct si_power_info *si_pi = si_get_pi(adev);
6774         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6775         int ret;
6776
6777         if (amdgpu_si_is_smc_running(adev))
6778                 return -EINVAL;
6779         if (pi->voltage_control || si_pi->voltage_control_svi2)
6780                 si_enable_voltage_control(adev, true);
6781         if (pi->mvdd_control)
6782                 si_get_mvdd_configuration(adev);
6783         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6784                 ret = si_construct_voltage_tables(adev);
6785                 if (ret) {
6786                         DRM_ERROR("si_construct_voltage_tables failed\n");
6787                         return ret;
6788                 }
6789         }
6790         if (eg_pi->dynamic_ac_timing) {
6791                 ret = si_initialize_mc_reg_table(adev);
6792                 if (ret)
6793                         eg_pi->dynamic_ac_timing = false;
6794         }
6795         if (pi->dynamic_ss)
6796                 si_enable_spread_spectrum(adev, true);
6797         if (pi->thermal_protection)
6798                 si_enable_thermal_protection(adev, true);
6799         si_setup_bsp(adev);
6800         si_program_git(adev);
6801         si_program_tp(adev);
6802         si_program_tpp(adev);
6803         si_program_sstp(adev);
6804         si_enable_display_gap(adev);
6805         si_program_vc(adev);
6806         ret = si_upload_firmware(adev);
6807         if (ret) {
6808                 DRM_ERROR("si_upload_firmware failed\n");
6809                 return ret;
6810         }
6811         ret = si_process_firmware_header(adev);
6812         if (ret) {
6813                 DRM_ERROR("si_process_firmware_header failed\n");
6814                 return ret;
6815         }
6816         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6817         if (ret) {
6818                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6819                 return ret;
6820         }
6821         ret = si_init_smc_table(adev);
6822         if (ret) {
6823                 DRM_ERROR("si_init_smc_table failed\n");
6824                 return ret;
6825         }
6826         ret = si_init_smc_spll_table(adev);
6827         if (ret) {
6828                 DRM_ERROR("si_init_smc_spll_table failed\n");
6829                 return ret;
6830         }
6831         ret = si_init_arb_table_index(adev);
6832         if (ret) {
6833                 DRM_ERROR("si_init_arb_table_index failed\n");
6834                 return ret;
6835         }
6836         if (eg_pi->dynamic_ac_timing) {
6837                 ret = si_populate_mc_reg_table(adev, boot_ps);
6838                 if (ret) {
6839                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6840                         return ret;
6841                 }
6842         }
6843         ret = si_initialize_smc_cac_tables(adev);
6844         if (ret) {
6845                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6846                 return ret;
6847         }
6848         ret = si_initialize_hardware_cac_manager(adev);
6849         if (ret) {
6850                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6851                 return ret;
6852         }
6853         ret = si_initialize_smc_dte_tables(adev);
6854         if (ret) {
6855                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6856                 return ret;
6857         }
6858         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6859         if (ret) {
6860                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6861                 return ret;
6862         }
6863         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6864         if (ret) {
6865                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6866                 return ret;
6867         }
6868         si_program_response_times(adev);
6869         si_program_ds_registers(adev);
6870         si_dpm_start_smc(adev);
6871         ret = si_notify_smc_display_change(adev, false);
6872         if (ret) {
6873                 DRM_ERROR("si_notify_smc_display_change failed\n");
6874                 return ret;
6875         }
6876         si_enable_sclk_control(adev, true);
6877         si_start_dpm(adev);
6878
6879         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6880         si_thermal_start_thermal_controller(adev);
6881
6882         return 0;
6883 }
6884
6885 static int si_set_temperature_range(struct amdgpu_device *adev)
6886 {
6887         int ret;
6888
6889         ret = si_thermal_enable_alert(adev, false);
6890         if (ret)
6891                 return ret;
6892         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6893         if (ret)
6894                 return ret;
6895         ret = si_thermal_enable_alert(adev, true);
6896         if (ret)
6897                 return ret;
6898
6899         return ret;
6900 }
6901
6902 static void si_dpm_disable(struct amdgpu_device *adev)
6903 {
6904         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6905         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6906
6907         if (!amdgpu_si_is_smc_running(adev))
6908                 return;
6909         si_thermal_stop_thermal_controller(adev);
6910         si_disable_ulv(adev);
6911         si_clear_vc(adev);
6912         if (pi->thermal_protection)
6913                 si_enable_thermal_protection(adev, false);
6914         si_enable_power_containment(adev, boot_ps, false);
6915         si_enable_smc_cac(adev, boot_ps, false);
6916         si_enable_spread_spectrum(adev, false);
6917         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6918         si_stop_dpm(adev);
6919         si_reset_to_default(adev);
6920         si_dpm_stop_smc(adev);
6921         si_force_switch_to_arb_f0(adev);
6922
6923         ni_update_current_ps(adev, boot_ps);
6924 }
6925
6926 static int si_dpm_pre_set_power_state(void *handle)
6927 {
6928         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6929         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6930         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6931         struct amdgpu_ps *new_ps = &requested_ps;
6932
6933         ni_update_requested_ps(adev, new_ps);
6934         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6935
6936         return 0;
6937 }
6938
6939 static int si_power_control_set_level(struct amdgpu_device *adev)
6940 {
6941         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6942         int ret;
6943
6944         ret = si_restrict_performance_levels_before_switch(adev);
6945         if (ret)
6946                 return ret;
6947         ret = si_halt_smc(adev);
6948         if (ret)
6949                 return ret;
6950         ret = si_populate_smc_tdp_limits(adev, new_ps);
6951         if (ret)
6952                 return ret;
6953         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6954         if (ret)
6955                 return ret;
6956         ret = si_resume_smc(adev);
6957         if (ret)
6958                 return ret;
6959         ret = si_set_sw_state(adev);
6960         if (ret)
6961                 return ret;
6962         return 0;
6963 }
6964
6965 static int si_dpm_set_power_state(void *handle)
6966 {
6967         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6968         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6969         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6970         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6971         int ret;
6972
6973         ret = si_disable_ulv(adev);
6974         if (ret) {
6975                 DRM_ERROR("si_disable_ulv failed\n");
6976                 return ret;
6977         }
6978         ret = si_restrict_performance_levels_before_switch(adev);
6979         if (ret) {
6980                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6981                 return ret;
6982         }
6983         if (eg_pi->pcie_performance_request)
6984                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
6985         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
6986         ret = si_enable_power_containment(adev, new_ps, false);
6987         if (ret) {
6988                 DRM_ERROR("si_enable_power_containment failed\n");
6989                 return ret;
6990         }
6991         ret = si_enable_smc_cac(adev, new_ps, false);
6992         if (ret) {
6993                 DRM_ERROR("si_enable_smc_cac failed\n");
6994                 return ret;
6995         }
6996         ret = si_halt_smc(adev);
6997         if (ret) {
6998                 DRM_ERROR("si_halt_smc failed\n");
6999                 return ret;
7000         }
7001         ret = si_upload_sw_state(adev, new_ps);
7002         if (ret) {
7003                 DRM_ERROR("si_upload_sw_state failed\n");
7004                 return ret;
7005         }
7006         ret = si_upload_smc_data(adev);
7007         if (ret) {
7008                 DRM_ERROR("si_upload_smc_data failed\n");
7009                 return ret;
7010         }
7011         ret = si_upload_ulv_state(adev);
7012         if (ret) {
7013                 DRM_ERROR("si_upload_ulv_state failed\n");
7014                 return ret;
7015         }
7016         if (eg_pi->dynamic_ac_timing) {
7017                 ret = si_upload_mc_reg_table(adev, new_ps);
7018                 if (ret) {
7019                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7020                         return ret;
7021                 }
7022         }
7023         ret = si_program_memory_timing_parameters(adev, new_ps);
7024         if (ret) {
7025                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7026                 return ret;
7027         }
7028         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7029
7030         ret = si_resume_smc(adev);
7031         if (ret) {
7032                 DRM_ERROR("si_resume_smc failed\n");
7033                 return ret;
7034         }
7035         ret = si_set_sw_state(adev);
7036         if (ret) {
7037                 DRM_ERROR("si_set_sw_state failed\n");
7038                 return ret;
7039         }
7040         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7041         if (eg_pi->pcie_performance_request)
7042                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7043         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7044         if (ret) {
7045                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7046                 return ret;
7047         }
7048         ret = si_enable_smc_cac(adev, new_ps, true);
7049         if (ret) {
7050                 DRM_ERROR("si_enable_smc_cac failed\n");
7051                 return ret;
7052         }
7053         ret = si_enable_power_containment(adev, new_ps, true);
7054         if (ret) {
7055                 DRM_ERROR("si_enable_power_containment failed\n");
7056                 return ret;
7057         }
7058
7059         ret = si_power_control_set_level(adev);
7060         if (ret) {
7061                 DRM_ERROR("si_power_control_set_level failed\n");
7062                 return ret;
7063         }
7064
7065         return 0;
7066 }
7067
7068 static void si_dpm_post_set_power_state(void *handle)
7069 {
7070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7071         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7072         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7073
7074         ni_update_current_ps(adev, new_ps);
7075 }
7076
7077 #if 0
7078 void si_dpm_reset_asic(struct amdgpu_device *adev)
7079 {
7080         si_restrict_performance_levels_before_switch(adev);
7081         si_disable_ulv(adev);
7082         si_set_boot_state(adev);
7083 }
7084 #endif
7085
7086 static void si_dpm_display_configuration_changed(void *handle)
7087 {
7088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7089
7090         si_program_display_gap(adev);
7091 }
7092
7093
7094 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7095                                           struct amdgpu_ps *rps,
7096                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7097                                           u8 table_rev)
7098 {
7099         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7100         rps->class = le16_to_cpu(non_clock_info->usClassification);
7101         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7102
7103         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7104                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7105                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7106         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7107                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7108                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7109         } else {
7110                 rps->vclk = 0;
7111                 rps->dclk = 0;
7112         }
7113
7114         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7115                 adev->pm.dpm.boot_ps = rps;
7116         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7117                 adev->pm.dpm.uvd_ps = rps;
7118 }
7119
7120 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7121                                       struct amdgpu_ps *rps, int index,
7122                                       union pplib_clock_info *clock_info)
7123 {
7124         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7125         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7126         struct si_power_info *si_pi = si_get_pi(adev);
7127         struct  si_ps *ps = si_get_ps(rps);
7128         u16 leakage_voltage;
7129         struct rv7xx_pl *pl = &ps->performance_levels[index];
7130         int ret;
7131
7132         ps->performance_level_count = index + 1;
7133
7134         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7135         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7136         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7137         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7138
7139         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7140         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7141         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7142         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7143                                                    si_pi->sys_pcie_mask,
7144                                                    si_pi->boot_pcie_gen,
7145                                                    clock_info->si.ucPCIEGen);
7146
7147         /* patch up vddc if necessary */
7148         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7149                                                         &leakage_voltage);
7150         if (ret == 0)
7151                 pl->vddc = leakage_voltage;
7152
7153         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7154                 pi->acpi_vddc = pl->vddc;
7155                 eg_pi->acpi_vddci = pl->vddci;
7156                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7157         }
7158
7159         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7160             index == 0) {
7161                 /* XXX disable for A0 tahiti */
7162                 si_pi->ulv.supported = false;
7163                 si_pi->ulv.pl = *pl;
7164                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7165                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7166                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7167                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7168         }
7169
7170         if (pi->min_vddc_in_table > pl->vddc)
7171                 pi->min_vddc_in_table = pl->vddc;
7172
7173         if (pi->max_vddc_in_table < pl->vddc)
7174                 pi->max_vddc_in_table = pl->vddc;
7175
7176         /* patch up boot state */
7177         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7178                 u16 vddc, vddci, mvdd;
7179                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7180                 pl->mclk = adev->clock.default_mclk;
7181                 pl->sclk = adev->clock.default_sclk;
7182                 pl->vddc = vddc;
7183                 pl->vddci = vddci;
7184                 si_pi->mvdd_bootup_value = mvdd;
7185         }
7186
7187         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7188             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7189                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7190                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7191                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7192                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7193         }
7194 }
7195
7196 union pplib_power_state {
7197         struct _ATOM_PPLIB_STATE v1;
7198         struct _ATOM_PPLIB_STATE_V2 v2;
7199 };
7200
7201 static int si_parse_power_table(struct amdgpu_device *adev)
7202 {
7203         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7204         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7205         union pplib_power_state *power_state;
7206         int i, j, k, non_clock_array_index, clock_array_index;
7207         union pplib_clock_info *clock_info;
7208         struct _StateArray *state_array;
7209         struct _ClockInfoArray *clock_info_array;
7210         struct _NonClockInfoArray *non_clock_info_array;
7211         union power_info *power_info;
7212         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7213         u16 data_offset;
7214         u8 frev, crev;
7215         u8 *power_state_offset;
7216         struct  si_ps *ps;
7217
7218         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7219                                    &frev, &crev, &data_offset))
7220                 return -EINVAL;
7221         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7222
7223         amdgpu_add_thermal_controller(adev);
7224
7225         state_array = (struct _StateArray *)
7226                 (mode_info->atom_context->bios + data_offset +
7227                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7228         clock_info_array = (struct _ClockInfoArray *)
7229                 (mode_info->atom_context->bios + data_offset +
7230                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7231         non_clock_info_array = (struct _NonClockInfoArray *)
7232                 (mode_info->atom_context->bios + data_offset +
7233                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7234
7235         adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
7236                                   sizeof(struct amdgpu_ps),
7237                                   GFP_KERNEL);
7238         if (!adev->pm.dpm.ps)
7239                 return -ENOMEM;
7240         power_state_offset = (u8 *)state_array->states;
7241         for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) {
7242                 u8 *idx;
7243                 power_state = (union pplib_power_state *)power_state_offset;
7244                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7245                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7246                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7247                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7248                 if (ps == NULL)
7249                         return -ENOMEM;
7250                 adev->pm.dpm.ps[i].ps_priv = ps;
7251                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7252                                               non_clock_info,
7253                                               non_clock_info_array->ucEntrySize);
7254                 k = 0;
7255                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7256                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7257                         clock_array_index = idx[j];
7258                         if (clock_array_index >= clock_info_array->ucNumEntries)
7259                                 continue;
7260                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7261                                 break;
7262                         clock_info = (union pplib_clock_info *)
7263                                 ((u8 *)&clock_info_array->clockInfo[0] +
7264                                  (clock_array_index * clock_info_array->ucEntrySize));
7265                         si_parse_pplib_clock_info(adev,
7266                                                   &adev->pm.dpm.ps[i], k,
7267                                                   clock_info);
7268                         k++;
7269                 }
7270                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7271                 adev->pm.dpm.num_ps++;
7272         }
7273
7274         /* fill in the vce power states */
7275         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7276                 u32 sclk, mclk;
7277                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7278                 clock_info = (union pplib_clock_info *)
7279                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7280                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7281                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7282                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7283                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7284                 adev->pm.dpm.vce_states[i].sclk = sclk;
7285                 adev->pm.dpm.vce_states[i].mclk = mclk;
7286         }
7287
7288         return 0;
7289 }
7290
7291 static int si_dpm_init(struct amdgpu_device *adev)
7292 {
7293         struct rv7xx_power_info *pi;
7294         struct evergreen_power_info *eg_pi;
7295         struct ni_power_info *ni_pi;
7296         struct si_power_info *si_pi;
7297         struct atom_clock_dividers dividers;
7298         int ret;
7299
7300         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7301         if (si_pi == NULL)
7302                 return -ENOMEM;
7303         adev->pm.dpm.priv = si_pi;
7304         ni_pi = &si_pi->ni;
7305         eg_pi = &ni_pi->eg;
7306         pi = &eg_pi->rv7xx;
7307
7308         si_pi->sys_pcie_mask =
7309                 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
7310         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7311         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7312
7313         si_set_max_cu_value(adev);
7314
7315         rv770_get_max_vddc(adev);
7316         si_get_leakage_vddc(adev);
7317         si_patch_dependency_tables_based_on_leakage(adev);
7318
7319         pi->acpi_vddc = 0;
7320         eg_pi->acpi_vddci = 0;
7321         pi->min_vddc_in_table = 0;
7322         pi->max_vddc_in_table = 0;
7323
7324         ret = amdgpu_get_platform_caps(adev);
7325         if (ret)
7326                 return ret;
7327
7328         ret = amdgpu_parse_extended_power_table(adev);
7329         if (ret)
7330                 return ret;
7331
7332         ret = si_parse_power_table(adev);
7333         if (ret)
7334                 return ret;
7335
7336         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7337                 kcalloc(4,
7338                         sizeof(struct amdgpu_clock_voltage_dependency_entry),
7339                         GFP_KERNEL);
7340         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7341                 amdgpu_free_extended_power_table(adev);
7342                 return -ENOMEM;
7343         }
7344         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7345         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7346         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7347         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7348         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7349         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7350         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7351         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7352         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7353
7354         if (adev->pm.dpm.voltage_response_time == 0)
7355                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7356         if (adev->pm.dpm.backbias_response_time == 0)
7357                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7358
7359         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7360                                              0, false, &dividers);
7361         if (ret)
7362                 pi->ref_div = dividers.ref_div + 1;
7363         else
7364                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7365
7366         eg_pi->smu_uvd_hs = false;
7367
7368         pi->mclk_strobe_mode_threshold = 40000;
7369         if (si_is_special_1gb_platform(adev))
7370                 pi->mclk_stutter_mode_threshold = 0;
7371         else
7372                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7373         pi->mclk_edc_enable_threshold = 40000;
7374         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7375
7376         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7377
7378         pi->voltage_control =
7379                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7380                                             VOLTAGE_OBJ_GPIO_LUT);
7381         if (!pi->voltage_control) {
7382                 si_pi->voltage_control_svi2 =
7383                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7384                                                     VOLTAGE_OBJ_SVID2);
7385                 if (si_pi->voltage_control_svi2)
7386                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7387                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7388         }
7389
7390         pi->mvdd_control =
7391                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7392                                             VOLTAGE_OBJ_GPIO_LUT);
7393
7394         eg_pi->vddci_control =
7395                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7396                                             VOLTAGE_OBJ_GPIO_LUT);
7397         if (!eg_pi->vddci_control)
7398                 si_pi->vddci_control_svi2 =
7399                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7400                                                     VOLTAGE_OBJ_SVID2);
7401
7402         si_pi->vddc_phase_shed_control =
7403                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7404                                             VOLTAGE_OBJ_PHASE_LUT);
7405
7406         rv770_get_engine_memory_ss(adev);
7407
7408         pi->asi = RV770_ASI_DFLT;
7409         pi->pasi = CYPRESS_HASI_DFLT;
7410         pi->vrc = SISLANDS_VRC_DFLT;
7411
7412         pi->gfx_clock_gating = true;
7413
7414         eg_pi->sclk_deep_sleep = true;
7415         si_pi->sclk_deep_sleep_above_low = false;
7416
7417         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7418                 pi->thermal_protection = true;
7419         else
7420                 pi->thermal_protection = false;
7421
7422         eg_pi->dynamic_ac_timing = true;
7423
7424         eg_pi->light_sleep = true;
7425 #if defined(CONFIG_ACPI)
7426         eg_pi->pcie_performance_request =
7427                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7428 #else
7429         eg_pi->pcie_performance_request = false;
7430 #endif
7431
7432         si_pi->sram_end = SMC_RAM_END;
7433
7434         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7435         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7436         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7437         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7438         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7439         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7440         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7441
7442         si_initialize_powertune_defaults(adev);
7443
7444         /* make sure dc limits are valid */
7445         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7446             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7447                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7448                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7449
7450         si_pi->fan_ctrl_is_in_default_mode = true;
7451
7452         return 0;
7453 }
7454
7455 static void si_dpm_fini(struct amdgpu_device *adev)
7456 {
7457         int i;
7458
7459         if (adev->pm.dpm.ps)
7460                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7461                         kfree(adev->pm.dpm.ps[i].ps_priv);
7462         kfree(adev->pm.dpm.ps);
7463         kfree(adev->pm.dpm.priv);
7464         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7465         amdgpu_free_extended_power_table(adev);
7466 }
7467
7468 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7469                                                     struct seq_file *m)
7470 {
7471         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7472         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7473         struct amdgpu_ps *rps = &eg_pi->current_rps;
7474         struct  si_ps *ps = si_get_ps(rps);
7475         struct rv7xx_pl *pl;
7476         u32 current_index =
7477                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7478                 CURRENT_STATE_INDEX_SHIFT;
7479
7480         if (current_index >= ps->performance_level_count) {
7481                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7482         } else {
7483                 pl = &ps->performance_levels[current_index];
7484                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7485                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7486                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7487         }
7488 }
7489
7490 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7491                                       struct amdgpu_irq_src *source,
7492                                       unsigned type,
7493                                       enum amdgpu_interrupt_state state)
7494 {
7495         u32 cg_thermal_int;
7496
7497         switch (type) {
7498         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7499                 switch (state) {
7500                 case AMDGPU_IRQ_STATE_DISABLE:
7501                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7502                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7503                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7504                         break;
7505                 case AMDGPU_IRQ_STATE_ENABLE:
7506                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7507                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7508                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7509                         break;
7510                 default:
7511                         break;
7512                 }
7513                 break;
7514
7515         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7516                 switch (state) {
7517                 case AMDGPU_IRQ_STATE_DISABLE:
7518                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7519                         cg_thermal_int |= THERM_INT_MASK_LOW;
7520                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7521                         break;
7522                 case AMDGPU_IRQ_STATE_ENABLE:
7523                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7524                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7525                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7526                         break;
7527                 default:
7528                         break;
7529                 }
7530                 break;
7531
7532         default:
7533                 break;
7534         }
7535         return 0;
7536 }
7537
7538 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7539                                     struct amdgpu_irq_src *source,
7540                                     struct amdgpu_iv_entry *entry)
7541 {
7542         bool queue_thermal = false;
7543
7544         if (entry == NULL)
7545                 return -EINVAL;
7546
7547         switch (entry->src_id) {
7548         case 230: /* thermal low to high */
7549                 DRM_DEBUG("IH: thermal low to high\n");
7550                 adev->pm.dpm.thermal.high_to_low = false;
7551                 queue_thermal = true;
7552                 break;
7553         case 231: /* thermal high to low */
7554                 DRM_DEBUG("IH: thermal high to low\n");
7555                 adev->pm.dpm.thermal.high_to_low = true;
7556                 queue_thermal = true;
7557                 break;
7558         default:
7559                 break;
7560         }
7561
7562         if (queue_thermal)
7563                 schedule_work(&adev->pm.dpm.thermal.work);
7564
7565         return 0;
7566 }
7567
7568 static int si_dpm_late_init(void *handle)
7569 {
7570         int ret;
7571         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7572
7573         if (!adev->pm.dpm_enabled)
7574                 return 0;
7575
7576         ret = si_set_temperature_range(adev);
7577         if (ret)
7578                 return ret;
7579 #if 0 //TODO ?
7580         si_dpm_powergate_uvd(adev, true);
7581 #endif
7582         return 0;
7583 }
7584
7585 /**
7586  * si_dpm_init_microcode - load ucode images from disk
7587  *
7588  * @adev: amdgpu_device pointer
7589  *
7590  * Use the firmware interface to load the ucode images into
7591  * the driver (not loaded into hw).
7592  * Returns 0 on success, error on failure.
7593  */
7594 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7595 {
7596         const char *chip_name;
7597         char fw_name[30];
7598         int err;
7599
7600         DRM_DEBUG("\n");
7601         switch (adev->asic_type) {
7602         case CHIP_TAHITI:
7603                 chip_name = "tahiti";
7604                 break;
7605         case CHIP_PITCAIRN:
7606                 if ((adev->pdev->revision == 0x81) &&
7607                     ((adev->pdev->device == 0x6810) ||
7608                     (adev->pdev->device == 0x6811)))
7609                         chip_name = "pitcairn_k";
7610                 else
7611                         chip_name = "pitcairn";
7612                 break;
7613         case CHIP_VERDE:
7614                 if (((adev->pdev->device == 0x6820) &&
7615                         ((adev->pdev->revision == 0x81) ||
7616                         (adev->pdev->revision == 0x83))) ||
7617                     ((adev->pdev->device == 0x6821) &&
7618                         ((adev->pdev->revision == 0x83) ||
7619                         (adev->pdev->revision == 0x87))) ||
7620                     ((adev->pdev->revision == 0x87) &&
7621                         ((adev->pdev->device == 0x6823) ||
7622                         (adev->pdev->device == 0x682b))))
7623                         chip_name = "verde_k";
7624                 else
7625                         chip_name = "verde";
7626                 break;
7627         case CHIP_OLAND:
7628                 if (((adev->pdev->revision == 0x81) &&
7629                         ((adev->pdev->device == 0x6600) ||
7630                         (adev->pdev->device == 0x6604) ||
7631                         (adev->pdev->device == 0x6605) ||
7632                         (adev->pdev->device == 0x6610))) ||
7633                     ((adev->pdev->revision == 0x83) &&
7634                         (adev->pdev->device == 0x6610)))
7635                         chip_name = "oland_k";
7636                 else
7637                         chip_name = "oland";
7638                 break;
7639         case CHIP_HAINAN:
7640                 if (((adev->pdev->revision == 0x81) &&
7641                         (adev->pdev->device == 0x6660)) ||
7642                     ((adev->pdev->revision == 0x83) &&
7643                         ((adev->pdev->device == 0x6660) ||
7644                         (adev->pdev->device == 0x6663) ||
7645                         (adev->pdev->device == 0x6665) ||
7646                          (adev->pdev->device == 0x6667))))
7647                         chip_name = "hainan_k";
7648                 else if ((adev->pdev->revision == 0xc3) &&
7649                          (adev->pdev->device == 0x6665))
7650                         chip_name = "banks_k_2";
7651                 else
7652                         chip_name = "hainan";
7653                 break;
7654         default: BUG();
7655         }
7656
7657         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
7658         err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
7659         if (err)
7660                 goto out;
7661         err = amdgpu_ucode_validate(adev->pm.fw);
7662
7663 out:
7664         if (err) {
7665                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7666                           err, fw_name);
7667                 release_firmware(adev->pm.fw);
7668                 adev->pm.fw = NULL;
7669         }
7670         return err;
7671
7672 }
7673
7674 static int si_dpm_sw_init(void *handle)
7675 {
7676         int ret;
7677         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7678
7679         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7680         if (ret)
7681                 return ret;
7682
7683         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7684         if (ret)
7685                 return ret;
7686
7687         /* default to balanced state */
7688         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7689         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7690         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7691         adev->pm.default_sclk = adev->clock.default_sclk;
7692         adev->pm.default_mclk = adev->clock.default_mclk;
7693         adev->pm.current_sclk = adev->clock.default_sclk;
7694         adev->pm.current_mclk = adev->clock.default_mclk;
7695         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7696
7697         if (amdgpu_dpm == 0)
7698                 return 0;
7699
7700         ret = si_dpm_init_microcode(adev);
7701         if (ret)
7702                 return ret;
7703
7704         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7705         mutex_lock(&adev->pm.mutex);
7706         ret = si_dpm_init(adev);
7707         if (ret)
7708                 goto dpm_failed;
7709         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7710         if (amdgpu_dpm == 1)
7711                 amdgpu_pm_print_power_states(adev);
7712         mutex_unlock(&adev->pm.mutex);
7713         DRM_INFO("amdgpu: dpm initialized\n");
7714
7715         return 0;
7716
7717 dpm_failed:
7718         si_dpm_fini(adev);
7719         mutex_unlock(&adev->pm.mutex);
7720         DRM_ERROR("amdgpu: dpm initialization failed\n");
7721         return ret;
7722 }
7723
7724 static int si_dpm_sw_fini(void *handle)
7725 {
7726         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7727
7728         flush_work(&adev->pm.dpm.thermal.work);
7729
7730         mutex_lock(&adev->pm.mutex);
7731         si_dpm_fini(adev);
7732         mutex_unlock(&adev->pm.mutex);
7733
7734         return 0;
7735 }
7736
7737 static int si_dpm_hw_init(void *handle)
7738 {
7739         int ret;
7740
7741         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7742
7743         if (!amdgpu_dpm)
7744                 return 0;
7745
7746         mutex_lock(&adev->pm.mutex);
7747         si_dpm_setup_asic(adev);
7748         ret = si_dpm_enable(adev);
7749         if (ret)
7750                 adev->pm.dpm_enabled = false;
7751         else
7752                 adev->pm.dpm_enabled = true;
7753         mutex_unlock(&adev->pm.mutex);
7754         amdgpu_pm_compute_clocks(adev);
7755         return ret;
7756 }
7757
7758 static int si_dpm_hw_fini(void *handle)
7759 {
7760         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7761
7762         if (adev->pm.dpm_enabled) {
7763                 mutex_lock(&adev->pm.mutex);
7764                 si_dpm_disable(adev);
7765                 mutex_unlock(&adev->pm.mutex);
7766         }
7767
7768         return 0;
7769 }
7770
7771 static int si_dpm_suspend(void *handle)
7772 {
7773         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7774
7775         if (adev->pm.dpm_enabled) {
7776                 mutex_lock(&adev->pm.mutex);
7777                 /* disable dpm */
7778                 si_dpm_disable(adev);
7779                 /* reset the power state */
7780                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7781                 mutex_unlock(&adev->pm.mutex);
7782         }
7783         return 0;
7784 }
7785
7786 static int si_dpm_resume(void *handle)
7787 {
7788         int ret;
7789         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7790
7791         if (adev->pm.dpm_enabled) {
7792                 /* asic init will reset to the boot state */
7793                 mutex_lock(&adev->pm.mutex);
7794                 si_dpm_setup_asic(adev);
7795                 ret = si_dpm_enable(adev);
7796                 if (ret)
7797                         adev->pm.dpm_enabled = false;
7798                 else
7799                         adev->pm.dpm_enabled = true;
7800                 mutex_unlock(&adev->pm.mutex);
7801                 if (adev->pm.dpm_enabled)
7802                         amdgpu_pm_compute_clocks(adev);
7803         }
7804         return 0;
7805 }
7806
7807 static bool si_dpm_is_idle(void *handle)
7808 {
7809         /* XXX */
7810         return true;
7811 }
7812
7813 static int si_dpm_wait_for_idle(void *handle)
7814 {
7815         /* XXX */
7816         return 0;
7817 }
7818
7819 static int si_dpm_soft_reset(void *handle)
7820 {
7821         return 0;
7822 }
7823
7824 static int si_dpm_set_clockgating_state(void *handle,
7825                                         enum amd_clockgating_state state)
7826 {
7827         return 0;
7828 }
7829
7830 static int si_dpm_set_powergating_state(void *handle,
7831                                         enum amd_powergating_state state)
7832 {
7833         return 0;
7834 }
7835
7836 /* get temperature in millidegrees */
7837 static int si_dpm_get_temp(void *handle)
7838 {
7839         u32 temp;
7840         int actual_temp = 0;
7841         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7842
7843         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7844                 CTF_TEMP_SHIFT;
7845
7846         if (temp & 0x200)
7847                 actual_temp = 255;
7848         else
7849                 actual_temp = temp & 0x1ff;
7850
7851         actual_temp = (actual_temp * 1000);
7852
7853         return actual_temp;
7854 }
7855
7856 static u32 si_dpm_get_sclk(void *handle, bool low)
7857 {
7858         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7859         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7860         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7861
7862         if (low)
7863                 return requested_state->performance_levels[0].sclk;
7864         else
7865                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7866 }
7867
7868 static u32 si_dpm_get_mclk(void *handle, bool low)
7869 {
7870         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7871         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7872         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7873
7874         if (low)
7875                 return requested_state->performance_levels[0].mclk;
7876         else
7877                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7878 }
7879
7880 static void si_dpm_print_power_state(void *handle,
7881                                      void *current_ps)
7882 {
7883         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7884         struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7885         struct  si_ps *ps = si_get_ps(rps);
7886         struct rv7xx_pl *pl;
7887         int i;
7888
7889         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7890         amdgpu_dpm_print_cap_info(rps->caps);
7891         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7892         for (i = 0; i < ps->performance_level_count; i++) {
7893                 pl = &ps->performance_levels[i];
7894                 if (adev->asic_type >= CHIP_TAHITI)
7895                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7896                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7897                 else
7898                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7899                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7900         }
7901         amdgpu_dpm_print_ps_status(adev, rps);
7902 }
7903
7904 static int si_dpm_early_init(void *handle)
7905 {
7906
7907         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7908
7909         adev->powerplay.pp_funcs = &si_dpm_funcs;
7910         adev->powerplay.pp_handle = adev;
7911         si_dpm_set_irq_funcs(adev);
7912         return 0;
7913 }
7914
7915 static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7916                                                 const struct rv7xx_pl *si_cpl2)
7917 {
7918         return ((si_cpl1->mclk == si_cpl2->mclk) &&
7919                   (si_cpl1->sclk == si_cpl2->sclk) &&
7920                   (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7921                   (si_cpl1->vddc == si_cpl2->vddc) &&
7922                   (si_cpl1->vddci == si_cpl2->vddci));
7923 }
7924
7925 static int si_check_state_equal(void *handle,
7926                                 void *current_ps,
7927                                 void *request_ps,
7928                                 bool *equal)
7929 {
7930         struct si_ps *si_cps;
7931         struct si_ps *si_rps;
7932         int i;
7933         struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
7934         struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
7935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7936
7937         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7938                 return -EINVAL;
7939
7940         si_cps = si_get_ps((struct amdgpu_ps *)cps);
7941         si_rps = si_get_ps((struct amdgpu_ps *)rps);
7942
7943         if (si_cps == NULL) {
7944                 printk("si_cps is NULL\n");
7945                 *equal = false;
7946                 return 0;
7947         }
7948
7949         if (si_cps->performance_level_count != si_rps->performance_level_count) {
7950                 *equal = false;
7951                 return 0;
7952         }
7953
7954         for (i = 0; i < si_cps->performance_level_count; i++) {
7955                 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7956                                         &(si_rps->performance_levels[i]))) {
7957                         *equal = false;
7958                         return 0;
7959                 }
7960         }
7961
7962         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7963         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7964         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7965
7966         return 0;
7967 }
7968
7969 static int si_dpm_read_sensor(void *handle, int idx,
7970                               void *value, int *size)
7971 {
7972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7973         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7974         struct amdgpu_ps *rps = &eg_pi->current_rps;
7975         struct  si_ps *ps = si_get_ps(rps);
7976         uint32_t sclk, mclk;
7977         u32 pl_index =
7978                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7979                 CURRENT_STATE_INDEX_SHIFT;
7980
7981         /* size must be at least 4 bytes for all sensors */
7982         if (*size < 4)
7983                 return -EINVAL;
7984
7985         switch (idx) {
7986         case AMDGPU_PP_SENSOR_GFX_SCLK:
7987                 if (pl_index < ps->performance_level_count) {
7988                         sclk = ps->performance_levels[pl_index].sclk;
7989                         *((uint32_t *)value) = sclk;
7990                         *size = 4;
7991                         return 0;
7992                 }
7993                 return -EINVAL;
7994         case AMDGPU_PP_SENSOR_GFX_MCLK:
7995                 if (pl_index < ps->performance_level_count) {
7996                         mclk = ps->performance_levels[pl_index].mclk;
7997                         *((uint32_t *)value) = mclk;
7998                         *size = 4;
7999                         return 0;
8000                 }
8001                 return -EINVAL;
8002         case AMDGPU_PP_SENSOR_GPU_TEMP:
8003                 *((uint32_t *)value) = si_dpm_get_temp(adev);
8004                 *size = 4;
8005                 return 0;
8006         default:
8007                 return -EINVAL;
8008         }
8009 }
8010
8011 static const struct amd_ip_funcs si_dpm_ip_funcs = {
8012         .name = "si_dpm",
8013         .early_init = si_dpm_early_init,
8014         .late_init = si_dpm_late_init,
8015         .sw_init = si_dpm_sw_init,
8016         .sw_fini = si_dpm_sw_fini,
8017         .hw_init = si_dpm_hw_init,
8018         .hw_fini = si_dpm_hw_fini,
8019         .suspend = si_dpm_suspend,
8020         .resume = si_dpm_resume,
8021         .is_idle = si_dpm_is_idle,
8022         .wait_for_idle = si_dpm_wait_for_idle,
8023         .soft_reset = si_dpm_soft_reset,
8024         .set_clockgating_state = si_dpm_set_clockgating_state,
8025         .set_powergating_state = si_dpm_set_powergating_state,
8026 };
8027
8028 const struct amdgpu_ip_block_version si_smu_ip_block =
8029 {
8030         .type = AMD_IP_BLOCK_TYPE_SMC,
8031         .major = 6,
8032         .minor = 0,
8033         .rev = 0,
8034         .funcs = &si_dpm_ip_funcs,
8035 };
8036
8037 static const struct amd_pm_funcs si_dpm_funcs = {
8038         .pre_set_power_state = &si_dpm_pre_set_power_state,
8039         .set_power_state = &si_dpm_set_power_state,
8040         .post_set_power_state = &si_dpm_post_set_power_state,
8041         .display_configuration_changed = &si_dpm_display_configuration_changed,
8042         .get_sclk = &si_dpm_get_sclk,
8043         .get_mclk = &si_dpm_get_mclk,
8044         .print_power_state = &si_dpm_print_power_state,
8045         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8046         .force_performance_level = &si_dpm_force_performance_level,
8047         .vblank_too_short = &si_dpm_vblank_too_short,
8048         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8049         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8050         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8051         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8052         .check_state_equal = &si_check_state_equal,
8053         .get_vce_clock_state = amdgpu_get_vce_clock_state,
8054         .read_sensor = &si_dpm_read_sensor,
8055 };
8056
8057 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8058         .set = si_dpm_set_interrupt_state,
8059         .process = si_dpm_process_interrupt,
8060 };
8061
8062 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8063 {
8064         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8065         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8066 }
8067