drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amd_pcie.h"
  30 #include "sid.h"
  31 #include "r600_dpm.h"
  32 #include "si_dpm.h"
  33 #include "atom.h"
  34 #include "../include/pptable.h"
  35 #include <linux/math64.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/firmware.h>
  38
  39 #define MC_CG_ARB_FREQ_F0           0x0a
  40 #define MC_CG_ARB_FREQ_F1           0x0b
  41 #define MC_CG_ARB_FREQ_F2           0x0c
  42 #define MC_CG_ARB_FREQ_F3           0x0d
  43
  44 #define SMC_RAM_END                 0x20000
  45
  46 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  47
  48
  49 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  55 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  56
  57 #define BIOS_SCRATCH_4                                    0x5cd
  58
  59 /*(DEBLOBBED)*/
  60
  61 union power_info {
  62         struct _ATOM_POWERPLAY_INFO info;
  63         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  64         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  65         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  66         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  67         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  68         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  69         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  70 };
  71
  72 union fan_info {
  73         struct _ATOM_PPLIB_FANTABLE fan;
  74         struct _ATOM_PPLIB_FANTABLE2 fan2;
  75         struct _ATOM_PPLIB_FANTABLE3 fan3;
  76 };
  77
  78 union pplib_clock_info {
  79         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  80         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  81         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  82         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  83         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  84 };
  85
  86 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  87 {
  88         R600_UTC_DFLT_00,
  89         R600_UTC_DFLT_01,
  90         R600_UTC_DFLT_02,
  91         R600_UTC_DFLT_03,
  92         R600_UTC_DFLT_04,
  93         R600_UTC_DFLT_05,
  94         R600_UTC_DFLT_06,
  95         R600_UTC_DFLT_07,
  96         R600_UTC_DFLT_08,
  97         R600_UTC_DFLT_09,
  98         R600_UTC_DFLT_10,
  99         R600_UTC_DFLT_11,
 100         R600_UTC_DFLT_12,
 101         R600_UTC_DFLT_13,
 102         R600_UTC_DFLT_14,
 103 };
 104
 105 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 106 {
 107         R600_DTC_DFLT_00,
 108         R600_DTC_DFLT_01,
 109         R600_DTC_DFLT_02,
 110         R600_DTC_DFLT_03,
 111         R600_DTC_DFLT_04,
 112         R600_DTC_DFLT_05,
 113         R600_DTC_DFLT_06,
 114         R600_DTC_DFLT_07,
 115         R600_DTC_DFLT_08,
 116         R600_DTC_DFLT_09,
 117         R600_DTC_DFLT_10,
 118         R600_DTC_DFLT_11,
 119         R600_DTC_DFLT_12,
 120         R600_DTC_DFLT_13,
 121         R600_DTC_DFLT_14,
 122 };
 123
 124 static const struct si_cac_config_reg cac_weights_tahiti[] =
 125 {
 126         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 127         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 128         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 129         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 130         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 131         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 132         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 133         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 134         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 135         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 136         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 137         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 138         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 139         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 141         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 142         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 143         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 144         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 145         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 146         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 147         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 148         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 149         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 150         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 151         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 152         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 153         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 154         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 155         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 156         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 157         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 159         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 160         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 161         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 163         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 164         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 165         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 166         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 169         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 170         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 172         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 173         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 174         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 186         { 0xFFFFFFFF }
 187 };
 188
 189 static const struct si_cac_config_reg lcac_tahiti[] =
 190 {
 191         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 192         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 193         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 194         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 195         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 196         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 197         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 198         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 199         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 200         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 201         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 202         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 203         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 204         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 205         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 206         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 207         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 208         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 209         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 210         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 211         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 212         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 213         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 214         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 215         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 216         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 217         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 218         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 219         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 220         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 221         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 222         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 223         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 224         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 225         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 226         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 227         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 228         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 229         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 230         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 231         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 232         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 233         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 234         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 235         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 236         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 237         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 238         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 239         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 240         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 241         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 242         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 243         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 244         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 245         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 246         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 247         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 248         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 249         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 250         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 251         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 252         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 253         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 254         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 255         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 256         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 257         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 258         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 259         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 260         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 261         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 262         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 263         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 264         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 265         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 266         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 267         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 268         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 269         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 270         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 271         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 272         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 273         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 274         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 275         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 276         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 277         { 0xFFFFFFFF }
 278
 279 };
 280
 281 static const struct si_cac_config_reg cac_override_tahiti[] =
 282 {
 283         { 0xFFFFFFFF }
 284 };
 285
 286 static const struct si_powertune_data powertune_data_tahiti =
 287 {
 288         ((1 << 16) | 27027),
 289         6,
 290         0,
 291         4,
 292         95,
 293         {
 294                 0UL,
 295                 0UL,
 296                 4521550UL,
 297                 309631529UL,
 298                 -1270850L,
 299                 4513710L,
 300                 40
 301         },
 302         595000000UL,
 303         12,
 304         {
 305                 0,
 306                 0,
 307                 0,
 308                 0,
 309                 0,
 310                 0,
 311                 0,
 312                 0
 313         },
 314         true
 315 };
 316
 317 static const struct si_dte_data dte_data_tahiti =
 318 {
 319         { 1159409, 0, 0, 0, 0 },
 320         { 777, 0, 0, 0, 0 },
 321         2,
 322         54000,
 323         127000,
 324         25,
 325         2,
 326         10,
 327         13,
 328         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 329         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 330         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 331         85,
 332         false
 333 };
 334
 335 #if 0
 336 static const struct si_dte_data dte_data_tahiti_le =
 337 {
 338         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 339         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 340         0x5,
 341         0xAFC8,
 342         0x64,
 343         0x32,
 344         1,
 345         0,
 346         0x10,
 347         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 348         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 349         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 350         85,
 351         true
 352 };
 353 #endif
 354
 355 static const struct si_dte_data dte_data_tahiti_pro =
 356 {
 357         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 358         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 359         5,
 360         45000,
 361         100,
 362         0xA,
 363         1,
 364         0,
 365         0x10,
 366         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 367         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 368         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 369         90,
 370         true
 371 };
 372
 373 static const struct si_dte_data dte_data_new_zealand =
 374 {
 375         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 376         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 377         0x5,
 378         0xAFC8,
 379         0x69,
 380         0x32,
 381         1,
 382         0,
 383         0x10,
 384         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 385         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 386         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 387         85,
 388         true
 389 };
 390
 391 static const struct si_dte_data dte_data_aruba_pro =
 392 {
 393         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 394         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 395         5,
 396         45000,
 397         100,
 398         0xA,
 399         1,
 400         0,
 401         0x10,
 402         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 403         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 404         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 405         90,
 406         true
 407 };
 408
 409 static const struct si_dte_data dte_data_malta =
 410 {
 411         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 412         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 413         5,
 414         45000,
 415         100,
 416         0xA,
 417         1,
 418         0,
 419         0x10,
 420         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 421         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 422         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 423         90,
 424         true
 425 };
 426
 427 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 428 {
 429         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 430         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 431         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 432         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 433         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 434         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 435         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 436         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 437         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 438         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 439         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 440         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 441         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 442         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 443         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 444         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 445         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 446         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 447         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 448         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 449         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 450         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 451         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 452         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 453         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 454         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 455         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 456         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 457         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 458         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 461         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 462         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 463         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 464         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 465         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 466         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 467         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 468         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 469         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 470         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 472         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 473         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 474         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 475         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 476         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 488         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 489         { 0xFFFFFFFF }
 490 };
 491
 492 static const struct si_cac_config_reg lcac_pitcairn[] =
 493 {
 494         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 495         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 496         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 497         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 498         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 499         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 500         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 501         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 502         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 503         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 504         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 505         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 506         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 507         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 508         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 509         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 510         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 511         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 512         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 513         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 514         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 515         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 516         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 517         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 518         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 519         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 520         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 521         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 522         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 523         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 524         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 525         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 526         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 527         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 528         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 529         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 530         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 531         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 532         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 533         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 534         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 535         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 536         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 537         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 538         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 539         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 540         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 541         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 542         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 543         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 544         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 545         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 546         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 547         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 548         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 549         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 550         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 551         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 552         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 553         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 554         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 555         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 556         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 557         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 558         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 559         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 560         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 561         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 562         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 563         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 564         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 565         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 566         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 567         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 568         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 569         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 570         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 571         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 572         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 573         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 574         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 575         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 576         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 577         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 578         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 579         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 580         { 0xFFFFFFFF }
 581 };
 582
 583 static const struct si_cac_config_reg cac_override_pitcairn[] =
 584 {
 585     { 0xFFFFFFFF }
 586 };
 587
 588 static const struct si_powertune_data powertune_data_pitcairn =
 589 {
 590         ((1 << 16) | 27027),
 591         5,
 592         0,
 593         6,
 594         100,
 595         {
 596                 51600000UL,
 597                 1800000UL,
 598                 7194395UL,
 599                 309631529UL,
 600                 -1270850L,
 601                 4513710L,
 602                 100
 603         },
 604         117830498UL,
 605         12,
 606         {
 607                 0,
 608                 0,
 609                 0,
 610                 0,
 611                 0,
 612                 0,
 613                 0,
 614                 0
 615         },
 616         true
 617 };
 618
 619 static const struct si_dte_data dte_data_pitcairn =
 620 {
 621         { 0, 0, 0, 0, 0 },
 622         { 0, 0, 0, 0, 0 },
 623         0,
 624         0,
 625         0,
 626         0,
 627         0,
 628         0,
 629         0,
 630         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 631         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 632         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 633         0,
 634         false
 635 };
 636
 637 static const struct si_dte_data dte_data_curacao_xt =
 638 {
 639         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 640         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 641         5,
 642         45000,
 643         100,
 644         0xA,
 645         1,
 646         0,
 647         0x10,
 648         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 649         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 650         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 651         90,
 652         true
 653 };
 654
 655 static const struct si_dte_data dte_data_curacao_pro =
 656 {
 657         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 658         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 659         5,
 660         45000,
 661         100,
 662         0xA,
 663         1,
 664         0,
 665         0x10,
 666         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 667         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 668         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 669         90,
 670         true
 671 };
 672
 673 static const struct si_dte_data dte_data_neptune_xt =
 674 {
 675         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 676         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 677         5,
 678         45000,
 679         100,
 680         0xA,
 681         1,
 682         0,
 683         0x10,
 684         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 685         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 686         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 687         90,
 688         true
 689 };
 690
 691 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 692 {
 693         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 694         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 695         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 696         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 697         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 698         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 699         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 700         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 701         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 702         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 703         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 704         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 705         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 706         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 707         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 708         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 709         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 710         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 711         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 712         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 713         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 714         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 715         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 716         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 717         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 718         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 719         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 720         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 722         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 723         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 724         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 725         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 726         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 727         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 728         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 729         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 731         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 733         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 734         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 735         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 736         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 737         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 738         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 739         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 740         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 741         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 753         { 0xFFFFFFFF }
 754 };
 755
 756 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 757 {
 758         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 759         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 760         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 761         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 762         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 763         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 764         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 765         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 766         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 767         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 768         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 769         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 770         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 771         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 772         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 773         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 774         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 775         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 776         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 777         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 778         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 779         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 780         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 781         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 782         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 783         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 784         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 785         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 787         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 788         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 789         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 790         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 791         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 792         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 793         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 794         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 796         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 798         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 799         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 800         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 801         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 802         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 803         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 804         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 805         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 806         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 818         { 0xFFFFFFFF }
 819 };
 820
 821 static const struct si_cac_config_reg cac_weights_heathrow[] =
 822 {
 823         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 824         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 825         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 826         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 827         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 828         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 829         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 830         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 831         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 832         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 833         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 834         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 835         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 836         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 837         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 838         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 839         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 840         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 841         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 842         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 843         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 844         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 845         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 846         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 847         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 848         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 849         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 850         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 852         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 853         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 854         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 855         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 856         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 857         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 858         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 859         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 861         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 863         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 864         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 865         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 866         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 867         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 868         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 869         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 870         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 871         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 883         { 0xFFFFFFFF }
 884 };
 885
 886 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 887 {
 888         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 889         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 890         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 891         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 892         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 893         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 894         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 895         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 896         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 897         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 898         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 899         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 900         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 901         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 902         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 903         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 904         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 905         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 906         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 907         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 908         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 909         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 910         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 911         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 912         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 913         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 914         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 915         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 917         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 918         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 919         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 920         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 921         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 922         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 923         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 924         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 926         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 928         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 929         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 930         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 931         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 932         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 933         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 934         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 935         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 936         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 937         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 947         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 948         { 0xFFFFFFFF }
 949 };
 950
 951 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 952 {
 953         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 954         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 955         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 956         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 957         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 958         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 959         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 960         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 961         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 962         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 963         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 964         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 965         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 966         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 967         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 968         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 969         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 970         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 971         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 972         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 973         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 974         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 975         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 976         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 977         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 978         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 979         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 980         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 981         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 984         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 985         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 986         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 987         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 988         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 989         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 990         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 991         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 992         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 993         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 994         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 995         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 996         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 997         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 998         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 999         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1000         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1001         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1002         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1013         { 0xFFFFFFFF }
1014 };
1015
1016 static const struct si_cac_config_reg lcac_cape_verde[] =
1017 {
1018         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1019         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1020         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1021         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1022         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1023         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1024         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1025         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1026         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1027         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1029         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1031         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1033         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1037         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1039         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1041         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1043         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1045         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1047         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1049         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1061         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1065         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1067         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1071         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072         { 0xFFFFFFFF }
1073 };
1074
1075 static const struct si_cac_config_reg cac_override_cape_verde[] =
1076 {
1077     { 0xFFFFFFFF }
1078 };
1079
1080 static const struct si_powertune_data powertune_data_cape_verde =
1081 {
1082         ((1 << 16) | 0x6993),
1083         5,
1084         0,
1085         7,
1086         105,
1087         {
1088                 0UL,
1089                 0UL,
1090                 7194395UL,
1091                 309631529UL,
1092                 -1270850L,
1093                 4513710L,
1094                 100
1095         },
1096         117830498UL,
1097         12,
1098         {
1099                 0,
1100                 0,
1101                 0,
1102                 0,
1103                 0,
1104                 0,
1105                 0,
1106                 0
1107         },
1108         true
1109 };
1110
1111 static const struct si_dte_data dte_data_cape_verde =
1112 {
1113         { 0, 0, 0, 0, 0 },
1114         { 0, 0, 0, 0, 0 },
1115         0,
1116         0,
1117         0,
1118         0,
1119         0,
1120         0,
1121         0,
1122         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1123         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1124         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1125         0,
1126         false
1127 };
1128
1129 static const struct si_dte_data dte_data_venus_xtx =
1130 {
1131         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1132         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1133         5,
1134         55000,
1135         0x69,
1136         0xA,
1137         1,
1138         0,
1139         0x3,
1140         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1141         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1142         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1143         90,
1144         true
1145 };
1146
1147 static const struct si_dte_data dte_data_venus_xt =
1148 {
1149         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1150         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1151         5,
1152         55000,
1153         0x69,
1154         0xA,
1155         1,
1156         0,
1157         0x3,
1158         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1159         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1160         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1161         90,
1162         true
1163 };
1164
1165 static const struct si_dte_data dte_data_venus_pro =
1166 {
1167         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1168         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1169         5,
1170         55000,
1171         0x69,
1172         0xA,
1173         1,
1174         0,
1175         0x3,
1176         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1177         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1178         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1179         90,
1180         true
1181 };
1182
1183 static const struct si_cac_config_reg cac_weights_oland[] =
1184 {
1185         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1186         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1187         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1188         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1189         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1190         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1191         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1192         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1193         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1194         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1195         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1196         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1197         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1198         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1199         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1200         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1201         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1202         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1203         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1204         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1205         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1206         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1207         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1208         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1209         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1210         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1211         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1212         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1214         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1215         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1216         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1217         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1218         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1219         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1220         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1221         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1223         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1225         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1226         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1227         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1228         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1229         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1231         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1232         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1233         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1245         { 0xFFFFFFFF }
1246 };
1247
1248 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1249 {
1250         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1251         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1252         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1253         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1254         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1255         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1256         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1257         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1258         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1259         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1260         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1261         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1262         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1263         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1264         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1265         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1266         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1267         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1268         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1269         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1270         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1271         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1272         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1273         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1274         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1275         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1276         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1277         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1278         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1279         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1280         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1281         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1282         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1283         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1284         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1285         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1286         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1288         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1290         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1291         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1292         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1293         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1294         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1296         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1297         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1298         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1301         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1302         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1308         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1310         { 0xFFFFFFFF }
1311 };
1312
1313 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1314 {
1315         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1316         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1317         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1318         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1319         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1320         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1321         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1322         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1323         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1324         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1325         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1326         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1327         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1328         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1329         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1330         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1331         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1332         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1333         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1334         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1335         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1336         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1337         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1338         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1339         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1340         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1341         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1342         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1343         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1344         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1345         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1346         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1347         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1348         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1349         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1350         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1351         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1353         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1355         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1356         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1357         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1358         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1359         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1361         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1362         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1363         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1366         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1367         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1373         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1375         { 0xFFFFFFFF }
1376 };
1377
1378 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1379 {
1380         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1381         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1382         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1383         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1384         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1385         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1386         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1387         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1388         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1389         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1390         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1391         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1392         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1393         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1394         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1395         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1396         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1397         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1398         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1399         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1400         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1401         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1402         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1403         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1404         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1405         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1406         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1407         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1408         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1409         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1410         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1411         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1412         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1413         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1414         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1415         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1416         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1418         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1420         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1421         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1422         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1423         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1424         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1426         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1427         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1428         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1429         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1430         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1431         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1432         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1437         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1438         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1439         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1440         { 0xFFFFFFFF }
1441 };
1442
1443 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1444 {
1445         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1446         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1447         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1448         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1449         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1450         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1451         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1452         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1453         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1454         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1455         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1456         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1457         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1458         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1459         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1460         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1461         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1462         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1463         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1464         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1465         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1466         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1467         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1468         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1469         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1470         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1471         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1472         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1473         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1474         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1475         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1476         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1477         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1478         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1479         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1481         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1482         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1484         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1485         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1486         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1487         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1488         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1489         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1491         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1492         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1493         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1494         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1495         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1496         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1497         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1502         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1503         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1504         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1505         { 0xFFFFFFFF }
1506 };
1507
1508 static const struct si_cac_config_reg lcac_oland[] =
1509 {
1510         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1511         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1513         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1515         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1517         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1518         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1519         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1521         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1523         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1525         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1527         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1529         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1531         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1533         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1539         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1547         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0xFFFFFFFF }
1553 };
1554
1555 static const struct si_cac_config_reg lcac_mars_pro[] =
1556 {
1557         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1558         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1559         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1560         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1561         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1562         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1563         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1564         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1565         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1566         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1570         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1572         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1574         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1576         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1578         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1580         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1586         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1594         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599         { 0xFFFFFFFF }
1600 };
1601
1602 static const struct si_cac_config_reg cac_override_oland[] =
1603 {
1604         { 0xFFFFFFFF }
1605 };
1606
1607 static const struct si_powertune_data powertune_data_oland =
1608 {
1609         ((1 << 16) | 0x6993),
1610         5,
1611         0,
1612         7,
1613         105,
1614         {
1615                 0UL,
1616                 0UL,
1617                 7194395UL,
1618                 309631529UL,
1619                 -1270850L,
1620                 4513710L,
1621                 100
1622         },
1623         117830498UL,
1624         12,
1625         {
1626                 0,
1627                 0,
1628                 0,
1629                 0,
1630                 0,
1631                 0,
1632                 0,
1633                 0
1634         },
1635         true
1636 };
1637
1638 static const struct si_powertune_data powertune_data_mars_pro =
1639 {
1640         ((1 << 16) | 0x6993),
1641         5,
1642         0,
1643         7,
1644         105,
1645         {
1646                 0UL,
1647                 0UL,
1648                 7194395UL,
1649                 309631529UL,
1650                 -1270850L,
1651                 4513710L,
1652                 100
1653         },
1654         117830498UL,
1655         12,
1656         {
1657                 0,
1658                 0,
1659                 0,
1660                 0,
1661                 0,
1662                 0,
1663                 0,
1664                 0
1665         },
1666         true
1667 };
1668
1669 static const struct si_dte_data dte_data_oland =
1670 {
1671         { 0, 0, 0, 0, 0 },
1672         { 0, 0, 0, 0, 0 },
1673         0,
1674         0,
1675         0,
1676         0,
1677         0,
1678         0,
1679         0,
1680         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1681         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1682         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1683         0,
1684         false
1685 };
1686
1687 static const struct si_dte_data dte_data_mars_pro =
1688 {
1689         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1690         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1691         5,
1692         55000,
1693         105,
1694         0xA,
1695         1,
1696         0,
1697         0x10,
1698         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1699         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1700         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1701         90,
1702         true
1703 };
1704
1705 static const struct si_dte_data dte_data_sun_xt =
1706 {
1707         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1708         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1709         5,
1710         55000,
1711         105,
1712         0xA,
1713         1,
1714         0,
1715         0x10,
1716         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1717         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1718         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1719         90,
1720         true
1721 };
1722
1723
1724 static const struct si_cac_config_reg cac_weights_hainan[] =
1725 {
1726         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1727         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1728         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1729         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1730         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1731         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1732         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1733         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1734         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1735         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1736         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1737         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1738         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1739         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1740         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1741         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1743         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1744         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1745         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1746         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1747         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1748         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1749         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1750         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1751         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1752         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1753         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1754         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1755         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1756         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1757         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1758         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1759         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1760         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1761         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1762         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1763         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1765         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1766         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1768         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1769         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1770         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1771         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1774         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1775         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1776         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1786         { 0xFFFFFFFF }
1787 };
1788
1789 static const struct si_powertune_data powertune_data_hainan =
1790 {
1791         ((1 << 16) | 0x6993),
1792         5,
1793         0,
1794         9,
1795         105,
1796         {
1797                 0UL,
1798                 0UL,
1799                 7194395UL,
1800                 309631529UL,
1801                 -1270850L,
1802                 4513710L,
1803                 100
1804         },
1805         117830498UL,
1806         12,
1807         {
1808                 0,
1809                 0,
1810                 0,
1811                 0,
1812                 0,
1813                 0,
1814                 0,
1815                 0
1816         },
1817         true
1818 };
1819
1820 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1821 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1822 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1823 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1824
1825 static int si_populate_voltage_value(struct amdgpu_device *adev,
1826                                      const struct atom_voltage_table *table,
1827                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1828 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1829                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1830                                     u16 *std_voltage);
1831 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1832                                       u16 reg_offset, u32 value);
1833 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1834                                          struct rv7xx_pl *pl,
1835                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1836 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1837                                     u32 engine_clock,
1838                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1839
1840 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1841 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1842 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1843 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1844
1845 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1846 {
1847         struct si_power_info *pi = adev->pm.dpm.priv;
1848         return pi;
1849 }
1850
1851 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1852                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1853 {
1854         s64 kt, kv, leakage_w, i_leakage, vddc;
1855         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1856         s64 tmp;
1857
1858         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1859         vddc = div64_s64(drm_int2fixp(v), 1000);
1860         temperature = div64_s64(drm_int2fixp(t), 1000);
1861
1862         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1863         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1864         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1865         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1866         t_ref = drm_int2fixp(coeff->t_ref);
1867
1868         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1869         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1870         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1871         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1872
1873         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1874
1875         *leakage = drm_fixp2int(leakage_w * 1000);
1876 }
1877
1878 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1879                                              const struct ni_leakage_coeffients *coeff,
1880                                              u16 v,
1881                                              s32 t,
1882                                              u32 i_leakage,
1883                                              u32 *leakage)
1884 {
1885         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1886 }
1887
1888 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1889                                                const u32 fixed_kt, u16 v,
1890                                                u32 ileakage, u32 *leakage)
1891 {
1892         s64 kt, kv, leakage_w, i_leakage, vddc;
1893
1894         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1895         vddc = div64_s64(drm_int2fixp(v), 1000);
1896
1897         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1898         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1899                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1900
1901         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1902
1903         *leakage = drm_fixp2int(leakage_w * 1000);
1904 }
1905
1906 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1907                                        const struct ni_leakage_coeffients *coeff,
1908                                        const u32 fixed_kt,
1909                                        u16 v,
1910                                        u32 i_leakage,
1911                                        u32 *leakage)
1912 {
1913         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1914 }
1915
1916
1917 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1918                                    struct si_dte_data *dte_data)
1919 {
1920         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1921         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1922         u32 k = dte_data->k;
1923         u32 t_max = dte_data->max_t;
1924         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1925         u32 t_0 = dte_data->t0;
1926         u32 i;
1927
1928         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1929                 dte_data->tdep_count = 3;
1930
1931                 for (i = 0; i < k; i++) {
1932                         dte_data->r[i] =
1933                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1934                                 (p_limit2  * (u32)100);
1935                 }
1936
1937                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1938
1939                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1940                         dte_data->tdep_r[i] = dte_data->r[4];
1941                 }
1942         } else {
1943                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1944         }
1945 }
1946
1947 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1948 {
1949         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1950
1951         return pi;
1952 }
1953
1954 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1955 {
1956         struct ni_power_info *pi = adev->pm.dpm.priv;
1957
1958         return pi;
1959 }
1960
1961 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1962 {
1963         struct  si_ps *ps = aps->ps_priv;
1964
1965         return ps;
1966 }
1967
1968 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1969 {
1970         struct ni_power_info *ni_pi = ni_get_pi(adev);
1971         struct si_power_info *si_pi = si_get_pi(adev);
1972         bool update_dte_from_pl2 = false;
1973
1974         if (adev->asic_type == CHIP_TAHITI) {
1975                 si_pi->cac_weights = cac_weights_tahiti;
1976                 si_pi->lcac_config = lcac_tahiti;
1977                 si_pi->cac_override = cac_override_tahiti;
1978                 si_pi->powertune_data = &powertune_data_tahiti;
1979                 si_pi->dte_data = dte_data_tahiti;
1980
1981                 switch (adev->pdev->device) {
1982                 case 0x6798:
1983                         si_pi->dte_data.enable_dte_by_default = true;
1984                         break;
1985                 case 0x6799:
1986                         si_pi->dte_data = dte_data_new_zealand;
1987                         break;
1988                 case 0x6790:
1989                 case 0x6791:
1990                 case 0x6792:
1991                 case 0x679E:
1992                         si_pi->dte_data = dte_data_aruba_pro;
1993                         update_dte_from_pl2 = true;
1994                         break;
1995                 case 0x679B:
1996                         si_pi->dte_data = dte_data_malta;
1997                         update_dte_from_pl2 = true;
1998                         break;
1999                 case 0x679A:
2000                         si_pi->dte_data = dte_data_tahiti_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 default:
2004                         if (si_pi->dte_data.enable_dte_by_default == true)
2005                                 DRM_ERROR("DTE is not enabled!\n");
2006                         break;
2007                 }
2008         } else if (adev->asic_type == CHIP_PITCAIRN) {
2009                 si_pi->cac_weights = cac_weights_pitcairn;
2010                 si_pi->lcac_config = lcac_pitcairn;
2011                 si_pi->cac_override = cac_override_pitcairn;
2012                 si_pi->powertune_data = &powertune_data_pitcairn;
2013
2014                 switch (adev->pdev->device) {
2015                 case 0x6810:
2016                 case 0x6818:
2017                         si_pi->dte_data = dte_data_curacao_xt;
2018                         update_dte_from_pl2 = true;
2019                         break;
2020                 case 0x6819:
2021                 case 0x6811:
2022                         si_pi->dte_data = dte_data_curacao_pro;
2023                         update_dte_from_pl2 = true;
2024                         break;
2025                 case 0x6800:
2026                 case 0x6806:
2027                         si_pi->dte_data = dte_data_neptune_xt;
2028                         update_dte_from_pl2 = true;
2029                         break;
2030                 default:
2031                         si_pi->dte_data = dte_data_pitcairn;
2032                         break;
2033                 }
2034         } else if (adev->asic_type == CHIP_VERDE) {
2035                 si_pi->lcac_config = lcac_cape_verde;
2036                 si_pi->cac_override = cac_override_cape_verde;
2037                 si_pi->powertune_data = &powertune_data_cape_verde;
2038
2039                 switch (adev->pdev->device) {
2040                 case 0x683B:
2041                 case 0x683F:
2042                 case 0x6829:
2043                 case 0x6835:
2044                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2045                         si_pi->dte_data = dte_data_cape_verde;
2046                         break;
2047                 case 0x682C:
2048                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2049                         si_pi->dte_data = dte_data_sun_xt;
2050                         update_dte_from_pl2 = true;
2051                         break;
2052                 case 0x6825:
2053                 case 0x6827:
2054                         si_pi->cac_weights = cac_weights_heathrow;
2055                         si_pi->dte_data = dte_data_cape_verde;
2056                         break;
2057                 case 0x6824:
2058                 case 0x682D:
2059                         si_pi->cac_weights = cac_weights_chelsea_xt;
2060                         si_pi->dte_data = dte_data_cape_verde;
2061                         break;
2062                 case 0x682F:
2063                         si_pi->cac_weights = cac_weights_chelsea_pro;
2064                         si_pi->dte_data = dte_data_cape_verde;
2065                         break;
2066                 case 0x6820:
2067                         si_pi->cac_weights = cac_weights_heathrow;
2068                         si_pi->dte_data = dte_data_venus_xtx;
2069                         break;
2070                 case 0x6821:
2071                         si_pi->cac_weights = cac_weights_heathrow;
2072                         si_pi->dte_data = dte_data_venus_xt;
2073                         break;
2074                 case 0x6823:
2075                 case 0x682B:
2076                 case 0x6822:
2077                 case 0x682A:
2078                         si_pi->cac_weights = cac_weights_chelsea_pro;
2079                         si_pi->dte_data = dte_data_venus_pro;
2080                         break;
2081                 default:
2082                         si_pi->cac_weights = cac_weights_cape_verde;
2083                         si_pi->dte_data = dte_data_cape_verde;
2084                         break;
2085                 }
2086         } else if (adev->asic_type == CHIP_OLAND) {
2087                 si_pi->lcac_config = lcac_mars_pro;
2088                 si_pi->cac_override = cac_override_oland;
2089                 si_pi->powertune_data = &powertune_data_mars_pro;
2090                 si_pi->dte_data = dte_data_mars_pro;
2091
2092                 switch (adev->pdev->device) {
2093                 case 0x6601:
2094                 case 0x6621:
2095                 case 0x6603:
2096                 case 0x6605:
2097                         si_pi->cac_weights = cac_weights_mars_pro;
2098                         update_dte_from_pl2 = true;
2099                         break;
2100                 case 0x6600:
2101                 case 0x6606:
2102                 case 0x6620:
2103                 case 0x6604:
2104                         si_pi->cac_weights = cac_weights_mars_xt;
2105                         update_dte_from_pl2 = true;
2106                         break;
2107                 case 0x6611:
2108                 case 0x6613:
2109                 case 0x6608:
2110                         si_pi->cac_weights = cac_weights_oland_pro;
2111                         update_dte_from_pl2 = true;
2112                         break;
2113                 case 0x6610:
2114                         si_pi->cac_weights = cac_weights_oland_xt;
2115                         update_dte_from_pl2 = true;
2116                         break;
2117                 default:
2118                         si_pi->cac_weights = cac_weights_oland;
2119                         si_pi->lcac_config = lcac_oland;
2120                         si_pi->cac_override = cac_override_oland;
2121                         si_pi->powertune_data = &powertune_data_oland;
2122                         si_pi->dte_data = dte_data_oland;
2123                         break;
2124                 }
2125         } else if (adev->asic_type == CHIP_HAINAN) {
2126                 si_pi->cac_weights = cac_weights_hainan;
2127                 si_pi->lcac_config = lcac_oland;
2128                 si_pi->cac_override = cac_override_oland;
2129                 si_pi->powertune_data = &powertune_data_hainan;
2130                 si_pi->dte_data = dte_data_sun_xt;
2131                 update_dte_from_pl2 = true;
2132         } else {
2133                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2134                 return;
2135         }
2136
2137         ni_pi->enable_power_containment = false;
2138         ni_pi->enable_cac = false;
2139         ni_pi->enable_sq_ramping = false;
2140         si_pi->enable_dte = false;
2141
2142         if (si_pi->powertune_data->enable_powertune_by_default) {
2143                 ni_pi->enable_power_containment = true;
2144                 ni_pi->enable_cac = true;
2145                 if (si_pi->dte_data.enable_dte_by_default) {
2146                         si_pi->enable_dte = true;
2147                         if (update_dte_from_pl2)
2148                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2149
2150                 }
2151                 ni_pi->enable_sq_ramping = true;
2152         }
2153
2154         ni_pi->driver_calculate_cac_leakage = true;
2155         ni_pi->cac_configuration_required = true;
2156
2157         if (ni_pi->cac_configuration_required) {
2158                 ni_pi->support_cac_long_term_average = true;
2159                 si_pi->dyn_powertune_data.l2_lta_window_size =
2160                         si_pi->powertune_data->l2_lta_window_size_default;
2161                 si_pi->dyn_powertune_data.lts_truncate =
2162                         si_pi->powertune_data->lts_truncate_default;
2163         } else {
2164                 ni_pi->support_cac_long_term_average = false;
2165                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2166                 si_pi->dyn_powertune_data.lts_truncate = 0;
2167         }
2168
2169         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2170 }
2171
2172 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2173 {
2174         return 1;
2175 }
2176
2177 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2178 {
2179         u32 xclk;
2180         u32 wintime;
2181         u32 cac_window;
2182         u32 cac_window_size;
2183
2184         xclk = amdgpu_asic_get_xclk(adev);
2185
2186         if (xclk == 0)
2187                 return 0;
2188
2189         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2190         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2191
2192         wintime = (cac_window_size * 100) / xclk;
2193
2194         return wintime;
2195 }
2196
2197 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2198 {
2199         return power_in_watts;
2200 }
2201
2202 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2203                                             bool adjust_polarity,
2204                                             u32 tdp_adjustment,
2205                                             u32 *tdp_limit,
2206                                             u32 *near_tdp_limit)
2207 {
2208         u32 adjustment_delta, max_tdp_limit;
2209
2210         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2211                 return -EINVAL;
2212
2213         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2214
2215         if (adjust_polarity) {
2216                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2217                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2218         } else {
2219                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2220                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2221                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2222                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2223                 else
2224                         *near_tdp_limit = 0;
2225         }
2226
2227         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2228                 return -EINVAL;
2229         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2230                 return -EINVAL;
2231
2232         return 0;
2233 }
2234
2235 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2236                                       struct amdgpu_ps *amdgpu_state)
2237 {
2238         struct ni_power_info *ni_pi = ni_get_pi(adev);
2239         struct si_power_info *si_pi = si_get_pi(adev);
2240
2241         if (ni_pi->enable_power_containment) {
2242                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2243                 PP_SIslands_PAPMParameters *papm_parm;
2244                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2245                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2246                 u32 tdp_limit;
2247                 u32 near_tdp_limit;
2248                 int ret;
2249
2250                 if (scaling_factor == 0)
2251                         return -EINVAL;
2252
2253                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2254
2255                 ret = si_calculate_adjusted_tdp_limits(adev,
2256                                                        false, /* ??? */
2257                                                        adev->pm.dpm.tdp_adjustment,
2258                                                        &tdp_limit,
2259                                                        &near_tdp_limit);
2260                 if (ret)
2261                         return ret;
2262
2263                 smc_table->dpm2Params.TDPLimit =
2264                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2265                 smc_table->dpm2Params.NearTDPLimit =
2266                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2267                 smc_table->dpm2Params.SafePowerLimit =
2268                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2269
2270                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2271                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2272                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2273                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2274                                                   sizeof(u32) * 3,
2275                                                   si_pi->sram_end);
2276                 if (ret)
2277                         return ret;
2278
2279                 if (si_pi->enable_ppm) {
2280                         papm_parm = &si_pi->papm_parm;
2281                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2282                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2283                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2284                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2285                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2286                         papm_parm->PlatformPowerLimit = 0xffffffff;
2287                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2288
2289                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2290                                                           (u8 *)papm_parm,
2291                                                           sizeof(PP_SIslands_PAPMParameters),
2292                                                           si_pi->sram_end);
2293                         if (ret)
2294                                 return ret;
2295                 }
2296         }
2297         return 0;
2298 }
2299
2300 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2301                                         struct amdgpu_ps *amdgpu_state)
2302 {
2303         struct ni_power_info *ni_pi = ni_get_pi(adev);
2304         struct si_power_info *si_pi = si_get_pi(adev);
2305
2306         if (ni_pi->enable_power_containment) {
2307                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2308                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2309                 int ret;
2310
2311                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2312
2313                 smc_table->dpm2Params.NearTDPLimit =
2314                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2315                 smc_table->dpm2Params.SafePowerLimit =
2316                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2317
2318                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2319                                                   (si_pi->state_table_start +
2320                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2321                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2322                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2323                                                   sizeof(u32) * 2,
2324                                                   si_pi->sram_end);
2325                 if (ret)
2326                         return ret;
2327         }
2328
2329         return 0;
2330 }
2331
2332 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2333                                                const u16 prev_std_vddc,
2334                                                const u16 curr_std_vddc)
2335 {
2336         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2337         u64 prev_vddc = (u64)prev_std_vddc;
2338         u64 curr_vddc = (u64)curr_std_vddc;
2339         u64 pwr_efficiency_ratio, n, d;
2340
2341         if ((prev_vddc == 0) || (curr_vddc == 0))
2342                 return 0;
2343
2344         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2345         d = prev_vddc * prev_vddc;
2346         pwr_efficiency_ratio = div64_u64(n, d);
2347
2348         if (pwr_efficiency_ratio > (u64)0xFFFF)
2349                 return 0;
2350
2351         return (u16)pwr_efficiency_ratio;
2352 }
2353
2354 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2355                                             struct amdgpu_ps *amdgpu_state)
2356 {
2357         struct si_power_info *si_pi = si_get_pi(adev);
2358
2359         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2360             amdgpu_state->vclk && amdgpu_state->dclk)
2361                 return true;
2362
2363         return false;
2364 }
2365
2366 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2367 {
2368         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2369
2370         return pi;
2371 }
2372
2373 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2374                                                 struct amdgpu_ps *amdgpu_state,
2375                                                 SISLANDS_SMC_SWSTATE *smc_state)
2376 {
2377         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2378         struct ni_power_info *ni_pi = ni_get_pi(adev);
2379         struct  si_ps *state = si_get_ps(amdgpu_state);
2380         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2381         u32 prev_sclk;
2382         u32 max_sclk;
2383         u32 min_sclk;
2384         u16 prev_std_vddc;
2385         u16 curr_std_vddc;
2386         int i;
2387         u16 pwr_efficiency_ratio;
2388         u8 max_ps_percent;
2389         bool disable_uvd_power_tune;
2390         int ret;
2391
2392         if (ni_pi->enable_power_containment == false)
2393                 return 0;
2394
2395         if (state->performance_level_count == 0)
2396                 return -EINVAL;
2397
2398         if (smc_state->levelCount != state->performance_level_count)
2399                 return -EINVAL;
2400
2401         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2402
2403         smc_state->levels[0].dpm2.MaxPS = 0;
2404         smc_state->levels[0].dpm2.NearTDPDec = 0;
2405         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2406         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2407         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2408
2409         for (i = 1; i < state->performance_level_count; i++) {
2410                 prev_sclk = state->performance_levels[i-1].sclk;
2411                 max_sclk  = state->performance_levels[i].sclk;
2412                 if (i == 1)
2413                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2414                 else
2415                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2416
2417                 if (prev_sclk > max_sclk)
2418                         return -EINVAL;
2419
2420                 if ((max_ps_percent == 0) ||
2421                     (prev_sclk == max_sclk) ||
2422                     disable_uvd_power_tune)
2423                         min_sclk = max_sclk;
2424                 else if (i == 1)
2425                         min_sclk = prev_sclk;
2426                 else
2427                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2428
2429                 if (min_sclk < state->performance_levels[0].sclk)
2430                         min_sclk = state->performance_levels[0].sclk;
2431
2432                 if (min_sclk == 0)
2433                         return -EINVAL;
2434
2435                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2436                                                 state->performance_levels[i-1].vddc, &vddc);
2437                 if (ret)
2438                         return ret;
2439
2440                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2441                 if (ret)
2442                         return ret;
2443
2444                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2445                                                 state->performance_levels[i].vddc, &vddc);
2446                 if (ret)
2447                         return ret;
2448
2449                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2450                 if (ret)
2451                         return ret;
2452
2453                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2454                                                                            prev_std_vddc, curr_std_vddc);
2455
2456                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2457                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2458                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2459                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2460                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2461         }
2462
2463         return 0;
2464 }
2465
2466 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2467                                          struct amdgpu_ps *amdgpu_state,
2468                                          SISLANDS_SMC_SWSTATE *smc_state)
2469 {
2470         struct ni_power_info *ni_pi = ni_get_pi(adev);
2471         struct  si_ps *state = si_get_ps(amdgpu_state);
2472         u32 sq_power_throttle, sq_power_throttle2;
2473         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2474         int i;
2475
2476         if (state->performance_level_count == 0)
2477                 return -EINVAL;
2478
2479         if (smc_state->levelCount != state->performance_level_count)
2480                 return -EINVAL;
2481
2482         if (adev->pm.dpm.sq_ramping_threshold == 0)
2483                 return -EINVAL;
2484
2485         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2486                 enable_sq_ramping = false;
2487
2488         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2489                 enable_sq_ramping = false;
2490
2491         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2492                 enable_sq_ramping = false;
2493
2494         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2495                 enable_sq_ramping = false;
2496
2497         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2498                 enable_sq_ramping = false;
2499
2500         for (i = 0; i < state->performance_level_count; i++) {
2501                 sq_power_throttle = 0;
2502                 sq_power_throttle2 = 0;
2503
2504                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2505                     enable_sq_ramping) {
2506                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2507                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2508                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2509                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2510                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2511                 } else {
2512                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2513                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2514                 }
2515
2516                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2517                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2518         }
2519
2520         return 0;
2521 }
2522
2523 static int si_enable_power_containment(struct amdgpu_device *adev,
2524                                        struct amdgpu_ps *amdgpu_new_state,
2525                                        bool enable)
2526 {
2527         struct ni_power_info *ni_pi = ni_get_pi(adev);
2528         PPSMC_Result smc_result;
2529         int ret = 0;
2530
2531         if (ni_pi->enable_power_containment) {
2532                 if (enable) {
2533                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2534                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2535                                 if (smc_result != PPSMC_Result_OK) {
2536                                         ret = -EINVAL;
2537                                         ni_pi->pc_enabled = false;
2538                                 } else {
2539                                         ni_pi->pc_enabled = true;
2540                                 }
2541                         }
2542                 } else {
2543                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2544                         if (smc_result != PPSMC_Result_OK)
2545                                 ret = -EINVAL;
2546                         ni_pi->pc_enabled = false;
2547                 }
2548         }
2549
2550         return ret;
2551 }
2552
2553 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2554 {
2555         struct si_power_info *si_pi = si_get_pi(adev);
2556         int ret = 0;
2557         struct si_dte_data *dte_data = &si_pi->dte_data;
2558         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2559         u32 table_size;
2560         u8 tdep_count;
2561         u32 i;
2562
2563         if (dte_data == NULL)
2564                 si_pi->enable_dte = false;
2565
2566         if (si_pi->enable_dte == false)
2567                 return 0;
2568
2569         if (dte_data->k <= 0)
2570                 return -EINVAL;
2571
2572         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2573         if (dte_tables == NULL) {
2574                 si_pi->enable_dte = false;
2575                 return -ENOMEM;
2576         }
2577
2578         table_size = dte_data->k;
2579
2580         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2581                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2582
2583         tdep_count = dte_data->tdep_count;
2584         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2585                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2586
2587         dte_tables->K = cpu_to_be32(table_size);
2588         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2589         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2590         dte_tables->WindowSize = dte_data->window_size;
2591         dte_tables->temp_select = dte_data->temp_select;
2592         dte_tables->DTE_mode = dte_data->dte_mode;
2593         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2594
2595         if (tdep_count > 0)
2596                 table_size--;
2597
2598         for (i = 0; i < table_size; i++) {
2599                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2600                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2601         }
2602
2603         dte_tables->Tdep_count = tdep_count;
2604
2605         for (i = 0; i < (u32)tdep_count; i++) {
2606                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2607                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2608                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2609         }
2610
2611         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2612                                           (u8 *)dte_tables,
2613                                           sizeof(Smc_SIslands_DTE_Configuration),
2614                                           si_pi->sram_end);
2615         kfree(dte_tables);
2616
2617         return ret;
2618 }
2619
2620 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2621                                           u16 *max, u16 *min)
2622 {
2623         struct si_power_info *si_pi = si_get_pi(adev);
2624         struct amdgpu_cac_leakage_table *table =
2625                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2626         u32 i;
2627         u32 v0_loadline;
2628
2629         if (table == NULL)
2630                 return -EINVAL;
2631
2632         *max = 0;
2633         *min = 0xFFFF;
2634
2635         for (i = 0; i < table->count; i++) {
2636                 if (table->entries[i].vddc > *max)
2637                         *max = table->entries[i].vddc;
2638                 if (table->entries[i].vddc < *min)
2639                         *min = table->entries[i].vddc;
2640         }
2641
2642         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2643                 return -EINVAL;
2644
2645         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2646
2647         if (v0_loadline > 0xFFFFUL)
2648                 return -EINVAL;
2649
2650         *min = (u16)v0_loadline;
2651
2652         if ((*min > *max) || (*max == 0) || (*min == 0))
2653                 return -EINVAL;
2654
2655         return 0;
2656 }
2657
2658 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2659 {
2660         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2661                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2662 }
2663
2664 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2665                                      PP_SIslands_CacConfig *cac_tables,
2666                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2667                                      u16 t0, u16 t_step)
2668 {
2669         struct si_power_info *si_pi = si_get_pi(adev);
2670         u32 leakage;
2671         unsigned int i, j;
2672         s32 t;
2673         u32 smc_leakage;
2674         u32 scaling_factor;
2675         u16 voltage;
2676
2677         scaling_factor = si_get_smc_power_scaling_factor(adev);
2678
2679         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2680                 t = (1000 * (i * t_step + t0));
2681
2682                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2683                         voltage = vddc_max - (vddc_step * j);
2684
2685                         si_calculate_leakage_for_v_and_t(adev,
2686                                                          &si_pi->powertune_data->leakage_coefficients,
2687                                                          voltage,
2688                                                          t,
2689                                                          si_pi->dyn_powertune_data.cac_leakage,
2690                                                          &leakage);
2691
2692                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2693
2694                         if (smc_leakage > 0xFFFF)
2695                                 smc_leakage = 0xFFFF;
2696
2697                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2698                                 cpu_to_be16((u16)smc_leakage);
2699                 }
2700         }
2701         return 0;
2702 }
2703
2704 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2705                                             PP_SIslands_CacConfig *cac_tables,
2706                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2707 {
2708         struct si_power_info *si_pi = si_get_pi(adev);
2709         u32 leakage;
2710         unsigned int i, j;
2711         u32 smc_leakage;
2712         u32 scaling_factor;
2713         u16 voltage;
2714
2715         scaling_factor = si_get_smc_power_scaling_factor(adev);
2716
2717         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2718                 voltage = vddc_max - (vddc_step * j);
2719
2720                 si_calculate_leakage_for_v(adev,
2721                                            &si_pi->powertune_data->leakage_coefficients,
2722                                            si_pi->powertune_data->fixed_kt,
2723                                            voltage,
2724                                            si_pi->dyn_powertune_data.cac_leakage,
2725                                            &leakage);
2726
2727                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2728
2729                 if (smc_leakage > 0xFFFF)
2730                         smc_leakage = 0xFFFF;
2731
2732                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2733                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2734                                 cpu_to_be16((u16)smc_leakage);
2735         }
2736         return 0;
2737 }
2738
2739 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2740 {
2741         struct ni_power_info *ni_pi = ni_get_pi(adev);
2742         struct si_power_info *si_pi = si_get_pi(adev);
2743         PP_SIslands_CacConfig *cac_tables = NULL;
2744         u16 vddc_max, vddc_min, vddc_step;
2745         u16 t0, t_step;
2746         u32 load_line_slope, reg;
2747         int ret = 0;
2748         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2749
2750         if (ni_pi->enable_cac == false)
2751                 return 0;
2752
2753         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2754         if (!cac_tables)
2755                 return -ENOMEM;
2756
2757         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2758         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2759         WREG32(CG_CAC_CTRL, reg);
2760
2761         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2762         si_pi->dyn_powertune_data.dc_pwr_value =
2763                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2764         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2765         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2766
2767         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2768
2769         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2770         if (ret)
2771                 goto done_free;
2772
2773         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2774         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2775         t_step = 4;
2776         t0 = 60;
2777
2778         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2779                 ret = si_init_dte_leakage_table(adev, cac_tables,
2780                                                 vddc_max, vddc_min, vddc_step,
2781                                                 t0, t_step);
2782         else
2783                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2784                                                        vddc_max, vddc_min, vddc_step);
2785         if (ret)
2786                 goto done_free;
2787
2788         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2789
2790         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2791         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2792         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2793         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2794         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2795         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2796         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2797         cac_tables->calculation_repeats = cpu_to_be32(2);
2798         cac_tables->dc_cac = cpu_to_be32(0);
2799         cac_tables->log2_PG_LKG_SCALE = 12;
2800         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2801         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2802         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2803
2804         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2805                                           (u8 *)cac_tables,
2806                                           sizeof(PP_SIslands_CacConfig),
2807                                           si_pi->sram_end);
2808
2809         if (ret)
2810                 goto done_free;
2811
2812         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2813
2814 done_free:
2815         if (ret) {
2816                 ni_pi->enable_cac = false;
2817                 ni_pi->enable_power_containment = false;
2818         }
2819
2820         kfree(cac_tables);
2821
2822         return ret;
2823 }
2824
2825 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2826                                            const struct si_cac_config_reg *cac_config_regs)
2827 {
2828         const struct si_cac_config_reg *config_regs = cac_config_regs;
2829         u32 data = 0, offset;
2830
2831         if (!config_regs)
2832                 return -EINVAL;
2833
2834         while (config_regs->offset != 0xFFFFFFFF) {
2835                 switch (config_regs->type) {
2836                 case SISLANDS_CACCONFIG_CGIND:
2837                         offset = SMC_CG_IND_START + config_regs->offset;
2838                         if (offset < SMC_CG_IND_END)
2839                                 data = RREG32_SMC(offset);
2840                         break;
2841                 default:
2842                         data = RREG32(config_regs->offset);
2843                         break;
2844                 }
2845
2846                 data &= ~config_regs->mask;
2847                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2848
2849                 switch (config_regs->type) {
2850                 case SISLANDS_CACCONFIG_CGIND:
2851                         offset = SMC_CG_IND_START + config_regs->offset;
2852                         if (offset < SMC_CG_IND_END)
2853                                 WREG32_SMC(offset, data);
2854                         break;
2855                 default:
2856                         WREG32(config_regs->offset, data);
2857                         break;
2858                 }
2859                 config_regs++;
2860         }
2861         return 0;
2862 }
2863
2864 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2865 {
2866         struct ni_power_info *ni_pi = ni_get_pi(adev);
2867         struct si_power_info *si_pi = si_get_pi(adev);
2868         int ret;
2869
2870         if ((ni_pi->enable_cac == false) ||
2871             (ni_pi->cac_configuration_required == false))
2872                 return 0;
2873
2874         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2875         if (ret)
2876                 return ret;
2877         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2878         if (ret)
2879                 return ret;
2880         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2881         if (ret)
2882                 return ret;
2883
2884         return 0;
2885 }
2886
2887 static int si_enable_smc_cac(struct amdgpu_device *adev,
2888                              struct amdgpu_ps *amdgpu_new_state,
2889                              bool enable)
2890 {
2891         struct ni_power_info *ni_pi = ni_get_pi(adev);
2892         struct si_power_info *si_pi = si_get_pi(adev);
2893         PPSMC_Result smc_result;
2894         int ret = 0;
2895
2896         if (ni_pi->enable_cac) {
2897                 if (enable) {
2898                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2899                                 if (ni_pi->support_cac_long_term_average) {
2900                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2901                                         if (smc_result != PPSMC_Result_OK)
2902                                                 ni_pi->support_cac_long_term_average = false;
2903                                 }
2904
2905                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2906                                 if (smc_result != PPSMC_Result_OK) {
2907                                         ret = -EINVAL;
2908                                         ni_pi->cac_enabled = false;
2909                                 } else {
2910                                         ni_pi->cac_enabled = true;
2911                                 }
2912
2913                                 if (si_pi->enable_dte) {
2914                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2915                                         if (smc_result != PPSMC_Result_OK)
2916                                                 ret = -EINVAL;
2917                                 }
2918                         }
2919                 } else if (ni_pi->cac_enabled) {
2920                         if (si_pi->enable_dte)
2921                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2922
2923                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2924
2925                         ni_pi->cac_enabled = false;
2926
2927                         if (ni_pi->support_cac_long_term_average)
2928                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2929                 }
2930         }
2931         return ret;
2932 }
2933
2934 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2935 {
2936         struct ni_power_info *ni_pi = ni_get_pi(adev);
2937         struct si_power_info *si_pi = si_get_pi(adev);
2938         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2939         SISLANDS_SMC_SCLK_VALUE sclk_params;
2940         u32 fb_div, p_div;
2941         u32 clk_s, clk_v;
2942         u32 sclk = 0;
2943         int ret = 0;
2944         u32 tmp;
2945         int i;
2946
2947         if (si_pi->spll_table_start == 0)
2948                 return -EINVAL;
2949
2950         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2951         if (spll_table == NULL)
2952                 return -ENOMEM;
2953
2954         for (i = 0; i < 256; i++) {
2955                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2956                 if (ret)
2957                         break;
2958                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2959                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2960                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2961                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2962
2963                 fb_div &= ~0x00001FFF;
2964                 fb_div >>= 1;
2965                 clk_v >>= 6;
2966
2967                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2968                         ret = -EINVAL;
2969                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2970                         ret = -EINVAL;
2971                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2972                         ret = -EINVAL;
2973                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2974                         ret = -EINVAL;
2975
2976                 if (ret)
2977                         break;
2978
2979                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2980                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2981                 spll_table->freq[i] = cpu_to_be32(tmp);
2982
2983                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2984                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2985                 spll_table->ss[i] = cpu_to_be32(tmp);
2986
2987                 sclk += 512;
2988         }
2989
2990
2991         if (!ret)
2992                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2993                                                   (u8 *)spll_table,
2994                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2995                                                   si_pi->sram_end);
2996
2997         if (ret)
2998                 ni_pi->enable_power_containment = false;
2999
3000         kfree(spll_table);
3001
3002         return ret;
3003 }
3004
3005 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3006                                                    u16 vce_voltage)
3007 {
3008         u16 highest_leakage = 0;
3009         struct si_power_info *si_pi = si_get_pi(adev);
3010         int i;
3011
3012         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3013                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3014                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3015         }
3016
3017         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3018                 return highest_leakage;
3019
3020         return vce_voltage;
3021 }
3022
3023 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3024                                     u32 evclk, u32 ecclk, u16 *voltage)
3025 {
3026         u32 i;
3027         int ret = -EINVAL;
3028         struct amdgpu_vce_clock_voltage_dependency_table *table =
3029                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3030
3031         if (((evclk == 0) && (ecclk == 0)) ||
3032             (table && (table->count == 0))) {
3033                 *voltage = 0;
3034                 return 0;
3035         }
3036
3037         for (i = 0; i < table->count; i++) {
3038                 if ((evclk <= table->entries[i].evclk) &&
3039                     (ecclk <= table->entries[i].ecclk)) {
3040                         *voltage = table->entries[i].v;
3041                         ret = 0;
3042                         break;
3043                 }
3044         }
3045
3046         /* if no match return the highest voltage */
3047         if (ret)
3048                 *voltage = table->entries[table->count - 1].v;
3049
3050         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3051
3052         return ret;
3053 }
3054
3055 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3056 {
3057
3058         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3059         /* we never hit the non-gddr5 limit so disable it */
3060         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3061
3062         if (vblank_time < switch_limit)
3063                 return true;
3064         else
3065                 return false;
3066
3067 }
3068
3069 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3070                                 u32 arb_freq_src, u32 arb_freq_dest)
3071 {
3072         u32 mc_arb_dram_timing;
3073         u32 mc_arb_dram_timing2;
3074         u32 burst_time;
3075         u32 mc_cg_config;
3076
3077         switch (arb_freq_src) {
3078         case MC_CG_ARB_FREQ_F0:
3079                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3080                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3081                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3082                 break;
3083         case MC_CG_ARB_FREQ_F1:
3084                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3085                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3086                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3087                 break;
3088         case MC_CG_ARB_FREQ_F2:
3089                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3090                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3091                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3092                 break;
3093         case MC_CG_ARB_FREQ_F3:
3094                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3095                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3096                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3097                 break;
3098         default:
3099                 return -EINVAL;
3100         }
3101
3102         switch (arb_freq_dest) {
3103         case MC_CG_ARB_FREQ_F0:
3104                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3105                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3106                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3107                 break;
3108         case MC_CG_ARB_FREQ_F1:
3109                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3110                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3111                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3112                 break;
3113         case MC_CG_ARB_FREQ_F2:
3114                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3115                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3116                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3117                 break;
3118         case MC_CG_ARB_FREQ_F3:
3119                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3120                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3121                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3122                 break;
3123         default:
3124                 return -EINVAL;
3125         }
3126
3127         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3128         WREG32(MC_CG_CONFIG, mc_cg_config);
3129         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3130
3131         return 0;
3132 }
3133
3134 static void ni_update_current_ps(struct amdgpu_device *adev,
3135                           struct amdgpu_ps *rps)
3136 {
3137         struct si_ps *new_ps = si_get_ps(rps);
3138         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3139         struct ni_power_info *ni_pi = ni_get_pi(adev);
3140
3141         eg_pi->current_rps = *rps;
3142         ni_pi->current_ps = *new_ps;
3143         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3144         adev->pm.dpm.current_ps = &eg_pi->current_rps;
3145 }
3146
3147 static void ni_update_requested_ps(struct amdgpu_device *adev,
3148                             struct amdgpu_ps *rps)
3149 {
3150         struct si_ps *new_ps = si_get_ps(rps);
3151         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3152         struct ni_power_info *ni_pi = ni_get_pi(adev);
3153
3154         eg_pi->requested_rps = *rps;
3155         ni_pi->requested_ps = *new_ps;
3156         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3157         adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3158 }
3159
3160 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3161                                            struct amdgpu_ps *new_ps,
3162                                            struct amdgpu_ps *old_ps)
3163 {
3164         struct si_ps *new_state = si_get_ps(new_ps);
3165         struct si_ps *current_state = si_get_ps(old_ps);
3166
3167         if ((new_ps->vclk == old_ps->vclk) &&
3168             (new_ps->dclk == old_ps->dclk))
3169                 return;
3170
3171         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3172             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3173                 return;
3174
3175         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3176 }
3177
3178 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3179                                           struct amdgpu_ps *new_ps,
3180                                           struct amdgpu_ps *old_ps)
3181 {
3182         struct si_ps *new_state = si_get_ps(new_ps);
3183         struct si_ps *current_state = si_get_ps(old_ps);
3184
3185         if ((new_ps->vclk == old_ps->vclk) &&
3186             (new_ps->dclk == old_ps->dclk))
3187                 return;
3188
3189         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3190             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3191                 return;
3192
3193         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3194 }
3195
3196 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3197 {
3198         unsigned int i;
3199
3200         for (i = 0; i < table->count; i++)
3201                 if (voltage <= table->entries[i].value)
3202                         return table->entries[i].value;
3203
3204         return table->entries[table->count - 1].value;
3205 }
3206
3207 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3208                                 u32 max_clock, u32 requested_clock)
3209 {
3210         unsigned int i;
3211
3212         if ((clocks == NULL) || (clocks->count == 0))
3213                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3214
3215         for (i = 0; i < clocks->count; i++) {
3216                 if (clocks->values[i] >= requested_clock)
3217                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3218         }
3219
3220         return (clocks->values[clocks->count - 1] < max_clock) ?
3221                 clocks->values[clocks->count - 1] : max_clock;
3222 }
3223
3224 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3225                               u32 max_mclk, u32 requested_mclk)
3226 {
3227         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3228                                     max_mclk, requested_mclk);
3229 }
3230
3231 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3232                               u32 max_sclk, u32 requested_sclk)
3233 {
3234         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3235                                     max_sclk, requested_sclk);
3236 }
3237
3238 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3239                                                             u32 *max_clock)
3240 {
3241         u32 i, clock = 0;
3242
3243         if ((table == NULL) || (table->count == 0)) {
3244                 *max_clock = clock;
3245                 return;
3246         }
3247
3248         for (i = 0; i < table->count; i++) {
3249                 if (clock < table->entries[i].clk)
3250                         clock = table->entries[i].clk;
3251         }
3252         *max_clock = clock;
3253 }
3254
3255 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3256                                                u32 clock, u16 max_voltage, u16 *voltage)
3257 {
3258         u32 i;
3259
3260         if ((table == NULL) || (table->count == 0))
3261                 return;
3262
3263         for (i= 0; i < table->count; i++) {
3264                 if (clock <= table->entries[i].clk) {
3265                         if (*voltage < table->entries[i].v)
3266                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3267                                            table->entries[i].v : max_voltage);
3268                         return;
3269                 }
3270         }
3271
3272         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3273 }
3274
3275 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3276                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3277                                           struct rv7xx_pl *pl)
3278 {
3279
3280         if ((pl->mclk == 0) || (pl->sclk == 0))
3281                 return;
3282
3283         if (pl->mclk == pl->sclk)
3284                 return;
3285
3286         if (pl->mclk > pl->sclk) {
3287                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3288                         pl->sclk = btc_get_valid_sclk(adev,
3289                                                       max_limits->sclk,
3290                                                       (pl->mclk +
3291                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3292                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3293         } else {
3294                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3295                         pl->mclk = btc_get_valid_mclk(adev,
3296                                                       max_limits->mclk,
3297                                                       pl->sclk -
3298                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3299         }
3300 }
3301
3302 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3303                                           u16 max_vddc, u16 max_vddci,
3304                                           u16 *vddc, u16 *vddci)
3305 {
3306         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3307         u16 new_voltage;
3308
3309         if ((0 == *vddc) || (0 == *vddci))
3310                 return;
3311
3312         if (*vddc > *vddci) {
3313                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3314                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3315                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3316                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3317                 }
3318         } else {
3319                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3320                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3321                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3322                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3323                 }
3324         }
3325 }
3326
3327 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3328                             u32 *p, u32 *u)
3329 {
3330         u32 b_c = 0;
3331         u32 i_c;
3332         u32 tmp;
3333
3334         i_c = (i * r_c) / 100;
3335         tmp = i_c >> p_b;
3336
3337         while (tmp) {
3338                 b_c++;
3339                 tmp >>= 1;
3340         }
3341
3342         *u = (b_c + 1) / 2;
3343         *p = i_c / (1 << (2 * (*u)));
3344 }
3345
3346 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3347 {
3348         u32 k, a, ah, al;
3349         u32 t1;
3350
3351         if ((fl == 0) || (fh == 0) || (fl > fh))
3352                 return -EINVAL;
3353
3354         k = (100 * fh) / fl;
3355         t1 = (t * (k - 100));
3356         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3357         a = (a + 5) / 10;
3358         ah = ((a * t) + 5000) / 10000;
3359         al = a - ah;
3360
3361         *th = t - ah;
3362         *tl = t + al;
3363
3364         return 0;
3365 }
3366
3367 static bool r600_is_uvd_state(u32 class, u32 class2)
3368 {
3369         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3370                 return true;
3371         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3372                 return true;
3373         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3374                 return true;
3375         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3376                 return true;
3377         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3378                 return true;
3379         return false;
3380 }
3381
3382 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3383 {
3384         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3385 }
3386
3387 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3388 {
3389         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3390         u16 vddc;
3391
3392         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3393                 pi->max_vddc = 0;
3394         else
3395                 pi->max_vddc = vddc;
3396 }
3397
3398 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3399 {
3400         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3401         struct amdgpu_atom_ss ss;
3402
3403         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3404                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3405         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3406                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3407
3408         if (pi->sclk_ss || pi->mclk_ss)
3409                 pi->dynamic_ss = true;
3410         else
3411                 pi->dynamic_ss = false;
3412 }
3413
3414
3415 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3416                                         struct amdgpu_ps *rps)
3417 {
3418         struct  si_ps *ps = si_get_ps(rps);
3419         struct amdgpu_clock_and_voltage_limits *max_limits;
3420         bool disable_mclk_switching = false;
3421         bool disable_sclk_switching = false;
3422         u32 mclk, sclk;
3423         u16 vddc, vddci, min_vce_voltage = 0;
3424         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3425         u32 max_sclk = 0, max_mclk = 0;
3426         int i;
3427
3428         if (adev->asic_type == CHIP_HAINAN) {
3429                 if ((adev->pdev->revision == 0x81) ||
3430                     (adev->pdev->revision == 0x83) ||
3431                     (adev->pdev->revision == 0xC3) ||
3432                     (adev->pdev->device == 0x6664) ||
3433                     (adev->pdev->device == 0x6665) ||
3434                     (adev->pdev->device == 0x6667)) {
3435                         max_sclk = 75000;
3436                 }
3437                 if ((adev->pdev->revision == 0xC3) ||
3438                     (adev->pdev->device == 0x6665)) {
3439                         max_sclk = 60000;
3440                         max_mclk = 80000;
3441                 }
3442         } else if (adev->asic_type == CHIP_OLAND) {
3443                 if ((adev->pdev->revision == 0xC7) ||
3444                     (adev->pdev->revision == 0x80) ||
3445                     (adev->pdev->revision == 0x81) ||
3446                     (adev->pdev->revision == 0x83) ||
3447                     (adev->pdev->revision == 0x87) ||
3448                     (adev->pdev->device == 0x6604) ||
3449                     (adev->pdev->device == 0x6605)) {
3450                         max_sclk = 75000;
3451                 }
3452         }
3453
3454         if (rps->vce_active) {
3455                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3456                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3457                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3458                                          &min_vce_voltage);
3459         } else {
3460                 rps->evclk = 0;
3461                 rps->ecclk = 0;
3462         }
3463
3464         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3465             si_dpm_vblank_too_short(adev))
3466                 disable_mclk_switching = true;
3467
3468         if (rps->vclk || rps->dclk) {
3469                 disable_mclk_switching = true;
3470                 disable_sclk_switching = true;
3471         }
3472
3473         if (adev->pm.dpm.ac_power)
3474                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3475         else
3476                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3477
3478         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3479                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3480                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3481         }
3482         if (adev->pm.dpm.ac_power == false) {
3483                 for (i = 0; i < ps->performance_level_count; i++) {
3484                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3485                                 ps->performance_levels[i].mclk = max_limits->mclk;
3486                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3487                                 ps->performance_levels[i].sclk = max_limits->sclk;
3488                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3489                                 ps->performance_levels[i].vddc = max_limits->vddc;
3490                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3491                                 ps->performance_levels[i].vddci = max_limits->vddci;
3492                 }
3493         }
3494
3495         /* limit clocks to max supported clocks based on voltage dependency tables */
3496         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3497                                                         &max_sclk_vddc);
3498         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3499                                                         &max_mclk_vddci);
3500         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3501                                                         &max_mclk_vddc);
3502
3503         for (i = 0; i < ps->performance_level_count; i++) {
3504                 if (max_sclk_vddc) {
3505                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3506                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3507                 }
3508                 if (max_mclk_vddci) {
3509                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3510                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3511                 }
3512                 if (max_mclk_vddc) {
3513                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3514                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3515                 }
3516                 if (max_mclk) {
3517                         if (ps->performance_levels[i].mclk > max_mclk)
3518                                 ps->performance_levels[i].mclk = max_mclk;
3519                 }
3520                 if (max_sclk) {
3521                         if (ps->performance_levels[i].sclk > max_sclk)
3522                                 ps->performance_levels[i].sclk = max_sclk;
3523                 }
3524         }
3525
3526         /* XXX validate the min clocks required for display */
3527
3528         if (disable_mclk_switching) {
3529                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3530                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3531         } else {
3532                 mclk = ps->performance_levels[0].mclk;
3533                 vddci = ps->performance_levels[0].vddci;
3534         }
3535
3536         if (disable_sclk_switching) {
3537                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3538                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3539         } else {
3540                 sclk = ps->performance_levels[0].sclk;
3541                 vddc = ps->performance_levels[0].vddc;
3542         }
3543
3544         if (rps->vce_active) {
3545                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3546                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3547                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3548                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3549         }
3550
3551         /* adjusted low state */
3552         ps->performance_levels[0].sclk = sclk;
3553         ps->performance_levels[0].mclk = mclk;
3554         ps->performance_levels[0].vddc = vddc;
3555         ps->performance_levels[0].vddci = vddci;
3556
3557         if (disable_sclk_switching) {
3558                 sclk = ps->performance_levels[0].sclk;
3559                 for (i = 1; i < ps->performance_level_count; i++) {
3560                         if (sclk < ps->performance_levels[i].sclk)
3561                                 sclk = ps->performance_levels[i].sclk;
3562                 }
3563                 for (i = 0; i < ps->performance_level_count; i++) {
3564                         ps->performance_levels[i].sclk = sclk;
3565                         ps->performance_levels[i].vddc = vddc;
3566                 }
3567         } else {
3568                 for (i = 1; i < ps->performance_level_count; i++) {
3569                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3570                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3571                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3572                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3573                 }
3574         }
3575
3576         if (disable_mclk_switching) {
3577                 mclk = ps->performance_levels[0].mclk;
3578                 for (i = 1; i < ps->performance_level_count; i++) {
3579                         if (mclk < ps->performance_levels[i].mclk)
3580                                 mclk = ps->performance_levels[i].mclk;
3581                 }
3582                 for (i = 0; i < ps->performance_level_count; i++) {
3583                         ps->performance_levels[i].mclk = mclk;
3584                         ps->performance_levels[i].vddci = vddci;
3585                 }
3586         } else {
3587                 for (i = 1; i < ps->performance_level_count; i++) {
3588                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3589                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3590                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3591                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3592                 }
3593         }
3594
3595         for (i = 0; i < ps->performance_level_count; i++)
3596                 btc_adjust_clock_combinations(adev, max_limits,
3597                                               &ps->performance_levels[i]);
3598
3599         for (i = 0; i < ps->performance_level_count; i++) {
3600                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3601                         ps->performance_levels[i].vddc = min_vce_voltage;
3602                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3603                                                    ps->performance_levels[i].sclk,
3604                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3605                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3606                                                    ps->performance_levels[i].mclk,
3607                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3608                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3609                                                    ps->performance_levels[i].mclk,
3610                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3611                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3612                                                    adev->clock.current_dispclk,
3613                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3614         }
3615
3616         for (i = 0; i < ps->performance_level_count; i++) {
3617                 btc_apply_voltage_delta_rules(adev,
3618                                               max_limits->vddc, max_limits->vddci,
3619                                               &ps->performance_levels[i].vddc,
3620                                               &ps->performance_levels[i].vddci);
3621         }
3622
3623         ps->dc_compatible = true;
3624         for (i = 0; i < ps->performance_level_count; i++) {
3625                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3626                         ps->dc_compatible = false;
3627         }
3628 }
3629
3630 #if 0
3631 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3632                                      u16 reg_offset, u32 *value)
3633 {
3634         struct si_power_info *si_pi = si_get_pi(adev);
3635
3636         return amdgpu_si_read_smc_sram_dword(adev,
3637                                              si_pi->soft_regs_start + reg_offset, value,
3638                                              si_pi->sram_end);
3639 }
3640 #endif
3641
3642 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3643                                       u16 reg_offset, u32 value)
3644 {
3645         struct si_power_info *si_pi = si_get_pi(adev);
3646
3647         return amdgpu_si_write_smc_sram_dword(adev,
3648                                               si_pi->soft_regs_start + reg_offset,
3649                                               value, si_pi->sram_end);
3650 }
3651
3652 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3653 {
3654         bool ret = false;
3655         u32 tmp, width, row, column, bank, density;
3656         bool is_memory_gddr5, is_special;
3657
3658         tmp = RREG32(MC_SEQ_MISC0);
3659         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3660         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3661                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3662
3663         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3664         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3665
3666         tmp = RREG32(MC_ARB_RAMCFG);
3667         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3668         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3669         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3670
3671         density = (1 << (row + column - 20 + bank)) * width;
3672
3673         if ((adev->pdev->device == 0x6819) &&
3674             is_memory_gddr5 && is_special && (density == 0x400))
3675                 ret = true;
3676
3677         return ret;
3678 }
3679
3680 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3681 {
3682         struct si_power_info *si_pi = si_get_pi(adev);
3683         u16 vddc, count = 0;
3684         int i, ret;
3685
3686         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3687                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3688
3689                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3690                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3691                         si_pi->leakage_voltage.entries[count].leakage_index =
3692                                 SISLANDS_LEAKAGE_INDEX0 + i;
3693                         count++;
3694                 }
3695         }
3696         si_pi->leakage_voltage.count = count;
3697 }
3698
3699 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3700                                                      u32 index, u16 *leakage_voltage)
3701 {
3702         struct si_power_info *si_pi = si_get_pi(adev);
3703         int i;
3704
3705         if (leakage_voltage == NULL)
3706                 return -EINVAL;
3707
3708         if ((index & 0xff00) != 0xff00)
3709                 return -EINVAL;
3710
3711         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3712                 return -EINVAL;
3713
3714         if (index < SISLANDS_LEAKAGE_INDEX0)
3715                 return -EINVAL;
3716
3717         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3718                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3719                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3720                         return 0;
3721                 }
3722         }
3723         return -EAGAIN;
3724 }
3725
3726 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3727 {
3728         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3729         bool want_thermal_protection;
3730         enum amdgpu_dpm_event_src dpm_event_src;
3731
3732         switch (sources) {
3733         case 0:
3734         default:
3735                 want_thermal_protection = false;
3736                 break;
3737         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3738                 want_thermal_protection = true;
3739                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3740                 break;
3741         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3742                 want_thermal_protection = true;
3743                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3744                 break;
3745         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3746               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3747                 want_thermal_protection = true;
3748                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3749                 break;
3750         }
3751
3752         if (want_thermal_protection) {
3753                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3754                 if (pi->thermal_protection)
3755                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3756         } else {
3757                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3758         }
3759 }
3760
3761 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3762                                            enum amdgpu_dpm_auto_throttle_src source,
3763                                            bool enable)
3764 {
3765         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3766
3767         if (enable) {
3768                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3769                         pi->active_auto_throttle_sources |= 1 << source;
3770                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3771                 }
3772         } else {
3773                 if (pi->active_auto_throttle_sources & (1 << source)) {
3774                         pi->active_auto_throttle_sources &= ~(1 << source);
3775                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3776                 }
3777         }
3778 }
3779
3780 static void si_start_dpm(struct amdgpu_device *adev)
3781 {
3782         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3783 }
3784
3785 static void si_stop_dpm(struct amdgpu_device *adev)
3786 {
3787         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3788 }
3789
3790 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3791 {
3792         if (enable)
3793                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3794         else
3795                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3796
3797 }
3798
3799 #if 0
3800 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3801                                                u32 thermal_level)
3802 {
3803         PPSMC_Result ret;
3804
3805         if (thermal_level == 0) {
3806                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3807                 if (ret == PPSMC_Result_OK)
3808                         return 0;
3809                 else
3810                         return -EINVAL;
3811         }
3812         return 0;
3813 }
3814
3815 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3816 {
3817         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3818 }
3819 #endif
3820
3821 #if 0
3822 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3823 {
3824         if (ac_power)
3825                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3826                         0 : -EINVAL;
3827
3828         return 0;
3829 }
3830 #endif
3831
3832 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3833                                                       PPSMC_Msg msg, u32 parameter)
3834 {
3835         WREG32(SMC_SCRATCH0, parameter);
3836         return amdgpu_si_send_msg_to_smc(adev, msg);
3837 }
3838
3839 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3840 {
3841         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3842                 return -EINVAL;
3843
3844         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3845                 0 : -EINVAL;
3846 }
3847
3848 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3849                                    enum amd_dpm_forced_level level)
3850 {
3851         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3852         struct  si_ps *ps = si_get_ps(rps);
3853         u32 levels = ps->performance_level_count;
3854
3855         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3856                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3857                         return -EINVAL;
3858
3859                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3860                         return -EINVAL;
3861         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3862                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3863                         return -EINVAL;
3864
3865                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3866                         return -EINVAL;
3867         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3868                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3869                         return -EINVAL;
3870
3871                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3872                         return -EINVAL;
3873         }
3874
3875         adev->pm.dpm.forced_level = level;
3876
3877         return 0;
3878 }
3879
3880 #if 0
3881 static int si_set_boot_state(struct amdgpu_device *adev)
3882 {
3883         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3884                 0 : -EINVAL;
3885 }
3886 #endif
3887
3888 static int si_set_sw_state(struct amdgpu_device *adev)
3889 {
3890         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3891                 0 : -EINVAL;
3892 }
3893
3894 static int si_halt_smc(struct amdgpu_device *adev)
3895 {
3896         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3897                 return -EINVAL;
3898
3899         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3900                 0 : -EINVAL;
3901 }
3902
3903 static int si_resume_smc(struct amdgpu_device *adev)
3904 {
3905         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3906                 return -EINVAL;
3907
3908         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3909                 0 : -EINVAL;
3910 }
3911
3912 static void si_dpm_start_smc(struct amdgpu_device *adev)
3913 {
3914         amdgpu_si_program_jump_on_start(adev);
3915         amdgpu_si_start_smc(adev);
3916         amdgpu_si_smc_clock(adev, true);
3917 }
3918
3919 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3920 {
3921         amdgpu_si_reset_smc(adev);
3922         amdgpu_si_smc_clock(adev, false);
3923 }
3924
3925 static int si_process_firmware_header(struct amdgpu_device *adev)
3926 {
3927         struct si_power_info *si_pi = si_get_pi(adev);
3928         u32 tmp;
3929         int ret;
3930
3931         ret = amdgpu_si_read_smc_sram_dword(adev,
3932                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3933                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3934                                             &tmp, si_pi->sram_end);
3935         if (ret)
3936                 return ret;
3937
3938         si_pi->state_table_start = tmp;
3939
3940         ret = amdgpu_si_read_smc_sram_dword(adev,
3941                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3942                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3943                                             &tmp, si_pi->sram_end);
3944         if (ret)
3945                 return ret;
3946
3947         si_pi->soft_regs_start = tmp;
3948
3949         ret = amdgpu_si_read_smc_sram_dword(adev,
3950                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3951                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3952                                             &tmp, si_pi->sram_end);
3953         if (ret)
3954                 return ret;
3955
3956         si_pi->mc_reg_table_start = tmp;
3957
3958         ret = amdgpu_si_read_smc_sram_dword(adev,
3959                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3960                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3961                                             &tmp, si_pi->sram_end);
3962         if (ret)
3963                 return ret;
3964
3965         si_pi->fan_table_start = tmp;
3966
3967         ret = amdgpu_si_read_smc_sram_dword(adev,
3968                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3969                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3970                                             &tmp, si_pi->sram_end);
3971         if (ret)
3972                 return ret;
3973
3974         si_pi->arb_table_start = tmp;
3975
3976         ret = amdgpu_si_read_smc_sram_dword(adev,
3977                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3978                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3979                                             &tmp, si_pi->sram_end);
3980         if (ret)
3981                 return ret;
3982
3983         si_pi->cac_table_start = tmp;
3984
3985         ret = amdgpu_si_read_smc_sram_dword(adev,
3986                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3987                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3988                                             &tmp, si_pi->sram_end);
3989         if (ret)
3990                 return ret;
3991
3992         si_pi->dte_table_start = tmp;
3993
3994         ret = amdgpu_si_read_smc_sram_dword(adev,
3995                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3996                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3997                                             &tmp, si_pi->sram_end);
3998         if (ret)
3999                 return ret;
4000
4001         si_pi->spll_table_start = tmp;
4002
4003         ret = amdgpu_si_read_smc_sram_dword(adev,
4004                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4005                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4006                                             &tmp, si_pi->sram_end);
4007         if (ret)
4008                 return ret;
4009
4010         si_pi->papm_cfg_table_start = tmp;
4011
4012         return ret;
4013 }
4014
4015 static void si_read_clock_registers(struct amdgpu_device *adev)
4016 {
4017         struct si_power_info *si_pi = si_get_pi(adev);
4018
4019         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4020         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4021         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4022         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4023         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4024         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4025         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4026         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4027         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4028         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4029         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4030         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4031         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4032         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4033         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4034 }
4035
4036 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4037                                           bool enable)
4038 {
4039         if (enable)
4040                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4041         else
4042                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4043 }
4044
4045 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4046 {
4047         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4048 }
4049
4050 #if 0
4051 static int si_enter_ulp_state(struct amdgpu_device *adev)
4052 {
4053         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4054
4055         udelay(25000);
4056
4057         return 0;
4058 }
4059
4060 static int si_exit_ulp_state(struct amdgpu_device *adev)
4061 {
4062         int i;
4063
4064         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4065
4066         udelay(7000);
4067
4068         for (i = 0; i < adev->usec_timeout; i++) {
4069                 if (RREG32(SMC_RESP_0) == 1)
4070                         break;
4071                 udelay(1000);
4072         }
4073
4074         return 0;
4075 }
4076 #endif
4077
4078 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4079                                      bool has_display)
4080 {
4081         PPSMC_Msg msg = has_display ?
4082                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4083
4084         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4085                 0 : -EINVAL;
4086 }
4087
4088 static void si_program_response_times(struct amdgpu_device *adev)
4089 {
4090         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4091         u32 vddc_dly, acpi_dly, vbi_dly;
4092         u32 reference_clock;
4093
4094         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4095
4096         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4097         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4098
4099         if (voltage_response_time == 0)
4100                 voltage_response_time = 1000;
4101
4102         acpi_delay_time = 15000;
4103         vbi_time_out = 100000;
4104
4105         reference_clock = amdgpu_asic_get_xclk(adev);
4106
4107         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4108         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4109         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4110
4111         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4112         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4113         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4114         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4115 }
4116
4117 static void si_program_ds_registers(struct amdgpu_device *adev)
4118 {
4119         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4120         u32 tmp;
4121
4122         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4123         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4124                 tmp = 0x10;
4125         else
4126                 tmp = 0x1;
4127
4128         if (eg_pi->sclk_deep_sleep) {
4129                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4130                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4131                          ~AUTOSCALE_ON_SS_CLEAR);
4132         }
4133 }
4134
4135 static void si_program_display_gap(struct amdgpu_device *adev)
4136 {
4137         u32 tmp, pipe;
4138         int i;
4139
4140         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4141         if (adev->pm.dpm.new_active_crtc_count > 0)
4142                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4143         else
4144                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4145
4146         if (adev->pm.dpm.new_active_crtc_count > 1)
4147                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4148         else
4149                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4150
4151         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4152
4153         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4154         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4155
4156         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4157             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4158                 /* find the first active crtc */
4159                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4160                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4161                                 break;
4162                 }
4163                 if (i == adev->mode_info.num_crtc)
4164                         pipe = 0;
4165                 else
4166                         pipe = i;
4167
4168                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4169                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4170                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4171         }
4172
4173         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4174          * This can be a problem on PowerXpress systems or if you want to use the card
4175          * for offscreen rendering or compute if there are no crtcs enabled.
4176          */
4177         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4178 }
4179
4180 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4181 {
4182         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4183
4184         if (enable) {
4185                 if (pi->sclk_ss)
4186                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4187         } else {
4188                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4189                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4190         }
4191 }
4192
4193 static void si_setup_bsp(struct amdgpu_device *adev)
4194 {
4195         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4196         u32 xclk = amdgpu_asic_get_xclk(adev);
4197
4198         r600_calculate_u_and_p(pi->asi,
4199                                xclk,
4200                                16,
4201                                &pi->bsp,
4202                                &pi->bsu);
4203
4204         r600_calculate_u_and_p(pi->pasi,
4205                                xclk,
4206                                16,
4207                                &pi->pbsp,
4208                                &pi->pbsu);
4209
4210
4211         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4212         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4213
4214         WREG32(CG_BSP, pi->dsp);
4215 }
4216
4217 static void si_program_git(struct amdgpu_device *adev)
4218 {
4219         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4220 }
4221
4222 static void si_program_tp(struct amdgpu_device *adev)
4223 {
4224         int i;
4225         enum r600_td td = R600_TD_DFLT;
4226
4227         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4228                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4229
4230         if (td == R600_TD_AUTO)
4231                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4232         else
4233                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4234
4235         if (td == R600_TD_UP)
4236                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4237
4238         if (td == R600_TD_DOWN)
4239                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4240 }
4241
4242 static void si_program_tpp(struct amdgpu_device *adev)
4243 {
4244         WREG32(CG_TPC, R600_TPC_DFLT);
4245 }
4246
4247 static void si_program_sstp(struct amdgpu_device *adev)
4248 {
4249         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4250 }
4251
4252 static void si_enable_display_gap(struct amdgpu_device *adev)
4253 {
4254         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4255
4256         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4257         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4258                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4259
4260         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4261         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4262                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4263         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4264 }
4265
4266 static void si_program_vc(struct amdgpu_device *adev)
4267 {
4268         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4269
4270         WREG32(CG_FTV, pi->vrc);
4271 }
4272
4273 static void si_clear_vc(struct amdgpu_device *adev)
4274 {
4275         WREG32(CG_FTV, 0);
4276 }
4277
4278 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4279 {
4280         u8 mc_para_index;
4281
4282         if (memory_clock < 10000)
4283                 mc_para_index = 0;
4284         else if (memory_clock >= 80000)
4285                 mc_para_index = 0x0f;
4286         else
4287                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4288         return mc_para_index;
4289 }
4290
4291 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4292 {
4293         u8 mc_para_index;
4294
4295         if (strobe_mode) {
4296                 if (memory_clock < 12500)
4297                         mc_para_index = 0x00;
4298                 else if (memory_clock > 47500)
4299                         mc_para_index = 0x0f;
4300                 else
4301                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4302         } else {
4303                 if (memory_clock < 65000)
4304                         mc_para_index = 0x00;
4305                 else if (memory_clock > 135000)
4306                         mc_para_index = 0x0f;
4307                 else
4308                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4309         }
4310         return mc_para_index;
4311 }
4312
4313 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4314 {
4315         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4316         bool strobe_mode = false;
4317         u8 result = 0;
4318
4319         if (mclk <= pi->mclk_strobe_mode_threshold)
4320                 strobe_mode = true;
4321
4322         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4323                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4324         else
4325                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4326
4327         if (strobe_mode)
4328                 result |= SISLANDS_SMC_STROBE_ENABLE;
4329
4330         return result;
4331 }
4332
4333 static int si_upload_firmware(struct amdgpu_device *adev)
4334 {
4335         struct si_power_info *si_pi = si_get_pi(adev);
4336
4337         amdgpu_si_reset_smc(adev);
4338         amdgpu_si_smc_clock(adev, false);
4339
4340         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4341 }
4342
4343 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4344                                               const struct atom_voltage_table *table,
4345                                               const struct amdgpu_phase_shedding_limits_table *limits)
4346 {
4347         u32 data, num_bits, num_levels;
4348
4349         if ((table == NULL) || (limits == NULL))
4350                 return false;
4351
4352         data = table->mask_low;
4353
4354         num_bits = hweight32(data);
4355
4356         if (num_bits == 0)
4357                 return false;
4358
4359         num_levels = (1 << num_bits);
4360
4361         if (table->count != num_levels)
4362                 return false;
4363
4364         if (limits->count != (num_levels - 1))
4365                 return false;
4366
4367         return true;
4368 }
4369
4370 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4371                                               u32 max_voltage_steps,
4372                                               struct atom_voltage_table *voltage_table)
4373 {
4374         unsigned int i, diff;
4375
4376         if (voltage_table->count <= max_voltage_steps)
4377                 return;
4378
4379         diff = voltage_table->count - max_voltage_steps;
4380
4381         for (i= 0; i < max_voltage_steps; i++)
4382                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4383
4384         voltage_table->count = max_voltage_steps;
4385 }
4386
4387 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4388                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4389                                      struct atom_voltage_table *voltage_table)
4390 {
4391         u32 i;
4392
4393         if (voltage_dependency_table == NULL)
4394                 return -EINVAL;
4395
4396         voltage_table->mask_low = 0;
4397         voltage_table->phase_delay = 0;
4398
4399         voltage_table->count = voltage_dependency_table->count;
4400         for (i = 0; i < voltage_table->count; i++) {
4401                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4402                 voltage_table->entries[i].smio_low = 0;
4403         }
4404
4405         return 0;
4406 }
4407
4408 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4409 {
4410         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4411         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4412         struct si_power_info *si_pi = si_get_pi(adev);
4413         int ret;
4414
4415         if (pi->voltage_control) {
4416                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4417                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4418                 if (ret)
4419                         return ret;
4420
4421                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4422                         si_trim_voltage_table_to_fit_state_table(adev,
4423                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4424                                                                  &eg_pi->vddc_voltage_table);
4425         } else if (si_pi->voltage_control_svi2) {
4426                 ret = si_get_svi2_voltage_table(adev,
4427                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4428                                                 &eg_pi->vddc_voltage_table);
4429                 if (ret)
4430                         return ret;
4431         } else {
4432                 return -EINVAL;
4433         }
4434
4435         if (eg_pi->vddci_control) {
4436                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4437                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4438                 if (ret)
4439                         return ret;
4440
4441                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4442                         si_trim_voltage_table_to_fit_state_table(adev,
4443                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4444                                                                  &eg_pi->vddci_voltage_table);
4445         }
4446         if (si_pi->vddci_control_svi2) {
4447                 ret = si_get_svi2_voltage_table(adev,
4448                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4449                                                 &eg_pi->vddci_voltage_table);
4450                 if (ret)
4451                         return ret;
4452         }
4453
4454         if (pi->mvdd_control) {
4455                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4456                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4457
4458                 if (ret) {
4459                         pi->mvdd_control = false;
4460                         return ret;
4461                 }
4462
4463                 if (si_pi->mvdd_voltage_table.count == 0) {
4464                         pi->mvdd_control = false;
4465                         return -EINVAL;
4466                 }
4467
4468                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4469                         si_trim_voltage_table_to_fit_state_table(adev,
4470                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4471                                                                  &si_pi->mvdd_voltage_table);
4472         }
4473
4474         if (si_pi->vddc_phase_shed_control) {
4475                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4476                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4477                 if (ret)
4478                         si_pi->vddc_phase_shed_control = false;
4479
4480                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4481                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4482                         si_pi->vddc_phase_shed_control = false;
4483         }
4484
4485         return 0;
4486 }
4487
4488 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4489                                           const struct atom_voltage_table *voltage_table,
4490                                           SISLANDS_SMC_STATETABLE *table)
4491 {
4492         unsigned int i;
4493
4494         for (i = 0; i < voltage_table->count; i++)
4495                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4496 }
4497
4498 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4499                                           SISLANDS_SMC_STATETABLE *table)
4500 {
4501         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4502         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4503         struct si_power_info *si_pi = si_get_pi(adev);
4504         u8 i;
4505
4506         if (si_pi->voltage_control_svi2) {
4507                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4508                         si_pi->svc_gpio_id);
4509                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4510                         si_pi->svd_gpio_id);
4511                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4512                                            2);
4513         } else {
4514                 if (eg_pi->vddc_voltage_table.count) {
4515                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4516                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4517                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4518
4519                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4520                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4521                                         table->maxVDDCIndexInPPTable = i;
4522                                         break;
4523                                 }
4524                         }
4525                 }
4526
4527                 if (eg_pi->vddci_voltage_table.count) {
4528                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4529
4530                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4531                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4532                 }
4533
4534
4535                 if (si_pi->mvdd_voltage_table.count) {
4536                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4537
4538                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4539                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4540                 }
4541
4542                 if (si_pi->vddc_phase_shed_control) {
4543                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4544                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4545                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4546
4547                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4548                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4549
4550                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4551                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4552                         } else {
4553                                 si_pi->vddc_phase_shed_control = false;
4554                         }
4555                 }
4556         }
4557
4558         return 0;
4559 }
4560
4561 static int si_populate_voltage_value(struct amdgpu_device *adev,
4562                                      const struct atom_voltage_table *table,
4563                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4564 {
4565         unsigned int i;
4566
4567         for (i = 0; i < table->count; i++) {
4568                 if (value <= table->entries[i].value) {
4569                         voltage->index = (u8)i;
4570                         voltage->value = cpu_to_be16(table->entries[i].value);
4571                         break;
4572                 }
4573         }
4574
4575         if (i >= table->count)
4576                 return -EINVAL;
4577
4578         return 0;
4579 }
4580
4581 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4582                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4583 {
4584         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4585         struct si_power_info *si_pi = si_get_pi(adev);
4586
4587         if (pi->mvdd_control) {
4588                 if (mclk <= pi->mvdd_split_frequency)
4589                         voltage->index = 0;
4590                 else
4591                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4592
4593                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4594         }
4595         return 0;
4596 }
4597
4598 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4599                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4600                                     u16 *std_voltage)
4601 {
4602         u16 v_index;
4603         bool voltage_found = false;
4604         *std_voltage = be16_to_cpu(voltage->value);
4605
4606         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4607                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4608                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4609                                 return -EINVAL;
4610
4611                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4612                                 if (be16_to_cpu(voltage->value) ==
4613                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4614                                         voltage_found = true;
4615                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4616                                                 *std_voltage =
4617                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4618                                         else
4619                                                 *std_voltage =
4620                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4621                                         break;
4622                                 }
4623                         }
4624
4625                         if (!voltage_found) {
4626                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4627                                         if (be16_to_cpu(voltage->value) <=
4628                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4629                                                 voltage_found = true;
4630                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4631                                                         *std_voltage =
4632                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4633                                                 else
4634                                                         *std_voltage =
4635                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4636                                                 break;
4637                                         }
4638                                 }
4639                         }
4640                 } else {
4641                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4642                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4643                 }
4644         }
4645
4646         return 0;
4647 }
4648
4649 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4650                                          u16 value, u8 index,
4651                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4652 {
4653         voltage->index = index;
4654         voltage->value = cpu_to_be16(value);
4655
4656         return 0;
4657 }
4658
4659 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4660                                             const struct amdgpu_phase_shedding_limits_table *limits,
4661                                             u16 voltage, u32 sclk, u32 mclk,
4662                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4663 {
4664         unsigned int i;
4665
4666         for (i = 0; i < limits->count; i++) {
4667                 if ((voltage <= limits->entries[i].voltage) &&
4668                     (sclk <= limits->entries[i].sclk) &&
4669                     (mclk <= limits->entries[i].mclk))
4670                         break;
4671         }
4672
4673         smc_voltage->phase_settings = (u8)i;
4674
4675         return 0;
4676 }
4677
4678 static int si_init_arb_table_index(struct amdgpu_device *adev)
4679 {
4680         struct si_power_info *si_pi = si_get_pi(adev);
4681         u32 tmp;
4682         int ret;
4683
4684         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4685                                             &tmp, si_pi->sram_end);
4686         if (ret)
4687                 return ret;
4688
4689         tmp &= 0x00FFFFFF;
4690         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4691
4692         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4693                                               tmp, si_pi->sram_end);
4694 }
4695
4696 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4697 {
4698         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4699 }
4700
4701 static int si_reset_to_default(struct amdgpu_device *adev)
4702 {
4703         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4704                 0 : -EINVAL;
4705 }
4706
4707 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4708 {
4709         struct si_power_info *si_pi = si_get_pi(adev);
4710         u32 tmp;
4711         int ret;
4712
4713         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4714                                             &tmp, si_pi->sram_end);
4715         if (ret)
4716                 return ret;
4717
4718         tmp = (tmp >> 24) & 0xff;
4719
4720         if (tmp == MC_CG_ARB_FREQ_F0)
4721                 return 0;
4722
4723         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4724 }
4725
4726 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4727                                             u32 engine_clock)
4728 {
4729         u32 dram_rows;
4730         u32 dram_refresh_rate;
4731         u32 mc_arb_rfsh_rate;
4732         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4733
4734         if (tmp >= 4)
4735                 dram_rows = 16384;
4736         else
4737                 dram_rows = 1 << (tmp + 10);
4738
4739         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4740         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4741
4742         return mc_arb_rfsh_rate;
4743 }
4744
4745 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4746                                                 struct rv7xx_pl *pl,
4747                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4748 {
4749         u32 dram_timing;
4750         u32 dram_timing2;
4751         u32 burst_time;
4752
4753         arb_regs->mc_arb_rfsh_rate =
4754                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4755
4756         amdgpu_atombios_set_engine_dram_timings(adev,
4757                                             pl->sclk,
4758                                             pl->mclk);
4759
4760         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4761         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4762         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4763
4764         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4765         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4766         arb_regs->mc_arb_burst_time = (u8)burst_time;
4767
4768         return 0;
4769 }
4770
4771 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4772                                                   struct amdgpu_ps *amdgpu_state,
4773                                                   unsigned int first_arb_set)
4774 {
4775         struct si_power_info *si_pi = si_get_pi(adev);
4776         struct  si_ps *state = si_get_ps(amdgpu_state);
4777         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4778         int i, ret = 0;
4779
4780         for (i = 0; i < state->performance_level_count; i++) {
4781                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4782                 if (ret)
4783                         break;
4784                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4785                                                   si_pi->arb_table_start +
4786                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4787                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4788                                                   (u8 *)&arb_regs,
4789                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4790                                                   si_pi->sram_end);
4791                 if (ret)
4792                         break;
4793         }
4794
4795         return ret;
4796 }
4797
4798 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4799                                                struct amdgpu_ps *amdgpu_new_state)
4800 {
4801         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4802                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4803 }
4804
4805 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4806                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4807 {
4808         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4809         struct si_power_info *si_pi = si_get_pi(adev);
4810
4811         if (pi->mvdd_control)
4812                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4813                                                  si_pi->mvdd_bootup_value, voltage);
4814
4815         return 0;
4816 }
4817
4818 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4819                                          struct amdgpu_ps *amdgpu_initial_state,
4820                                          SISLANDS_SMC_STATETABLE *table)
4821 {
4822         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4823         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4824         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4825         struct si_power_info *si_pi = si_get_pi(adev);
4826         u32 reg;
4827         int ret;
4828
4829         table->initialState.levels[0].mclk.vDLL_CNTL =
4830                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4831         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4832                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4833         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4834                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4835         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4836                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4837         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4838                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4839         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4840                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4841         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4842                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4843         table->initialState.levels[0].mclk.vMPLL_SS =
4844                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4845         table->initialState.levels[0].mclk.vMPLL_SS2 =
4846                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4847
4848         table->initialState.levels[0].mclk.mclk_value =
4849                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4850
4851         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4852                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4853         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4854                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4855         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4856                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4857         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4858                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4859         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4860                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4861         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4862                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4863
4864         table->initialState.levels[0].sclk.sclk_value =
4865                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4866
4867         table->initialState.levels[0].arbRefreshState =
4868                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4869
4870         table->initialState.levels[0].ACIndex = 0;
4871
4872         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4873                                         initial_state->performance_levels[0].vddc,
4874                                         &table->initialState.levels[0].vddc);
4875
4876         if (!ret) {
4877                 u16 std_vddc;
4878
4879                 ret = si_get_std_voltage_value(adev,
4880                                                &table->initialState.levels[0].vddc,
4881                                                &std_vddc);
4882                 if (!ret)
4883                         si_populate_std_voltage_value(adev, std_vddc,
4884                                                       table->initialState.levels[0].vddc.index,
4885                                                       &table->initialState.levels[0].std_vddc);
4886         }
4887
4888         if (eg_pi->vddci_control)
4889                 si_populate_voltage_value(adev,
4890                                           &eg_pi->vddci_voltage_table,
4891                                           initial_state->performance_levels[0].vddci,
4892                                           &table->initialState.levels[0].vddci);
4893
4894         if (si_pi->vddc_phase_shed_control)
4895                 si_populate_phase_shedding_value(adev,
4896                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4897                                                  initial_state->performance_levels[0].vddc,
4898                                                  initial_state->performance_levels[0].sclk,
4899                                                  initial_state->performance_levels[0].mclk,
4900                                                  &table->initialState.levels[0].vddc);
4901
4902         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4903
4904         reg = CG_R(0xffff) | CG_L(0);
4905         table->initialState.levels[0].aT = cpu_to_be32(reg);
4906         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4907         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4908
4909         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4910                 table->initialState.levels[0].strobeMode =
4911                         si_get_strobe_mode_settings(adev,
4912                                                     initial_state->performance_levels[0].mclk);
4913
4914                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4915                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4916                 else
4917                         table->initialState.levels[0].mcFlags =  0;
4918         }
4919
4920         table->initialState.levelCount = 1;
4921
4922         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4923
4924         table->initialState.levels[0].dpm2.MaxPS = 0;
4925         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4926         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4927         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4928         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4929
4930         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4931         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4932
4933         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4934         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4935
4936         return 0;
4937 }
4938
4939 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4940                                       SISLANDS_SMC_STATETABLE *table)
4941 {
4942         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4943         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4944         struct si_power_info *si_pi = si_get_pi(adev);
4945         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4946         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4947         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4948         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4949         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4950         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4951         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4952         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4953         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4954         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4955         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4956         u32 reg;
4957         int ret;
4958
4959         table->ACPIState = table->initialState;
4960
4961         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4962
4963         if (pi->acpi_vddc) {
4964                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4965                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4966                 if (!ret) {
4967                         u16 std_vddc;
4968
4969                         ret = si_get_std_voltage_value(adev,
4970                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4971                         if (!ret)
4972                                 si_populate_std_voltage_value(adev, std_vddc,
4973                                                               table->ACPIState.levels[0].vddc.index,
4974                                                               &table->ACPIState.levels[0].std_vddc);
4975                 }
4976                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4977
4978                 if (si_pi->vddc_phase_shed_control) {
4979                         si_populate_phase_shedding_value(adev,
4980                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4981                                                          pi->acpi_vddc,
4982                                                          0,
4983                                                          0,
4984                                                          &table->ACPIState.levels[0].vddc);
4985                 }
4986         } else {
4987                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4988                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4989                 if (!ret) {
4990                         u16 std_vddc;
4991
4992                         ret = si_get_std_voltage_value(adev,
4993                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4994
4995                         if (!ret)
4996                                 si_populate_std_voltage_value(adev, std_vddc,
4997                                                               table->ACPIState.levels[0].vddc.index,
4998                                                               &table->ACPIState.levels[0].std_vddc);
4999                 }
5000                 table->ACPIState.levels[0].gen2PCIE =
5001                         (u8)amdgpu_get_pcie_gen_support(adev,
5002                                                         si_pi->sys_pcie_mask,
5003                                                         si_pi->boot_pcie_gen,
5004                                                         AMDGPU_PCIE_GEN1);
5005
5006                 if (si_pi->vddc_phase_shed_control)
5007                         si_populate_phase_shedding_value(adev,
5008                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5009                                                          pi->min_vddc_in_table,
5010                                                          0,
5011                                                          0,
5012                                                          &table->ACPIState.levels[0].vddc);
5013         }
5014
5015         if (pi->acpi_vddc) {
5016                 if (eg_pi->acpi_vddci)
5017                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5018                                                   eg_pi->acpi_vddci,
5019                                                   &table->ACPIState.levels[0].vddci);
5020         }
5021
5022         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5023         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5024
5025         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5026
5027         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5028         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5029
5030         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5031                 cpu_to_be32(dll_cntl);
5032         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5033                 cpu_to_be32(mclk_pwrmgt_cntl);
5034         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5035                 cpu_to_be32(mpll_ad_func_cntl);
5036         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5037                 cpu_to_be32(mpll_dq_func_cntl);
5038         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5039                 cpu_to_be32(mpll_func_cntl);
5040         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5041                 cpu_to_be32(mpll_func_cntl_1);
5042         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5043                 cpu_to_be32(mpll_func_cntl_2);
5044         table->ACPIState.levels[0].mclk.vMPLL_SS =
5045                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5046         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5047                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5048
5049         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5050                 cpu_to_be32(spll_func_cntl);
5051         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5052                 cpu_to_be32(spll_func_cntl_2);
5053         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5054                 cpu_to_be32(spll_func_cntl_3);
5055         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5056                 cpu_to_be32(spll_func_cntl_4);
5057
5058         table->ACPIState.levels[0].mclk.mclk_value = 0;
5059         table->ACPIState.levels[0].sclk.sclk_value = 0;
5060
5061         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5062
5063         if (eg_pi->dynamic_ac_timing)
5064                 table->ACPIState.levels[0].ACIndex = 0;
5065
5066         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5067         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5068         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5069         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5070         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5071
5072         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5073         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5074
5075         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5076         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5077
5078         return 0;
5079 }
5080
5081 static int si_populate_ulv_state(struct amdgpu_device *adev,
5082                                  SISLANDS_SMC_SWSTATE *state)
5083 {
5084         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5085         struct si_power_info *si_pi = si_get_pi(adev);
5086         struct si_ulv_param *ulv = &si_pi->ulv;
5087         u32 sclk_in_sr = 1350; /* ??? */
5088         int ret;
5089
5090         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5091                                             &state->levels[0]);
5092         if (!ret) {
5093                 if (eg_pi->sclk_deep_sleep) {
5094                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5095                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5096                         else
5097                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5098                 }
5099                 if (ulv->one_pcie_lane_in_ulv)
5100                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5101                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5102                 state->levels[0].ACIndex = 1;
5103                 state->levels[0].std_vddc = state->levels[0].vddc;
5104                 state->levelCount = 1;
5105
5106                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5107         }
5108
5109         return ret;
5110 }
5111
5112 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5113 {
5114         struct si_power_info *si_pi = si_get_pi(adev);
5115         struct si_ulv_param *ulv = &si_pi->ulv;
5116         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5117         int ret;
5118
5119         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5120                                                    &arb_regs);
5121         if (ret)
5122                 return ret;
5123
5124         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5125                                    ulv->volt_change_delay);
5126
5127         ret = amdgpu_si_copy_bytes_to_smc(adev,
5128                                           si_pi->arb_table_start +
5129                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5130                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5131                                           (u8 *)&arb_regs,
5132                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5133                                           si_pi->sram_end);
5134
5135         return ret;
5136 }
5137
5138 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5139 {
5140         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5141
5142         pi->mvdd_split_frequency = 30000;
5143 }
5144
5145 static int si_init_smc_table(struct amdgpu_device *adev)
5146 {
5147         struct si_power_info *si_pi = si_get_pi(adev);
5148         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5149         const struct si_ulv_param *ulv = &si_pi->ulv;
5150         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5151         int ret;
5152         u32 lane_width;
5153         u32 vr_hot_gpio;
5154
5155         si_populate_smc_voltage_tables(adev, table);
5156
5157         switch (adev->pm.int_thermal_type) {
5158         case THERMAL_TYPE_SI:
5159         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5160                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5161                 break;
5162         case THERMAL_TYPE_NONE:
5163                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5164                 break;
5165         default:
5166                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5167                 break;
5168         }
5169
5170         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5171                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5172
5173         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5174                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5175                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5176         }
5177
5178         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5179                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5180
5181         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5182                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5183
5184         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5185                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5186
5187         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5188                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5189                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5190                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5191                                            vr_hot_gpio);
5192         }
5193
5194         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5195         if (ret)
5196                 return ret;
5197
5198         ret = si_populate_smc_acpi_state(adev, table);
5199         if (ret)
5200                 return ret;
5201
5202         table->driverState = table->initialState;
5203
5204         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5205                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5206         if (ret)
5207                 return ret;
5208
5209         if (ulv->supported && ulv->pl.vddc) {
5210                 ret = si_populate_ulv_state(adev, &table->ULVState);
5211                 if (ret)
5212                         return ret;
5213
5214                 ret = si_program_ulv_memory_timing_parameters(adev);
5215                 if (ret)
5216                         return ret;
5217
5218                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5219                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5220
5221                 lane_width = amdgpu_get_pcie_lanes(adev);
5222                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5223         } else {
5224                 table->ULVState = table->initialState;
5225         }
5226
5227         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5228                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5229                                            si_pi->sram_end);
5230 }
5231
5232 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5233                                     u32 engine_clock,
5234                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5235 {
5236         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5237         struct si_power_info *si_pi = si_get_pi(adev);
5238         struct atom_clock_dividers dividers;
5239         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5240         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5241         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5242         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5243         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5244         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5245         u64 tmp;
5246         u32 reference_clock = adev->clock.spll.reference_freq;
5247         u32 reference_divider;
5248         u32 fbdiv;
5249         int ret;
5250
5251         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5252                                              engine_clock, false, &dividers);
5253         if (ret)
5254                 return ret;
5255
5256         reference_divider = 1 + dividers.ref_div;
5257
5258         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5259         do_div(tmp, reference_clock);
5260         fbdiv = (u32) tmp;
5261
5262         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5263         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5264         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5265
5266         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5267         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5268
5269         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5270         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5271         spll_func_cntl_3 |= SPLL_DITHEN;
5272
5273         if (pi->sclk_ss) {
5274                 struct amdgpu_atom_ss ss;
5275                 u32 vco_freq = engine_clock * dividers.post_div;
5276
5277                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5278                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5279                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5280                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5281
5282                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5283                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5284                         cg_spll_spread_spectrum |= SSEN;
5285
5286                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5287                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5288                 }
5289         }
5290
5291         sclk->sclk_value = engine_clock;
5292         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5293         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5294         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5295         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5296         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5297         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5298
5299         return 0;
5300 }
5301
5302 static int si_populate_sclk_value(struct amdgpu_device *adev,
5303                                   u32 engine_clock,
5304                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5305 {
5306         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5307         int ret;
5308
5309         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5310         if (!ret) {
5311                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5312                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5313                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5314                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5315                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5316                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5317                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5318         }
5319
5320         return ret;
5321 }
5322
5323 static int si_populate_mclk_value(struct amdgpu_device *adev,
5324                                   u32 engine_clock,
5325                                   u32 memory_clock,
5326                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5327                                   bool strobe_mode,
5328                                   bool dll_state_on)
5329 {
5330         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5331         struct si_power_info *si_pi = si_get_pi(adev);
5332         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5333         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5334         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5335         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5336         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5337         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5338         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5339         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5340         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5341         struct atom_mpll_param mpll_param;
5342         int ret;
5343
5344         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5345         if (ret)
5346                 return ret;
5347
5348         mpll_func_cntl &= ~BWCTRL_MASK;
5349         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5350
5351         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5352         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5353                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5354
5355         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5356         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5357
5358         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5359                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5360                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5361                         YCLK_POST_DIV(mpll_param.post_div);
5362         }
5363
5364         if (pi->mclk_ss) {
5365                 struct amdgpu_atom_ss ss;
5366                 u32 freq_nom;
5367                 u32 tmp;
5368                 u32 reference_clock = adev->clock.mpll.reference_freq;
5369
5370                 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5371                         freq_nom = memory_clock * 4;
5372                 else
5373                         freq_nom = memory_clock * 2;
5374
5375                 tmp = freq_nom / reference_clock;
5376                 tmp = tmp * tmp;
5377                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5378                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5379                         u32 clks = reference_clock * 5 / ss.rate;
5380                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5381
5382                         mpll_ss1 &= ~CLKV_MASK;
5383                         mpll_ss1 |= CLKV(clkv);
5384
5385                         mpll_ss2 &= ~CLKS_MASK;
5386                         mpll_ss2 |= CLKS(clks);
5387                 }
5388         }
5389
5390         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5391         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5392
5393         if (dll_state_on)
5394                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5395         else
5396                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5397
5398         mclk->mclk_value = cpu_to_be32(memory_clock);
5399         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5400         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5401         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5402         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5403         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5404         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5405         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5406         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5407         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5408
5409         return 0;
5410 }
5411
5412 static void si_populate_smc_sp(struct amdgpu_device *adev,
5413                                struct amdgpu_ps *amdgpu_state,
5414                                SISLANDS_SMC_SWSTATE *smc_state)
5415 {
5416         struct  si_ps *ps = si_get_ps(amdgpu_state);
5417         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5418         int i;
5419
5420         for (i = 0; i < ps->performance_level_count - 1; i++)
5421                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5422
5423         smc_state->levels[ps->performance_level_count - 1].bSP =
5424                 cpu_to_be32(pi->psp);
5425 }
5426
5427 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5428                                          struct rv7xx_pl *pl,
5429                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5430 {
5431         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5432         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5433         struct si_power_info *si_pi = si_get_pi(adev);
5434         int ret;
5435         bool dll_state_on;
5436         u16 std_vddc;
5437         bool gmc_pg = false;
5438
5439         if (eg_pi->pcie_performance_request &&
5440             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5441                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5442         else
5443                 level->gen2PCIE = (u8)pl->pcie_gen;
5444
5445         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5446         if (ret)
5447                 return ret;
5448
5449         level->mcFlags =  0;
5450
5451         if (pi->mclk_stutter_mode_threshold &&
5452             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5453             !eg_pi->uvd_enabled &&
5454             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5455             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5456                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5457
5458                 if (gmc_pg)
5459                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5460         }
5461
5462         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5463                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5464                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5465
5466                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5467                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5468
5469                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5470
5471                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5472                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5473                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5474                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5475                         else
5476                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5477                 } else {
5478                         dll_state_on = false;
5479                 }
5480         } else {
5481                 level->strobeMode = si_get_strobe_mode_settings(adev,
5482                                                                 pl->mclk);
5483
5484                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5485         }
5486
5487         ret = si_populate_mclk_value(adev,
5488                                      pl->sclk,
5489                                      pl->mclk,
5490                                      &level->mclk,
5491                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5492         if (ret)
5493                 return ret;
5494
5495         ret = si_populate_voltage_value(adev,
5496                                         &eg_pi->vddc_voltage_table,
5497                                         pl->vddc, &level->vddc);
5498         if (ret)
5499                 return ret;
5500
5501
5502         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5503         if (ret)
5504                 return ret;
5505
5506         ret = si_populate_std_voltage_value(adev, std_vddc,
5507                                             level->vddc.index, &level->std_vddc);
5508         if (ret)
5509                 return ret;
5510
5511         if (eg_pi->vddci_control) {
5512                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5513                                                 pl->vddci, &level->vddci);
5514                 if (ret)
5515                         return ret;
5516         }
5517
5518         if (si_pi->vddc_phase_shed_control) {
5519                 ret = si_populate_phase_shedding_value(adev,
5520                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5521                                                        pl->vddc,
5522                                                        pl->sclk,
5523                                                        pl->mclk,
5524                                                        &level->vddc);
5525                 if (ret)
5526                         return ret;
5527         }
5528
5529         level->MaxPoweredUpCU = si_pi->max_cu;
5530
5531         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5532
5533         return ret;
5534 }
5535
5536 static int si_populate_smc_t(struct amdgpu_device *adev,
5537                              struct amdgpu_ps *amdgpu_state,
5538                              SISLANDS_SMC_SWSTATE *smc_state)
5539 {
5540         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5541         struct  si_ps *state = si_get_ps(amdgpu_state);
5542         u32 a_t;
5543         u32 t_l, t_h;
5544         u32 high_bsp;
5545         int i, ret;
5546
5547         if (state->performance_level_count >= 9)
5548                 return -EINVAL;
5549
5550         if (state->performance_level_count < 2) {
5551                 a_t = CG_R(0xffff) | CG_L(0);
5552                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5553                 return 0;
5554         }
5555
5556         smc_state->levels[0].aT = cpu_to_be32(0);
5557
5558         for (i = 0; i <= state->performance_level_count - 2; i++) {
5559                 ret = r600_calculate_at(
5560                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5561                         100 * R600_AH_DFLT,
5562                         state->performance_levels[i + 1].sclk,
5563                         state->performance_levels[i].sclk,
5564                         &t_l,
5565                         &t_h);
5566
5567                 if (ret) {
5568                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5569                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5570                 }
5571
5572                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5573                 a_t |= CG_R(t_l * pi->bsp / 20000);
5574                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5575
5576                 high_bsp = (i == state->performance_level_count - 2) ?
5577                         pi->pbsp : pi->bsp;
5578                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5579                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5580         }
5581
5582         return 0;
5583 }
5584
5585 static int si_disable_ulv(struct amdgpu_device *adev)
5586 {
5587         struct si_power_info *si_pi = si_get_pi(adev);
5588         struct si_ulv_param *ulv = &si_pi->ulv;
5589
5590         if (ulv->supported)
5591                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5592                         0 : -EINVAL;
5593
5594         return 0;
5595 }
5596
5597 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5598                                        struct amdgpu_ps *amdgpu_state)
5599 {
5600         const struct si_power_info *si_pi = si_get_pi(adev);
5601         const struct si_ulv_param *ulv = &si_pi->ulv;
5602         const struct  si_ps *state = si_get_ps(amdgpu_state);
5603         int i;
5604
5605         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5606                 return false;
5607
5608         /* XXX validate against display requirements! */
5609
5610         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5611                 if (adev->clock.current_dispclk <=
5612                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5613                         if (ulv->pl.vddc <
5614                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5615                                 return false;
5616                 }
5617         }
5618
5619         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5620                 return false;
5621
5622         return true;
5623 }
5624
5625 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5626                                                        struct amdgpu_ps *amdgpu_new_state)
5627 {
5628         const struct si_power_info *si_pi = si_get_pi(adev);
5629         const struct si_ulv_param *ulv = &si_pi->ulv;
5630
5631         if (ulv->supported) {
5632                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5633                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5634                                 0 : -EINVAL;
5635         }
5636         return 0;
5637 }
5638
5639 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5640                                          struct amdgpu_ps *amdgpu_state,
5641                                          SISLANDS_SMC_SWSTATE *smc_state)
5642 {
5643         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5644         struct ni_power_info *ni_pi = ni_get_pi(adev);
5645         struct si_power_info *si_pi = si_get_pi(adev);
5646         struct  si_ps *state = si_get_ps(amdgpu_state);
5647         int i, ret;
5648         u32 threshold;
5649         u32 sclk_in_sr = 1350; /* ??? */
5650
5651         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5652                 return -EINVAL;
5653
5654         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5655
5656         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5657                 eg_pi->uvd_enabled = true;
5658                 if (eg_pi->smu_uvd_hs)
5659                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5660         } else {
5661                 eg_pi->uvd_enabled = false;
5662         }
5663
5664         if (state->dc_compatible)
5665                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5666
5667         smc_state->levelCount = 0;
5668         for (i = 0; i < state->performance_level_count; i++) {
5669                 if (eg_pi->sclk_deep_sleep) {
5670                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5671                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5672                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5673                                 else
5674                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5675                         }
5676                 }
5677
5678                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5679                                                     &smc_state->levels[i]);
5680                 smc_state->levels[i].arbRefreshState =
5681                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5682
5683                 if (ret)
5684                         return ret;
5685
5686                 if (ni_pi->enable_power_containment)
5687                         smc_state->levels[i].displayWatermark =
5688                                 (state->performance_levels[i].sclk < threshold) ?
5689                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5690                 else
5691                         smc_state->levels[i].displayWatermark = (i < 2) ?
5692                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5693
5694                 if (eg_pi->dynamic_ac_timing)
5695                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5696                 else
5697                         smc_state->levels[i].ACIndex = 0;
5698
5699                 smc_state->levelCount++;
5700         }
5701
5702         si_write_smc_soft_register(adev,
5703                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5704                                    threshold / 512);
5705
5706         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5707
5708         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5709         if (ret)
5710                 ni_pi->enable_power_containment = false;
5711
5712         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5713         if (ret)
5714                 ni_pi->enable_sq_ramping = false;
5715
5716         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5717 }
5718
5719 static int si_upload_sw_state(struct amdgpu_device *adev,
5720                               struct amdgpu_ps *amdgpu_new_state)
5721 {
5722         struct si_power_info *si_pi = si_get_pi(adev);
5723         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5724         int ret;
5725         u32 address = si_pi->state_table_start +
5726                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5727         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5728                 ((new_state->performance_level_count - 1) *
5729                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5730         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5731
5732         memset(smc_state, 0, state_size);
5733
5734         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5735         if (ret)
5736                 return ret;
5737
5738         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5739                                            state_size, si_pi->sram_end);
5740 }
5741
5742 static int si_upload_ulv_state(struct amdgpu_device *adev)
5743 {
5744         struct si_power_info *si_pi = si_get_pi(adev);
5745         struct si_ulv_param *ulv = &si_pi->ulv;
5746         int ret = 0;
5747
5748         if (ulv->supported && ulv->pl.vddc) {
5749                 u32 address = si_pi->state_table_start +
5750                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5751                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5752                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5753
5754                 memset(smc_state, 0, state_size);
5755
5756                 ret = si_populate_ulv_state(adev, smc_state);
5757                 if (!ret)
5758                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5759                                                           state_size, si_pi->sram_end);
5760         }
5761
5762         return ret;
5763 }
5764
5765 static int si_upload_smc_data(struct amdgpu_device *adev)
5766 {
5767         struct amdgpu_crtc *amdgpu_crtc = NULL;
5768         int i;
5769
5770         if (adev->pm.dpm.new_active_crtc_count == 0)
5771                 return 0;
5772
5773         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5774                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5775                         amdgpu_crtc = adev->mode_info.crtcs[i];
5776                         break;
5777                 }
5778         }
5779
5780         if (amdgpu_crtc == NULL)
5781                 return 0;
5782
5783         if (amdgpu_crtc->line_time <= 0)
5784                 return 0;
5785
5786         if (si_write_smc_soft_register(adev,
5787                                        SI_SMC_SOFT_REGISTER_crtc_index,
5788                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5789                 return 0;
5790
5791         if (si_write_smc_soft_register(adev,
5792                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5793                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5794                 return 0;
5795
5796         if (si_write_smc_soft_register(adev,
5797                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5798                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5799                 return 0;
5800
5801         return 0;
5802 }
5803
5804 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5805                                        struct si_mc_reg_table *table)
5806 {
5807         u8 i, j, k;
5808         u32 temp_reg;
5809
5810         for (i = 0, j = table->last; i < table->last; i++) {
5811                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5812                         return -EINVAL;
5813                 switch (table->mc_reg_address[i].s1) {
5814                 case MC_SEQ_MISC1:
5815                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5816                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5817                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5818                         for (k = 0; k < table->num_entries; k++)
5819                                 table->mc_reg_table_entry[k].mc_data[j] =
5820                                         ((temp_reg & 0xffff0000)) |
5821                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5822                         j++;
5823                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5824                                 return -EINVAL;
5825
5826                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5827                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5828                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5829                         for (k = 0; k < table->num_entries; k++) {
5830                                 table->mc_reg_table_entry[k].mc_data[j] =
5831                                         (temp_reg & 0xffff0000) |
5832                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5833                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5834                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5835                         }
5836                         j++;
5837                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5838                                 return -EINVAL;
5839
5840                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5841                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5842                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5843                                 for (k = 0; k < table->num_entries; k++)
5844                                         table->mc_reg_table_entry[k].mc_data[j] =
5845                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5846                                 j++;
5847                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5848                                         return -EINVAL;
5849                         }
5850                         break;
5851                 case MC_SEQ_RESERVE_M:
5852                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5853                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5854                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5855                         for(k = 0; k < table->num_entries; k++)
5856                                 table->mc_reg_table_entry[k].mc_data[j] =
5857                                         (temp_reg & 0xffff0000) |
5858                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5859                         j++;
5860                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5861                                 return -EINVAL;
5862                         break;
5863                 default:
5864                         break;
5865                 }
5866         }
5867
5868         table->last = j;
5869
5870         return 0;
5871 }
5872
5873 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5874 {
5875         bool result = true;
5876         switch (in_reg) {
5877         case  MC_SEQ_RAS_TIMING:
5878                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5879                 break;
5880         case MC_SEQ_CAS_TIMING:
5881                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5882                 break;
5883         case MC_SEQ_MISC_TIMING:
5884                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5885                 break;
5886         case MC_SEQ_MISC_TIMING2:
5887                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5888                 break;
5889         case MC_SEQ_RD_CTL_D0:
5890                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5891                 break;
5892         case MC_SEQ_RD_CTL_D1:
5893                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5894                 break;
5895         case MC_SEQ_WR_CTL_D0:
5896                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5897                 break;
5898         case MC_SEQ_WR_CTL_D1:
5899                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5900                 break;
5901         case MC_PMG_CMD_EMRS:
5902                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5903                 break;
5904         case MC_PMG_CMD_MRS:
5905                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5906                 break;
5907         case MC_PMG_CMD_MRS1:
5908                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5909                 break;
5910         case MC_SEQ_PMG_TIMING:
5911                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5912                 break;
5913         case MC_PMG_CMD_MRS2:
5914                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5915                 break;
5916         case MC_SEQ_WR_CTL_2:
5917                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5918                 break;
5919         default:
5920                 result = false;
5921                 break;
5922         }
5923
5924         return result;
5925 }
5926
5927 static void si_set_valid_flag(struct si_mc_reg_table *table)
5928 {
5929         u8 i, j;
5930
5931         for (i = 0; i < table->last; i++) {
5932                 for (j = 1; j < table->num_entries; j++) {
5933                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5934                                 table->valid_flag |= 1 << i;
5935                                 break;
5936                         }
5937                 }
5938         }
5939 }
5940
5941 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5942 {
5943         u32 i;
5944         u16 address;
5945
5946         for (i = 0; i < table->last; i++)
5947                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5948                         address : table->mc_reg_address[i].s1;
5949
5950 }
5951
5952 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5953                                       struct si_mc_reg_table *si_table)
5954 {
5955         u8 i, j;
5956
5957         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5958                 return -EINVAL;
5959         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5960                 return -EINVAL;
5961
5962         for (i = 0; i < table->last; i++)
5963                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5964         si_table->last = table->last;
5965
5966         for (i = 0; i < table->num_entries; i++) {
5967                 si_table->mc_reg_table_entry[i].mclk_max =
5968                         table->mc_reg_table_entry[i].mclk_max;
5969                 for (j = 0; j < table->last; j++) {
5970                         si_table->mc_reg_table_entry[i].mc_data[j] =
5971                                 table->mc_reg_table_entry[i].mc_data[j];
5972                 }
5973         }
5974         si_table->num_entries = table->num_entries;
5975
5976         return 0;
5977 }
5978
5979 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
5980 {
5981         struct si_power_info *si_pi = si_get_pi(adev);
5982         struct atom_mc_reg_table *table;
5983         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5984         u8 module_index = rv770_get_memory_module_index(adev);
5985         int ret;
5986
5987         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5988         if (!table)
5989                 return -ENOMEM;
5990
5991         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5992         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5993         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5994         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5995         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5996         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5997         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5998         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5999         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6000         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6001         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6002         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6003         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6004         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6005
6006         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6007         if (ret)
6008                 goto init_mc_done;
6009
6010         ret = si_copy_vbios_mc_reg_table(table, si_table);
6011         if (ret)
6012                 goto init_mc_done;
6013
6014         si_set_s0_mc_reg_index(si_table);
6015
6016         ret = si_set_mc_special_registers(adev, si_table);
6017         if (ret)
6018                 goto init_mc_done;
6019
6020         si_set_valid_flag(si_table);
6021
6022 init_mc_done:
6023         kfree(table);
6024
6025         return ret;
6026
6027 }
6028
6029 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6030                                          SMC_SIslands_MCRegisters *mc_reg_table)
6031 {
6032         struct si_power_info *si_pi = si_get_pi(adev);
6033         u32 i, j;
6034
6035         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6036                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6037                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6038                                 break;
6039                         mc_reg_table->address[i].s0 =
6040                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6041                         mc_reg_table->address[i].s1 =
6042                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6043                         i++;
6044                 }
6045         }
6046         mc_reg_table->last = (u8)i;
6047 }
6048
6049 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6050                                     SMC_SIslands_MCRegisterSet *data,
6051                                     u32 num_entries, u32 valid_flag)
6052 {
6053         u32 i, j;
6054
6055         for(i = 0, j = 0; j < num_entries; j++) {
6056                 if (valid_flag & (1 << j)) {
6057                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6058                         i++;
6059                 }
6060         }
6061 }
6062
6063 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6064                                                  struct rv7xx_pl *pl,
6065                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6066 {
6067         struct si_power_info *si_pi = si_get_pi(adev);
6068         u32 i = 0;
6069
6070         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6071                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6072                         break;
6073         }
6074
6075         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6076                 --i;
6077
6078         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6079                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6080                                 si_pi->mc_reg_table.valid_flag);
6081 }
6082
6083 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6084                                            struct amdgpu_ps *amdgpu_state,
6085                                            SMC_SIslands_MCRegisters *mc_reg_table)
6086 {
6087         struct si_ps *state = si_get_ps(amdgpu_state);
6088         int i;
6089
6090         for (i = 0; i < state->performance_level_count; i++) {
6091                 si_convert_mc_reg_table_entry_to_smc(adev,
6092                                                      &state->performance_levels[i],
6093                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6094         }
6095 }
6096
6097 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6098                                     struct amdgpu_ps *amdgpu_boot_state)
6099 {
6100         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6101         struct si_power_info *si_pi = si_get_pi(adev);
6102         struct si_ulv_param *ulv = &si_pi->ulv;
6103         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6104
6105         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6106
6107         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6108
6109         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6110
6111         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6112                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6113
6114         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6115                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6116                                 si_pi->mc_reg_table.last,
6117                                 si_pi->mc_reg_table.valid_flag);
6118
6119         if (ulv->supported && ulv->pl.vddc != 0)
6120                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6121                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6122         else
6123                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6124                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6125                                         si_pi->mc_reg_table.last,
6126                                         si_pi->mc_reg_table.valid_flag);
6127
6128         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6129
6130         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6131                                            (u8 *)smc_mc_reg_table,
6132                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6133 }
6134
6135 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6136                                   struct amdgpu_ps *amdgpu_new_state)
6137 {
6138         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6139         struct si_power_info *si_pi = si_get_pi(adev);
6140         u32 address = si_pi->mc_reg_table_start +
6141                 offsetof(SMC_SIslands_MCRegisters,
6142                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6143         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6144
6145         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6146
6147         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6148
6149         return amdgpu_si_copy_bytes_to_smc(adev, address,
6150                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6151                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6152                                            si_pi->sram_end);
6153 }
6154
6155 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6156 {
6157         if (enable)
6158                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6159         else
6160                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6161 }
6162
6163 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6164                                                       struct amdgpu_ps *amdgpu_state)
6165 {
6166         struct si_ps *state = si_get_ps(amdgpu_state);
6167         int i;
6168         u16 pcie_speed, max_speed = 0;
6169
6170         for (i = 0; i < state->performance_level_count; i++) {
6171                 pcie_speed = state->performance_levels[i].pcie_gen;
6172                 if (max_speed < pcie_speed)
6173                         max_speed = pcie_speed;
6174         }
6175         return max_speed;
6176 }
6177
6178 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6179 {
6180         u32 speed_cntl;
6181
6182         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6183         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6184
6185         return (u16)speed_cntl;
6186 }
6187
6188 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6189                                                              struct amdgpu_ps *amdgpu_new_state,
6190                                                              struct amdgpu_ps *amdgpu_current_state)
6191 {
6192         struct si_power_info *si_pi = si_get_pi(adev);
6193         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6194         enum amdgpu_pcie_gen current_link_speed;
6195
6196         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6197                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6198         else
6199                 current_link_speed = si_pi->force_pcie_gen;
6200
6201         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6202         si_pi->pspp_notify_required = false;
6203         if (target_link_speed > current_link_speed) {
6204                 switch (target_link_speed) {
6205 #if defined(CONFIG_ACPI)
6206                 case AMDGPU_PCIE_GEN3:
6207                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6208                                 break;
6209                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6210                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6211                                 break;
6212                 case AMDGPU_PCIE_GEN2:
6213                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6214                                 break;
6215 #endif
6216                 default:
6217                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6218                         break;
6219                 }
6220         } else {
6221                 if (target_link_speed < current_link_speed)
6222                         si_pi->pspp_notify_required = true;
6223         }
6224 }
6225
6226 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6227                                                            struct amdgpu_ps *amdgpu_new_state,
6228                                                            struct amdgpu_ps *amdgpu_current_state)
6229 {
6230         struct si_power_info *si_pi = si_get_pi(adev);
6231         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6232         u8 request;
6233
6234         if (si_pi->pspp_notify_required) {
6235                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6236                         request = PCIE_PERF_REQ_PECI_GEN3;
6237                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6238                         request = PCIE_PERF_REQ_PECI_GEN2;
6239                 else
6240                         request = PCIE_PERF_REQ_PECI_GEN1;
6241
6242                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6243                     (si_get_current_pcie_speed(adev) > 0))
6244                         return;
6245
6246 #if defined(CONFIG_ACPI)
6247                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6248 #endif
6249         }
6250 }
6251
6252 #if 0
6253 static int si_ds_request(struct amdgpu_device *adev,
6254                          bool ds_status_on, u32 count_write)
6255 {
6256         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6257
6258         if (eg_pi->sclk_deep_sleep) {
6259                 if (ds_status_on)
6260                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6261                                 PPSMC_Result_OK) ?
6262                                 0 : -EINVAL;
6263                 else
6264                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6265                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6266         }
6267         return 0;
6268 }
6269 #endif
6270
6271 static void si_set_max_cu_value(struct amdgpu_device *adev)
6272 {
6273         struct si_power_info *si_pi = si_get_pi(adev);
6274
6275         if (adev->asic_type == CHIP_VERDE) {
6276                 switch (adev->pdev->device) {
6277                 case 0x6820:
6278                 case 0x6825:
6279                 case 0x6821:
6280                 case 0x6823:
6281                 case 0x6827:
6282                         si_pi->max_cu = 10;
6283                         break;
6284                 case 0x682D:
6285                 case 0x6824:
6286                 case 0x682F:
6287                 case 0x6826:
6288                         si_pi->max_cu = 8;
6289                         break;
6290                 case 0x6828:
6291                 case 0x6830:
6292                 case 0x6831:
6293                 case 0x6838:
6294                 case 0x6839:
6295                 case 0x683D:
6296                         si_pi->max_cu = 10;
6297                         break;
6298                 case 0x683B:
6299                 case 0x683F:
6300                 case 0x6829:
6301                         si_pi->max_cu = 8;
6302                         break;
6303                 default:
6304                         si_pi->max_cu = 0;
6305                         break;
6306                 }
6307         } else {
6308                 si_pi->max_cu = 0;
6309         }
6310 }
6311
6312 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6313                                                              struct amdgpu_clock_voltage_dependency_table *table)
6314 {
6315         u32 i;
6316         int j;
6317         u16 leakage_voltage;
6318
6319         if (table) {
6320                 for (i = 0; i < table->count; i++) {
6321                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6322                                                                           table->entries[i].v,
6323                                                                           &leakage_voltage)) {
6324                         case 0:
6325                                 table->entries[i].v = leakage_voltage;
6326                                 break;
6327                         case -EAGAIN:
6328                                 return -EINVAL;
6329                         case -EINVAL:
6330                         default:
6331                                 break;
6332                         }
6333                 }
6334
6335                 for (j = (table->count - 2); j >= 0; j--) {
6336                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6337                                 table->entries[j].v : table->entries[j + 1].v;
6338                 }
6339         }
6340         return 0;
6341 }
6342
6343 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6344 {
6345         int ret = 0;
6346
6347         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6348                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6349         if (ret)
6350                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6351         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6352                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6353         if (ret)
6354                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6355         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6356                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6357         if (ret)
6358                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6359         return ret;
6360 }
6361
6362 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6363                                           struct amdgpu_ps *amdgpu_new_state,
6364                                           struct amdgpu_ps *amdgpu_current_state)
6365 {
6366         u32 lane_width;
6367         u32 new_lane_width =
6368                 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6369         u32 current_lane_width =
6370                 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6371
6372         if (new_lane_width != current_lane_width) {
6373                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6374                 lane_width = amdgpu_get_pcie_lanes(adev);
6375                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6376         }
6377 }
6378
6379 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6380 {
6381         si_read_clock_registers(adev);
6382         si_enable_acpi_power_management(adev);
6383 }
6384
6385 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6386                                    bool enable)
6387 {
6388         u32 thermal_int = RREG32(CG_THERMAL_INT);
6389
6390         if (enable) {
6391                 PPSMC_Result result;
6392
6393                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6394                 WREG32(CG_THERMAL_INT, thermal_int);
6395                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6396                 if (result != PPSMC_Result_OK) {
6397                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6398                         return -EINVAL;
6399                 }
6400         } else {
6401                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6402                 WREG32(CG_THERMAL_INT, thermal_int);
6403         }
6404
6405         return 0;
6406 }
6407
6408 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6409                                             int min_temp, int max_temp)
6410 {
6411         int low_temp = 0 * 1000;
6412         int high_temp = 255 * 1000;
6413
6414         if (low_temp < min_temp)
6415                 low_temp = min_temp;
6416         if (high_temp > max_temp)
6417                 high_temp = max_temp;
6418         if (high_temp < low_temp) {
6419                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6420                 return -EINVAL;
6421         }
6422
6423         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6424         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6425         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6426
6427         adev->pm.dpm.thermal.min_temp = low_temp;
6428         adev->pm.dpm.thermal.max_temp = high_temp;
6429
6430         return 0;
6431 }
6432
6433 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6434 {
6435         struct si_power_info *si_pi = si_get_pi(adev);
6436         u32 tmp;
6437
6438         if (si_pi->fan_ctrl_is_in_default_mode) {
6439                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6440                 si_pi->fan_ctrl_default_mode = tmp;
6441                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6442                 si_pi->t_min = tmp;
6443                 si_pi->fan_ctrl_is_in_default_mode = false;
6444         }
6445
6446         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6447         tmp |= TMIN(0);
6448         WREG32(CG_FDO_CTRL2, tmp);
6449
6450         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6451         tmp |= FDO_PWM_MODE(mode);
6452         WREG32(CG_FDO_CTRL2, tmp);
6453 }
6454
6455 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6456 {
6457         struct si_power_info *si_pi = si_get_pi(adev);
6458         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6459         u32 duty100;
6460         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6461         u16 fdo_min, slope1, slope2;
6462         u32 reference_clock, tmp;
6463         int ret;
6464         u64 tmp64;
6465
6466         if (!si_pi->fan_table_start) {
6467                 adev->pm.dpm.fan.ucode_fan_control = false;
6468                 return 0;
6469         }
6470
6471         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6472
6473         if (duty100 == 0) {
6474                 adev->pm.dpm.fan.ucode_fan_control = false;
6475                 return 0;
6476         }
6477
6478         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6479         do_div(tmp64, 10000);
6480         fdo_min = (u16)tmp64;
6481
6482         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6483         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6484
6485         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6486         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6487
6488         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6489         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6490
6491         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6492         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6493         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6494         fan_table.slope1 = cpu_to_be16(slope1);
6495         fan_table.slope2 = cpu_to_be16(slope2);
6496         fan_table.fdo_min = cpu_to_be16(fdo_min);
6497         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6498         fan_table.hys_up = cpu_to_be16(1);
6499         fan_table.hys_slope = cpu_to_be16(1);
6500         fan_table.temp_resp_lim = cpu_to_be16(5);
6501         reference_clock = amdgpu_asic_get_xclk(adev);
6502
6503         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6504                                                 reference_clock) / 1600);
6505         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6506
6507         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6508         fan_table.temp_src = (uint8_t)tmp;
6509
6510         ret = amdgpu_si_copy_bytes_to_smc(adev,
6511                                           si_pi->fan_table_start,
6512                                           (u8 *)(&fan_table),
6513                                           sizeof(fan_table),
6514                                           si_pi->sram_end);
6515
6516         if (ret) {
6517                 DRM_ERROR("Failed to load fan table to the SMC.");
6518                 adev->pm.dpm.fan.ucode_fan_control = false;
6519         }
6520
6521         return ret;
6522 }
6523
6524 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6525 {
6526         struct si_power_info *si_pi = si_get_pi(adev);
6527         PPSMC_Result ret;
6528
6529         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6530         if (ret == PPSMC_Result_OK) {
6531                 si_pi->fan_is_controlled_by_smc = true;
6532                 return 0;
6533         } else {
6534                 return -EINVAL;
6535         }
6536 }
6537
6538 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6539 {
6540         struct si_power_info *si_pi = si_get_pi(adev);
6541         PPSMC_Result ret;
6542
6543         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6544
6545         if (ret == PPSMC_Result_OK) {
6546                 si_pi->fan_is_controlled_by_smc = false;
6547                 return 0;
6548         } else {
6549                 return -EINVAL;
6550         }
6551 }
6552
6553 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6554                                       u32 *speed)
6555 {
6556         u32 duty, duty100;
6557         u64 tmp64;
6558
6559         if (adev->pm.no_fan)
6560                 return -ENOENT;
6561
6562         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6563         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6564
6565         if (duty100 == 0)
6566                 return -EINVAL;
6567
6568         tmp64 = (u64)duty * 100;
6569         do_div(tmp64, duty100);
6570         *speed = (u32)tmp64;
6571
6572         if (*speed > 100)
6573                 *speed = 100;
6574
6575         return 0;
6576 }
6577
6578 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6579                                       u32 speed)
6580 {
6581         struct si_power_info *si_pi = si_get_pi(adev);
6582         u32 tmp;
6583         u32 duty, duty100;
6584         u64 tmp64;
6585
6586         if (adev->pm.no_fan)
6587                 return -ENOENT;
6588
6589         if (si_pi->fan_is_controlled_by_smc)
6590                 return -EINVAL;
6591
6592         if (speed > 100)
6593                 return -EINVAL;
6594
6595         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6596
6597         if (duty100 == 0)
6598                 return -EINVAL;
6599
6600         tmp64 = (u64)speed * duty100;
6601         do_div(tmp64, 100);
6602         duty = (u32)tmp64;
6603
6604         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6605         tmp |= FDO_STATIC_DUTY(duty);
6606         WREG32(CG_FDO_CTRL0, tmp);
6607
6608         return 0;
6609 }
6610
6611 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6612 {
6613         if (mode) {
6614                 /* stop auto-manage */
6615                 if (adev->pm.dpm.fan.ucode_fan_control)
6616                         si_fan_ctrl_stop_smc_fan_control(adev);
6617                 si_fan_ctrl_set_static_mode(adev, mode);
6618         } else {
6619                 /* restart auto-manage */
6620                 if (adev->pm.dpm.fan.ucode_fan_control)
6621                         si_thermal_start_smc_fan_control(adev);
6622                 else
6623                         si_fan_ctrl_set_default_mode(adev);
6624         }
6625 }
6626
6627 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6628 {
6629         struct si_power_info *si_pi = si_get_pi(adev);
6630         u32 tmp;
6631
6632         if (si_pi->fan_is_controlled_by_smc)
6633                 return 0;
6634
6635         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6636         return (tmp >> FDO_PWM_MODE_SHIFT);
6637 }
6638
6639 #if 0
6640 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6641                                          u32 *speed)
6642 {
6643         u32 tach_period;
6644         u32 xclk = amdgpu_asic_get_xclk(adev);
6645
6646         if (adev->pm.no_fan)
6647                 return -ENOENT;
6648
6649         if (adev->pm.fan_pulses_per_revolution == 0)
6650                 return -ENOENT;
6651
6652         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6653         if (tach_period == 0)
6654                 return -ENOENT;
6655
6656         *speed = 60 * xclk * 10000 / tach_period;
6657
6658         return 0;
6659 }
6660
6661 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6662                                          u32 speed)
6663 {
6664         u32 tach_period, tmp;
6665         u32 xclk = amdgpu_asic_get_xclk(adev);
6666
6667         if (adev->pm.no_fan)
6668                 return -ENOENT;
6669
6670         if (adev->pm.fan_pulses_per_revolution == 0)
6671                 return -ENOENT;
6672
6673         if ((speed < adev->pm.fan_min_rpm) ||
6674             (speed > adev->pm.fan_max_rpm))
6675                 return -EINVAL;
6676
6677         if (adev->pm.dpm.fan.ucode_fan_control)
6678                 si_fan_ctrl_stop_smc_fan_control(adev);
6679
6680         tach_period = 60 * xclk * 10000 / (8 * speed);
6681         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6682         tmp |= TARGET_PERIOD(tach_period);
6683         WREG32(CG_TACH_CTRL, tmp);
6684
6685         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6686
6687         return 0;
6688 }
6689 #endif
6690
6691 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6692 {
6693         struct si_power_info *si_pi = si_get_pi(adev);
6694         u32 tmp;
6695
6696         if (!si_pi->fan_ctrl_is_in_default_mode) {
6697                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6698                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6699                 WREG32(CG_FDO_CTRL2, tmp);
6700
6701                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6702                 tmp |= TMIN(si_pi->t_min);
6703                 WREG32(CG_FDO_CTRL2, tmp);
6704                 si_pi->fan_ctrl_is_in_default_mode = true;
6705         }
6706 }
6707
6708 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6709 {
6710         if (adev->pm.dpm.fan.ucode_fan_control) {
6711                 si_fan_ctrl_start_smc_fan_control(adev);
6712                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6713         }
6714 }
6715
6716 static void si_thermal_initialize(struct amdgpu_device *adev)
6717 {
6718         u32 tmp;
6719
6720         if (adev->pm.fan_pulses_per_revolution) {
6721                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6722                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6723                 WREG32(CG_TACH_CTRL, tmp);
6724         }
6725
6726         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6727         tmp |= TACH_PWM_RESP_RATE(0x28);
6728         WREG32(CG_FDO_CTRL2, tmp);
6729 }
6730
6731 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6732 {
6733         int ret;
6734
6735         si_thermal_initialize(adev);
6736         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6737         if (ret)
6738                 return ret;
6739         ret = si_thermal_enable_alert(adev, true);
6740         if (ret)
6741                 return ret;
6742         if (adev->pm.dpm.fan.ucode_fan_control) {
6743                 ret = si_halt_smc(adev);
6744                 if (ret)
6745                         return ret;
6746                 ret = si_thermal_setup_fan_table(adev);
6747                 if (ret)
6748                         return ret;
6749                 ret = si_resume_smc(adev);
6750                 if (ret)
6751                         return ret;
6752                 si_thermal_start_smc_fan_control(adev);
6753         }
6754
6755         return 0;
6756 }
6757
6758 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6759 {
6760         if (!adev->pm.no_fan) {
6761                 si_fan_ctrl_set_default_mode(adev);
6762                 si_fan_ctrl_stop_smc_fan_control(adev);
6763         }
6764 }
6765
6766 static int si_dpm_enable(struct amdgpu_device *adev)
6767 {
6768         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6769         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6770         struct si_power_info *si_pi = si_get_pi(adev);
6771         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6772         int ret;
6773
6774         if (amdgpu_si_is_smc_running(adev))
6775                 return -EINVAL;
6776         if (pi->voltage_control || si_pi->voltage_control_svi2)
6777                 si_enable_voltage_control(adev, true);
6778         if (pi->mvdd_control)
6779                 si_get_mvdd_configuration(adev);
6780         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6781                 ret = si_construct_voltage_tables(adev);
6782                 if (ret) {
6783                         DRM_ERROR("si_construct_voltage_tables failed\n");
6784                         return ret;
6785                 }
6786         }
6787         if (eg_pi->dynamic_ac_timing) {
6788                 ret = si_initialize_mc_reg_table(adev);
6789                 if (ret)
6790                         eg_pi->dynamic_ac_timing = false;
6791         }
6792         if (pi->dynamic_ss)
6793                 si_enable_spread_spectrum(adev, true);
6794         if (pi->thermal_protection)
6795                 si_enable_thermal_protection(adev, true);
6796         si_setup_bsp(adev);
6797         si_program_git(adev);
6798         si_program_tp(adev);
6799         si_program_tpp(adev);
6800         si_program_sstp(adev);
6801         si_enable_display_gap(adev);
6802         si_program_vc(adev);
6803         ret = si_upload_firmware(adev);
6804         if (ret) {
6805                 DRM_ERROR("si_upload_firmware failed\n");
6806                 return ret;
6807         }
6808         ret = si_process_firmware_header(adev);
6809         if (ret) {
6810                 DRM_ERROR("si_process_firmware_header failed\n");
6811                 return ret;
6812         }
6813         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6814         if (ret) {
6815                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6816                 return ret;
6817         }
6818         ret = si_init_smc_table(adev);
6819         if (ret) {
6820                 DRM_ERROR("si_init_smc_table failed\n");
6821                 return ret;
6822         }
6823         ret = si_init_smc_spll_table(adev);
6824         if (ret) {
6825                 DRM_ERROR("si_init_smc_spll_table failed\n");
6826                 return ret;
6827         }
6828         ret = si_init_arb_table_index(adev);
6829         if (ret) {
6830                 DRM_ERROR("si_init_arb_table_index failed\n");
6831                 return ret;
6832         }
6833         if (eg_pi->dynamic_ac_timing) {
6834                 ret = si_populate_mc_reg_table(adev, boot_ps);
6835                 if (ret) {
6836                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6837                         return ret;
6838                 }
6839         }
6840         ret = si_initialize_smc_cac_tables(adev);
6841         if (ret) {
6842                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6843                 return ret;
6844         }
6845         ret = si_initialize_hardware_cac_manager(adev);
6846         if (ret) {
6847                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6848                 return ret;
6849         }
6850         ret = si_initialize_smc_dte_tables(adev);
6851         if (ret) {
6852                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6853                 return ret;
6854         }
6855         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6856         if (ret) {
6857                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6858                 return ret;
6859         }
6860         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6861         if (ret) {
6862                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6863                 return ret;
6864         }
6865         si_program_response_times(adev);
6866         si_program_ds_registers(adev);
6867         si_dpm_start_smc(adev);
6868         ret = si_notify_smc_display_change(adev, false);
6869         if (ret) {
6870                 DRM_ERROR("si_notify_smc_display_change failed\n");
6871                 return ret;
6872         }
6873         si_enable_sclk_control(adev, true);
6874         si_start_dpm(adev);
6875
6876         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6877         si_thermal_start_thermal_controller(adev);
6878
6879         return 0;
6880 }
6881
6882 static int si_set_temperature_range(struct amdgpu_device *adev)
6883 {
6884         int ret;
6885
6886         ret = si_thermal_enable_alert(adev, false);
6887         if (ret)
6888                 return ret;
6889         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6890         if (ret)
6891                 return ret;
6892         ret = si_thermal_enable_alert(adev, true);
6893         if (ret)
6894                 return ret;
6895
6896         return ret;
6897 }
6898
6899 static void si_dpm_disable(struct amdgpu_device *adev)
6900 {
6901         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6902         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6903
6904         if (!amdgpu_si_is_smc_running(adev))
6905                 return;
6906         si_thermal_stop_thermal_controller(adev);
6907         si_disable_ulv(adev);
6908         si_clear_vc(adev);
6909         if (pi->thermal_protection)
6910                 si_enable_thermal_protection(adev, false);
6911         si_enable_power_containment(adev, boot_ps, false);
6912         si_enable_smc_cac(adev, boot_ps, false);
6913         si_enable_spread_spectrum(adev, false);
6914         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6915         si_stop_dpm(adev);
6916         si_reset_to_default(adev);
6917         si_dpm_stop_smc(adev);
6918         si_force_switch_to_arb_f0(adev);
6919
6920         ni_update_current_ps(adev, boot_ps);
6921 }
6922
6923 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6924 {
6925         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6926         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6927         struct amdgpu_ps *new_ps = &requested_ps;
6928
6929         ni_update_requested_ps(adev, new_ps);
6930         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6931
6932         return 0;
6933 }
6934
6935 static int si_power_control_set_level(struct amdgpu_device *adev)
6936 {
6937         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6938         int ret;
6939
6940         ret = si_restrict_performance_levels_before_switch(adev);
6941         if (ret)
6942                 return ret;
6943         ret = si_halt_smc(adev);
6944         if (ret)
6945                 return ret;
6946         ret = si_populate_smc_tdp_limits(adev, new_ps);
6947         if (ret)
6948                 return ret;
6949         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6950         if (ret)
6951                 return ret;
6952         ret = si_resume_smc(adev);
6953         if (ret)
6954                 return ret;
6955         ret = si_set_sw_state(adev);
6956         if (ret)
6957                 return ret;
6958         return 0;
6959 }
6960
6961 static int si_dpm_set_power_state(struct amdgpu_device *adev)
6962 {
6963         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6964         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6965         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6966         int ret;
6967
6968         ret = si_disable_ulv(adev);
6969         if (ret) {
6970                 DRM_ERROR("si_disable_ulv failed\n");
6971                 return ret;
6972         }
6973         ret = si_restrict_performance_levels_before_switch(adev);
6974         if (ret) {
6975                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6976                 return ret;
6977         }
6978         if (eg_pi->pcie_performance_request)
6979                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
6980         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
6981         ret = si_enable_power_containment(adev, new_ps, false);
6982         if (ret) {
6983                 DRM_ERROR("si_enable_power_containment failed\n");
6984                 return ret;
6985         }
6986         ret = si_enable_smc_cac(adev, new_ps, false);
6987         if (ret) {
6988                 DRM_ERROR("si_enable_smc_cac failed\n");
6989                 return ret;
6990         }
6991         ret = si_halt_smc(adev);
6992         if (ret) {
6993                 DRM_ERROR("si_halt_smc failed\n");
6994                 return ret;
6995         }
6996         ret = si_upload_sw_state(adev, new_ps);
6997         if (ret) {
6998                 DRM_ERROR("si_upload_sw_state failed\n");
6999                 return ret;
7000         }
7001         ret = si_upload_smc_data(adev);
7002         if (ret) {
7003                 DRM_ERROR("si_upload_smc_data failed\n");
7004                 return ret;
7005         }
7006         ret = si_upload_ulv_state(adev);
7007         if (ret) {
7008                 DRM_ERROR("si_upload_ulv_state failed\n");
7009                 return ret;
7010         }
7011         if (eg_pi->dynamic_ac_timing) {
7012                 ret = si_upload_mc_reg_table(adev, new_ps);
7013                 if (ret) {
7014                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7015                         return ret;
7016                 }
7017         }
7018         ret = si_program_memory_timing_parameters(adev, new_ps);
7019         if (ret) {
7020                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7021                 return ret;
7022         }
7023         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7024
7025         ret = si_resume_smc(adev);
7026         if (ret) {
7027                 DRM_ERROR("si_resume_smc failed\n");
7028                 return ret;
7029         }
7030         ret = si_set_sw_state(adev);
7031         if (ret) {
7032                 DRM_ERROR("si_set_sw_state failed\n");
7033                 return ret;
7034         }
7035         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7036         if (eg_pi->pcie_performance_request)
7037                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7038         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7039         if (ret) {
7040                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7041                 return ret;
7042         }
7043         ret = si_enable_smc_cac(adev, new_ps, true);
7044         if (ret) {
7045                 DRM_ERROR("si_enable_smc_cac failed\n");
7046                 return ret;
7047         }
7048         ret = si_enable_power_containment(adev, new_ps, true);
7049         if (ret) {
7050                 DRM_ERROR("si_enable_power_containment failed\n");
7051                 return ret;
7052         }
7053
7054         ret = si_power_control_set_level(adev);
7055         if (ret) {
7056                 DRM_ERROR("si_power_control_set_level failed\n");
7057                 return ret;
7058         }
7059
7060         return 0;
7061 }
7062
7063 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7064 {
7065         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7066         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7067
7068         ni_update_current_ps(adev, new_ps);
7069 }
7070
7071 #if 0
7072 void si_dpm_reset_asic(struct amdgpu_device *adev)
7073 {
7074         si_restrict_performance_levels_before_switch(adev);
7075         si_disable_ulv(adev);
7076         si_set_boot_state(adev);
7077 }
7078 #endif
7079
7080 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7081 {
7082         si_program_display_gap(adev);
7083 }
7084
7085
7086 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7087                                           struct amdgpu_ps *rps,
7088                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7089                                           u8 table_rev)
7090 {
7091         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7092         rps->class = le16_to_cpu(non_clock_info->usClassification);
7093         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7094
7095         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7096                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7097                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7098         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7099                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7100                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7101         } else {
7102                 rps->vclk = 0;
7103                 rps->dclk = 0;
7104         }
7105
7106         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7107                 adev->pm.dpm.boot_ps = rps;
7108         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7109                 adev->pm.dpm.uvd_ps = rps;
7110 }
7111
7112 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7113                                       struct amdgpu_ps *rps, int index,
7114                                       union pplib_clock_info *clock_info)
7115 {
7116         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7117         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7118         struct si_power_info *si_pi = si_get_pi(adev);
7119         struct  si_ps *ps = si_get_ps(rps);
7120         u16 leakage_voltage;
7121         struct rv7xx_pl *pl = &ps->performance_levels[index];
7122         int ret;
7123
7124         ps->performance_level_count = index + 1;
7125
7126         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7127         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7128         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7129         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7130
7131         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7132         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7133         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7134         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7135                                                    si_pi->sys_pcie_mask,
7136                                                    si_pi->boot_pcie_gen,
7137                                                    clock_info->si.ucPCIEGen);
7138
7139         /* patch up vddc if necessary */
7140         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7141                                                         &leakage_voltage);
7142         if (ret == 0)
7143                 pl->vddc = leakage_voltage;
7144
7145         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7146                 pi->acpi_vddc = pl->vddc;
7147                 eg_pi->acpi_vddci = pl->vddci;
7148                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7149         }
7150
7151         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7152             index == 0) {
7153                 /* XXX disable for A0 tahiti */
7154                 si_pi->ulv.supported = false;
7155                 si_pi->ulv.pl = *pl;
7156                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7157                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7158                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7159                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7160         }
7161
7162         if (pi->min_vddc_in_table > pl->vddc)
7163                 pi->min_vddc_in_table = pl->vddc;
7164
7165         if (pi->max_vddc_in_table < pl->vddc)
7166                 pi->max_vddc_in_table = pl->vddc;
7167
7168         /* patch up boot state */
7169         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7170                 u16 vddc, vddci, mvdd;
7171                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7172                 pl->mclk = adev->clock.default_mclk;
7173                 pl->sclk = adev->clock.default_sclk;
7174                 pl->vddc = vddc;
7175                 pl->vddci = vddci;
7176                 si_pi->mvdd_bootup_value = mvdd;
7177         }
7178
7179         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7180             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7181                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7182                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7183                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7184                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7185         }
7186 }
7187
7188 union pplib_power_state {
7189         struct _ATOM_PPLIB_STATE v1;
7190         struct _ATOM_PPLIB_STATE_V2 v2;
7191 };
7192
7193 static int si_parse_power_table(struct amdgpu_device *adev)
7194 {
7195         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7196         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7197         union pplib_power_state *power_state;
7198         int i, j, k, non_clock_array_index, clock_array_index;
7199         union pplib_clock_info *clock_info;
7200         struct _StateArray *state_array;
7201         struct _ClockInfoArray *clock_info_array;
7202         struct _NonClockInfoArray *non_clock_info_array;
7203         union power_info *power_info;
7204         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7205         u16 data_offset;
7206         u8 frev, crev;
7207         u8 *power_state_offset;
7208         struct  si_ps *ps;
7209
7210         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7211                                    &frev, &crev, &data_offset))
7212                 return -EINVAL;
7213         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7214
7215         amdgpu_add_thermal_controller(adev);
7216
7217         state_array = (struct _StateArray *)
7218                 (mode_info->atom_context->bios + data_offset +
7219                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7220         clock_info_array = (struct _ClockInfoArray *)
7221                 (mode_info->atom_context->bios + data_offset +
7222                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7223         non_clock_info_array = (struct _NonClockInfoArray *)
7224                 (mode_info->atom_context->bios + data_offset +
7225                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7226
7227         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7228                                   state_array->ucNumEntries, GFP_KERNEL);
7229         if (!adev->pm.dpm.ps)
7230                 return -ENOMEM;
7231         power_state_offset = (u8 *)state_array->states;
7232         for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) {
7233                 u8 *idx;
7234                 power_state = (union pplib_power_state *)power_state_offset;
7235                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7236                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7237                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7238                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7239                 if (ps == NULL)
7240                         return -ENOMEM;
7241                 adev->pm.dpm.ps[i].ps_priv = ps;
7242                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7243                                               non_clock_info,
7244                                               non_clock_info_array->ucEntrySize);
7245                 k = 0;
7246                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7247                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7248                         clock_array_index = idx[j];
7249                         if (clock_array_index >= clock_info_array->ucNumEntries)
7250                                 continue;
7251                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7252                                 break;
7253                         clock_info = (union pplib_clock_info *)
7254                                 ((u8 *)&clock_info_array->clockInfo[0] +
7255                                  (clock_array_index * clock_info_array->ucEntrySize));
7256                         si_parse_pplib_clock_info(adev,
7257                                                   &adev->pm.dpm.ps[i], k,
7258                                                   clock_info);
7259                         k++;
7260                 }
7261                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7262                 adev->pm.dpm.num_ps++;
7263         }
7264
7265         /* fill in the vce power states */
7266         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7267                 u32 sclk, mclk;
7268                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7269                 clock_info = (union pplib_clock_info *)
7270                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7271                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7272                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7273                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7274                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7275                 adev->pm.dpm.vce_states[i].sclk = sclk;
7276                 adev->pm.dpm.vce_states[i].mclk = mclk;
7277         }
7278
7279         return 0;
7280 }
7281
7282 static int si_dpm_init(struct amdgpu_device *adev)
7283 {
7284         struct rv7xx_power_info *pi;
7285         struct evergreen_power_info *eg_pi;
7286         struct ni_power_info *ni_pi;
7287         struct si_power_info *si_pi;
7288         struct atom_clock_dividers dividers;
7289         int ret;
7290
7291         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7292         if (si_pi == NULL)
7293                 return -ENOMEM;
7294         adev->pm.dpm.priv = si_pi;
7295         ni_pi = &si_pi->ni;
7296         eg_pi = &ni_pi->eg;
7297         pi = &eg_pi->rv7xx;
7298
7299         si_pi->sys_pcie_mask =
7300                 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
7301                 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
7302         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7303         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7304
7305         si_set_max_cu_value(adev);
7306
7307         rv770_get_max_vddc(adev);
7308         si_get_leakage_vddc(adev);
7309         si_patch_dependency_tables_based_on_leakage(adev);
7310
7311         pi->acpi_vddc = 0;
7312         eg_pi->acpi_vddci = 0;
7313         pi->min_vddc_in_table = 0;
7314         pi->max_vddc_in_table = 0;
7315
7316         ret = amdgpu_get_platform_caps(adev);
7317         if (ret)
7318                 return ret;
7319
7320         ret = amdgpu_parse_extended_power_table(adev);
7321         if (ret)
7322                 return ret;
7323
7324         ret = si_parse_power_table(adev);
7325         if (ret)
7326                 return ret;
7327
7328         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7329                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7330         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7331                 amdgpu_free_extended_power_table(adev);
7332                 return -ENOMEM;
7333         }
7334         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7335         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7336         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7337         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7338         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7339         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7340         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7341         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7342         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7343
7344         if (adev->pm.dpm.voltage_response_time == 0)
7345                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7346         if (adev->pm.dpm.backbias_response_time == 0)
7347                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7348
7349         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7350                                              0, false, &dividers);
7351         if (ret)
7352                 pi->ref_div = dividers.ref_div + 1;
7353         else
7354                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7355
7356         eg_pi->smu_uvd_hs = false;
7357
7358         pi->mclk_strobe_mode_threshold = 40000;
7359         if (si_is_special_1gb_platform(adev))
7360                 pi->mclk_stutter_mode_threshold = 0;
7361         else
7362                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7363         pi->mclk_edc_enable_threshold = 40000;
7364         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7365
7366         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7367
7368         pi->voltage_control =
7369                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7370                                             VOLTAGE_OBJ_GPIO_LUT);
7371         if (!pi->voltage_control) {
7372                 si_pi->voltage_control_svi2 =
7373                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7374                                                     VOLTAGE_OBJ_SVID2);
7375                 if (si_pi->voltage_control_svi2)
7376                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7377                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7378         }
7379
7380         pi->mvdd_control =
7381                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7382                                             VOLTAGE_OBJ_GPIO_LUT);
7383
7384         eg_pi->vddci_control =
7385                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7386                                             VOLTAGE_OBJ_GPIO_LUT);
7387         if (!eg_pi->vddci_control)
7388                 si_pi->vddci_control_svi2 =
7389                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7390                                                     VOLTAGE_OBJ_SVID2);
7391
7392         si_pi->vddc_phase_shed_control =
7393                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7394                                             VOLTAGE_OBJ_PHASE_LUT);
7395
7396         rv770_get_engine_memory_ss(adev);
7397
7398         pi->asi = RV770_ASI_DFLT;
7399         pi->pasi = CYPRESS_HASI_DFLT;
7400         pi->vrc = SISLANDS_VRC_DFLT;
7401
7402         pi->gfx_clock_gating = true;
7403
7404         eg_pi->sclk_deep_sleep = true;
7405         si_pi->sclk_deep_sleep_above_low = false;
7406
7407         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7408                 pi->thermal_protection = true;
7409         else
7410                 pi->thermal_protection = false;
7411
7412         eg_pi->dynamic_ac_timing = true;
7413
7414         eg_pi->light_sleep = true;
7415 #if defined(CONFIG_ACPI)
7416         eg_pi->pcie_performance_request =
7417                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7418 #else
7419         eg_pi->pcie_performance_request = false;
7420 #endif
7421
7422         si_pi->sram_end = SMC_RAM_END;
7423
7424         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7425         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7426         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7427         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7428         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7429         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7430         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7431
7432         si_initialize_powertune_defaults(adev);
7433
7434         /* make sure dc limits are valid */
7435         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7436             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7437                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7438                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7439
7440         si_pi->fan_ctrl_is_in_default_mode = true;
7441
7442         return 0;
7443 }
7444
7445 static void si_dpm_fini(struct amdgpu_device *adev)
7446 {
7447         int i;
7448
7449         if (adev->pm.dpm.ps)
7450                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7451                         kfree(adev->pm.dpm.ps[i].ps_priv);
7452         kfree(adev->pm.dpm.ps);
7453         kfree(adev->pm.dpm.priv);
7454         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7455         amdgpu_free_extended_power_table(adev);
7456 }
7457
7458 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7459                                                     struct seq_file *m)
7460 {
7461         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7462         struct amdgpu_ps *rps = &eg_pi->current_rps;
7463         struct  si_ps *ps = si_get_ps(rps);
7464         struct rv7xx_pl *pl;
7465         u32 current_index =
7466                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7467                 CURRENT_STATE_INDEX_SHIFT;
7468
7469         if (current_index >= ps->performance_level_count) {
7470                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7471         } else {
7472                 pl = &ps->performance_levels[current_index];
7473                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7474                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7475                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7476         }
7477 }
7478
7479 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7480                                       struct amdgpu_irq_src *source,
7481                                       unsigned type,
7482                                       enum amdgpu_interrupt_state state)
7483 {
7484         u32 cg_thermal_int;
7485
7486         switch (type) {
7487         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7488                 switch (state) {
7489                 case AMDGPU_IRQ_STATE_DISABLE:
7490                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7491                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7492                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7493                         break;
7494                 case AMDGPU_IRQ_STATE_ENABLE:
7495                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7496                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7497                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7498                         break;
7499                 default:
7500                         break;
7501                 }
7502                 break;
7503
7504         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7505                 switch (state) {
7506                 case AMDGPU_IRQ_STATE_DISABLE:
7507                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7508                         cg_thermal_int |= THERM_INT_MASK_LOW;
7509                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7510                         break;
7511                 case AMDGPU_IRQ_STATE_ENABLE:
7512                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7513                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7514                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7515                         break;
7516                 default:
7517                         break;
7518                 }
7519                 break;
7520
7521         default:
7522                 break;
7523         }
7524         return 0;
7525 }
7526
7527 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7528                                     struct amdgpu_irq_src *source,
7529                                     struct amdgpu_iv_entry *entry)
7530 {
7531         bool queue_thermal = false;
7532
7533         if (entry == NULL)
7534                 return -EINVAL;
7535
7536         switch (entry->src_id) {
7537         case 230: /* thermal low to high */
7538                 DRM_DEBUG("IH: thermal low to high\n");
7539                 adev->pm.dpm.thermal.high_to_low = false;
7540                 queue_thermal = true;
7541                 break;
7542         case 231: /* thermal high to low */
7543                 DRM_DEBUG("IH: thermal high to low\n");
7544                 adev->pm.dpm.thermal.high_to_low = true;
7545                 queue_thermal = true;
7546                 break;
7547         default:
7548                 break;
7549         }
7550
7551         if (queue_thermal)
7552                 schedule_work(&adev->pm.dpm.thermal.work);
7553
7554         return 0;
7555 }
7556
7557 static int si_dpm_late_init(void *handle)
7558 {
7559         int ret;
7560         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7561
7562         if (!amdgpu_dpm)
7563                 return 0;
7564
7565         /* init the sysfs and debugfs files late */
7566         ret = amdgpu_pm_sysfs_init(adev);
7567         if (ret)
7568                 return ret;
7569
7570         ret = si_set_temperature_range(adev);
7571         if (ret)
7572                 return ret;
7573 #if 0 //TODO ?
7574         si_dpm_powergate_uvd(adev, true);
7575 #endif
7576         return 0;
7577 }
7578
7579 /**
7580  * si_dpm_init_microcode - load ucode images from disk
7581  *
7582  * @adev: amdgpu_device pointer
7583  *
7584  * Use the firmware interface to load the ucode images into
7585  * the driver (not loaded into hw).
7586  * Returns 0 on success, error on failure.
7587  */
7588 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7589 {
7590         const char *chip_name;
7591         char fw_name[30];
7592         int err;
7593
7594         DRM_DEBUG("\n");
7595         switch (adev->asic_type) {
7596         case CHIP_TAHITI:
7597                 chip_name = "tahiti";
7598                 break;
7599         case CHIP_PITCAIRN:
7600                 if ((adev->pdev->revision == 0x81) &&
7601                     ((adev->pdev->device == 0x6810) ||
7602                     (adev->pdev->device == 0x6811)))
7603                         chip_name = "pitcairn_k";
7604                 else
7605                         chip_name = "pitcairn";
7606                 break;
7607         case CHIP_VERDE:
7608                 if (((adev->pdev->device == 0x6820) &&
7609                         ((adev->pdev->revision == 0x81) ||
7610                         (adev->pdev->revision == 0x83))) ||
7611                     ((adev->pdev->device == 0x6821) &&
7612                         ((adev->pdev->revision == 0x83) ||
7613                         (adev->pdev->revision == 0x87))) ||
7614                     ((adev->pdev->revision == 0x87) &&
7615                         ((adev->pdev->device == 0x6823) ||
7616                         (adev->pdev->device == 0x682b))))
7617                         chip_name = "verde_k";
7618                 else
7619                         chip_name = "verde";
7620                 break;
7621         case CHIP_OLAND:
7622                 if (((adev->pdev->revision == 0x81) &&
7623                         ((adev->pdev->device == 0x6600) ||
7624                         (adev->pdev->device == 0x6604) ||
7625                         (adev->pdev->device == 0x6605) ||
7626                         (adev->pdev->device == 0x6610))) ||
7627                     ((adev->pdev->revision == 0x83) &&
7628                         (adev->pdev->device == 0x6610)))
7629                         chip_name = "oland_k";
7630                 else
7631                         chip_name = "oland";
7632                 break;
7633         case CHIP_HAINAN:
7634                 if (((adev->pdev->revision == 0x81) &&
7635                         (adev->pdev->device == 0x6660)) ||
7636                     ((adev->pdev->revision == 0x83) &&
7637                         ((adev->pdev->device == 0x6660) ||
7638                         (adev->pdev->device == 0x6663) ||
7639                         (adev->pdev->device == 0x6665) ||
7640                          (adev->pdev->device == 0x6667))))
7641                         chip_name = "hainan_k";
7642                 else if ((adev->pdev->revision == 0xc3) &&
7643                          (adev->pdev->device == 0x6665))
7644                         chip_name = "banks_k_2";
7645                 else
7646                         chip_name = "hainan";
7647                 break;
7648         default: BUG();
7649         }
7650
7651         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
7652         err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
7653         if (err)
7654                 goto out;
7655         err = amdgpu_ucode_validate(adev->pm.fw);
7656
7657 out:
7658         if (err) {
7659                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7660                           err, fw_name);
7661                 release_firmware(adev->pm.fw);
7662                 adev->pm.fw = NULL;
7663         }
7664         return err;
7665
7666 }
7667
7668 static int si_dpm_sw_init(void *handle)
7669 {
7670         int ret;
7671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7672
7673         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7674         if (ret)
7675                 return ret;
7676
7677         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7678         if (ret)
7679                 return ret;
7680
7681         /* default to balanced state */
7682         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7683         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7684         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7685         adev->pm.default_sclk = adev->clock.default_sclk;
7686         adev->pm.default_mclk = adev->clock.default_mclk;
7687         adev->pm.current_sclk = adev->clock.default_sclk;
7688         adev->pm.current_mclk = adev->clock.default_mclk;
7689         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7690
7691         if (amdgpu_dpm == 0)
7692                 return 0;
7693
7694         ret = si_dpm_init_microcode(adev);
7695         if (ret)
7696                 return ret;
7697
7698         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7699         mutex_lock(&adev->pm.mutex);
7700         ret = si_dpm_init(adev);
7701         if (ret)
7702                 goto dpm_failed;
7703         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7704         if (amdgpu_dpm == 1)
7705                 amdgpu_pm_print_power_states(adev);
7706         mutex_unlock(&adev->pm.mutex);
7707         DRM_INFO("amdgpu: dpm initialized\n");
7708
7709         return 0;
7710
7711 dpm_failed:
7712         si_dpm_fini(adev);
7713         mutex_unlock(&adev->pm.mutex);
7714         DRM_ERROR("amdgpu: dpm initialization failed\n");
7715         return ret;
7716 }
7717
7718 static int si_dpm_sw_fini(void *handle)
7719 {
7720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7721
7722         flush_work(&adev->pm.dpm.thermal.work);
7723
7724         mutex_lock(&adev->pm.mutex);
7725         amdgpu_pm_sysfs_fini(adev);
7726         si_dpm_fini(adev);
7727         mutex_unlock(&adev->pm.mutex);
7728
7729         return 0;
7730 }
7731
7732 static int si_dpm_hw_init(void *handle)
7733 {
7734         int ret;
7735
7736         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7737
7738         if (!amdgpu_dpm)
7739                 return 0;
7740
7741         mutex_lock(&adev->pm.mutex);
7742         si_dpm_setup_asic(adev);
7743         ret = si_dpm_enable(adev);
7744         if (ret)
7745                 adev->pm.dpm_enabled = false;
7746         else
7747                 adev->pm.dpm_enabled = true;
7748         mutex_unlock(&adev->pm.mutex);
7749         amdgpu_pm_compute_clocks(adev);
7750         return ret;
7751 }
7752
7753 static int si_dpm_hw_fini(void *handle)
7754 {
7755         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7756
7757         if (adev->pm.dpm_enabled) {
7758                 mutex_lock(&adev->pm.mutex);
7759                 si_dpm_disable(adev);
7760                 mutex_unlock(&adev->pm.mutex);
7761         }
7762
7763         return 0;
7764 }
7765
7766 static int si_dpm_suspend(void *handle)
7767 {
7768         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7769
7770         if (adev->pm.dpm_enabled) {
7771                 mutex_lock(&adev->pm.mutex);
7772                 /* disable dpm */
7773                 si_dpm_disable(adev);
7774                 /* reset the power state */
7775                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7776                 mutex_unlock(&adev->pm.mutex);
7777         }
7778         return 0;
7779 }
7780
7781 static int si_dpm_resume(void *handle)
7782 {
7783         int ret;
7784         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7785
7786         if (adev->pm.dpm_enabled) {
7787                 /* asic init will reset to the boot state */
7788                 mutex_lock(&adev->pm.mutex);
7789                 si_dpm_setup_asic(adev);
7790                 ret = si_dpm_enable(adev);
7791                 if (ret)
7792                         adev->pm.dpm_enabled = false;
7793                 else
7794                         adev->pm.dpm_enabled = true;
7795                 mutex_unlock(&adev->pm.mutex);
7796                 if (adev->pm.dpm_enabled)
7797                         amdgpu_pm_compute_clocks(adev);
7798         }
7799         return 0;
7800 }
7801
7802 static bool si_dpm_is_idle(void *handle)
7803 {
7804         /* XXX */
7805         return true;
7806 }
7807
7808 static int si_dpm_wait_for_idle(void *handle)
7809 {
7810         /* XXX */
7811         return 0;
7812 }
7813
7814 static int si_dpm_soft_reset(void *handle)
7815 {
7816         return 0;
7817 }
7818
7819 static int si_dpm_set_clockgating_state(void *handle,
7820                                         enum amd_clockgating_state state)
7821 {
7822         return 0;
7823 }
7824
7825 static int si_dpm_set_powergating_state(void *handle,
7826                                         enum amd_powergating_state state)
7827 {
7828         return 0;
7829 }
7830
7831 /* get temperature in millidegrees */
7832 static int si_dpm_get_temp(struct amdgpu_device *adev)
7833 {
7834         u32 temp;
7835         int actual_temp = 0;
7836
7837         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7838                 CTF_TEMP_SHIFT;
7839
7840         if (temp & 0x200)
7841                 actual_temp = 255;
7842         else
7843                 actual_temp = temp & 0x1ff;
7844
7845         actual_temp = (actual_temp * 1000);
7846
7847         return actual_temp;
7848 }
7849
7850 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7851 {
7852         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7853         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7854
7855         if (low)
7856                 return requested_state->performance_levels[0].sclk;
7857         else
7858                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7859 }
7860
7861 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7862 {
7863         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7864         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7865
7866         if (low)
7867                 return requested_state->performance_levels[0].mclk;
7868         else
7869                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7870 }
7871
7872 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7873                                      struct amdgpu_ps *rps)
7874 {
7875         struct  si_ps *ps = si_get_ps(rps);
7876         struct rv7xx_pl *pl;
7877         int i;
7878
7879         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7880         amdgpu_dpm_print_cap_info(rps->caps);
7881         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7882         for (i = 0; i < ps->performance_level_count; i++) {
7883                 pl = &ps->performance_levels[i];
7884                 if (adev->asic_type >= CHIP_TAHITI)
7885                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7886                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7887                 else
7888                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7889                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7890         }
7891         amdgpu_dpm_print_ps_status(adev, rps);
7892 }
7893
7894 static int si_dpm_early_init(void *handle)
7895 {
7896
7897         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7898
7899         si_dpm_set_dpm_funcs(adev);
7900         si_dpm_set_irq_funcs(adev);
7901         return 0;
7902 }
7903
7904 static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7905                                                 const struct rv7xx_pl *si_cpl2)
7906 {
7907         return ((si_cpl1->mclk == si_cpl2->mclk) &&
7908                   (si_cpl1->sclk == si_cpl2->sclk) &&
7909                   (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7910                   (si_cpl1->vddc == si_cpl2->vddc) &&
7911                   (si_cpl1->vddci == si_cpl2->vddci));
7912 }
7913
7914 static int si_check_state_equal(struct amdgpu_device *adev,
7915                                 struct amdgpu_ps *cps,
7916                                 struct amdgpu_ps *rps,
7917                                 bool *equal)
7918 {
7919         struct si_ps *si_cps;
7920         struct si_ps *si_rps;
7921         int i;
7922
7923         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7924                 return -EINVAL;
7925
7926         si_cps = si_get_ps(cps);
7927         si_rps = si_get_ps(rps);
7928
7929         if (si_cps == NULL) {
7930                 printk("si_cps is NULL\n");
7931                 *equal = false;
7932                 return 0;
7933         }
7934
7935         if (si_cps->performance_level_count != si_rps->performance_level_count) {
7936                 *equal = false;
7937                 return 0;
7938         }
7939
7940         for (i = 0; i < si_cps->performance_level_count; i++) {
7941                 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7942                                         &(si_rps->performance_levels[i]))) {
7943                         *equal = false;
7944                         return 0;
7945                 }
7946         }
7947
7948         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7949         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7950         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7951
7952         return 0;
7953 }
7954
7955 static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx,
7956                               void *value, int *size)
7957 {
7958         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7959         struct amdgpu_ps *rps = &eg_pi->current_rps;
7960         struct  si_ps *ps = si_get_ps(rps);
7961         uint32_t sclk, mclk;
7962         u32 pl_index =
7963                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7964                 CURRENT_STATE_INDEX_SHIFT;
7965
7966         /* size must be at least 4 bytes for all sensors */
7967         if (*size < 4)
7968                 return -EINVAL;
7969
7970         switch (idx) {
7971         case AMDGPU_PP_SENSOR_GFX_SCLK:
7972                 if (pl_index < ps->performance_level_count) {
7973                         sclk = ps->performance_levels[pl_index].sclk;
7974                         *((uint32_t *)value) = sclk;
7975                         *size = 4;
7976                         return 0;
7977                 }
7978                 return -EINVAL;
7979         case AMDGPU_PP_SENSOR_GFX_MCLK:
7980                 if (pl_index < ps->performance_level_count) {
7981                         mclk = ps->performance_levels[pl_index].mclk;
7982                         *((uint32_t *)value) = mclk;
7983                         *size = 4;
7984                         return 0;
7985                 }
7986                 return -EINVAL;
7987         case AMDGPU_PP_SENSOR_GPU_TEMP:
7988                 *((uint32_t *)value) = si_dpm_get_temp(adev);
7989                 *size = 4;
7990                 return 0;
7991         default:
7992                 return -EINVAL;
7993         }
7994 }
7995
7996 const struct amd_ip_funcs si_dpm_ip_funcs = {
7997         .name = "si_dpm",
7998         .early_init = si_dpm_early_init,
7999         .late_init = si_dpm_late_init,
8000         .sw_init = si_dpm_sw_init,
8001         .sw_fini = si_dpm_sw_fini,
8002         .hw_init = si_dpm_hw_init,
8003         .hw_fini = si_dpm_hw_fini,
8004         .suspend = si_dpm_suspend,
8005         .resume = si_dpm_resume,
8006         .is_idle = si_dpm_is_idle,
8007         .wait_for_idle = si_dpm_wait_for_idle,
8008         .soft_reset = si_dpm_soft_reset,
8009         .set_clockgating_state = si_dpm_set_clockgating_state,
8010         .set_powergating_state = si_dpm_set_powergating_state,
8011 };
8012
8013 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8014         .get_temperature = &si_dpm_get_temp,
8015         .pre_set_power_state = &si_dpm_pre_set_power_state,
8016         .set_power_state = &si_dpm_set_power_state,
8017         .post_set_power_state = &si_dpm_post_set_power_state,
8018         .display_configuration_changed = &si_dpm_display_configuration_changed,
8019         .get_sclk = &si_dpm_get_sclk,
8020         .get_mclk = &si_dpm_get_mclk,
8021         .print_power_state = &si_dpm_print_power_state,
8022         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8023         .force_performance_level = &si_dpm_force_performance_level,
8024         .vblank_too_short = &si_dpm_vblank_too_short,
8025         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8026         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8027         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8028         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8029         .check_state_equal = &si_check_state_equal,
8030         .get_vce_clock_state = amdgpu_get_vce_clock_state,
8031         .read_sensor = &si_dpm_read_sensor,
8032 };
8033
8034 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8035 {
8036         if (adev->pm.funcs == NULL)
8037                 adev->pm.funcs = &si_dpm_funcs;
8038 }
8039
8040 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8041         .set = si_dpm_set_interrupt_state,
8042         .process = si_dpm_process_interrupt,
8043 };
8044
8045 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8046 {
8047         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8048         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8049 }
8050