drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "uvd/uvd_7_0_offset.h"
  38 #include "gc/gc_9_0_offset.h"
  39 #include "gc/gc_9_0_sh_mask.h"
  40 #include "sdma0/sdma0_4_0_offset.h"
  41 #include "sdma1/sdma1_4_0_offset.h"
  42 #include "hdp/hdp_4_0_offset.h"
  43 #include "hdp/hdp_4_0_sh_mask.h"
  44 #include "smuio/smuio_9_0_offset.h"
  45 #include "smuio/smuio_9_0_sh_mask.h"
  46
  47 #include "soc15.h"
  48 #include "soc15_common.h"
  49 #include "gfx_v9_0.h"
  50 #include "gmc_v9_0.h"
  51 #include "gfxhub_v1_0.h"
  52 #include "mmhub_v1_0.h"
  53 #include "df_v1_7.h"
  54 #include "df_v3_6.h"
  55 #include "vega10_ih.h"
  56 #include "sdma_v4_0.h"
  57 #include "uvd_v7_0.h"
  58 #include "vce_v4_0.h"
  59 #include "vcn_v1_0.h"
  60 #include "dce_virtual.h"
  61 #include "mxgpu_ai.h"
  62
  63 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  64 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  65 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  66 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  67
  68 /*
  69  * Indirect registers accessor
  70  */
  71 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  72 {
  73         unsigned long flags, address, data;
  74         u32 r;
  75         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  76         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  77
  78         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  79         WREG32(address, reg);
  80         (void)RREG32(address);
  81         r = RREG32(data);
  82         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  83         return r;
  84 }
  85
  86 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  87 {
  88         unsigned long flags, address, data;
  89
  90         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  91         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  92
  93         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  94         WREG32(address, reg);
  95         (void)RREG32(address);
  96         WREG32(data, v);
  97         (void)RREG32(data);
  98         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  99 }
 100
 101 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 102 {
 103         unsigned long flags, address, data;
 104         u32 r;
 105
 106         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 107         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 108
 109         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 110         WREG32(address, ((reg) & 0x1ff));
 111         r = RREG32(data);
 112         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 113         return r;
 114 }
 115
 116 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 117 {
 118         unsigned long flags, address, data;
 119
 120         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 121         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 122
 123         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 124         WREG32(address, ((reg) & 0x1ff));
 125         WREG32(data, (v));
 126         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 127 }
 128
 129 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 130 {
 131         unsigned long flags, address, data;
 132         u32 r;
 133
 134         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 135         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 136
 137         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 138         WREG32(address, (reg));
 139         r = RREG32(data);
 140         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 141         return r;
 142 }
 143
 144 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 145 {
 146         unsigned long flags, address, data;
 147
 148         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 149         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 150
 151         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 152         WREG32(address, (reg));
 153         WREG32(data, (v));
 154         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 155 }
 156
 157 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 158 {
 159         unsigned long flags;
 160         u32 r;
 161
 162         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 163         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 164         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 165         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 166         return r;
 167 }
 168
 169 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 170 {
 171         unsigned long flags;
 172
 173         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 174         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 175         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 176         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 177 }
 178
 179 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 180 {
 181         unsigned long flags;
 182         u32 r;
 183
 184         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 185         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 186         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 187         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 188         return r;
 189 }
 190
 191 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 192 {
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 196         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 197         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 198         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 199 }
 200
 201 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 202 {
 203         return adev->nbio_funcs->get_memsize(adev);
 204 }
 205
 206 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 207 {
 208         u32 reference_clock = adev->clock.spll.reference_freq;
 209
 210         if (adev->asic_type == CHIP_RAVEN)
 211                 return reference_clock / 4;
 212
 213         return reference_clock;
 214 }
 215
 216
 217 void soc15_grbm_select(struct amdgpu_device *adev,
 218                      u32 me, u32 pipe, u32 queue, u32 vmid)
 219 {
 220         u32 grbm_gfx_cntl = 0;
 221         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 222         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 223         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 224         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 225
 226         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 227 }
 228
 229 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 230 {
 231         /* todo */
 232 }
 233
 234 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 235 {
 236         /* todo */
 237         return false;
 238 }
 239
 240 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 241                                      u8 *bios, u32 length_bytes)
 242 {
 243         u32 *dw_ptr;
 244         u32 i, length_dw;
 245
 246         if (bios == NULL)
 247                 return false;
 248         if (length_bytes == 0)
 249                 return false;
 250         /* APU vbios image is part of sbios image */
 251         if (adev->flags & AMD_IS_APU)
 252                 return false;
 253
 254         dw_ptr = (u32 *)bios;
 255         length_dw = ALIGN(length_bytes, 4) / 4;
 256
 257         /* set rom index to 0 */
 258         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 259         /* read out the rom data */
 260         for (i = 0; i < length_dw; i++)
 261                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 262
 263         return true;
 264 }
 265
 266 struct soc15_allowed_register_entry {
 267         uint32_t hwip;
 268         uint32_t inst;
 269         uint32_t seg;
 270         uint32_t reg_offset;
 271         bool grbm_indexed;
 272 };
 273
 274
 275 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 276         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 277         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 278         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 279         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 280         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 281         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 282         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 283         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 284         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 285         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 286         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 287         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 288         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 289         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 290         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 291         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 292         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 293         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 294         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 295 };
 296
 297 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 298                                          u32 sh_num, u32 reg_offset)
 299 {
 300         uint32_t val;
 301
 302         mutex_lock(&adev->grbm_idx_mutex);
 303         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 304                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 305
 306         val = RREG32(reg_offset);
 307
 308         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 309                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 310         mutex_unlock(&adev->grbm_idx_mutex);
 311         return val;
 312 }
 313
 314 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 315                                          bool indexed, u32 se_num,
 316                                          u32 sh_num, u32 reg_offset)
 317 {
 318         if (indexed) {
 319                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 320         } else {
 321                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 322                         return adev->gfx.config.gb_addr_config;
 323                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 324                         return adev->gfx.config.db_debug2;
 325                 return RREG32(reg_offset);
 326         }
 327 }
 328
 329 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 330                             u32 sh_num, u32 reg_offset, u32 *value)
 331 {
 332         uint32_t i;
 333         struct soc15_allowed_register_entry  *en;
 334
 335         *value = 0;
 336         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 337                 en = &soc15_allowed_read_registers[i];
 338                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 339                                         + en->reg_offset))
 340                         continue;
 341
 342                 *value = soc15_get_register_value(adev,
 343                                                   soc15_allowed_read_registers[i].grbm_indexed,
 344                                                   se_num, sh_num, reg_offset);
 345                 return 0;
 346         }
 347         return -EINVAL;
 348 }
 349
 350
 351 /**
 352  * soc15_program_register_sequence - program an array of registers.
 353  *
 354  * @adev: amdgpu_device pointer
 355  * @regs: pointer to the register array
 356  * @array_size: size of the register array
 357  *
 358  * Programs an array or registers with and and or masks.
 359  * This is a helper for setting golden registers.
 360  */
 361
 362 void soc15_program_register_sequence(struct amdgpu_device *adev,
 363                                              const struct soc15_reg_golden *regs,
 364                                              const u32 array_size)
 365 {
 366         const struct soc15_reg_golden *entry;
 367         u32 tmp, reg;
 368         int i;
 369
 370         for (i = 0; i < array_size; ++i) {
 371                 entry = &regs[i];
 372                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 373
 374                 if (entry->and_mask == 0xffffffff) {
 375                         tmp = entry->or_mask;
 376                 } else {
 377                         tmp = RREG32(reg);
 378                         tmp &= ~(entry->and_mask);
 379                         tmp |= entry->or_mask;
 380                 }
 381                 WREG32(reg, tmp);
 382         }
 383
 384 }
 385
 386
 387 static int soc15_asic_reset(struct amdgpu_device *adev)
 388 {
 389         u32 i;
 390
 391         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 392
 393         dev_info(adev->dev, "GPU reset\n");
 394
 395         /* disable BM */
 396         pci_clear_master(adev->pdev);
 397
 398         pci_save_state(adev->pdev);
 399
 400         psp_gpu_reset(adev);
 401
 402         pci_restore_state(adev->pdev);
 403
 404         /* wait for asic to come out of reset */
 405         for (i = 0; i < adev->usec_timeout; i++) {
 406                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 407
 408                 if (memsize != 0xffffffff)
 409                         break;
 410                 udelay(1);
 411         }
 412
 413         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 414
 415         return 0;
 416 }
 417
 418 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 419                         u32 cntl_reg, u32 status_reg)
 420 {
 421         return 0;
 422 }*/
 423
 424 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 425 {
 426         /*int r;
 427
 428         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 429         if (r)
 430                 return r;
 431
 432         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 433         */
 434         return 0;
 435 }
 436
 437 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 438 {
 439         /* todo */
 440
 441         return 0;
 442 }
 443
 444 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 445 {
 446         if (pci_is_root_bus(adev->pdev->bus))
 447                 return;
 448
 449         if (amdgpu_pcie_gen2 == 0)
 450                 return;
 451
 452         if (adev->flags & AMD_IS_APU)
 453                 return;
 454
 455         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 456                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 457                 return;
 458
 459         /* todo */
 460 }
 461
 462 static void soc15_program_aspm(struct amdgpu_device *adev)
 463 {
 464
 465         if (amdgpu_aspm == 0)
 466                 return;
 467
 468         /* todo */
 469 }
 470
 471 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 472                                            bool enable)
 473 {
 474         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 475         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 476 }
 477
 478 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 479 {
 480         .type = AMD_IP_BLOCK_TYPE_COMMON,
 481         .major = 2,
 482         .minor = 0,
 483         .rev = 0,
 484         .funcs = &soc15_common_ip_funcs,
 485 };
 486
 487 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 488 {
 489         /* Set IP register base before any HW register access */
 490         switch (adev->asic_type) {
 491         case CHIP_VEGA10:
 492         case CHIP_VEGA12:
 493         case CHIP_RAVEN:
 494                 vega10_reg_base_init(adev);
 495                 break;
 496         case CHIP_VEGA20:
 497                 vega20_reg_base_init(adev);
 498                 break;
 499         default:
 500                 return -EINVAL;
 501         }
 502
 503         if (adev->flags & AMD_IS_APU)
 504                 adev->nbio_funcs = &nbio_v7_0_funcs;
 505         else if (adev->asic_type == CHIP_VEGA20)
 506                 adev->nbio_funcs = &nbio_v7_0_funcs;
 507         else
 508                 adev->nbio_funcs = &nbio_v6_1_funcs;
 509
 510         if (adev->asic_type == CHIP_VEGA20)
 511                 adev->df_funcs = &df_v3_6_funcs;
 512         else
 513                 adev->df_funcs = &df_v1_7_funcs;
 514         adev->nbio_funcs->detect_hw_virt(adev);
 515
 516         if (amdgpu_sriov_vf(adev))
 517                 adev->virt.ops = &xgpu_ai_virt_ops;
 518
 519         switch (adev->asic_type) {
 520         case CHIP_VEGA10:
 521         case CHIP_VEGA12:
 522         case CHIP_VEGA20:
 523                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 524                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 525                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 526                 if (adev->asic_type != CHIP_VEGA20) {
 527                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 528                         if (!amdgpu_sriov_vf(adev))
 529                                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 530                 }
 531                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 532                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 533 #if defined(CONFIG_DRM_AMD_DC)
 534                 else if (amdgpu_device_has_dc_support(adev))
 535                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 536 #else
 537 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 538 #endif
 539                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 540                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 541                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 542                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 543                 break;
 544         case CHIP_RAVEN:
 545                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 546                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 547                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 548                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 549                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 550                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 551                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 552 #if defined(CONFIG_DRM_AMD_DC)
 553                 else if (amdgpu_device_has_dc_support(adev))
 554                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 555 #else
 556 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 557 #endif
 558                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 559                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 560                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 561                 break;
 562         default:
 563                 return -EINVAL;
 564         }
 565
 566         return 0;
 567 }
 568
 569 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 570 {
 571         return adev->nbio_funcs->get_rev_id(adev);
 572 }
 573
 574 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 575 {
 576         adev->nbio_funcs->hdp_flush(adev, ring);
 577 }
 578
 579 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 580                                  struct amdgpu_ring *ring)
 581 {
 582         if (!ring || !ring->funcs->emit_wreg)
 583                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 584         else
 585                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 586                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 587 }
 588
 589 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 590 {
 591         /* change this when we implement soft reset */
 592         return true;
 593 }
 594
 595 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 596 {
 597         .read_disabled_bios = &soc15_read_disabled_bios,
 598         .read_bios_from_rom = &soc15_read_bios_from_rom,
 599         .read_register = &soc15_read_register,
 600         .reset = &soc15_asic_reset,
 601         .set_vga_state = &soc15_vga_set_state,
 602         .get_xclk = &soc15_get_xclk,
 603         .set_uvd_clocks = &soc15_set_uvd_clocks,
 604         .set_vce_clocks = &soc15_set_vce_clocks,
 605         .get_config_memsize = &soc15_get_config_memsize,
 606         .flush_hdp = &soc15_flush_hdp,
 607         .invalidate_hdp = &soc15_invalidate_hdp,
 608         .need_full_reset = &soc15_need_full_reset,
 609 };
 610
 611 static int soc15_common_early_init(void *handle)
 612 {
 613         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 614
 615         adev->smc_rreg = NULL;
 616         adev->smc_wreg = NULL;
 617         adev->pcie_rreg = &soc15_pcie_rreg;
 618         adev->pcie_wreg = &soc15_pcie_wreg;
 619         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 620         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 621         adev->didt_rreg = &soc15_didt_rreg;
 622         adev->didt_wreg = &soc15_didt_wreg;
 623         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 624         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 625         adev->se_cac_rreg = &soc15_se_cac_rreg;
 626         adev->se_cac_wreg = &soc15_se_cac_wreg;
 627
 628         adev->asic_funcs = &soc15_asic_funcs;
 629
 630         adev->rev_id = soc15_get_rev_id(adev);
 631         adev->external_rev_id = 0xFF;
 632         switch (adev->asic_type) {
 633         case CHIP_VEGA10:
 634                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 635                         AMD_CG_SUPPORT_GFX_MGLS |
 636                         AMD_CG_SUPPORT_GFX_RLC_LS |
 637                         AMD_CG_SUPPORT_GFX_CP_LS |
 638                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 639                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 640                         AMD_CG_SUPPORT_GFX_CGCG |
 641                         AMD_CG_SUPPORT_GFX_CGLS |
 642                         AMD_CG_SUPPORT_BIF_MGCG |
 643                         AMD_CG_SUPPORT_BIF_LS |
 644                         AMD_CG_SUPPORT_HDP_LS |
 645                         AMD_CG_SUPPORT_DRM_MGCG |
 646                         AMD_CG_SUPPORT_DRM_LS |
 647                         AMD_CG_SUPPORT_ROM_MGCG |
 648                         AMD_CG_SUPPORT_DF_MGCG |
 649                         AMD_CG_SUPPORT_SDMA_MGCG |
 650                         AMD_CG_SUPPORT_SDMA_LS |
 651                         AMD_CG_SUPPORT_MC_MGCG |
 652                         AMD_CG_SUPPORT_MC_LS;
 653                 adev->pg_flags = 0;
 654                 adev->external_rev_id = 0x1;
 655                 break;
 656         case CHIP_VEGA12:
 657                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 658                         AMD_CG_SUPPORT_GFX_MGLS |
 659                         AMD_CG_SUPPORT_GFX_CGCG |
 660                         AMD_CG_SUPPORT_GFX_CGLS |
 661                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 662                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 663                         AMD_CG_SUPPORT_GFX_CP_LS |
 664                         AMD_CG_SUPPORT_MC_LS |
 665                         AMD_CG_SUPPORT_MC_MGCG |
 666                         AMD_CG_SUPPORT_SDMA_MGCG |
 667                         AMD_CG_SUPPORT_SDMA_LS |
 668                         AMD_CG_SUPPORT_BIF_MGCG |
 669                         AMD_CG_SUPPORT_BIF_LS |
 670                         AMD_CG_SUPPORT_HDP_MGCG |
 671                         AMD_CG_SUPPORT_HDP_LS |
 672                         AMD_CG_SUPPORT_ROM_MGCG |
 673                         AMD_CG_SUPPORT_VCE_MGCG |
 674                         AMD_CG_SUPPORT_UVD_MGCG;
 675                 adev->pg_flags = 0;
 676                 adev->external_rev_id = adev->rev_id + 0x14;
 677                 break;
 678         case CHIP_VEGA20:
 679                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 680                         AMD_CG_SUPPORT_GFX_MGLS |
 681                         AMD_CG_SUPPORT_GFX_CGCG |
 682                         AMD_CG_SUPPORT_GFX_CGLS |
 683                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 684                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 685                         AMD_CG_SUPPORT_GFX_CP_LS |
 686                         AMD_CG_SUPPORT_MC_LS |
 687                         AMD_CG_SUPPORT_MC_MGCG |
 688                         AMD_CG_SUPPORT_SDMA_MGCG |
 689                         AMD_CG_SUPPORT_SDMA_LS |
 690                         AMD_CG_SUPPORT_BIF_MGCG |
 691                         AMD_CG_SUPPORT_BIF_LS |
 692                         AMD_CG_SUPPORT_HDP_MGCG |
 693                         AMD_CG_SUPPORT_HDP_LS |
 694                         AMD_CG_SUPPORT_ROM_MGCG |
 695                         AMD_CG_SUPPORT_VCE_MGCG |
 696                         AMD_CG_SUPPORT_UVD_MGCG;
 697                 adev->pg_flags = 0;
 698                 adev->external_rev_id = adev->rev_id + 0x28;
 699                 break;
 700         case CHIP_RAVEN:
 701                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 702                         AMD_CG_SUPPORT_GFX_MGLS |
 703                         AMD_CG_SUPPORT_GFX_RLC_LS |
 704                         AMD_CG_SUPPORT_GFX_CP_LS |
 705                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 706                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 707                         AMD_CG_SUPPORT_GFX_CGCG |
 708                         AMD_CG_SUPPORT_GFX_CGLS |
 709                         AMD_CG_SUPPORT_BIF_MGCG |
 710                         AMD_CG_SUPPORT_BIF_LS |
 711                         AMD_CG_SUPPORT_HDP_MGCG |
 712                         AMD_CG_SUPPORT_HDP_LS |
 713                         AMD_CG_SUPPORT_DRM_MGCG |
 714                         AMD_CG_SUPPORT_DRM_LS |
 715                         AMD_CG_SUPPORT_ROM_MGCG |
 716                         AMD_CG_SUPPORT_MC_MGCG |
 717                         AMD_CG_SUPPORT_MC_LS |
 718                         AMD_CG_SUPPORT_SDMA_MGCG |
 719                         AMD_CG_SUPPORT_SDMA_LS |
 720                         AMD_CG_SUPPORT_VCN_MGCG;
 721
 722                 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 723
 724                 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
 725                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 726                                 AMD_PG_SUPPORT_CP |
 727                                 AMD_PG_SUPPORT_RLC_SMU_HS;
 728
 729                 adev->external_rev_id = 0x1;
 730                 break;
 731         default:
 732                 /* FIXME: not supported yet */
 733                 return -EINVAL;
 734         }
 735
 736         if (amdgpu_sriov_vf(adev)) {
 737                 amdgpu_virt_init_setting(adev);
 738                 xgpu_ai_mailbox_set_irq_funcs(adev);
 739         }
 740
 741         return 0;
 742 }
 743
 744 static int soc15_common_late_init(void *handle)
 745 {
 746         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 747
 748         if (amdgpu_sriov_vf(adev))
 749                 xgpu_ai_mailbox_get_irq(adev);
 750
 751         return 0;
 752 }
 753
 754 static int soc15_common_sw_init(void *handle)
 755 {
 756         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 757
 758         if (amdgpu_sriov_vf(adev))
 759                 xgpu_ai_mailbox_add_irq_id(adev);
 760
 761         return 0;
 762 }
 763
 764 static int soc15_common_sw_fini(void *handle)
 765 {
 766         return 0;
 767 }
 768
 769 static int soc15_common_hw_init(void *handle)
 770 {
 771         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 772
 773         /* enable pcie gen2/3 link */
 774         soc15_pcie_gen3_enable(adev);
 775         /* enable aspm */
 776         soc15_program_aspm(adev);
 777         /* setup nbio registers */
 778         adev->nbio_funcs->init_registers(adev);
 779         /* enable the doorbell aperture */
 780         soc15_enable_doorbell_aperture(adev, true);
 781
 782         return 0;
 783 }
 784
 785 static int soc15_common_hw_fini(void *handle)
 786 {
 787         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 788
 789         /* disable the doorbell aperture */
 790         soc15_enable_doorbell_aperture(adev, false);
 791         if (amdgpu_sriov_vf(adev))
 792                 xgpu_ai_mailbox_put_irq(adev);
 793
 794         return 0;
 795 }
 796
 797 static int soc15_common_suspend(void *handle)
 798 {
 799         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 800
 801         return soc15_common_hw_fini(adev);
 802 }
 803
 804 static int soc15_common_resume(void *handle)
 805 {
 806         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 807
 808         return soc15_common_hw_init(adev);
 809 }
 810
 811 static bool soc15_common_is_idle(void *handle)
 812 {
 813         return true;
 814 }
 815
 816 static int soc15_common_wait_for_idle(void *handle)
 817 {
 818         return 0;
 819 }
 820
 821 static int soc15_common_soft_reset(void *handle)
 822 {
 823         return 0;
 824 }
 825
 826 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 827 {
 828         uint32_t def, data;
 829
 830         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 831
 832         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 833                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 834         else
 835                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 836
 837         if (def != data)
 838                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 839 }
 840
 841 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 842 {
 843         uint32_t def, data;
 844
 845         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 846
 847         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 848                 data &= ~(0x01000000 |
 849                           0x02000000 |
 850                           0x04000000 |
 851                           0x08000000 |
 852                           0x10000000 |
 853                           0x20000000 |
 854                           0x40000000 |
 855                           0x80000000);
 856         else
 857                 data |= (0x01000000 |
 858                          0x02000000 |
 859                          0x04000000 |
 860                          0x08000000 |
 861                          0x10000000 |
 862                          0x20000000 |
 863                          0x40000000 |
 864                          0x80000000);
 865
 866         if (def != data)
 867                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 868 }
 869
 870 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 871 {
 872         uint32_t def, data;
 873
 874         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 875
 876         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 877                 data |= 1;
 878         else
 879                 data &= ~1;
 880
 881         if (def != data)
 882                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 883 }
 884
 885 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 886                                                        bool enable)
 887 {
 888         uint32_t def, data;
 889
 890         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 891
 892         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 893                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 894                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 895         else
 896                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 897                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 898
 899         if (def != data)
 900                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 901 }
 902
 903 static int soc15_common_set_clockgating_state(void *handle,
 904                                             enum amd_clockgating_state state)
 905 {
 906         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 907
 908         if (amdgpu_sriov_vf(adev))
 909                 return 0;
 910
 911         switch (adev->asic_type) {
 912         case CHIP_VEGA10:
 913         case CHIP_VEGA12:
 914         case CHIP_VEGA20:
 915                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 916                                 state == AMD_CG_STATE_GATE ? true : false);
 917                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 918                                 state == AMD_CG_STATE_GATE ? true : false);
 919                 soc15_update_hdp_light_sleep(adev,
 920                                 state == AMD_CG_STATE_GATE ? true : false);
 921                 soc15_update_drm_clock_gating(adev,
 922                                 state == AMD_CG_STATE_GATE ? true : false);
 923                 soc15_update_drm_light_sleep(adev,
 924                                 state == AMD_CG_STATE_GATE ? true : false);
 925                 soc15_update_rom_medium_grain_clock_gating(adev,
 926                                 state == AMD_CG_STATE_GATE ? true : false);
 927                 adev->df_funcs->update_medium_grain_clock_gating(adev,
 928                                 state == AMD_CG_STATE_GATE ? true : false);
 929                 break;
 930         case CHIP_RAVEN:
 931                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 932                                 state == AMD_CG_STATE_GATE ? true : false);
 933                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 934                                 state == AMD_CG_STATE_GATE ? true : false);
 935                 soc15_update_hdp_light_sleep(adev,
 936                                 state == AMD_CG_STATE_GATE ? true : false);
 937                 soc15_update_drm_clock_gating(adev,
 938                                 state == AMD_CG_STATE_GATE ? true : false);
 939                 soc15_update_drm_light_sleep(adev,
 940                                 state == AMD_CG_STATE_GATE ? true : false);
 941                 soc15_update_rom_medium_grain_clock_gating(adev,
 942                                 state == AMD_CG_STATE_GATE ? true : false);
 943                 break;
 944         default:
 945                 break;
 946         }
 947         return 0;
 948 }
 949
 950 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 951 {
 952         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 953         int data;
 954
 955         if (amdgpu_sriov_vf(adev))
 956                 *flags = 0;
 957
 958         adev->nbio_funcs->get_clockgating_state(adev, flags);
 959
 960         /* AMD_CG_SUPPORT_HDP_LS */
 961         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 962         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 963                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 964
 965         /* AMD_CG_SUPPORT_DRM_MGCG */
 966         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 967         if (!(data & 0x01000000))
 968                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 969
 970         /* AMD_CG_SUPPORT_DRM_LS */
 971         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 972         if (data & 0x1)
 973                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 974
 975         /* AMD_CG_SUPPORT_ROM_MGCG */
 976         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 977         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 978                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 979
 980         adev->df_funcs->get_clockgating_state(adev, flags);
 981 }
 982
 983 static int soc15_common_set_powergating_state(void *handle,
 984                                             enum amd_powergating_state state)
 985 {
 986         /* todo */
 987         return 0;
 988 }
 989
 990 const struct amd_ip_funcs soc15_common_ip_funcs = {
 991         .name = "soc15_common",
 992         .early_init = soc15_common_early_init,
 993         .late_init = soc15_common_late_init,
 994         .sw_init = soc15_common_sw_init,
 995         .sw_fini = soc15_common_sw_fini,
 996         .hw_init = soc15_common_hw_init,
 997         .hw_fini = soc15_common_hw_fini,
 998         .suspend = soc15_common_suspend,
 999         .resume = soc15_common_resume,
1000         .is_idle = soc15_common_is_idle,
1001         .wait_for_idle = soc15_common_wait_for_idle,
1002         .soft_reset = soc15_common_soft_reset,
1003         .set_clockgating_state = soc15_common_set_clockgating_state,
1004         .set_powergating_state = soc15_common_set_powergating_state,
1005         .get_clockgating_state= soc15_common_get_clockgating_state,
1006 };