drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "cikd.h"
  30
  31 #include "uvd/uvd_4_2_d.h"
  32 #include "uvd/uvd_4_2_sh_mask.h"
  33
  34 #include "oss/oss_2_0_d.h"
  35 #include "oss/oss_2_0_sh_mask.h"
  36
  37 #include "bif/bif_4_1_d.h"
  38
  39 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
  40 static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
  41 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
  42 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
  43 static int uvd_v4_2_start(struct amdgpu_device *adev);
  44 static void uvd_v4_2_stop(struct amdgpu_device *adev);
  45
  46 /**
  47  * uvd_v4_2_ring_get_rptr - get read pointer
  48  *
  49  * @ring: amdgpu_ring pointer
  50  *
  51  * Returns the current hardware read pointer
  52  */
  53 static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
  54 {
  55         struct amdgpu_device *adev = ring->adev;
  56
  57         return RREG32(mmUVD_RBC_RB_RPTR);
  58 }
  59
  60 /**
  61  * uvd_v4_2_ring_get_wptr - get write pointer
  62  *
  63  * @ring: amdgpu_ring pointer
  64  *
  65  * Returns the current hardware write pointer
  66  */
  67 static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
  68 {
  69         struct amdgpu_device *adev = ring->adev;
  70
  71         return RREG32(mmUVD_RBC_RB_WPTR);
  72 }
  73
  74 /**
  75  * uvd_v4_2_ring_set_wptr - set write pointer
  76  *
  77  * @ring: amdgpu_ring pointer
  78  *
  79  * Commits the write pointer to the hardware
  80  */
  81 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
  82 {
  83         struct amdgpu_device *adev = ring->adev;
  84
  85         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
  86 }
  87
  88 static int uvd_v4_2_early_init(void *handle)
  89 {
  90         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  91
  92         uvd_v4_2_set_ring_funcs(adev);
  93         uvd_v4_2_set_irq_funcs(adev);
  94
  95         return 0;
  96 }
  97
  98 static int uvd_v4_2_sw_init(void *handle)
  99 {
 100         struct amdgpu_ring *ring;
 101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 102         int r;
 103
 104         /* UVD TRAP */
 105         r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
 106         if (r)
 107                 return r;
 108
 109         r = amdgpu_uvd_sw_init(adev);
 110         if (r)
 111                 return r;
 112
 113         r = amdgpu_uvd_resume(adev);
 114         if (r)
 115                 return r;
 116
 117         ring = &adev->uvd.ring;
 118         sprintf(ring->name, "uvd");
 119         r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf,
 120                              &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
 121
 122         return r;
 123 }
 124
 125 static int uvd_v4_2_sw_fini(void *handle)
 126 {
 127         int r;
 128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 129
 130         r = amdgpu_uvd_suspend(adev);
 131         if (r)
 132                 return r;
 133
 134         r = amdgpu_uvd_sw_fini(adev);
 135         if (r)
 136                 return r;
 137
 138         return r;
 139 }
 140
 141 /**
 142  * uvd_v4_2_hw_init - start and test UVD block
 143  *
 144  * @adev: amdgpu_device pointer
 145  *
 146  * Initialize the hardware, boot up the VCPU and do some testing
 147  */
 148 static int uvd_v4_2_hw_init(void *handle)
 149 {
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151         struct amdgpu_ring *ring = &adev->uvd.ring;
 152         uint32_t tmp;
 153         int r;
 154
 155         /* raise clocks while booting up the VCPU */
 156         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
 157
 158         r = uvd_v4_2_start(adev);
 159         if (r)
 160                 goto done;
 161
 162         ring->ready = true;
 163         r = amdgpu_ring_test_ring(ring);
 164         if (r) {
 165                 ring->ready = false;
 166                 goto done;
 167         }
 168
 169         r = amdgpu_ring_alloc(ring, 10);
 170         if (r) {
 171                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 172                 goto done;
 173         }
 174
 175         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 176         amdgpu_ring_write(ring, tmp);
 177         amdgpu_ring_write(ring, 0xFFFFF);
 178
 179         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 180         amdgpu_ring_write(ring, tmp);
 181         amdgpu_ring_write(ring, 0xFFFFF);
 182
 183         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 184         amdgpu_ring_write(ring, tmp);
 185         amdgpu_ring_write(ring, 0xFFFFF);
 186
 187         /* Clear timeout status bits */
 188         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 189         amdgpu_ring_write(ring, 0x8);
 190
 191         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 192         amdgpu_ring_write(ring, 3);
 193
 194         amdgpu_ring_commit(ring);
 195
 196 done:
 197         /* lower clocks again */
 198         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 199
 200         if (!r)
 201                 DRM_INFO("UVD initialized successfully.\n");
 202
 203         return r;
 204 }
 205
 206 /**
 207  * uvd_v4_2_hw_fini - stop the hardware block
 208  *
 209  * @adev: amdgpu_device pointer
 210  *
 211  * Stop the UVD block, mark ring as not ready any more
 212  */
 213 static int uvd_v4_2_hw_fini(void *handle)
 214 {
 215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 216         struct amdgpu_ring *ring = &adev->uvd.ring;
 217
 218         uvd_v4_2_stop(adev);
 219         ring->ready = false;
 220
 221         return 0;
 222 }
 223
 224 static int uvd_v4_2_suspend(void *handle)
 225 {
 226         int r;
 227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 228
 229         r = uvd_v4_2_hw_fini(adev);
 230         if (r)
 231                 return r;
 232
 233         r = amdgpu_uvd_suspend(adev);
 234         if (r)
 235                 return r;
 236
 237         return r;
 238 }
 239
 240 static int uvd_v4_2_resume(void *handle)
 241 {
 242         int r;
 243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 244
 245         r = amdgpu_uvd_resume(adev);
 246         if (r)
 247                 return r;
 248
 249         r = uvd_v4_2_hw_init(adev);
 250         if (r)
 251                 return r;
 252
 253         return r;
 254 }
 255
 256 /**
 257  * uvd_v4_2_start - start UVD block
 258  *
 259  * @adev: amdgpu_device pointer
 260  *
 261  * Setup and start the UVD block
 262  */
 263 static int uvd_v4_2_start(struct amdgpu_device *adev)
 264 {
 265         struct amdgpu_ring *ring = &adev->uvd.ring;
 266         uint32_t rb_bufsz;
 267         int i, j, r;
 268
 269         /* disable byte swapping */
 270         u32 lmi_swap_cntl = 0;
 271         u32 mp_swap_cntl = 0;
 272
 273         uvd_v4_2_mc_resume(adev);
 274
 275         /* disable clock gating */
 276         WREG32(mmUVD_CGC_GATE, 0);
 277
 278         /* disable interupt */
 279         WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 280
 281         /* Stall UMC and register bus before resetting VCPU */
 282         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 283         mdelay(1);
 284
 285         /* put LMI, VCPU, RBC etc... into reset */
 286         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 287                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 288                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 289                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 290                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 291         mdelay(5);
 292
 293         /* take UVD block out of reset */
 294         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 295         mdelay(5);
 296
 297         /* initialize UVD memory controller */
 298         WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
 299                              (1 << 21) | (1 << 9) | (1 << 20));
 300
 301 #ifdef __BIG_ENDIAN
 302         /* swap (8 in 32) RB and IB */
 303         lmi_swap_cntl = 0xa;
 304         mp_swap_cntl = 0;
 305 #endif
 306         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 307         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 308
 309         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 310         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 311         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 312         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 313         WREG32(mmUVD_MPC_SET_ALU, 0);
 314         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 315
 316         /* take all subblocks out of reset, except VCPU */
 317         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 318         mdelay(5);
 319
 320         /* enable VCPU clock */
 321         WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 322
 323         /* enable UMC */
 324         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 325
 326         /* boot up the VCPU */
 327         WREG32(mmUVD_SOFT_RESET, 0);
 328         mdelay(10);
 329
 330         for (i = 0; i < 10; ++i) {
 331                 uint32_t status;
 332                 for (j = 0; j < 100; ++j) {
 333                         status = RREG32(mmUVD_STATUS);
 334                         if (status & 2)
 335                                 break;
 336                         mdelay(10);
 337                 }
 338                 r = 0;
 339                 if (status & 2)
 340                         break;
 341
 342                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 343                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 344                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 345                 mdelay(10);
 346                 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 347                 mdelay(10);
 348                 r = -1;
 349         }
 350
 351         if (r) {
 352                 DRM_ERROR("UVD not responding, giving up!!!\n");
 353                 return r;
 354         }
 355
 356         /* enable interupt */
 357         WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
 358
 359         /* force RBC into idle state */
 360         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 361
 362         /* Set the write pointer delay */
 363         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 364
 365         /* programm the 4GB memory segment for rptr and ring buffer */
 366         WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
 367                                    (0x7 << 16) | (0x1 << 31));
 368
 369         /* Initialize the ring buffer's read and write pointers */
 370         WREG32(mmUVD_RBC_RB_RPTR, 0x0);
 371
 372         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 373         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 374
 375         /* set the ring address */
 376         WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
 377
 378         /* Set ring buffer size */
 379         rb_bufsz = order_base_2(ring->ring_size);
 380         rb_bufsz = (0x1 << 8) | rb_bufsz;
 381         WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
 382
 383         return 0;
 384 }
 385
 386 /**
 387  * uvd_v4_2_stop - stop UVD block
 388  *
 389  * @adev: amdgpu_device pointer
 390  *
 391  * stop the UVD block
 392  */
 393 static void uvd_v4_2_stop(struct amdgpu_device *adev)
 394 {
 395         /* force RBC into idle state */
 396         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 397
 398         /* Stall UMC and register bus before resetting VCPU */
 399         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 400         mdelay(1);
 401
 402         /* put VCPU into reset */
 403         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 404         mdelay(5);
 405
 406         /* disable VCPU clock */
 407         WREG32(mmUVD_VCPU_CNTL, 0x0);
 408
 409         /* Unstall UMC and register bus */
 410         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 411 }
 412
 413 /**
 414  * uvd_v4_2_ring_emit_fence - emit an fence & trap command
 415  *
 416  * @ring: amdgpu_ring pointer
 417  * @fence: fence to emit
 418  *
 419  * Write a fence and a trap command to the ring.
 420  */
 421 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 422                                      unsigned flags)
 423 {
 424         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 425
 426         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 427         amdgpu_ring_write(ring, seq);
 428         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 429         amdgpu_ring_write(ring, addr & 0xffffffff);
 430         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 431         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 432         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 433         amdgpu_ring_write(ring, 0);
 434
 435         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 436         amdgpu_ring_write(ring, 0);
 437         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 438         amdgpu_ring_write(ring, 0);
 439         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 440         amdgpu_ring_write(ring, 2);
 441 }
 442
 443 /**
 444  * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush
 445  *
 446  * @ring: amdgpu_ring pointer
 447  *
 448  * Emits an hdp flush.
 449  */
 450 static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 451 {
 452         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 453         amdgpu_ring_write(ring, 0);
 454 }
 455
 456 /**
 457  * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate
 458  *
 459  * @ring: amdgpu_ring pointer
 460  *
 461  * Emits an hdp invalidate.
 462  */
 463 static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 464 {
 465         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 466         amdgpu_ring_write(ring, 1);
 467 }
 468
 469 /**
 470  * uvd_v4_2_ring_test_ring - register write test
 471  *
 472  * @ring: amdgpu_ring pointer
 473  *
 474  * Test if we can successfully write to the context register
 475  */
 476 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
 477 {
 478         struct amdgpu_device *adev = ring->adev;
 479         uint32_t tmp = 0;
 480         unsigned i;
 481         int r;
 482
 483         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 484         r = amdgpu_ring_alloc(ring, 3);
 485         if (r) {
 486                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 487                           ring->idx, r);
 488                 return r;
 489         }
 490         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 491         amdgpu_ring_write(ring, 0xDEADBEEF);
 492         amdgpu_ring_commit(ring);
 493         for (i = 0; i < adev->usec_timeout; i++) {
 494                 tmp = RREG32(mmUVD_CONTEXT_ID);
 495                 if (tmp == 0xDEADBEEF)
 496                         break;
 497                 DRM_UDELAY(1);
 498         }
 499
 500         if (i < adev->usec_timeout) {
 501                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 502                          ring->idx, i);
 503         } else {
 504                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 505                           ring->idx, tmp);
 506                 r = -EINVAL;
 507         }
 508         return r;
 509 }
 510
 511 /**
 512  * uvd_v4_2_ring_emit_ib - execute indirect buffer
 513  *
 514  * @ring: amdgpu_ring pointer
 515  * @ib: indirect buffer to execute
 516  *
 517  * Write ring commands to execute the indirect buffer
 518  */
 519 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
 520                                   struct amdgpu_ib *ib,
 521                                   unsigned vm_id, bool ctx_switch)
 522 {
 523         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
 524         amdgpu_ring_write(ring, ib->gpu_addr);
 525         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 526         amdgpu_ring_write(ring, ib->length_dw);
 527 }
 528
 529 static unsigned uvd_v4_2_ring_get_emit_ib_size(struct amdgpu_ring *ring)
 530 {
 531         return
 532                 4; /* uvd_v4_2_ring_emit_ib */
 533 }
 534
 535 static unsigned uvd_v4_2_ring_get_dma_frame_size(struct amdgpu_ring *ring)
 536 {
 537         return
 538                 2 + /* uvd_v4_2_ring_emit_hdp_flush */
 539                 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */
 540                 14; /* uvd_v4_2_ring_emit_fence  x1 no user fence */
 541 }
 542
 543 /**
 544  * uvd_v4_2_mc_resume - memory controller programming
 545  *
 546  * @adev: amdgpu_device pointer
 547  *
 548  * Let the UVD memory controller know it's offsets
 549  */
 550 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
 551 {
 552         uint64_t addr;
 553         uint32_t size;
 554
 555         /* programm the VCPU memory controller bits 0-27 */
 556         addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
 557         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
 558         WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
 559         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 560
 561         addr += size;
 562         size = AMDGPU_UVD_HEAP_SIZE >> 3;
 563         WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
 564         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 565
 566         addr += size;
 567         size = (AMDGPU_UVD_STACK_SIZE +
 568                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
 569         WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
 570         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 571
 572         /* bits 28-31 */
 573         addr = (adev->uvd.gpu_addr >> 28) & 0xF;
 574         WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
 575
 576         /* bits 32-39 */
 577         addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
 578         WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 579
 580         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 581         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 582         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 583
 584         uvd_v4_2_init_cg(adev);
 585 }
 586
 587 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
 588                                  bool enable)
 589 {
 590         u32 orig, data;
 591
 592         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
 593                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 594                 data = 0xfff;
 595                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 596
 597                 orig = data = RREG32(mmUVD_CGC_CTRL);
 598                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 599                 if (orig != data)
 600                         WREG32(mmUVD_CGC_CTRL, data);
 601         } else {
 602                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 603                 data &= ~0xfff;
 604                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 605
 606                 orig = data = RREG32(mmUVD_CGC_CTRL);
 607                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 608                 if (orig != data)
 609                         WREG32(mmUVD_CGC_CTRL, data);
 610         }
 611 }
 612
 613 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
 614                              bool sw_mode)
 615 {
 616         u32 tmp, tmp2;
 617
 618         tmp = RREG32(mmUVD_CGC_CTRL);
 619         tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 620         tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 621                 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
 622                 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
 623
 624         if (sw_mode) {
 625                 tmp &= ~0x7ffff800;
 626                 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
 627                         UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
 628                         (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
 629         } else {
 630                 tmp |= 0x7ffff800;
 631                 tmp2 = 0;
 632         }
 633
 634         WREG32(mmUVD_CGC_CTRL, tmp);
 635         WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
 636 }
 637
 638 static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
 639 {
 640         bool hw_mode = true;
 641
 642         if (hw_mode) {
 643                 uvd_v4_2_set_dcm(adev, false);
 644         } else {
 645                 u32 tmp = RREG32(mmUVD_CGC_CTRL);
 646                 tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 647                 WREG32(mmUVD_CGC_CTRL, tmp);
 648         }
 649 }
 650
 651 static bool uvd_v4_2_is_idle(void *handle)
 652 {
 653         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 654
 655         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 656 }
 657
 658 static int uvd_v4_2_wait_for_idle(void *handle)
 659 {
 660         unsigned i;
 661         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 662
 663         for (i = 0; i < adev->usec_timeout; i++) {
 664                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 665                         return 0;
 666         }
 667         return -ETIMEDOUT;
 668 }
 669
 670 static int uvd_v4_2_soft_reset(void *handle)
 671 {
 672         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 673
 674         uvd_v4_2_stop(adev);
 675
 676         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 677                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 678         mdelay(5);
 679
 680         return uvd_v4_2_start(adev);
 681 }
 682
 683 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
 684                                         struct amdgpu_irq_src *source,
 685                                         unsigned type,
 686                                         enum amdgpu_interrupt_state state)
 687 {
 688         // TODO
 689         return 0;
 690 }
 691
 692 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
 693                                       struct amdgpu_irq_src *source,
 694                                       struct amdgpu_iv_entry *entry)
 695 {
 696         DRM_DEBUG("IH: UVD TRAP\n");
 697         amdgpu_fence_process(&adev->uvd.ring);
 698         return 0;
 699 }
 700
 701 static int uvd_v4_2_set_clockgating_state(void *handle,
 702                                           enum amd_clockgating_state state)
 703 {
 704         bool gate = false;
 705         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 706
 707         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
 708                 return 0;
 709
 710         if (state == AMD_CG_STATE_GATE)
 711                 gate = true;
 712
 713         uvd_v4_2_enable_mgcg(adev, gate);
 714
 715         return 0;
 716 }
 717
 718 static int uvd_v4_2_set_powergating_state(void *handle,
 719                                           enum amd_powergating_state state)
 720 {
 721         /* This doesn't actually powergate the UVD block.
 722          * That's done in the dpm code via the SMC.  This
 723          * just re-inits the block as necessary.  The actual
 724          * gating still happens in the dpm code.  We should
 725          * revisit this when there is a cleaner line between
 726          * the smc and the hw blocks
 727          */
 728         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 729
 730         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
 731                 return 0;
 732
 733         if (state == AMD_PG_STATE_GATE) {
 734                 uvd_v4_2_stop(adev);
 735                 return 0;
 736         } else {
 737                 return uvd_v4_2_start(adev);
 738         }
 739 }
 740
 741 const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
 742         .name = "uvd_v4_2",
 743         .early_init = uvd_v4_2_early_init,
 744         .late_init = NULL,
 745         .sw_init = uvd_v4_2_sw_init,
 746         .sw_fini = uvd_v4_2_sw_fini,
 747         .hw_init = uvd_v4_2_hw_init,
 748         .hw_fini = uvd_v4_2_hw_fini,
 749         .suspend = uvd_v4_2_suspend,
 750         .resume = uvd_v4_2_resume,
 751         .is_idle = uvd_v4_2_is_idle,
 752         .wait_for_idle = uvd_v4_2_wait_for_idle,
 753         .soft_reset = uvd_v4_2_soft_reset,
 754         .set_clockgating_state = uvd_v4_2_set_clockgating_state,
 755         .set_powergating_state = uvd_v4_2_set_powergating_state,
 756 };
 757
 758 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
 759         .get_rptr = uvd_v4_2_ring_get_rptr,
 760         .get_wptr = uvd_v4_2_ring_get_wptr,
 761         .set_wptr = uvd_v4_2_ring_set_wptr,
 762         .parse_cs = amdgpu_uvd_ring_parse_cs,
 763         .emit_ib = uvd_v4_2_ring_emit_ib,
 764         .emit_fence = uvd_v4_2_ring_emit_fence,
 765         .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush,
 766         .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate,
 767         .test_ring = uvd_v4_2_ring_test_ring,
 768         .test_ib = amdgpu_uvd_ring_test_ib,
 769         .insert_nop = amdgpu_ring_insert_nop,
 770         .pad_ib = amdgpu_ring_generic_pad_ib,
 771         .begin_use = amdgpu_uvd_ring_begin_use,
 772         .end_use = amdgpu_uvd_ring_end_use,
 773         .get_emit_ib_size = uvd_v4_2_ring_get_emit_ib_size,
 774         .get_dma_frame_size = uvd_v4_2_ring_get_dma_frame_size,
 775 };
 776
 777 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
 778 {
 779         adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
 780 }
 781
 782 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
 783         .set = uvd_v4_2_set_interrupt_state,
 784         .process = uvd_v4_2_process_interrupt,
 785 };
 786
 787 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
 788 {
 789         adev->uvd.irq.num_types = 1;
 790         adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
 791 }