drivers/gpu/drm/amd/amdgpu/vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/slab.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_atombios.h"
  27 #include "amdgpu_ih.h"
  28 #include "amdgpu_uvd.h"
  29 #include "amdgpu_vce.h"
  30 #include "amdgpu_ucode.h"
  31 #include "atom.h"
  32 #include "amd_pcie.h"
  33
  34 #include "gmc/gmc_8_1_d.h"
  35 #include "gmc/gmc_8_1_sh_mask.h"
  36
  37 #include "oss/oss_3_0_d.h"
  38 #include "oss/oss_3_0_sh_mask.h"
  39
  40 #include "bif/bif_5_0_d.h"
  41 #include "bif/bif_5_0_sh_mask.h"
  42
  43 #include "gca/gfx_8_0_d.h"
  44 #include "gca/gfx_8_0_sh_mask.h"
  45
  46 #include "smu/smu_7_1_1_d.h"
  47 #include "smu/smu_7_1_1_sh_mask.h"
  48
  49 #include "uvd/uvd_5_0_d.h"
  50 #include "uvd/uvd_5_0_sh_mask.h"
  51
  52 #include "vce/vce_3_0_d.h"
  53 #include "vce/vce_3_0_sh_mask.h"
  54
  55 #include "dce/dce_10_0_d.h"
  56 #include "dce/dce_10_0_sh_mask.h"
  57
  58 #include "vid.h"
  59 #include "vi.h"
  60 #include "vi_dpm.h"
  61 #include "gmc_v8_0.h"
  62 #include "gmc_v7_0.h"
  63 #include "gfx_v8_0.h"
  64 #include "sdma_v2_4.h"
  65 #include "sdma_v3_0.h"
  66 #include "dce_v10_0.h"
  67 #include "dce_v11_0.h"
  68 #include "iceland_ih.h"
  69 #include "tonga_ih.h"
  70 #include "cz_ih.h"
  71 #include "uvd_v5_0.h"
  72 #include "uvd_v6_0.h"
  73 #include "vce_v3_0.h"
  74 #include "amdgpu_powerplay.h"
  75 #if defined(CONFIG_DRM_AMD_ACP)
  76 #include "amdgpu_acp.h"
  77 #endif
  78 #include "dce_virtual.h"
  79 #include "mxgpu_vi.h"
  80
  81 /*
  82  * Indirect registers accessor
  83  */
  84 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  85 {
  86         unsigned long flags;
  87         u32 r;
  88
  89         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  90         WREG32(mmPCIE_INDEX, reg);
  91         (void)RREG32(mmPCIE_INDEX);
  92         r = RREG32(mmPCIE_DATA);
  93         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  94         return r;
  95 }
  96
  97 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  98 {
  99         unsigned long flags;
 100
 101         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 102         WREG32(mmPCIE_INDEX, reg);
 103         (void)RREG32(mmPCIE_INDEX);
 104         WREG32(mmPCIE_DATA, v);
 105         (void)RREG32(mmPCIE_DATA);
 106         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 107 }
 108
 109 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
 110 {
 111         unsigned long flags;
 112         u32 r;
 113
 114         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 115         WREG32(mmSMC_IND_INDEX_11, (reg));
 116         r = RREG32(mmSMC_IND_DATA_11);
 117         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 118         return r;
 119 }
 120
 121 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 122 {
 123         unsigned long flags;
 124
 125         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 126         WREG32(mmSMC_IND_INDEX_11, (reg));
 127         WREG32(mmSMC_IND_DATA_11, (v));
 128         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 129 }
 130
 131 /* smu_8_0_d.h */
 132 #define mmMP0PUB_IND_INDEX                                                      0x180
 133 #define mmMP0PUB_IND_DATA                                                       0x181
 134
 135 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
 136 {
 137         unsigned long flags;
 138         u32 r;
 139
 140         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 141         WREG32(mmMP0PUB_IND_INDEX, (reg));
 142         r = RREG32(mmMP0PUB_IND_DATA);
 143         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 144         return r;
 145 }
 146
 147 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 152         WREG32(mmMP0PUB_IND_INDEX, (reg));
 153         WREG32(mmMP0PUB_IND_DATA, (v));
 154         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 155 }
 156
 157 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 158 {
 159         unsigned long flags;
 160         u32 r;
 161
 162         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 163         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 164         r = RREG32(mmUVD_CTX_DATA);
 165         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 166         return r;
 167 }
 168
 169 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 170 {
 171         unsigned long flags;
 172
 173         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 174         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 175         WREG32(mmUVD_CTX_DATA, (v));
 176         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 177 }
 178
 179 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
 180 {
 181         unsigned long flags;
 182         u32 r;
 183
 184         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 185         WREG32(mmDIDT_IND_INDEX, (reg));
 186         r = RREG32(mmDIDT_IND_DATA);
 187         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 188         return r;
 189 }
 190
 191 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 192 {
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 196         WREG32(mmDIDT_IND_INDEX, (reg));
 197         WREG32(mmDIDT_IND_DATA, (v));
 198         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 199 }
 200
 201 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 202 {
 203         unsigned long flags;
 204         u32 r;
 205
 206         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 207         WREG32(mmGC_CAC_IND_INDEX, (reg));
 208         r = RREG32(mmGC_CAC_IND_DATA);
 209         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 210         return r;
 211 }
 212
 213 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 214 {
 215         unsigned long flags;
 216
 217         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 218         WREG32(mmGC_CAC_IND_INDEX, (reg));
 219         WREG32(mmGC_CAC_IND_DATA, (v));
 220         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 221 }
 222
 223
 224 static const u32 tonga_mgcg_cgcg_init[] =
 225 {
 226         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 227         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 228         mmPCIE_DATA, 0x000f0000, 0x00000000,
 229         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 230         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 231         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 232         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 233 };
 234
 235 static const u32 fiji_mgcg_cgcg_init[] =
 236 {
 237         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 238         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 239         mmPCIE_DATA, 0x000f0000, 0x00000000,
 240         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 241         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 242         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 243         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 244 };
 245
 246 static const u32 iceland_mgcg_cgcg_init[] =
 247 {
 248         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 249         mmPCIE_DATA, 0x000f0000, 0x00000000,
 250         mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
 251         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 252         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 253 };
 254
 255 static const u32 cz_mgcg_cgcg_init[] =
 256 {
 257         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 258         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 259         mmPCIE_DATA, 0x000f0000, 0x00000000,
 260         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 261         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 262 };
 263
 264 static const u32 stoney_mgcg_cgcg_init[] =
 265 {
 266         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
 267         mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
 268         mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
 269 };
 270
 271 static void vi_init_golden_registers(struct amdgpu_device *adev)
 272 {
 273         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 274         mutex_lock(&adev->grbm_idx_mutex);
 275
 276         if (amdgpu_sriov_vf(adev)) {
 277                 xgpu_vi_init_golden_registers(adev);
 278                 mutex_unlock(&adev->grbm_idx_mutex);
 279                 return;
 280         }
 281
 282         switch (adev->asic_type) {
 283         case CHIP_TOPAZ:
 284                 amdgpu_program_register_sequence(adev,
 285                                                  iceland_mgcg_cgcg_init,
 286                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 287                 break;
 288         case CHIP_FIJI:
 289                 amdgpu_program_register_sequence(adev,
 290                                                  fiji_mgcg_cgcg_init,
 291                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 292                 break;
 293         case CHIP_TONGA:
 294                 amdgpu_program_register_sequence(adev,
 295                                                  tonga_mgcg_cgcg_init,
 296                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 297                 break;
 298         case CHIP_CARRIZO:
 299                 amdgpu_program_register_sequence(adev,
 300                                                  cz_mgcg_cgcg_init,
 301                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 302                 break;
 303         case CHIP_STONEY:
 304                 amdgpu_program_register_sequence(adev,
 305                                                  stoney_mgcg_cgcg_init,
 306                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 307                 break;
 308         case CHIP_POLARIS11:
 309         case CHIP_POLARIS10:
 310         case CHIP_POLARIS12:
 311         default:
 312                 break;
 313         }
 314         mutex_unlock(&adev->grbm_idx_mutex);
 315 }
 316
 317 /**
 318  * vi_get_xclk - get the xclk
 319  *
 320  * @adev: amdgpu_device pointer
 321  *
 322  * Returns the reference clock used by the gfx engine
 323  * (VI).
 324  */
 325 static u32 vi_get_xclk(struct amdgpu_device *adev)
 326 {
 327         u32 reference_clock = adev->clock.spll.reference_freq;
 328         u32 tmp;
 329
 330         if (adev->flags & AMD_IS_APU)
 331                 return reference_clock;
 332
 333         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
 334         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
 335                 return 1000;
 336
 337         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
 338         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
 339                 return reference_clock / 4;
 340
 341         return reference_clock;
 342 }
 343
 344 /**
 345  * vi_srbm_select - select specific register instances
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @me: selected ME (micro engine)
 349  * @pipe: pipe
 350  * @queue: queue
 351  * @vmid: VMID
 352  *
 353  * Switches the currently active registers instances.  Some
 354  * registers are instanced per VMID, others are instanced per
 355  * me/pipe/queue combination.
 356  */
 357 void vi_srbm_select(struct amdgpu_device *adev,
 358                      u32 me, u32 pipe, u32 queue, u32 vmid)
 359 {
 360         u32 srbm_gfx_cntl = 0;
 361         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 362         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 363         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
 364         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
 365         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 366 }
 367
 368 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
 369 {
 370         /* todo */
 371 }
 372
 373 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
 374 {
 375         u32 bus_cntl;
 376         u32 d1vga_control = 0;
 377         u32 d2vga_control = 0;
 378         u32 vga_render_control = 0;
 379         u32 rom_cntl;
 380         bool r;
 381
 382         bus_cntl = RREG32(mmBUS_CNTL);
 383         if (adev->mode_info.num_crtc) {
 384                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 385                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 386                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 387         }
 388         rom_cntl = RREG32_SMC(ixROM_CNTL);
 389
 390         /* enable the rom */
 391         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 392         if (adev->mode_info.num_crtc) {
 393                 /* Disable VGA mode */
 394                 WREG32(mmD1VGA_CONTROL,
 395                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 396                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 397                 WREG32(mmD2VGA_CONTROL,
 398                        (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
 399                                           D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
 400                 WREG32(mmVGA_RENDER_CONTROL,
 401                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 402         }
 403         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 404
 405         r = amdgpu_read_bios(adev);
 406
 407         /* restore regs */
 408         WREG32(mmBUS_CNTL, bus_cntl);
 409         if (adev->mode_info.num_crtc) {
 410                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 411                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 412                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 413         }
 414         WREG32_SMC(ixROM_CNTL, rom_cntl);
 415         return r;
 416 }
 417
 418 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
 419                                   u8 *bios, u32 length_bytes)
 420 {
 421         u32 *dw_ptr;
 422         unsigned long flags;
 423         u32 i, length_dw;
 424
 425         if (bios == NULL)
 426                 return false;
 427         if (length_bytes == 0)
 428                 return false;
 429         /* APU vbios image is part of sbios image */
 430         if (adev->flags & AMD_IS_APU)
 431                 return false;
 432
 433         dw_ptr = (u32 *)bios;
 434         length_dw = ALIGN(length_bytes, 4) / 4;
 435         /* take the smc lock since we are using the smc index */
 436         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 437         /* set rom index to 0 */
 438         WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
 439         WREG32(mmSMC_IND_DATA_11, 0);
 440         /* set index to data for continous read */
 441         WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
 442         for (i = 0; i < length_dw; i++)
 443                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
 444         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 445
 446         return true;
 447 }
 448
 449 static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
 450 {
 451         uint32_t reg = 0;
 452
 453         if (adev->asic_type == CHIP_TONGA ||
 454             adev->asic_type == CHIP_FIJI) {
 455                reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
 456                /* bit0: 0 means pf and 1 means vf */
 457                /* bit31: 0 means disable IOV and 1 means enable */
 458                if (reg & 1)
 459                        adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 460
 461                if (reg & 0x80000000)
 462                        adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 463         }
 464
 465         if (reg == 0) {
 466                 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
 467                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 468         }
 469 }
 470
 471 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
 472         {mmGRBM_STATUS},
 473         {mmGRBM_STATUS2},
 474         {mmGRBM_STATUS_SE0},
 475         {mmGRBM_STATUS_SE1},
 476         {mmGRBM_STATUS_SE2},
 477         {mmGRBM_STATUS_SE3},
 478         {mmSRBM_STATUS},
 479         {mmSRBM_STATUS2},
 480         {mmSRBM_STATUS3},
 481         {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
 482         {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
 483         {mmCP_STAT},
 484         {mmCP_STALLED_STAT1},
 485         {mmCP_STALLED_STAT2},
 486         {mmCP_STALLED_STAT3},
 487         {mmCP_CPF_BUSY_STAT},
 488         {mmCP_CPF_STALLED_STAT1},
 489         {mmCP_CPF_STATUS},
 490         {mmCP_CPC_BUSY_STAT},
 491         {mmCP_CPC_STALLED_STAT1},
 492         {mmCP_CPC_STATUS},
 493         {mmGB_ADDR_CONFIG},
 494         {mmMC_ARB_RAMCFG},
 495         {mmGB_TILE_MODE0},
 496         {mmGB_TILE_MODE1},
 497         {mmGB_TILE_MODE2},
 498         {mmGB_TILE_MODE3},
 499         {mmGB_TILE_MODE4},
 500         {mmGB_TILE_MODE5},
 501         {mmGB_TILE_MODE6},
 502         {mmGB_TILE_MODE7},
 503         {mmGB_TILE_MODE8},
 504         {mmGB_TILE_MODE9},
 505         {mmGB_TILE_MODE10},
 506         {mmGB_TILE_MODE11},
 507         {mmGB_TILE_MODE12},
 508         {mmGB_TILE_MODE13},
 509         {mmGB_TILE_MODE14},
 510         {mmGB_TILE_MODE15},
 511         {mmGB_TILE_MODE16},
 512         {mmGB_TILE_MODE17},
 513         {mmGB_TILE_MODE18},
 514         {mmGB_TILE_MODE19},
 515         {mmGB_TILE_MODE20},
 516         {mmGB_TILE_MODE21},
 517         {mmGB_TILE_MODE22},
 518         {mmGB_TILE_MODE23},
 519         {mmGB_TILE_MODE24},
 520         {mmGB_TILE_MODE25},
 521         {mmGB_TILE_MODE26},
 522         {mmGB_TILE_MODE27},
 523         {mmGB_TILE_MODE28},
 524         {mmGB_TILE_MODE29},
 525         {mmGB_TILE_MODE30},
 526         {mmGB_TILE_MODE31},
 527         {mmGB_MACROTILE_MODE0},
 528         {mmGB_MACROTILE_MODE1},
 529         {mmGB_MACROTILE_MODE2},
 530         {mmGB_MACROTILE_MODE3},
 531         {mmGB_MACROTILE_MODE4},
 532         {mmGB_MACROTILE_MODE5},
 533         {mmGB_MACROTILE_MODE6},
 534         {mmGB_MACROTILE_MODE7},
 535         {mmGB_MACROTILE_MODE8},
 536         {mmGB_MACROTILE_MODE9},
 537         {mmGB_MACROTILE_MODE10},
 538         {mmGB_MACROTILE_MODE11},
 539         {mmGB_MACROTILE_MODE12},
 540         {mmGB_MACROTILE_MODE13},
 541         {mmGB_MACROTILE_MODE14},
 542         {mmGB_MACROTILE_MODE15},
 543         {mmCC_RB_BACKEND_DISABLE, true},
 544         {mmGC_USER_RB_BACKEND_DISABLE, true},
 545         {mmGB_BACKEND_MAP, false},
 546         {mmPA_SC_RASTER_CONFIG, true},
 547         {mmPA_SC_RASTER_CONFIG_1, true},
 548 };
 549
 550 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
 551                                       bool indexed, u32 se_num,
 552                                       u32 sh_num, u32 reg_offset)
 553 {
 554         if (indexed) {
 555                 uint32_t val;
 556                 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
 557                 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
 558
 559                 switch (reg_offset) {
 560                 case mmCC_RB_BACKEND_DISABLE:
 561                         return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
 562                 case mmGC_USER_RB_BACKEND_DISABLE:
 563                         return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
 564                 case mmPA_SC_RASTER_CONFIG:
 565                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
 566                 case mmPA_SC_RASTER_CONFIG_1:
 567                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
 568                 }
 569
 570                 mutex_lock(&adev->grbm_idx_mutex);
 571                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 572                         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 573
 574                 val = RREG32(reg_offset);
 575
 576                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 577                         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 578                 mutex_unlock(&adev->grbm_idx_mutex);
 579                 return val;
 580         } else {
 581                 unsigned idx;
 582
 583                 switch (reg_offset) {
 584                 case mmGB_ADDR_CONFIG:
 585                         return adev->gfx.config.gb_addr_config;
 586                 case mmMC_ARB_RAMCFG:
 587                         return adev->gfx.config.mc_arb_ramcfg;
 588                 case mmGB_TILE_MODE0:
 589                 case mmGB_TILE_MODE1:
 590                 case mmGB_TILE_MODE2:
 591                 case mmGB_TILE_MODE3:
 592                 case mmGB_TILE_MODE4:
 593                 case mmGB_TILE_MODE5:
 594                 case mmGB_TILE_MODE6:
 595                 case mmGB_TILE_MODE7:
 596                 case mmGB_TILE_MODE8:
 597                 case mmGB_TILE_MODE9:
 598                 case mmGB_TILE_MODE10:
 599                 case mmGB_TILE_MODE11:
 600                 case mmGB_TILE_MODE12:
 601                 case mmGB_TILE_MODE13:
 602                 case mmGB_TILE_MODE14:
 603                 case mmGB_TILE_MODE15:
 604                 case mmGB_TILE_MODE16:
 605                 case mmGB_TILE_MODE17:
 606                 case mmGB_TILE_MODE18:
 607                 case mmGB_TILE_MODE19:
 608                 case mmGB_TILE_MODE20:
 609                 case mmGB_TILE_MODE21:
 610                 case mmGB_TILE_MODE22:
 611                 case mmGB_TILE_MODE23:
 612                 case mmGB_TILE_MODE24:
 613                 case mmGB_TILE_MODE25:
 614                 case mmGB_TILE_MODE26:
 615                 case mmGB_TILE_MODE27:
 616                 case mmGB_TILE_MODE28:
 617                 case mmGB_TILE_MODE29:
 618                 case mmGB_TILE_MODE30:
 619                 case mmGB_TILE_MODE31:
 620                         idx = (reg_offset - mmGB_TILE_MODE0);
 621                         return adev->gfx.config.tile_mode_array[idx];
 622                 case mmGB_MACROTILE_MODE0:
 623                 case mmGB_MACROTILE_MODE1:
 624                 case mmGB_MACROTILE_MODE2:
 625                 case mmGB_MACROTILE_MODE3:
 626                 case mmGB_MACROTILE_MODE4:
 627                 case mmGB_MACROTILE_MODE5:
 628                 case mmGB_MACROTILE_MODE6:
 629                 case mmGB_MACROTILE_MODE7:
 630                 case mmGB_MACROTILE_MODE8:
 631                 case mmGB_MACROTILE_MODE9:
 632                 case mmGB_MACROTILE_MODE10:
 633                 case mmGB_MACROTILE_MODE11:
 634                 case mmGB_MACROTILE_MODE12:
 635                 case mmGB_MACROTILE_MODE13:
 636                 case mmGB_MACROTILE_MODE14:
 637                 case mmGB_MACROTILE_MODE15:
 638                         idx = (reg_offset - mmGB_MACROTILE_MODE0);
 639                         return adev->gfx.config.macrotile_mode_array[idx];
 640                 default:
 641                         return RREG32(reg_offset);
 642                 }
 643         }
 644 }
 645
 646 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 647                             u32 sh_num, u32 reg_offset, u32 *value)
 648 {
 649         uint32_t i;
 650
 651         *value = 0;
 652         for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
 653                 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
 654
 655                 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
 656                         continue;
 657
 658                 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
 659                                                reg_offset);
 660                 return 0;
 661         }
 662         return -EINVAL;
 663 }
 664
 665 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 666 {
 667         u32 i;
 668
 669         dev_info(adev->dev, "GPU pci config reset\n");
 670
 671         /* disable BM */
 672         pci_clear_master(adev->pdev);
 673         /* reset */
 674         amdgpu_pci_config_reset(adev);
 675
 676         udelay(100);
 677
 678         /* wait for asic to come out of reset */
 679         for (i = 0; i < adev->usec_timeout; i++) {
 680                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
 681                         /* enable BM */
 682                         pci_set_master(adev->pdev);
 683                         adev->has_hw_reset = true;
 684                         return 0;
 685                 }
 686                 udelay(1);
 687         }
 688         return -EINVAL;
 689 }
 690
 691 /**
 692  * vi_asic_reset - soft reset GPU
 693  *
 694  * @adev: amdgpu_device pointer
 695  *
 696  * Look up which blocks are hung and attempt
 697  * to reset them.
 698  * Returns 0 for success.
 699  */
 700 static int vi_asic_reset(struct amdgpu_device *adev)
 701 {
 702         int r;
 703
 704         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 705
 706         r = vi_gpu_pci_config_reset(adev);
 707
 708         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 709
 710         return r;
 711 }
 712
 713 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
 714 {
 715         return RREG32(mmCONFIG_MEMSIZE);
 716 }
 717
 718 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 719                         u32 cntl_reg, u32 status_reg)
 720 {
 721         int r, i;
 722         struct atom_clock_dividers dividers;
 723         uint32_t tmp;
 724
 725         r = amdgpu_atombios_get_clock_dividers(adev,
 726                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 727                                                clock, false, &dividers);
 728         if (r)
 729                 return r;
 730
 731         tmp = RREG32_SMC(cntl_reg);
 732
 733         if (adev->flags & AMD_IS_APU)
 734                 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
 735         else
 736                 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
 737                                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
 738         tmp |= dividers.post_divider;
 739         WREG32_SMC(cntl_reg, tmp);
 740
 741         for (i = 0; i < 100; i++) {
 742                 tmp = RREG32_SMC(status_reg);
 743                 if (adev->flags & AMD_IS_APU) {
 744                         if (tmp & 0x10000)
 745                                 break;
 746                 } else {
 747                         if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
 748                                 break;
 749                 }
 750                 mdelay(10);
 751         }
 752         if (i == 100)
 753                 return -ETIMEDOUT;
 754         return 0;
 755 }
 756
 757 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0
 758 #define ixGNB_CLK1_STATUS   0xD822010C
 759 #define ixGNB_CLK2_DFS_CNTL 0xD8220110
 760 #define ixGNB_CLK2_STATUS   0xD822012C
 761 #define ixGNB_CLK3_DFS_CNTL 0xD8220130
 762 #define ixGNB_CLK3_STATUS   0xD822014C
 763
 764 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 765 {
 766         int r;
 767
 768         if (adev->flags & AMD_IS_APU) {
 769                 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
 770                 if (r)
 771                         return r;
 772
 773                 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
 774                 if (r)
 775                         return r;
 776         } else {
 777                 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 778                 if (r)
 779                         return r;
 780
 781                 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 782                 if (r)
 783                         return r;
 784         }
 785
 786         return 0;
 787 }
 788
 789 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 790 {
 791         int r, i;
 792         struct atom_clock_dividers dividers;
 793         u32 tmp;
 794         u32 reg_ctrl;
 795         u32 reg_status;
 796         u32 status_mask;
 797         u32 reg_mask;
 798
 799         if (adev->flags & AMD_IS_APU) {
 800                 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
 801                 reg_status = ixGNB_CLK3_STATUS;
 802                 status_mask = 0x00010000;
 803                 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
 804         } else {
 805                 reg_ctrl = ixCG_ECLK_CNTL;
 806                 reg_status = ixCG_ECLK_STATUS;
 807                 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
 808                 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
 809         }
 810
 811         r = amdgpu_atombios_get_clock_dividers(adev,
 812                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 813                                                ecclk, false, &dividers);
 814         if (r)
 815                 return r;
 816
 817         for (i = 0; i < 100; i++) {
 818                 if (RREG32_SMC(reg_status) & status_mask)
 819                         break;
 820                 mdelay(10);
 821         }
 822
 823         if (i == 100)
 824                 return -ETIMEDOUT;
 825
 826         tmp = RREG32_SMC(reg_ctrl);
 827         tmp &= ~reg_mask;
 828         tmp |= dividers.post_divider;
 829         WREG32_SMC(reg_ctrl, tmp);
 830
 831         for (i = 0; i < 100; i++) {
 832                 if (RREG32_SMC(reg_status) & status_mask)
 833                         break;
 834                 mdelay(10);
 835         }
 836
 837         if (i == 100)
 838                 return -ETIMEDOUT;
 839
 840         return 0;
 841 }
 842
 843 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
 844 {
 845         if (pci_is_root_bus(adev->pdev->bus))
 846                 return;
 847
 848         if (amdgpu_pcie_gen2 == 0)
 849                 return;
 850
 851         if (adev->flags & AMD_IS_APU)
 852                 return;
 853
 854         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 855                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 856                 return;
 857
 858         /* todo */
 859 }
 860
 861 static void vi_program_aspm(struct amdgpu_device *adev)
 862 {
 863
 864         if (amdgpu_aspm == 0)
 865                 return;
 866
 867         /* todo */
 868 }
 869
 870 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
 871                                         bool enable)
 872 {
 873         u32 tmp;
 874
 875         /* not necessary on CZ */
 876         if (adev->flags & AMD_IS_APU)
 877                 return;
 878
 879         tmp = RREG32(mmBIF_DOORBELL_APER_EN);
 880         if (enable)
 881                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
 882         else
 883                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
 884
 885         WREG32(mmBIF_DOORBELL_APER_EN, tmp);
 886 }
 887
 888 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
 889 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
 890 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
 891
 892 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
 893 {
 894         if (adev->flags & AMD_IS_APU)
 895                 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
 896                         >> ATI_REV_ID_FUSE_MACRO__SHIFT;
 897         else
 898                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
 899                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
 900 }
 901
 902 static const struct amdgpu_asic_funcs vi_asic_funcs =
 903 {
 904         .read_disabled_bios = &vi_read_disabled_bios,
 905         .read_bios_from_rom = &vi_read_bios_from_rom,
 906         .read_register = &vi_read_register,
 907         .reset = &vi_asic_reset,
 908         .set_vga_state = &vi_vga_set_state,
 909         .get_xclk = &vi_get_xclk,
 910         .set_uvd_clocks = &vi_set_uvd_clocks,
 911         .set_vce_clocks = &vi_set_vce_clocks,
 912         .get_config_memsize = &vi_get_config_memsize,
 913 };
 914
 915 #define CZ_REV_BRISTOL(rev)      \
 916         ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
 917
 918 static int vi_common_early_init(void *handle)
 919 {
 920         bool smc_enabled = false;
 921         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 922
 923         if (adev->flags & AMD_IS_APU) {
 924                 adev->smc_rreg = &cz_smc_rreg;
 925                 adev->smc_wreg = &cz_smc_wreg;
 926         } else {
 927                 adev->smc_rreg = &vi_smc_rreg;
 928                 adev->smc_wreg = &vi_smc_wreg;
 929         }
 930         adev->pcie_rreg = &vi_pcie_rreg;
 931         adev->pcie_wreg = &vi_pcie_wreg;
 932         adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
 933         adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
 934         adev->didt_rreg = &vi_didt_rreg;
 935         adev->didt_wreg = &vi_didt_wreg;
 936         adev->gc_cac_rreg = &vi_gc_cac_rreg;
 937         adev->gc_cac_wreg = &vi_gc_cac_wreg;
 938
 939         adev->asic_funcs = &vi_asic_funcs;
 940
 941         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
 942                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
 943                 smc_enabled = true;
 944
 945         adev->rev_id = vi_get_rev_id(adev);
 946         adev->external_rev_id = 0xFF;
 947         switch (adev->asic_type) {
 948         case CHIP_TOPAZ:
 949                 adev->cg_flags = 0;
 950                 adev->pg_flags = 0;
 951                 adev->external_rev_id = 0x1;
 952                 break;
 953         case CHIP_FIJI:
 954                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 955                         AMD_CG_SUPPORT_GFX_MGLS |
 956                         AMD_CG_SUPPORT_GFX_RLC_LS |
 957                         AMD_CG_SUPPORT_GFX_CP_LS |
 958                         AMD_CG_SUPPORT_GFX_CGTS |
 959                         AMD_CG_SUPPORT_GFX_CGTS_LS |
 960                         AMD_CG_SUPPORT_GFX_CGCG |
 961                         AMD_CG_SUPPORT_GFX_CGLS |
 962                         AMD_CG_SUPPORT_SDMA_MGCG |
 963                         AMD_CG_SUPPORT_SDMA_LS |
 964                         AMD_CG_SUPPORT_BIF_LS |
 965                         AMD_CG_SUPPORT_HDP_MGCG |
 966                         AMD_CG_SUPPORT_HDP_LS |
 967                         AMD_CG_SUPPORT_ROM_MGCG |
 968                         AMD_CG_SUPPORT_MC_MGCG |
 969                         AMD_CG_SUPPORT_MC_LS |
 970                         AMD_CG_SUPPORT_UVD_MGCG;
 971                 adev->pg_flags = 0;
 972                 adev->external_rev_id = adev->rev_id + 0x3c;
 973                 break;
 974         case CHIP_TONGA:
 975                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 976                         AMD_CG_SUPPORT_GFX_CGCG |
 977                         AMD_CG_SUPPORT_GFX_CGLS |
 978                         AMD_CG_SUPPORT_SDMA_MGCG |
 979                         AMD_CG_SUPPORT_SDMA_LS |
 980                         AMD_CG_SUPPORT_BIF_LS |
 981                         AMD_CG_SUPPORT_HDP_MGCG |
 982                         AMD_CG_SUPPORT_HDP_LS |
 983                         AMD_CG_SUPPORT_ROM_MGCG |
 984                         AMD_CG_SUPPORT_MC_MGCG |
 985                         AMD_CG_SUPPORT_MC_LS |
 986                         AMD_CG_SUPPORT_DRM_LS |
 987                         AMD_CG_SUPPORT_UVD_MGCG;
 988                 adev->pg_flags = 0;
 989                 adev->external_rev_id = adev->rev_id + 0x14;
 990                 break;
 991         case CHIP_POLARIS11:
 992                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 993                         AMD_CG_SUPPORT_GFX_RLC_LS |
 994                         AMD_CG_SUPPORT_GFX_CP_LS |
 995                         AMD_CG_SUPPORT_GFX_CGCG |
 996                         AMD_CG_SUPPORT_GFX_CGLS |
 997                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 998                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 999                         AMD_CG_SUPPORT_SDMA_MGCG |
1000                         AMD_CG_SUPPORT_SDMA_LS |
1001                         AMD_CG_SUPPORT_BIF_MGCG |
1002                         AMD_CG_SUPPORT_BIF_LS |
1003                         AMD_CG_SUPPORT_HDP_MGCG |
1004                         AMD_CG_SUPPORT_HDP_LS |
1005                         AMD_CG_SUPPORT_ROM_MGCG |
1006                         AMD_CG_SUPPORT_MC_MGCG |
1007                         AMD_CG_SUPPORT_MC_LS |
1008                         AMD_CG_SUPPORT_DRM_LS |
1009                         AMD_CG_SUPPORT_UVD_MGCG |
1010                         AMD_CG_SUPPORT_VCE_MGCG;
1011                 adev->pg_flags = 0;
1012                 adev->external_rev_id = adev->rev_id + 0x5A;
1013                 break;
1014         case CHIP_POLARIS10:
1015                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1016                         AMD_CG_SUPPORT_GFX_RLC_LS |
1017                         AMD_CG_SUPPORT_GFX_CP_LS |
1018                         AMD_CG_SUPPORT_GFX_CGCG |
1019                         AMD_CG_SUPPORT_GFX_CGLS |
1020                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1021                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1022                         AMD_CG_SUPPORT_SDMA_MGCG |
1023                         AMD_CG_SUPPORT_SDMA_LS |
1024                         AMD_CG_SUPPORT_BIF_MGCG |
1025                         AMD_CG_SUPPORT_BIF_LS |
1026                         AMD_CG_SUPPORT_HDP_MGCG |
1027                         AMD_CG_SUPPORT_HDP_LS |
1028                         AMD_CG_SUPPORT_ROM_MGCG |
1029                         AMD_CG_SUPPORT_MC_MGCG |
1030                         AMD_CG_SUPPORT_MC_LS |
1031                         AMD_CG_SUPPORT_DRM_LS |
1032                         AMD_CG_SUPPORT_UVD_MGCG |
1033                         AMD_CG_SUPPORT_VCE_MGCG;
1034                 adev->pg_flags = 0;
1035                 adev->external_rev_id = adev->rev_id + 0x50;
1036                 break;
1037         case CHIP_POLARIS12:
1038                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1039                         AMD_CG_SUPPORT_GFX_RLC_LS |
1040                         AMD_CG_SUPPORT_GFX_CP_LS |
1041                         AMD_CG_SUPPORT_GFX_CGCG |
1042                         AMD_CG_SUPPORT_GFX_CGLS |
1043                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1044                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1045                         AMD_CG_SUPPORT_SDMA_MGCG |
1046                         AMD_CG_SUPPORT_SDMA_LS |
1047                         AMD_CG_SUPPORT_BIF_MGCG |
1048                         AMD_CG_SUPPORT_BIF_LS |
1049                         AMD_CG_SUPPORT_HDP_MGCG |
1050                         AMD_CG_SUPPORT_HDP_LS |
1051                         AMD_CG_SUPPORT_ROM_MGCG |
1052                         AMD_CG_SUPPORT_MC_MGCG |
1053                         AMD_CG_SUPPORT_MC_LS |
1054                         AMD_CG_SUPPORT_DRM_LS |
1055                         AMD_CG_SUPPORT_UVD_MGCG |
1056                         AMD_CG_SUPPORT_VCE_MGCG;
1057                 adev->pg_flags = 0;
1058                 adev->external_rev_id = adev->rev_id + 0x64;
1059                 break;
1060         case CHIP_CARRIZO:
1061                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1062                         AMD_CG_SUPPORT_GFX_MGCG |
1063                         AMD_CG_SUPPORT_GFX_MGLS |
1064                         AMD_CG_SUPPORT_GFX_RLC_LS |
1065                         AMD_CG_SUPPORT_GFX_CP_LS |
1066                         AMD_CG_SUPPORT_GFX_CGTS |
1067                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1068                         AMD_CG_SUPPORT_GFX_CGCG |
1069                         AMD_CG_SUPPORT_GFX_CGLS |
1070                         AMD_CG_SUPPORT_BIF_LS |
1071                         AMD_CG_SUPPORT_HDP_MGCG |
1072                         AMD_CG_SUPPORT_HDP_LS |
1073                         AMD_CG_SUPPORT_SDMA_MGCG |
1074                         AMD_CG_SUPPORT_SDMA_LS |
1075                         AMD_CG_SUPPORT_VCE_MGCG;
1076                 /* rev0 hardware requires workarounds to support PG */
1077                 adev->pg_flags = 0;
1078                 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1079                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1080                                 AMD_PG_SUPPORT_GFX_PIPELINE |
1081                                 AMD_PG_SUPPORT_CP |
1082                                 AMD_PG_SUPPORT_UVD |
1083                                 AMD_PG_SUPPORT_VCE;
1084                 }
1085                 adev->external_rev_id = adev->rev_id + 0x1;
1086                 break;
1087         case CHIP_STONEY:
1088                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1089                         AMD_CG_SUPPORT_GFX_MGCG |
1090                         AMD_CG_SUPPORT_GFX_MGLS |
1091                         AMD_CG_SUPPORT_GFX_RLC_LS |
1092                         AMD_CG_SUPPORT_GFX_CP_LS |
1093                         AMD_CG_SUPPORT_GFX_CGTS |
1094                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1095                         AMD_CG_SUPPORT_GFX_CGCG |
1096                         AMD_CG_SUPPORT_GFX_CGLS |
1097                         AMD_CG_SUPPORT_BIF_LS |
1098                         AMD_CG_SUPPORT_HDP_MGCG |
1099                         AMD_CG_SUPPORT_HDP_LS |
1100                         AMD_CG_SUPPORT_SDMA_MGCG |
1101                         AMD_CG_SUPPORT_SDMA_LS |
1102                         AMD_CG_SUPPORT_VCE_MGCG;
1103                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1104                         AMD_PG_SUPPORT_GFX_SMG |
1105                         AMD_PG_SUPPORT_GFX_PIPELINE |
1106                         AMD_PG_SUPPORT_CP |
1107                         AMD_PG_SUPPORT_UVD |
1108                         AMD_PG_SUPPORT_VCE;
1109                 adev->external_rev_id = adev->rev_id + 0x61;
1110                 break;
1111         default:
1112                 /* FIXME: not supported yet */
1113                 return -EINVAL;
1114         }
1115
1116         if (amdgpu_sriov_vf(adev)) {
1117                 amdgpu_virt_init_setting(adev);
1118                 xgpu_vi_mailbox_set_irq_funcs(adev);
1119         }
1120
1121         /* vi use smc load by default */
1122         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1123
1124         amdgpu_get_pcie_info(adev);
1125
1126         return 0;
1127 }
1128
1129 static int vi_common_late_init(void *handle)
1130 {
1131         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132
1133         if (amdgpu_sriov_vf(adev))
1134                 xgpu_vi_mailbox_get_irq(adev);
1135
1136         return 0;
1137 }
1138
1139 static int vi_common_sw_init(void *handle)
1140 {
1141         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1142
1143         if (amdgpu_sriov_vf(adev))
1144                 xgpu_vi_mailbox_add_irq_id(adev);
1145
1146         return 0;
1147 }
1148
1149 static int vi_common_sw_fini(void *handle)
1150 {
1151         return 0;
1152 }
1153
1154 static int vi_common_hw_init(void *handle)
1155 {
1156         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1157
1158         /* move the golden regs per IP block */
1159         vi_init_golden_registers(adev);
1160         /* enable pcie gen2/3 link */
1161         vi_pcie_gen3_enable(adev);
1162         /* enable aspm */
1163         vi_program_aspm(adev);
1164         /* enable the doorbell aperture */
1165         vi_enable_doorbell_aperture(adev, true);
1166
1167         return 0;
1168 }
1169
1170 static int vi_common_hw_fini(void *handle)
1171 {
1172         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1173
1174         /* enable the doorbell aperture */
1175         vi_enable_doorbell_aperture(adev, false);
1176
1177         if (amdgpu_sriov_vf(adev))
1178                 xgpu_vi_mailbox_put_irq(adev);
1179
1180         return 0;
1181 }
1182
1183 static int vi_common_suspend(void *handle)
1184 {
1185         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1186
1187         return vi_common_hw_fini(adev);
1188 }
1189
1190 static int vi_common_resume(void *handle)
1191 {
1192         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1193
1194         return vi_common_hw_init(adev);
1195 }
1196
1197 static bool vi_common_is_idle(void *handle)
1198 {
1199         return true;
1200 }
1201
1202 static int vi_common_wait_for_idle(void *handle)
1203 {
1204         return 0;
1205 }
1206
1207 static int vi_common_soft_reset(void *handle)
1208 {
1209         return 0;
1210 }
1211
1212 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1213                                                    bool enable)
1214 {
1215         uint32_t temp, data;
1216
1217         temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1218
1219         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1220                 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1221                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1222                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1223         else
1224                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1225                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1226                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1227
1228         if (temp != data)
1229                 WREG32_PCIE(ixPCIE_CNTL2, data);
1230 }
1231
1232 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1233                                                     bool enable)
1234 {
1235         uint32_t temp, data;
1236
1237         temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1238
1239         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1240                 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1241         else
1242                 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1243
1244         if (temp != data)
1245                 WREG32(mmHDP_HOST_PATH_CNTL, data);
1246 }
1247
1248 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1249                                       bool enable)
1250 {
1251         uint32_t temp, data;
1252
1253         temp = data = RREG32(mmHDP_MEM_POWER_LS);
1254
1255         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1256                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1257         else
1258                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1259
1260         if (temp != data)
1261                 WREG32(mmHDP_MEM_POWER_LS, data);
1262 }
1263
1264 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1265                                       bool enable)
1266 {
1267         uint32_t temp, data;
1268
1269         temp = data = RREG32(0x157a);
1270
1271         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1272                 data |= 1;
1273         else
1274                 data &= ~1;
1275
1276         if (temp != data)
1277                 WREG32(0x157a, data);
1278 }
1279
1280
1281 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1282                                                     bool enable)
1283 {
1284         uint32_t temp, data;
1285
1286         temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1287
1288         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1289                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1290                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1291         else
1292                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1293                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1294
1295         if (temp != data)
1296                 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1297 }
1298
1299 static int vi_common_set_clockgating_state_by_smu(void *handle,
1300                                            enum amd_clockgating_state state)
1301 {
1302         uint32_t msg_id, pp_state = 0;
1303         uint32_t pp_support_state = 0;
1304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305         void *pp_handle = adev->powerplay.pp_handle;
1306
1307         if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1308                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1309                         pp_support_state = AMD_CG_SUPPORT_MC_LS;
1310                         pp_state = PP_STATE_LS;
1311                 }
1312                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1313                         pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
1314                         pp_state |= PP_STATE_CG;
1315                 }
1316                 if (state == AMD_CG_STATE_UNGATE)
1317                         pp_state = 0;
1318                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1319                                PP_BLOCK_SYS_MC,
1320                                pp_support_state,
1321                                pp_state);
1322                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1323         }
1324
1325         if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1326                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1327                         pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
1328                         pp_state = PP_STATE_LS;
1329                 }
1330                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1331                         pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
1332                         pp_state |= PP_STATE_CG;
1333                 }
1334                 if (state == AMD_CG_STATE_UNGATE)
1335                         pp_state = 0;
1336                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1337                                PP_BLOCK_SYS_SDMA,
1338                                pp_support_state,
1339                                pp_state);
1340                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1341         }
1342
1343         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1344                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1345                         pp_support_state = AMD_CG_SUPPORT_HDP_LS;
1346                         pp_state = PP_STATE_LS;
1347                 }
1348                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1349                         pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
1350                         pp_state |= PP_STATE_CG;
1351                 }
1352                 if (state == AMD_CG_STATE_UNGATE)
1353                         pp_state = 0;
1354                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1355                                PP_BLOCK_SYS_HDP,
1356                                pp_support_state,
1357                                pp_state);
1358                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1359         }
1360
1361
1362         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1363                 if (state == AMD_CG_STATE_UNGATE)
1364                         pp_state = 0;
1365                 else
1366                         pp_state = PP_STATE_LS;
1367
1368                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1369                                PP_BLOCK_SYS_BIF,
1370                                PP_STATE_SUPPORT_LS,
1371                                 pp_state);
1372                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1373         }
1374         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1375                 if (state == AMD_CG_STATE_UNGATE)
1376                         pp_state = 0;
1377                 else
1378                         pp_state = PP_STATE_CG;
1379
1380                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1381                                PP_BLOCK_SYS_BIF,
1382                                PP_STATE_SUPPORT_CG,
1383                                pp_state);
1384                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1385         }
1386
1387         if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1388
1389                 if (state == AMD_CG_STATE_UNGATE)
1390                         pp_state = 0;
1391                 else
1392                         pp_state = PP_STATE_LS;
1393
1394                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1395                                PP_BLOCK_SYS_DRM,
1396                                PP_STATE_SUPPORT_LS,
1397                                pp_state);
1398                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1399         }
1400
1401         if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1402
1403                 if (state == AMD_CG_STATE_UNGATE)
1404                         pp_state = 0;
1405                 else
1406                         pp_state = PP_STATE_CG;
1407
1408                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1409                                PP_BLOCK_SYS_ROM,
1410                                PP_STATE_SUPPORT_CG,
1411                                pp_state);
1412                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1413         }
1414         return 0;
1415 }
1416
1417 static int vi_common_set_clockgating_state(void *handle,
1418                                            enum amd_clockgating_state state)
1419 {
1420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421
1422         if (amdgpu_sriov_vf(adev))
1423                 return 0;
1424
1425         switch (adev->asic_type) {
1426         case CHIP_FIJI:
1427                 vi_update_bif_medium_grain_light_sleep(adev,
1428                                 state == AMD_CG_STATE_GATE);
1429                 vi_update_hdp_medium_grain_clock_gating(adev,
1430                                 state == AMD_CG_STATE_GATE);
1431                 vi_update_hdp_light_sleep(adev,
1432                                 state == AMD_CG_STATE_GATE);
1433                 vi_update_rom_medium_grain_clock_gating(adev,
1434                                 state == AMD_CG_STATE_GATE);
1435                 break;
1436         case CHIP_CARRIZO:
1437         case CHIP_STONEY:
1438                 vi_update_bif_medium_grain_light_sleep(adev,
1439                                 state == AMD_CG_STATE_GATE);
1440                 vi_update_hdp_medium_grain_clock_gating(adev,
1441                                 state == AMD_CG_STATE_GATE);
1442                 vi_update_hdp_light_sleep(adev,
1443                                 state == AMD_CG_STATE_GATE);
1444                 vi_update_drm_light_sleep(adev,
1445                                 state == AMD_CG_STATE_GATE);
1446                 break;
1447         case CHIP_TONGA:
1448         case CHIP_POLARIS10:
1449         case CHIP_POLARIS11:
1450         case CHIP_POLARIS12:
1451                 vi_common_set_clockgating_state_by_smu(adev, state);
1452         default:
1453                 break;
1454         }
1455         return 0;
1456 }
1457
1458 static int vi_common_set_powergating_state(void *handle,
1459                                             enum amd_powergating_state state)
1460 {
1461         return 0;
1462 }
1463
1464 static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1465 {
1466         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1467         int data;
1468
1469         if (amdgpu_sriov_vf(adev))
1470                 *flags = 0;
1471
1472         /* AMD_CG_SUPPORT_BIF_LS */
1473         data = RREG32_PCIE(ixPCIE_CNTL2);
1474         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1475                 *flags |= AMD_CG_SUPPORT_BIF_LS;
1476
1477         /* AMD_CG_SUPPORT_HDP_LS */
1478         data = RREG32(mmHDP_MEM_POWER_LS);
1479         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1480                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1481
1482         /* AMD_CG_SUPPORT_HDP_MGCG */
1483         data = RREG32(mmHDP_HOST_PATH_CNTL);
1484         if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1485                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1486
1487         /* AMD_CG_SUPPORT_ROM_MGCG */
1488         data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1489         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1490                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1491 }
1492
1493 static const struct amd_ip_funcs vi_common_ip_funcs = {
1494         .name = "vi_common",
1495         .early_init = vi_common_early_init,
1496         .late_init = vi_common_late_init,
1497         .sw_init = vi_common_sw_init,
1498         .sw_fini = vi_common_sw_fini,
1499         .hw_init = vi_common_hw_init,
1500         .hw_fini = vi_common_hw_fini,
1501         .suspend = vi_common_suspend,
1502         .resume = vi_common_resume,
1503         .is_idle = vi_common_is_idle,
1504         .wait_for_idle = vi_common_wait_for_idle,
1505         .soft_reset = vi_common_soft_reset,
1506         .set_clockgating_state = vi_common_set_clockgating_state,
1507         .set_powergating_state = vi_common_set_powergating_state,
1508         .get_clockgating_state = vi_common_get_clockgating_state,
1509 };
1510
1511 static const struct amdgpu_ip_block_version vi_common_ip_block =
1512 {
1513         .type = AMD_IP_BLOCK_TYPE_COMMON,
1514         .major = 1,
1515         .minor = 0,
1516         .rev = 0,
1517         .funcs = &vi_common_ip_funcs,
1518 };
1519
1520 int vi_set_ip_blocks(struct amdgpu_device *adev)
1521 {
1522         /* in early init stage, vbios code won't work */
1523         vi_detect_hw_virtualization(adev);
1524
1525         if (amdgpu_sriov_vf(adev))
1526                 adev->virt.ops = &xgpu_vi_virt_ops;
1527
1528         switch (adev->asic_type) {
1529         case CHIP_TOPAZ:
1530                 /* topaz has no DCE, UVD, VCE */
1531                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1532                 amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block);
1533                 amdgpu_ip_block_add(adev, &iceland_ih_ip_block);
1534                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1535                 if (adev->enable_virtual_display)
1536                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1537                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1538                 amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block);
1539                 break;
1540         case CHIP_FIJI:
1541                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1542                 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
1543                 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1544                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1545                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1546                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1547                 else
1548                         amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
1549                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1550                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1551                 if (!amdgpu_sriov_vf(adev)) {
1552                         amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1553                         amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1554                 }
1555                 break;
1556         case CHIP_TONGA:
1557                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1558                 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1559                 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1560                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1561                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1562                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1563                 else
1564                         amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
1565                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1566                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1567                 if (!amdgpu_sriov_vf(adev)) {
1568                         amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
1569                         amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1570                 }
1571                 break;
1572         case CHIP_POLARIS11:
1573         case CHIP_POLARIS10:
1574         case CHIP_POLARIS12:
1575                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1576                 amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
1577                 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1578                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1579                 if (adev->enable_virtual_display)
1580                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1581                 else
1582                         amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
1583                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1584                 amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block);
1585                 amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block);
1586                 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1587                 break;
1588         case CHIP_CARRIZO:
1589                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1590                 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1591                 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1592                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1593                 if (adev->enable_virtual_display)
1594                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1595                 else
1596                         amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1597                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1598                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1599                 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1600                 amdgpu_ip_block_add(adev, &vce_v3_1_ip_block);
1601 #if defined(CONFIG_DRM_AMD_ACP)
1602                 amdgpu_ip_block_add(adev, &acp_ip_block);
1603 #endif
1604                 break;
1605         case CHIP_STONEY:
1606                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1607                 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1608                 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1609                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1610                 if (adev->enable_virtual_display)
1611                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1612                 else
1613                         amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1614                 amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
1615                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1616                 amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block);
1617                 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1618 #if defined(CONFIG_DRM_AMD_ACP)
1619                 amdgpu_ip_block_add(adev, &acp_ip_block);
1620 #endif
1621                 break;
1622         default:
1623                 /* FIXME: not supported yet */
1624                 return -EINVAL;
1625         }
1626
1627         return 0;
1628 }