drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/drmP.h>
  27
  28 #include "dm_services_types.h"
  29 #include "dc.h"
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_dm.h"
  33 #include "amdgpu_dm_irq.h"
  34
  35 /******************************************************************************
  36  * Private declarations.
  37  *****************************************************************************/
  38
  39 struct handler_common_data {
  40         struct list_head list;
  41         interrupt_handler handler;
  42         void *handler_arg;
  43
  44         /* DM which this handler belongs to */
  45         struct amdgpu_display_manager *dm;
  46 };
  47
  48 struct amdgpu_dm_irq_handler_data {
  49         struct handler_common_data hcd;
  50         /* DAL irq source which registered for this interrupt. */
  51         enum dc_irq_source irq_source;
  52 };
  53
  54 #define DM_IRQ_TABLE_LOCK(adev, flags) \
  55         spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
  56
  57 #define DM_IRQ_TABLE_UNLOCK(adev, flags) \
  58         spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
  59
  60 /******************************************************************************
  61  * Private functions.
  62  *****************************************************************************/
  63
  64 static void init_handler_common_data(struct handler_common_data *hcd,
  65                                      void (*ih)(void *),
  66                                      void *args,
  67                                      struct amdgpu_display_manager *dm)
  68 {
  69         hcd->handler = ih;
  70         hcd->handler_arg = args;
  71         hcd->dm = dm;
  72 }
  73
  74 /**
  75  * dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
  76  *
  77  * @work: work struct
  78  */
  79 static void dm_irq_work_func(struct work_struct *work)
  80 {
  81         struct list_head *entry;
  82         struct irq_list_head *irq_list_head =
  83                 container_of(work, struct irq_list_head, work);
  84         struct list_head *handler_list = &irq_list_head->head;
  85         struct amdgpu_dm_irq_handler_data *handler_data;
  86
  87         list_for_each(entry, handler_list) {
  88                 handler_data =
  89                         list_entry(
  90                                 entry,
  91                                 struct amdgpu_dm_irq_handler_data,
  92                                 hcd.list);
  93
  94                 DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
  95                                 handler_data->irq_source);
  96
  97                 DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
  98                         handler_data->irq_source);
  99
 100                 handler_data->hcd.handler(handler_data->hcd.handler_arg);
 101         }
 102
 103         /* Call a DAL subcomponent which registered for interrupt notification
 104          * at INTERRUPT_LOW_IRQ_CONTEXT.
 105          * (The most common use is HPD interrupt) */
 106 }
 107
 108 /**
 109  * Remove a handler and return a pointer to hander list from which the
 110  * handler was removed.
 111  */
 112 static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
 113                                             void *ih,
 114                                             const struct dc_interrupt_params *int_params)
 115 {
 116         struct list_head *hnd_list;
 117         struct list_head *entry, *tmp;
 118         struct amdgpu_dm_irq_handler_data *handler;
 119         unsigned long irq_table_flags;
 120         bool handler_removed = false;
 121         enum dc_irq_source irq_source;
 122
 123         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 124
 125         irq_source = int_params->irq_source;
 126
 127         switch (int_params->int_context) {
 128         case INTERRUPT_HIGH_IRQ_CONTEXT:
 129                 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
 130                 break;
 131         case INTERRUPT_LOW_IRQ_CONTEXT:
 132         default:
 133                 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
 134                 break;
 135         }
 136
 137         list_for_each_safe(entry, tmp, hnd_list) {
 138
 139                 handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
 140                                 hcd.list);
 141
 142                 if (ih == handler) {
 143                         /* Found our handler. Remove it from the list. */
 144                         list_del(&handler->hcd.list);
 145                         handler_removed = true;
 146                         break;
 147                 }
 148         }
 149
 150         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 151
 152         if (handler_removed == false) {
 153                 /* Not necessarily an error - caller may not
 154                  * know the context. */
 155                 return NULL;
 156         }
 157
 158         kfree(handler);
 159
 160         DRM_DEBUG_KMS(
 161         "DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
 162                 ih, int_params->irq_source, int_params->int_context);
 163
 164         return hnd_list;
 165 }
 166
 167 static bool
 168 validate_irq_registration_params(struct dc_interrupt_params *int_params,
 169                                  void (*ih)(void *))
 170 {
 171         if (NULL == int_params || NULL == ih) {
 172                 DRM_ERROR("DM_IRQ: invalid input!\n");
 173                 return false;
 174         }
 175
 176         if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
 177                 DRM_ERROR("DM_IRQ: invalid context: %d!\n",
 178                                 int_params->int_context);
 179                 return false;
 180         }
 181
 182         if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
 183                 DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
 184                                 int_params->irq_source);
 185                 return false;
 186         }
 187
 188         return true;
 189 }
 190
 191 static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
 192                                                irq_handler_idx handler_idx)
 193 {
 194         if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
 195                 DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
 196                 return false;
 197         }
 198
 199         if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
 200                 DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
 201                 return false;
 202         }
 203
 204         return true;
 205 }
 206 /******************************************************************************
 207  * Public functions.
 208  *
 209  * Note: caller is responsible for input validation.
 210  *****************************************************************************/
 211
 212 void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
 213                                        struct dc_interrupt_params *int_params,
 214                                        void (*ih)(void *),
 215                                        void *handler_args)
 216 {
 217         struct list_head *hnd_list;
 218         struct amdgpu_dm_irq_handler_data *handler_data;
 219         unsigned long irq_table_flags;
 220         enum dc_irq_source irq_source;
 221
 222         if (false == validate_irq_registration_params(int_params, ih))
 223                 return DAL_INVALID_IRQ_HANDLER_IDX;
 224
 225         handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
 226         if (!handler_data) {
 227                 DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
 228                 return DAL_INVALID_IRQ_HANDLER_IDX;
 229         }
 230
 231         memset(handler_data, 0, sizeof(*handler_data));
 232
 233         init_handler_common_data(&handler_data->hcd, ih, handler_args,
 234                         &adev->dm);
 235
 236         irq_source = int_params->irq_source;
 237
 238         handler_data->irq_source = irq_source;
 239
 240         /* Lock the list, add the handler. */
 241         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 242
 243         switch (int_params->int_context) {
 244         case INTERRUPT_HIGH_IRQ_CONTEXT:
 245                 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
 246                 break;
 247         case INTERRUPT_LOW_IRQ_CONTEXT:
 248         default:
 249                 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
 250                 break;
 251         }
 252
 253         list_add_tail(&handler_data->hcd.list, hnd_list);
 254
 255         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 256
 257         /* This pointer will be stored by code which requested interrupt
 258          * registration.
 259          * The same pointer will be needed in order to unregister the
 260          * interrupt. */
 261
 262         DRM_DEBUG_KMS(
 263                 "DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
 264                 handler_data,
 265                 irq_source,
 266                 int_params->int_context);
 267
 268         return handler_data;
 269 }
 270
 271 void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
 272                                         enum dc_irq_source irq_source,
 273                                         void *ih)
 274 {
 275         struct list_head *handler_list;
 276         struct dc_interrupt_params int_params;
 277         int i;
 278
 279         if (false == validate_irq_unregistration_params(irq_source, ih))
 280                 return;
 281
 282         memset(&int_params, 0, sizeof(int_params));
 283
 284         int_params.irq_source = irq_source;
 285
 286         for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
 287
 288                 int_params.int_context = i;
 289
 290                 handler_list = remove_irq_handler(adev, ih, &int_params);
 291
 292                 if (handler_list != NULL)
 293                         break;
 294         }
 295
 296         if (handler_list == NULL) {
 297                 /* If we got here, it means we searched all irq contexts
 298                  * for this irq source, but the handler was not found. */
 299                 DRM_ERROR(
 300                 "DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
 301                         ih, irq_source);
 302         }
 303 }
 304
 305 int amdgpu_dm_irq_init(struct amdgpu_device *adev)
 306 {
 307         int src;
 308         struct irq_list_head *lh;
 309
 310         DRM_DEBUG_KMS("DM_IRQ\n");
 311
 312         spin_lock_init(&adev->dm.irq_handler_list_table_lock);
 313
 314         for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
 315                 /* low context handler list init */
 316                 lh = &adev->dm.irq_handler_list_low_tab[src];
 317                 INIT_LIST_HEAD(&lh->head);
 318                 INIT_WORK(&lh->work, dm_irq_work_func);
 319
 320                 /* high context handler init */
 321                 INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
 322         }
 323
 324         return 0;
 325 }
 326
 327 /* DM IRQ and timer resource release */
 328 void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
 329 {
 330         int src;
 331         struct irq_list_head *lh;
 332         unsigned long irq_table_flags;
 333         DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
 334         for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
 335                 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 336                 /* The handler was removed from the table,
 337                  * it means it is safe to flush all the 'work'
 338                  * (because no code can schedule a new one). */
 339                 lh = &adev->dm.irq_handler_list_low_tab[src];
 340                 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 341                 flush_work(&lh->work);
 342         }
 343 }
 344
 345 int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
 346 {
 347         int src;
 348         struct list_head *hnd_list_h;
 349         struct list_head *hnd_list_l;
 350         unsigned long irq_table_flags;
 351
 352         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 353
 354         DRM_DEBUG_KMS("DM_IRQ: suspend\n");
 355
 356         /**
 357          * Disable HW interrupt  for HPD and HPDRX only since FLIP and VBLANK
 358          * will be disabled from manage_dm_interrupts on disable CRTC.
 359          */
 360         for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
 361                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 362                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 363                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 364                         dc_interrupt_set(adev->dm.dc, src, false);
 365
 366                 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 367                 flush_work(&adev->dm.irq_handler_list_low_tab[src].work);
 368
 369                 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 370         }
 371
 372         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 373         return 0;
 374 }
 375
 376 int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
 377 {
 378         int src;
 379         struct list_head *hnd_list_h, *hnd_list_l;
 380         unsigned long irq_table_flags;
 381
 382         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 383
 384         DRM_DEBUG_KMS("DM_IRQ: early resume\n");
 385
 386         /* re-enable short pulse interrupts HW interrupt */
 387         for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
 388                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 389                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 390                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 391                         dc_interrupt_set(adev->dm.dc, src, true);
 392         }
 393
 394         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 395
 396         return 0;
 397 }
 398
 399 int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
 400 {
 401         int src;
 402         struct list_head *hnd_list_h, *hnd_list_l;
 403         unsigned long irq_table_flags;
 404
 405         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 406
 407         DRM_DEBUG_KMS("DM_IRQ: resume\n");
 408
 409         /**
 410          * Renable HW interrupt  for HPD and only since FLIP and VBLANK
 411          * will be enabled from manage_dm_interrupts on enable CRTC.
 412          */
 413         for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
 414                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 415                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 416                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 417                         dc_interrupt_set(adev->dm.dc, src, true);
 418         }
 419
 420         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 421         return 0;
 422 }
 423
 424 /**
 425  * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
 426  * "irq_source".
 427  */
 428 static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
 429                                         enum dc_irq_source irq_source)
 430 {
 431         unsigned long irq_table_flags;
 432         struct work_struct *work = NULL;
 433
 434         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 435
 436         if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head))
 437                 work = &adev->dm.irq_handler_list_low_tab[irq_source].work;
 438
 439         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 440
 441         if (work) {
 442                 if (!schedule_work(work))
 443                         DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n",
 444                                                 irq_source);
 445         }
 446
 447 }
 448
 449 /** amdgpu_dm_irq_immediate_work
 450  *  Callback high irq work immediately, don't send to work queue
 451  */
 452 static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
 453                                          enum dc_irq_source irq_source)
 454 {
 455         struct amdgpu_dm_irq_handler_data *handler_data;
 456         struct list_head *entry;
 457         unsigned long irq_table_flags;
 458
 459         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 460
 461         list_for_each(
 462                 entry,
 463                 &adev->dm.irq_handler_list_high_tab[irq_source]) {
 464
 465                 handler_data =
 466                         list_entry(
 467                                 entry,
 468                                 struct amdgpu_dm_irq_handler_data,
 469                                 hcd.list);
 470
 471                 /* Call a subcomponent which registered for immediate
 472                  * interrupt notification */
 473                 handler_data->hcd.handler(handler_data->hcd.handler_arg);
 474         }
 475
 476         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 477 }
 478
 479 /*
 480  * amdgpu_dm_irq_handler
 481  *
 482  * Generic IRQ handler, calls all registered high irq work immediately, and
 483  * schedules work for low irq
 484  */
 485 static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
 486                                  struct amdgpu_irq_src *source,
 487                                  struct amdgpu_iv_entry *entry)
 488 {
 489
 490         enum dc_irq_source src =
 491                 dc_interrupt_to_irq_source(
 492                         adev->dm.dc,
 493                         entry->src_id,
 494                         entry->src_data[0]);
 495
 496         dc_interrupt_ack(adev->dm.dc, src);
 497
 498         /* Call high irq work immediately */
 499         amdgpu_dm_irq_immediate_work(adev, src);
 500         /*Schedule low_irq work */
 501         amdgpu_dm_irq_schedule_work(adev, src);
 502
 503         return 0;
 504 }
 505
 506 static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
 507 {
 508         switch (type) {
 509         case AMDGPU_HPD_1:
 510                 return DC_IRQ_SOURCE_HPD1;
 511         case AMDGPU_HPD_2:
 512                 return DC_IRQ_SOURCE_HPD2;
 513         case AMDGPU_HPD_3:
 514                 return DC_IRQ_SOURCE_HPD3;
 515         case AMDGPU_HPD_4:
 516                 return DC_IRQ_SOURCE_HPD4;
 517         case AMDGPU_HPD_5:
 518                 return DC_IRQ_SOURCE_HPD5;
 519         case AMDGPU_HPD_6:
 520                 return DC_IRQ_SOURCE_HPD6;
 521         default:
 522                 return DC_IRQ_SOURCE_INVALID;
 523         }
 524 }
 525
 526 static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
 527                                        struct amdgpu_irq_src *source,
 528                                        unsigned type,
 529                                        enum amdgpu_interrupt_state state)
 530 {
 531         enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
 532         bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
 533
 534         dc_interrupt_set(adev->dm.dc, src, st);
 535         return 0;
 536 }
 537
 538 static inline int dm_irq_state(struct amdgpu_device *adev,
 539                                struct amdgpu_irq_src *source,
 540                                unsigned crtc_id,
 541                                enum amdgpu_interrupt_state state,
 542                                const enum irq_type dal_irq_type,
 543                                const char *func)
 544 {
 545         bool st;
 546         enum dc_irq_source irq_source;
 547
 548         struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
 549
 550         if (!acrtc) {
 551                 DRM_ERROR(
 552                         "%s: crtc is NULL at id :%d\n",
 553                         func,
 554                         crtc_id);
 555                 return 0;
 556         }
 557
 558         if (acrtc->otg_inst == -1)
 559                 return 0;
 560
 561         irq_source = dal_irq_type + acrtc->otg_inst;
 562
 563         st = (state == AMDGPU_IRQ_STATE_ENABLE);
 564
 565         dc_interrupt_set(adev->dm.dc, irq_source, st);
 566         return 0;
 567 }
 568
 569 static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
 570                                          struct amdgpu_irq_src *source,
 571                                          unsigned crtc_id,
 572                                          enum amdgpu_interrupt_state state)
 573 {
 574         return dm_irq_state(
 575                 adev,
 576                 source,
 577                 crtc_id,
 578                 state,
 579                 IRQ_TYPE_PFLIP,
 580                 __func__);
 581 }
 582
 583 static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
 584                                         struct amdgpu_irq_src *source,
 585                                         unsigned crtc_id,
 586                                         enum amdgpu_interrupt_state state)
 587 {
 588         return dm_irq_state(
 589                 adev,
 590                 source,
 591                 crtc_id,
 592                 state,
 593                 IRQ_TYPE_VBLANK,
 594                 __func__);
 595 }
 596
 597 static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
 598         .set = amdgpu_dm_set_crtc_irq_state,
 599         .process = amdgpu_dm_irq_handler,
 600 };
 601
 602 static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
 603         .set = amdgpu_dm_set_pflip_irq_state,
 604         .process = amdgpu_dm_irq_handler,
 605 };
 606
 607 static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
 608         .set = amdgpu_dm_set_hpd_irq_state,
 609         .process = amdgpu_dm_irq_handler,
 610 };
 611
 612 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
 613 {
 614
 615         adev->crtc_irq.num_types = adev->mode_info.num_crtc;
 616         adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
 617
 618         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
 619         adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
 620
 621         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
 622         adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
 623 }
 624
 625 /*
 626  * amdgpu_dm_hpd_init - hpd setup callback.
 627  *
 628  * @adev: amdgpu_device pointer
 629  *
 630  * Setup the hpd pins used by the card (evergreen+).
 631  * Enable the pin, set the polarity, and enable the hpd interrupts.
 632  */
 633 void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
 634 {
 635         struct drm_device *dev = adev->ddev;
 636         struct drm_connector *connector;
 637
 638         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 639                 struct amdgpu_dm_connector *amdgpu_dm_connector =
 640                                 to_amdgpu_dm_connector(connector);
 641
 642                 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
 643
 644                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
 645                         dc_interrupt_set(adev->dm.dc,
 646                                         dc_link->irq_source_hpd,
 647                                         true);
 648                 }
 649
 650                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
 651                         dc_interrupt_set(adev->dm.dc,
 652                                         dc_link->irq_source_hpd_rx,
 653                                         true);
 654                 }
 655         }
 656 }
 657
 658 /**
 659  * amdgpu_dm_hpd_fini - hpd tear down callback.
 660  *
 661  * @adev: amdgpu_device pointer
 662  *
 663  * Tear down the hpd pins used by the card (evergreen+).
 664  * Disable the hpd interrupts.
 665  */
 666 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
 667 {
 668         struct drm_device *dev = adev->ddev;
 669         struct drm_connector *connector;
 670
 671         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 672                 struct amdgpu_dm_connector *amdgpu_dm_connector =
 673                                 to_amdgpu_dm_connector(connector);
 674                 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
 675
 676                 dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
 677
 678                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
 679                         dc_interrupt_set(adev->dm.dc,
 680                                         dc_link->irq_source_hpd_rx,
 681                                         false);
 682                 }
 683         }
 684 }