drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "atom.h"
  29
  30 #include "include/bios_parser_types.h"
  31
  32 #include "../command_table_helper2.h"
  33
  34 static uint8_t phy_id_to_atom(enum transmitter t)
  35 {
  36         uint8_t atom_phy_id;
  37
  38         switch (t) {
  39         case TRANSMITTER_UNIPHY_A:
  40                 atom_phy_id = ATOM_PHY_ID_UNIPHYA;
  41                 break;
  42         case TRANSMITTER_UNIPHY_B:
  43                 atom_phy_id = ATOM_PHY_ID_UNIPHYB;
  44                 break;
  45         case TRANSMITTER_UNIPHY_C:
  46                 atom_phy_id = ATOM_PHY_ID_UNIPHYC;
  47                 break;
  48         case TRANSMITTER_UNIPHY_D:
  49                 atom_phy_id = ATOM_PHY_ID_UNIPHYD;
  50                 break;
  51         case TRANSMITTER_UNIPHY_E:
  52                 atom_phy_id = ATOM_PHY_ID_UNIPHYE;
  53                 break;
  54         case TRANSMITTER_UNIPHY_F:
  55                 atom_phy_id = ATOM_PHY_ID_UNIPHYF;
  56                 break;
  57         case TRANSMITTER_UNIPHY_G:
  58                 atom_phy_id = ATOM_PHY_ID_UNIPHYG;
  59                 break;
  60         default:
  61                 atom_phy_id = ATOM_PHY_ID_UNIPHYA;
  62                 break;
  63         }
  64         return atom_phy_id;
  65 }
  66
  67 static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
  68 {
  69         uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
  70
  71         switch (s) {
  72         case SIGNAL_TYPE_DISPLAY_PORT:
  73         case SIGNAL_TYPE_EDP:
  74                 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
  75                 break;
  76         case SIGNAL_TYPE_DVI_SINGLE_LINK:
  77         case SIGNAL_TYPE_DVI_DUAL_LINK:
  78                 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
  79                 break;
  80         case SIGNAL_TYPE_HDMI_TYPE_A:
  81                 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI;
  82                 break;
  83         case SIGNAL_TYPE_DISPLAY_PORT_MST:
  84                 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST;
  85                 break;
  86         default:
  87                 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
  88                 break;
  89         }
  90
  91         return atom_dig_mode;
  92 }
  93
  94 static uint8_t clock_source_id_to_atom_phy_clk_src_id(
  95                 enum clock_source_id id)
  96 {
  97         uint8_t atom_phy_clk_src_id = 0;
  98
  99         switch (id) {
 100         case CLOCK_SOURCE_ID_PLL0:
 101                 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
 102                 break;
 103         case CLOCK_SOURCE_ID_PLL1:
 104                 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
 105                 break;
 106         case CLOCK_SOURCE_ID_PLL2:
 107                 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
 108                 break;
 109         case CLOCK_SOURCE_ID_EXTERNAL:
 110                 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
 111                 break;
 112         default:
 113                 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
 114                 break;
 115         }
 116
 117         return atom_phy_clk_src_id >> 2;
 118 }
 119
 120 static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
 121 {
 122         uint8_t atom_hpd_sel = 0;
 123
 124         switch (id) {
 125         case HPD_SOURCEID1:
 126                 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD1_SEL;
 127                 break;
 128         case HPD_SOURCEID2:
 129                 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD2_SEL;
 130                 break;
 131         case HPD_SOURCEID3:
 132                 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD3_SEL;
 133                 break;
 134         case HPD_SOURCEID4:
 135                 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD4_SEL;
 136                 break;
 137         case HPD_SOURCEID5:
 138                 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD5_SEL;
 139                 break;
 140         case HPD_SOURCEID6:
 141                 atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD6_SEL;
 142                 break;
 143         case HPD_SOURCEID_UNKNOWN:
 144         default:
 145                 atom_hpd_sel = 0;
 146                 break;
 147         }
 148         return atom_hpd_sel;
 149 }
 150
 151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
 152 {
 153         uint8_t atom_dig_encoder_sel = 0;
 154
 155         switch (id) {
 156         case ENGINE_ID_DIGA:
 157                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
 158                 break;
 159         case ENGINE_ID_DIGB:
 160                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
 161                 break;
 162         case ENGINE_ID_DIGC:
 163                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
 164                 break;
 165         case ENGINE_ID_DIGD:
 166                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
 167                 break;
 168         case ENGINE_ID_DIGE:
 169                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
 170                 break;
 171         case ENGINE_ID_DIGF:
 172                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
 173                 break;
 174         case ENGINE_ID_DIGG:
 175                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
 176                 break;
 177         case ENGINE_ID_UNKNOWN:
 178                 /* No DIG_FRONT is associated to DIG_BACKEND */
 179                 atom_dig_encoder_sel = 0;
 180                 break;
 181         default:
 182                 atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
 183                 break;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static bool clock_source_id_to_atom(
 190         enum clock_source_id id,
 191         uint32_t *atom_pll_id)
 192 {
 193         bool result = true;
 194
 195         if (atom_pll_id != NULL)
 196                 switch (id) {
 197                 case CLOCK_SOURCE_COMBO_PHY_PLL0:
 198                         *atom_pll_id = ATOM_COMBOPHY_PLL0;
 199                         break;
 200                 case CLOCK_SOURCE_COMBO_PHY_PLL1:
 201                         *atom_pll_id = ATOM_COMBOPHY_PLL1;
 202                         break;
 203                 case CLOCK_SOURCE_COMBO_PHY_PLL2:
 204                         *atom_pll_id = ATOM_COMBOPHY_PLL2;
 205                         break;
 206                 case CLOCK_SOURCE_COMBO_PHY_PLL3:
 207                         *atom_pll_id = ATOM_COMBOPHY_PLL3;
 208                         break;
 209                 case CLOCK_SOURCE_COMBO_PHY_PLL4:
 210                         *atom_pll_id = ATOM_COMBOPHY_PLL4;
 211                         break;
 212                 case CLOCK_SOURCE_COMBO_PHY_PLL5:
 213                         *atom_pll_id = ATOM_COMBOPHY_PLL5;
 214                         break;
 215                 case CLOCK_SOURCE_COMBO_DISPLAY_PLL0:
 216                         *atom_pll_id = ATOM_PPLL0;
 217                         break;
 218                 case CLOCK_SOURCE_ID_DFS:
 219                         *atom_pll_id = ATOM_GCK_DFS;
 220                         break;
 221                 case CLOCK_SOURCE_ID_VCE:
 222                         *atom_pll_id = ATOM_DP_DTO;
 223                         break;
 224                 case CLOCK_SOURCE_ID_DP_DTO:
 225                         *atom_pll_id = ATOM_DP_DTO;
 226                         break;
 227                 case CLOCK_SOURCE_ID_UNDEFINED:
 228                         /* Should not happen */
 229                         *atom_pll_id = ATOM_PPLL_INVALID;
 230                         result = false;
 231                         break;
 232                 default:
 233                         result = false;
 234                         break;
 235                 }
 236
 237         return result;
 238 }
 239
 240 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
 241 {
 242         bool result = false;
 243
 244         if (atom_engine_id != NULL)
 245                 switch (id) {
 246                 case ENGINE_ID_DIGA:
 247                         *atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
 248                         result = true;
 249                         break;
 250                 case ENGINE_ID_DIGB:
 251                         *atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
 252                         result = true;
 253                         break;
 254                 case ENGINE_ID_DIGC:
 255                         *atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
 256                         result = true;
 257                         break;
 258                 case ENGINE_ID_DIGD:
 259                         *atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
 260                         result = true;
 261                         break;
 262                 case ENGINE_ID_DIGE:
 263                         *atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
 264                         result = true;
 265                         break;
 266                 case ENGINE_ID_DIGF:
 267                         *atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
 268                         result = true;
 269                         break;
 270                 case ENGINE_ID_DIGG:
 271                         *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
 272                         result = true;
 273                         break;
 274                 case ENGINE_ID_DACA:
 275                         *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
 276                         result = true;
 277                         break;
 278                 default:
 279                         break;
 280                 }
 281
 282         return result;
 283 }
 284
 285 static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
 286 {
 287         uint8_t atom_action = 0;
 288
 289         switch (action) {
 290         case ENCODER_CONTROL_ENABLE:
 291                 atom_action = ATOM_ENABLE;
 292                 break;
 293         case ENCODER_CONTROL_DISABLE:
 294                 atom_action = ATOM_DISABLE;
 295                 break;
 296         case ENCODER_CONTROL_SETUP:
 297                 atom_action = ATOM_ENCODER_CMD_STREAM_SETUP;
 298                 break;
 299         case ENCODER_CONTROL_INIT:
 300                 atom_action = ATOM_ENCODER_INIT;
 301                 break;
 302         default:
 303                 BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
 304                 break;
 305         }
 306
 307         return atom_action;
 308 }
 309
 310 static uint8_t disp_power_gating_action_to_atom(
 311         enum bp_pipe_control_action action)
 312 {
 313         uint8_t atom_pipe_action = 0;
 314
 315         switch (action) {
 316         case ASIC_PIPE_DISABLE:
 317                 atom_pipe_action = ATOM_DISABLE;
 318                 break;
 319         case ASIC_PIPE_ENABLE:
 320                 atom_pipe_action = ATOM_ENABLE;
 321                 break;
 322         case ASIC_PIPE_INIT:
 323                 atom_pipe_action = ATOM_INIT;
 324                 break;
 325         default:
 326                 ASSERT_CRITICAL(false); /* Unhandle action in driver! */
 327                 break;
 328         }
 329
 330         return atom_pipe_action;
 331 }
 332
 333 static bool dc_clock_type_to_atom(
 334                 enum bp_dce_clock_type id,
 335                 uint32_t *atom_clock_type)
 336 {
 337         bool retCode = true;
 338
 339         if (atom_clock_type != NULL) {
 340                 switch (id) {
 341                 case DCECLOCK_TYPE_DISPLAY_CLOCK:
 342                         *atom_clock_type = DCE_CLOCK_TYPE_DISPCLK;
 343                         break;
 344
 345                 case DCECLOCK_TYPE_DPREFCLK:
 346                         *atom_clock_type = DCE_CLOCK_TYPE_DPREFCLK;
 347                         break;
 348
 349                 default:
 350                         ASSERT_CRITICAL(false); /* Unhandle action in driver! */
 351                         break;
 352                 }
 353         }
 354
 355         return retCode;
 356 }
 357
 358 static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)
 359 {
 360         uint8_t atomColorDepth = 0;
 361
 362         switch (id) {
 363         case TRANSMITTER_COLOR_DEPTH_24:
 364                 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
 365                 break;
 366         case TRANSMITTER_COLOR_DEPTH_30:
 367                 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
 368                 break;
 369         case TRANSMITTER_COLOR_DEPTH_36:
 370                 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
 371                 break;
 372         case TRANSMITTER_COLOR_DEPTH_48:
 373                 atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
 374                 break;
 375         default:
 376                 ASSERT_CRITICAL(false); /* Unhandle action in driver! */
 377                 break;
 378         }
 379
 380         return atomColorDepth;
 381 }
 382
 383 /* function table */
 384 static const struct command_table_helper command_table_helper_funcs = {
 385         .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom2,
 386         .encoder_action_to_atom = encoder_action_to_atom,
 387         .engine_bp_to_atom = engine_bp_to_atom,
 388         .clock_source_id_to_atom = clock_source_id_to_atom,
 389         .clock_source_id_to_atom_phy_clk_src_id =
 390                         clock_source_id_to_atom_phy_clk_src_id,
 391         .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
 392         .hpd_sel_to_atom = hpd_sel_to_atom,
 393         .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
 394         .phy_id_to_atom = phy_id_to_atom,
 395         .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
 396         .clock_source_id_to_ref_clk_src = NULL,
 397         .transmitter_bp_to_atom = NULL,
 398         .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom2,
 399         .encoder_mode_bp_to_atom =
 400                         dal_cmd_table_helper_encoder_mode_bp_to_atom2,
 401         .dc_clock_type_to_atom = dc_clock_type_to_atom,
 402         .transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
 403 };
 404
 405 /*
 406  * dal_cmd_tbl_helper_dce110_get_table
 407  *
 408  * @brief
 409  * Initialize command table helper functions
 410  *
 411  * @param
 412  * const struct command_table_helper **h - [out] struct of functions
 413  *
 414  */
 415 const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void)
 416 {
 417         return &command_table_helper_funcs;
 418 }