drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36 #include "opp.h"
  37
  38 #include "link_encoder.h"
  39 #include "hw_sequencer.h"
  40 #include "resource.h"
  41 #include "abm.h"
  42 #include "fixed31_32.h"
  43 #include "dpcd_defs.h"
  44 #include "dmcu.h"
  45
  46 #include "dce/dce_11_0_d.h"
  47 #include "dce/dce_11_0_enum.h"
  48 #include "dce/dce_11_0_sh_mask.h"
  49
  50 #define DC_LOGGER_INIT(logger)
  51
  52
  53 #define LINK_INFO(...) \
  54         DC_LOG_HW_HOTPLUG(  \
  55                 __VA_ARGS__)
  56
  57 /*******************************************************************************
  58  * Private structures
  59  ******************************************************************************/
  60
  61 enum {
  62         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  63         PEAK_FACTOR_X1000 = 1006,
  64         /*
  65         * Some receivers fail to train on first try and are good
  66         * on subsequent tries. 2 retries should be plenty. If we
  67         * don't have a successful training then we don't expect to
  68         * ever get one.
  69         */
  70         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  71 };
  72
  73 /*******************************************************************************
  74  * Private functions
  75  ******************************************************************************/
  76 static void destruct(struct dc_link *link)
  77 {
  78         int i;
  79
  80         if (link->ddc)
  81                 dal_ddc_service_destroy(&link->ddc);
  82
  83         if(link->link_enc)
  84                 link->link_enc->funcs->destroy(&link->link_enc);
  85
  86         if (link->local_sink)
  87                 dc_sink_release(link->local_sink);
  88
  89         for (i = 0; i < link->sink_count; ++i)
  90                 dc_sink_release(link->remote_sinks[i]);
  91 }
  92
  93 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  94                 struct graphics_object_id link_id,
  95                 struct gpio_service *gpio_service)
  96 {
  97         enum bp_result bp_result;
  98         struct graphics_object_hpd_info hpd_info;
  99         struct gpio_pin_info pin_info;
 100
 101         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 102                 return NULL;
 103
 104         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 105                 hpd_info.hpd_int_gpio_uid, &pin_info);
 106
 107         if (bp_result != BP_RESULT_OK) {
 108                 ASSERT(bp_result == BP_RESULT_NORECORD);
 109                 return NULL;
 110         }
 111
 112         return dal_gpio_service_create_irq(
 113                 gpio_service,
 114                 pin_info.offset,
 115                 pin_info.mask);
 116 }
 117
 118 /*
 119  *  Function: program_hpd_filter
 120  *
 121  *  @brief
 122  *     Programs HPD filter on associated HPD line
 123  *
 124  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 125  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 126  *
 127  *  @return
 128  *     true on success, false otherwise
 129  */
 130 static bool program_hpd_filter(
 131         const struct dc_link *link)
 132 {
 133         bool result = false;
 134
 135         struct gpio *hpd;
 136
 137         int delay_on_connect_in_ms = 0;
 138         int delay_on_disconnect_in_ms = 0;
 139
 140         if (link->is_hpd_filter_disabled)
 141                 return false;
 142         /* Verify feature is supported */
 143         switch (link->connector_signal) {
 144         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 145         case SIGNAL_TYPE_DVI_DUAL_LINK:
 146         case SIGNAL_TYPE_HDMI_TYPE_A:
 147                 /* Program hpd filter */
 148                 delay_on_connect_in_ms = 500;
 149                 delay_on_disconnect_in_ms = 100;
 150                 break;
 151         case SIGNAL_TYPE_DISPLAY_PORT:
 152         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 153                 /* Program hpd filter to allow DP signal to settle */
 154                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 155                  *      only 100ms on DELL U2413
 156                  * 0:   some passive dongle still show aux mode instead of i2c
 157                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 158                  *      also see intermittent i2c read issues.
 159                  */
 160                 delay_on_connect_in_ms = 80;
 161                 delay_on_disconnect_in_ms = 0;
 162                 break;
 163         case SIGNAL_TYPE_LVDS:
 164         case SIGNAL_TYPE_EDP:
 165         default:
 166                 /* Don't program hpd filter */
 167                 return false;
 168         }
 169
 170         /* Obtain HPD handle */
 171         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 172
 173         if (!hpd)
 174                 return result;
 175
 176         /* Setup HPD filtering */
 177         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 178                 struct gpio_hpd_config config;
 179
 180                 config.delay_on_connect = delay_on_connect_in_ms;
 181                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 182
 183                 dal_irq_setup_hpd_filter(hpd, &config);
 184
 185                 dal_gpio_close(hpd);
 186
 187                 result = true;
 188         } else {
 189                 ASSERT_CRITICAL(false);
 190         }
 191
 192         /* Release HPD handle */
 193         dal_gpio_destroy_irq(&hpd);
 194
 195         return result;
 196 }
 197
 198 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 199 {
 200         uint32_t is_hpd_high = 0;
 201         struct gpio *hpd_pin;
 202
 203         /* todo: may need to lock gpio access */
 204         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 205         if (hpd_pin == NULL)
 206                 goto hpd_gpio_failure;
 207
 208         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 209         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 210         dal_gpio_close(hpd_pin);
 211         dal_gpio_destroy_irq(&hpd_pin);
 212
 213         if (is_hpd_high) {
 214                 *type = dc_connection_single;
 215                 /* TODO: need to do the actual detection */
 216         } else {
 217                 *type = dc_connection_none;
 218         }
 219
 220         return true;
 221
 222 hpd_gpio_failure:
 223         return false;
 224 }
 225
 226 static enum ddc_transaction_type get_ddc_transaction_type(
 227                 enum signal_type sink_signal)
 228 {
 229         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 230
 231         switch (sink_signal) {
 232         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 233         case SIGNAL_TYPE_DVI_DUAL_LINK:
 234         case SIGNAL_TYPE_HDMI_TYPE_A:
 235         case SIGNAL_TYPE_LVDS:
 236         case SIGNAL_TYPE_RGB:
 237                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 238                 break;
 239
 240         case SIGNAL_TYPE_DISPLAY_PORT:
 241         case SIGNAL_TYPE_EDP:
 242                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 243                 break;
 244
 245         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 246                 /* MST does not use I2COverAux, but there is the
 247                  * SPECIAL use case for "immediate dwnstrm device
 248                  * access" (EPR#370830). */
 249                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 250                 break;
 251
 252         default:
 253                 break;
 254         }
 255
 256         return transaction_type;
 257 }
 258
 259 static enum signal_type get_basic_signal_type(
 260         struct graphics_object_id encoder,
 261         struct graphics_object_id downstream)
 262 {
 263         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 264                 switch (downstream.id) {
 265                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 266                         switch (encoder.id) {
 267                         case ENCODER_ID_INTERNAL_DAC1:
 268                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 269                         case ENCODER_ID_INTERNAL_DAC2:
 270                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 271                                 return SIGNAL_TYPE_RGB;
 272                         default:
 273                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 274                         }
 275                 break;
 276                 case CONNECTOR_ID_DUAL_LINK_DVII:
 277                 {
 278                         switch (encoder.id) {
 279                         case ENCODER_ID_INTERNAL_DAC1:
 280                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 281                         case ENCODER_ID_INTERNAL_DAC2:
 282                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 283                                 return SIGNAL_TYPE_RGB;
 284                         default:
 285                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 286                         }
 287                 }
 288                 break;
 289                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 290                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 291                 case CONNECTOR_ID_DUAL_LINK_DVID:
 292                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 293                 case CONNECTOR_ID_VGA:
 294                         return SIGNAL_TYPE_RGB;
 295                 case CONNECTOR_ID_HDMI_TYPE_A:
 296                         return SIGNAL_TYPE_HDMI_TYPE_A;
 297                 case CONNECTOR_ID_LVDS:
 298                         return SIGNAL_TYPE_LVDS;
 299                 case CONNECTOR_ID_DISPLAY_PORT:
 300                         return SIGNAL_TYPE_DISPLAY_PORT;
 301                 case CONNECTOR_ID_EDP:
 302                         return SIGNAL_TYPE_EDP;
 303                 default:
 304                         return SIGNAL_TYPE_NONE;
 305                 }
 306         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 307                 switch (downstream.id) {
 308                 case ENCODER_ID_EXTERNAL_NUTMEG:
 309                 case ENCODER_ID_EXTERNAL_TRAVIS:
 310                         return SIGNAL_TYPE_DISPLAY_PORT;
 311                 default:
 312                         return SIGNAL_TYPE_NONE;
 313                 }
 314         }
 315
 316         return SIGNAL_TYPE_NONE;
 317 }
 318
 319 /*
 320  * @brief
 321  * Check whether there is a dongle on DP connector
 322  */
 323 bool dc_link_is_dp_sink_present(struct dc_link *link)
 324 {
 325         enum gpio_result gpio_result;
 326         uint32_t clock_pin = 0;
 327         uint8_t retry = 0;
 328         struct ddc *ddc;
 329
 330         enum connector_id connector_id =
 331                 dal_graphics_object_id_get_connector_id(link->link_id);
 332
 333         bool present =
 334                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 335                 (connector_id == CONNECTOR_ID_EDP));
 336
 337         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 338
 339         if (!ddc) {
 340                 BREAK_TO_DEBUGGER();
 341                 return present;
 342         }
 343
 344         /* Open GPIO and set it to I2C mode */
 345         /* Note: this GpioMode_Input will be converted
 346          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 347          * which indicates we need additional delay */
 348
 349         if (GPIO_RESULT_OK != dal_ddc_open(
 350                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 351                 dal_ddc_close(ddc);
 352
 353                 return present;
 354         }
 355
 356         /*
 357          * Read GPIO: DP sink is present if both clock and data pins are zero
 358          *
 359          * [W/A] plug-unplug DP cable, sometimes customer board has
 360          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 361          * then monitor can't br light up. Add retry 3 times
 362          * But in real passive dongle, it need additional 3ms to detect
 363          */
 364         do {
 365                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 366                 ASSERT(gpio_result == GPIO_RESULT_OK);
 367                 if (clock_pin)
 368                         udelay(1000);
 369                 else
 370                         break;
 371         } while (retry++ < 3);
 372
 373         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 374
 375         dal_ddc_close(ddc);
 376
 377         return present;
 378 }
 379
 380 /*
 381  * @brief
 382  * Detect output sink type
 383  */
 384 static enum signal_type link_detect_sink(
 385         struct dc_link *link,
 386         enum dc_detect_reason reason)
 387 {
 388         enum signal_type result = get_basic_signal_type(
 389                 link->link_enc->id, link->link_id);
 390
 391         /* Internal digital encoder will detect only dongles
 392          * that require digital signal */
 393
 394         /* Detection mechanism is different
 395          * for different native connectors.
 396          * LVDS connector supports only LVDS signal;
 397          * PCIE is a bus slot, the actual connector needs to be detected first;
 398          * eDP connector supports only eDP signal;
 399          * HDMI should check straps for audio */
 400
 401         /* PCIE detects the actual connector on add-on board */
 402
 403         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 404                 /* ZAZTODO implement PCIE add-on card detection */
 405         }
 406
 407         switch (link->link_id.id) {
 408         case CONNECTOR_ID_HDMI_TYPE_A: {
 409                 /* check audio support:
 410                  * if native HDMI is not supported, switch to DVI */
 411                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 412
 413                 if (!aud_support->hdmi_audio_native)
 414                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 415                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 416         }
 417         break;
 418         case CONNECTOR_ID_DISPLAY_PORT: {
 419                 /* DP HPD short pulse. Passive DP dongle will not
 420                  * have short pulse
 421                  */
 422                 if (reason != DETECT_REASON_HPDRX) {
 423                         /* Check whether DP signal detected: if not -
 424                          * we assume signal is DVI; it could be corrected
 425                          * to HDMI after dongle detection
 426                          */
 427                         if (!dm_helpers_is_dp_sink_present(link))
 428                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 429                 }
 430         }
 431         break;
 432         default:
 433         break;
 434         }
 435
 436         return result;
 437 }
 438
 439 static enum signal_type decide_signal_from_strap_and_dongle_type(
 440                 enum display_dongle_type dongle_type,
 441                 struct audio_support *audio_support)
 442 {
 443         enum signal_type signal = SIGNAL_TYPE_NONE;
 444
 445         switch (dongle_type) {
 446         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 447                 if (audio_support->hdmi_audio_on_dongle)
 448                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 449                 else
 450                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 451                 break;
 452         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 453                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 454                 break;
 455         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 456                 if (audio_support->hdmi_audio_native)
 457                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 458                 else
 459                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 460                 break;
 461         default:
 462                 signal = SIGNAL_TYPE_NONE;
 463                 break;
 464         }
 465
 466         return signal;
 467 }
 468
 469 static enum signal_type dp_passive_dongle_detection(
 470                 struct ddc_service *ddc,
 471                 struct display_sink_capability *sink_cap,
 472                 struct audio_support *audio_support)
 473 {
 474         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 475                                                 ddc, sink_cap);
 476         return decide_signal_from_strap_and_dongle_type(
 477                         sink_cap->dongle_type,
 478                         audio_support);
 479 }
 480
 481 static void link_disconnect_sink(struct dc_link *link)
 482 {
 483         if (link->local_sink) {
 484                 dc_sink_release(link->local_sink);
 485                 link->local_sink = NULL;
 486         }
 487
 488         link->dpcd_sink_count = 0;
 489 }
 490
 491 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 492 {
 493         dc_sink_release(link->local_sink);
 494         link->local_sink = prev_sink;
 495 }
 496
 497
 498 static bool detect_dp(
 499         struct dc_link *link,
 500         struct display_sink_capability *sink_caps,
 501         bool *converter_disable_audio,
 502         struct audio_support *audio_support,
 503         enum dc_detect_reason reason)
 504 {
 505         bool boot = false;
 506         sink_caps->signal = link_detect_sink(link, reason);
 507         sink_caps->transaction_type =
 508                 get_ddc_transaction_type(sink_caps->signal);
 509
 510         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 511                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 512                 if (!detect_dp_sink_caps(link))
 513                         return false;
 514
 515                 if (is_mst_supported(link)) {
 516                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 517                         link->type = dc_connection_mst_branch;
 518
 519                         dal_ddc_service_set_transaction_type(
 520                                                         link->ddc,
 521                                                         sink_caps->transaction_type);
 522
 523                         /*
 524                          * This call will initiate MST topology discovery. Which
 525                          * will detect MST ports and add new DRM connector DRM
 526                          * framework. Then read EDID via remote i2c over aux. In
 527                          * the end, will notify DRM detect result and save EDID
 528                          * into DRM framework.
 529                          *
 530                          * .detect is called by .fill_modes.
 531                          * .fill_modes is called by user mode ioctl
 532                          * DRM_IOCTL_MODE_GETCONNECTOR.
 533                          *
 534                          * .get_modes is called by .fill_modes.
 535                          *
 536                          * call .get_modes, AMDGPU DM implementation will create
 537                          * new dc_sink and add to dc_link. For long HPD plug
 538                          * in/out, MST has its own handle.
 539                          *
 540                          * Therefore, just after dc_create, link->sink is not
 541                          * created for MST until user mode app calls
 542                          * DRM_IOCTL_MODE_GETCONNECTOR.
 543                          *
 544                          * Need check ->sink usages in case ->sink = NULL
 545                          * TODO: s3 resume check
 546                          */
 547                         if (reason == DETECT_REASON_BOOT)
 548                                 boot = true;
 549
 550                         dm_helpers_dp_update_branch_info(
 551                                 link->ctx,
 552                                 link);
 553
 554                         if (!dm_helpers_dp_mst_start_top_mgr(
 555                                 link->ctx,
 556                                 link, boot)) {
 557                                 /* MST not supported */
 558                                 link->type = dc_connection_single;
 559                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 560                         }
 561                 }
 562
 563                 if (link->type != dc_connection_mst_branch &&
 564                         is_dp_active_dongle(link)) {
 565                         /* DP active dongles */
 566                         link->type = dc_connection_active_dongle;
 567                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 568                                 /*
 569                                  * active dongle unplug processing for short irq
 570                                  */
 571                                 link_disconnect_sink(link);
 572                                 return true;
 573                         }
 574
 575                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 576                                 *converter_disable_audio = true;
 577                 }
 578         } else {
 579                 /* DP passive dongles */
 580                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 581                                 sink_caps,
 582                                 audio_support);
 583         }
 584
 585         return true;
 586 }
 587
 588 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 589 {
 590         if (old_edid->length != new_edid->length)
 591                 return false;
 592
 593         if (new_edid->length == 0)
 594                 return false;
 595
 596         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 597 }
 598
 599 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 600 {
 601         struct dc_sink_init_data sink_init_data = { 0 };
 602         struct display_sink_capability sink_caps = { 0 };
 603         uint8_t i;
 604         bool converter_disable_audio = false;
 605         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 606         bool same_edid = false;
 607         enum dc_edid_status edid_status;
 608         struct dc_context *dc_ctx = link->ctx;
 609         struct dc_sink *sink = NULL;
 610         struct dc_sink *prev_sink = NULL;
 611         struct dpcd_caps prev_dpcd_caps;
 612         bool same_dpcd = true;
 613         enum dc_connection_type new_connection_type = dc_connection_none;
 614         DC_LOGGER_INIT(link->ctx->logger);
 615         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 616                 return false;
 617
 618         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 619                 BREAK_TO_DEBUGGER();
 620                 return false;
 621         }
 622
 623         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 624                         link->local_sink)
 625                 return true;
 626
 627         prev_sink = link->local_sink;
 628         if (prev_sink != NULL) {
 629                 dc_sink_retain(prev_sink);
 630                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 631         }
 632         link_disconnect_sink(link);
 633
 634         if (new_connection_type != dc_connection_none) {
 635                 link->type = new_connection_type;
 636
 637                 /* From Disconnected-to-Connected. */
 638                 switch (link->connector_signal) {
 639                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 640                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 641                         if (aud_support->hdmi_audio_native)
 642                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 643                         else
 644                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 645                         break;
 646                 }
 647
 648                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 649                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 650                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 651                         break;
 652                 }
 653
 654                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 655                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 656                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 657                         break;
 658                 }
 659
 660                 case SIGNAL_TYPE_EDP: {
 661                         detect_edp_sink_caps(link);
 662                         sink_caps.transaction_type =
 663                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 664                         sink_caps.signal = SIGNAL_TYPE_EDP;
 665                         break;
 666                 }
 667
 668                 case SIGNAL_TYPE_DISPLAY_PORT: {
 669                         if (!detect_dp(
 670                                 link,
 671                                 &sink_caps,
 672                                 &converter_disable_audio,
 673                                 aud_support, reason)) {
 674                                 if (prev_sink != NULL)
 675                                         dc_sink_release(prev_sink);
 676                                 return false;
 677                         }
 678
 679                         // Check if dpcp block is the same
 680                         if (prev_sink != NULL) {
 681                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 682                                         same_dpcd = false;
 683                         }
 684                         /* Active dongle downstream unplug */
 685                         if (link->type == dc_connection_active_dongle
 686                                         && link->dpcd_caps.sink_count.
 687                                         bits.SINK_COUNT == 0) {
 688                                 if (prev_sink != NULL)
 689                                         dc_sink_release(prev_sink);
 690                                 return true;
 691                         }
 692
 693                         if (link->type == dc_connection_mst_branch) {
 694                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 695                                         link->link_index);
 696                                 /* Need to setup mst link_cap struct here
 697                                  * otherwise dc_link_detect() will leave mst link_cap
 698                                  * empty which leads to allocate_mst_payload() has "0"
 699                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 700                                  */
 701                                 link->verified_link_cap = link->reported_link_cap;
 702                                 if (prev_sink != NULL)
 703                                         dc_sink_release(prev_sink);
 704                                 return false;
 705                         }
 706
 707                         break;
 708                 }
 709
 710                 default:
 711                         DC_ERROR("Invalid connector type! signal:%d\n",
 712                                 link->connector_signal);
 713                         if (prev_sink != NULL)
 714                                 dc_sink_release(prev_sink);
 715                         return false;
 716                 } /* switch() */
 717
 718                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 719                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 720                                         bits.SINK_COUNT;
 721                 else
 722                         link->dpcd_sink_count = 1;
 723
 724                 dal_ddc_service_set_transaction_type(
 725                                                 link->ddc,
 726                                                 sink_caps.transaction_type);
 727
 728                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 729                                 link->ddc);
 730
 731                 sink_init_data.link = link;
 732                 sink_init_data.sink_signal = sink_caps.signal;
 733
 734                 sink = dc_sink_create(&sink_init_data);
 735                 if (!sink) {
 736                         DC_ERROR("Failed to create sink!\n");
 737                         if (prev_sink != NULL)
 738                                 dc_sink_release(prev_sink);
 739                         return false;
 740                 }
 741
 742                 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 743                 sink->converter_disable_audio = converter_disable_audio;
 744
 745                 link->local_sink = sink;
 746
 747                 edid_status = dm_helpers_read_local_edid(
 748                                 link->ctx,
 749                                 link,
 750                                 sink);
 751
 752                 switch (edid_status) {
 753                 case EDID_BAD_CHECKSUM:
 754                         DC_LOG_ERROR("EDID checksum invalid.\n");
 755                         break;
 756                 case EDID_NO_RESPONSE:
 757                         DC_LOG_ERROR("No EDID read.\n");
 758
 759                         /*
 760                          * Abort detection for non-DP connectors if we have
 761                          * no EDID
 762                          *
 763                          * DP needs to report as connected if HDP is high
 764                          * even if we have no EDID in order to go to
 765                          * fail-safe mode
 766                          */
 767                         if (dc_is_hdmi_signal(link->connector_signal) ||
 768                             dc_is_dvi_signal(link->connector_signal)) {
 769                                 if (prev_sink != NULL)
 770                                         dc_sink_release(prev_sink);
 771                                 link_disconnect_sink(link);
 772
 773                                 return false;
 774                         }
 775                         /*
 776                          * Abort detection for DP connectors if we have
 777                          * no EDID and connector is active converter
 778                          * as there are no display downstream
 779                          *
 780                          */
 781                         if (dc_is_dp_sst_signal(link->connector_signal) &&
 782                                 (link->dpcd_caps.dongle_type ==
 783                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER ||
 784                                 link->dpcd_caps.dongle_type ==
 785                                                 DISPLAY_DONGLE_DP_DVI_CONVERTER)) {
 786                                 if (prev_sink)
 787                                         dc_sink_release(prev_sink);
 788                                 link_disconnect_sink(link);
 789
 790                                 return false;
 791                         }
 792                 default:
 793                         break;
 794                 }
 795
 796                 // Check if edid is the same
 797                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 798                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 799
 800                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 801                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 802                         /*
 803                          * TODO debug why Dell 2413 doesn't like
 804                          *  two link trainings
 805                          */
 806
 807                         /* deal with non-mst cases */
 808                         for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
 809                                 int fail_count = 0;
 810
 811                                 dp_verify_link_cap(link,
 812                                                   &link->reported_link_cap,
 813                                                   &fail_count);
 814
 815                                 if (fail_count == 0)
 816                                         break;
 817                         }
 818
 819                 } else {
 820                         // If edid is the same, then discard new sink and revert back to original sink
 821                         if (same_edid) {
 822                                 link_disconnect_remap(prev_sink, link);
 823                                 sink = prev_sink;
 824                                 prev_sink = NULL;
 825
 826                         }
 827                 }
 828
 829                 /* HDMI-DVI Dongle */
 830                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 831                                 !sink->edid_caps.edid_hdmi)
 832                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 833
 834                 /* Connectivity log: detection */
 835                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 836                         CONN_DATA_DETECT(link,
 837                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 838                                         EDID_BLOCK_SIZE,
 839                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 840                 }
 841
 842                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 843                         "manufacturer_id = %X, "
 844                         "product_id = %X, "
 845                         "serial_number = %X, "
 846                         "manufacture_week = %d, "
 847                         "manufacture_year = %d, "
 848                         "display_name = %s, "
 849                         "speaker_flag = %d, "
 850                         "audio_mode_count = %d\n",
 851                         __func__,
 852                         sink->edid_caps.manufacturer_id,
 853                         sink->edid_caps.product_id,
 854                         sink->edid_caps.serial_number,
 855                         sink->edid_caps.manufacture_week,
 856                         sink->edid_caps.manufacture_year,
 857                         sink->edid_caps.display_name,
 858                         sink->edid_caps.speaker_flags,
 859                         sink->edid_caps.audio_mode_count);
 860
 861                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 862                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 863                                 "format_code = %d, "
 864                                 "channel_count = %d, "
 865                                 "sample_rate = %d, "
 866                                 "sample_size = %d\n",
 867                                 __func__,
 868                                 i,
 869                                 sink->edid_caps.audio_modes[i].format_code,
 870                                 sink->edid_caps.audio_modes[i].channel_count,
 871                                 sink->edid_caps.audio_modes[i].sample_rate,
 872                                 sink->edid_caps.audio_modes[i].sample_size);
 873                 }
 874
 875         } else {
 876                 /* From Connected-to-Disconnected. */
 877                 if (link->type == dc_connection_mst_branch) {
 878                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 879                                 link->link_index);
 880
 881                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 882
 883                         link->mst_stream_alloc_table.stream_count = 0;
 884                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 885                 }
 886
 887                 link->type = dc_connection_none;
 888                 sink_caps.signal = SIGNAL_TYPE_NONE;
 889         }
 890
 891         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
 892                 link->link_index, sink,
 893                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 894                         "Disconnected":"Connected"), prev_sink,
 895                         same_dpcd, same_edid);
 896
 897         if (prev_sink != NULL)
 898                 dc_sink_release(prev_sink);
 899
 900         return true;
 901 }
 902
 903 static enum hpd_source_id get_hpd_line(
 904                 struct dc_link *link)
 905 {
 906         struct gpio *hpd;
 907         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 908
 909         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 910
 911         if (hpd) {
 912                 switch (dal_irq_get_source(hpd)) {
 913                 case DC_IRQ_SOURCE_HPD1:
 914                         hpd_id = HPD_SOURCEID1;
 915                 break;
 916                 case DC_IRQ_SOURCE_HPD2:
 917                         hpd_id = HPD_SOURCEID2;
 918                 break;
 919                 case DC_IRQ_SOURCE_HPD3:
 920                         hpd_id = HPD_SOURCEID3;
 921                 break;
 922                 case DC_IRQ_SOURCE_HPD4:
 923                         hpd_id = HPD_SOURCEID4;
 924                 break;
 925                 case DC_IRQ_SOURCE_HPD5:
 926                         hpd_id = HPD_SOURCEID5;
 927                 break;
 928                 case DC_IRQ_SOURCE_HPD6:
 929                         hpd_id = HPD_SOURCEID6;
 930                 break;
 931                 default:
 932                         BREAK_TO_DEBUGGER();
 933                 break;
 934                 }
 935
 936                 dal_gpio_destroy_irq(&hpd);
 937         }
 938
 939         return hpd_id;
 940 }
 941
 942 static enum channel_id get_ddc_line(struct dc_link *link)
 943 {
 944         struct ddc *ddc;
 945         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 946
 947         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 948
 949         if (ddc) {
 950                 switch (dal_ddc_get_line(ddc)) {
 951                 case GPIO_DDC_LINE_DDC1:
 952                         channel = CHANNEL_ID_DDC1;
 953                         break;
 954                 case GPIO_DDC_LINE_DDC2:
 955                         channel = CHANNEL_ID_DDC2;
 956                         break;
 957                 case GPIO_DDC_LINE_DDC3:
 958                         channel = CHANNEL_ID_DDC3;
 959                         break;
 960                 case GPIO_DDC_LINE_DDC4:
 961                         channel = CHANNEL_ID_DDC4;
 962                         break;
 963                 case GPIO_DDC_LINE_DDC5:
 964                         channel = CHANNEL_ID_DDC5;
 965                         break;
 966                 case GPIO_DDC_LINE_DDC6:
 967                         channel = CHANNEL_ID_DDC6;
 968                         break;
 969                 case GPIO_DDC_LINE_DDC_VGA:
 970                         channel = CHANNEL_ID_DDC_VGA;
 971                         break;
 972                 case GPIO_DDC_LINE_I2C_PAD:
 973                         channel = CHANNEL_ID_I2C_PAD;
 974                         break;
 975                 default:
 976                         BREAK_TO_DEBUGGER();
 977                         break;
 978                 }
 979         }
 980
 981         return channel;
 982 }
 983
 984 static enum transmitter translate_encoder_to_transmitter(
 985         struct graphics_object_id encoder)
 986 {
 987         switch (encoder.id) {
 988         case ENCODER_ID_INTERNAL_UNIPHY:
 989                 switch (encoder.enum_id) {
 990                 case ENUM_ID_1:
 991                         return TRANSMITTER_UNIPHY_A;
 992                 case ENUM_ID_2:
 993                         return TRANSMITTER_UNIPHY_B;
 994                 default:
 995                         return TRANSMITTER_UNKNOWN;
 996                 }
 997         break;
 998         case ENCODER_ID_INTERNAL_UNIPHY1:
 999                 switch (encoder.enum_id) {
1000                 case ENUM_ID_1:
1001                         return TRANSMITTER_UNIPHY_C;
1002                 case ENUM_ID_2:
1003                         return TRANSMITTER_UNIPHY_D;
1004                 default:
1005                         return TRANSMITTER_UNKNOWN;
1006                 }
1007         break;
1008         case ENCODER_ID_INTERNAL_UNIPHY2:
1009                 switch (encoder.enum_id) {
1010                 case ENUM_ID_1:
1011                         return TRANSMITTER_UNIPHY_E;
1012                 case ENUM_ID_2:
1013                         return TRANSMITTER_UNIPHY_F;
1014                 default:
1015                         return TRANSMITTER_UNKNOWN;
1016                 }
1017         break;
1018         case ENCODER_ID_INTERNAL_UNIPHY3:
1019                 switch (encoder.enum_id) {
1020                 case ENUM_ID_1:
1021                         return TRANSMITTER_UNIPHY_G;
1022                 default:
1023                         return TRANSMITTER_UNKNOWN;
1024                 }
1025         break;
1026         case ENCODER_ID_EXTERNAL_NUTMEG:
1027                 switch (encoder.enum_id) {
1028                 case ENUM_ID_1:
1029                         return TRANSMITTER_NUTMEG_CRT;
1030                 default:
1031                         return TRANSMITTER_UNKNOWN;
1032                 }
1033         break;
1034         case ENCODER_ID_EXTERNAL_TRAVIS:
1035                 switch (encoder.enum_id) {
1036                 case ENUM_ID_1:
1037                         return TRANSMITTER_TRAVIS_CRT;
1038                 case ENUM_ID_2:
1039                         return TRANSMITTER_TRAVIS_LCD;
1040                 default:
1041                         return TRANSMITTER_UNKNOWN;
1042                 }
1043         break;
1044         default:
1045                 return TRANSMITTER_UNKNOWN;
1046         }
1047 }
1048
1049 static bool construct(
1050         struct dc_link *link,
1051         const struct link_init_data *init_params)
1052 {
1053         uint8_t i;
1054         struct gpio *hpd_gpio = NULL;
1055         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1056         struct dc_context *dc_ctx = init_params->ctx;
1057         struct encoder_init_data enc_init_data = { 0 };
1058         struct integrated_info info = {{{ 0 }}};
1059         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1060         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1061         DC_LOGGER_INIT(dc_ctx->logger);
1062
1063         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1064         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1065
1066         link->link_status.dpcd_caps = &link->dpcd_caps;
1067
1068         link->dc = init_params->dc;
1069         link->ctx = dc_ctx;
1070         link->link_index = init_params->link_index;
1071
1072         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1073
1074         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1075                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1076                          __func__, init_params->connector_index,
1077                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1078                 goto create_fail;
1079         }
1080
1081         if (link->dc->res_pool->funcs->link_init)
1082                 link->dc->res_pool->funcs->link_init(link);
1083
1084         hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1085
1086         if (hpd_gpio != NULL)
1087                 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1088
1089         switch (link->link_id.id) {
1090         case CONNECTOR_ID_HDMI_TYPE_A:
1091                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1092
1093                 break;
1094         case CONNECTOR_ID_SINGLE_LINK_DVID:
1095         case CONNECTOR_ID_SINGLE_LINK_DVII:
1096                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1097                 break;
1098         case CONNECTOR_ID_DUAL_LINK_DVID:
1099         case CONNECTOR_ID_DUAL_LINK_DVII:
1100                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1101                 break;
1102         case CONNECTOR_ID_DISPLAY_PORT:
1103                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1104
1105                 if (hpd_gpio != NULL)
1106                         link->irq_source_hpd_rx =
1107                                         dal_irq_get_rx_source(hpd_gpio);
1108
1109                 break;
1110         case CONNECTOR_ID_EDP:
1111                 link->connector_signal = SIGNAL_TYPE_EDP;
1112
1113                 if (hpd_gpio != NULL) {
1114                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1115                         link->irq_source_hpd_rx =
1116                                         dal_irq_get_rx_source(hpd_gpio);
1117                 }
1118                 break;
1119         default:
1120                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1121                 goto create_fail;
1122         }
1123
1124         if (hpd_gpio != NULL) {
1125                 dal_gpio_destroy_irq(&hpd_gpio);
1126                 hpd_gpio = NULL;
1127         }
1128
1129         /* TODO: #DAL3 Implement id to str function.*/
1130         LINK_INFO("Connector[%d] description:"
1131                         "signal %d\n",
1132                         init_params->connector_index,
1133                         link->connector_signal);
1134
1135         ddc_service_init_data.ctx = link->ctx;
1136         ddc_service_init_data.id = link->link_id;
1137         ddc_service_init_data.link = link;
1138         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1139
1140         if (link->ddc == NULL) {
1141                 DC_ERROR("Failed to create ddc_service!\n");
1142                 goto ddc_create_fail;
1143         }
1144
1145         if (!link->ddc->ddc_pin) {
1146                 DC_ERROR("Failed to get I2C info for connector!\n");
1147                 goto ddc_create_fail;
1148         }
1149
1150         link->ddc_hw_inst =
1151                 dal_ddc_get_line(
1152                         dal_ddc_service_get_ddc_pin(link->ddc));
1153
1154         enc_init_data.ctx = dc_ctx;
1155         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1156         enc_init_data.connector = link->link_id;
1157         enc_init_data.channel = get_ddc_line(link);
1158         enc_init_data.hpd_source = get_hpd_line(link);
1159
1160         link->hpd_src = enc_init_data.hpd_source;
1161
1162         enc_init_data.transmitter =
1163                         translate_encoder_to_transmitter(enc_init_data.encoder);
1164         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1165                                                                 &enc_init_data);
1166
1167         if( link->link_enc == NULL) {
1168                 DC_ERROR("Failed to create link encoder!\n");
1169                 goto link_enc_create_fail;
1170         }
1171
1172         link->link_enc_hw_inst = link->link_enc->transmitter;
1173
1174         for (i = 0; i < 4; i++) {
1175                 if (BP_RESULT_OK !=
1176                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1177                         DC_ERROR("Failed to find device tag!\n");
1178                         goto device_tag_fail;
1179                 }
1180
1181                 /* Look for device tag that matches connector signal,
1182                  * CRT for rgb, LCD for other supported signal tyes
1183                  */
1184                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1185                         continue;
1186                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1187                         && link->connector_signal != SIGNAL_TYPE_RGB)
1188                         continue;
1189                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1190                         && link->connector_signal == SIGNAL_TYPE_RGB)
1191                         continue;
1192                 break;
1193         }
1194
1195         if (bios->integrated_info)
1196                 info = *bios->integrated_info;
1197
1198         /* Look for channel mapping corresponding to connector and device tag */
1199         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1200                 struct external_display_path *path =
1201                         &info.ext_disp_conn_info.path[i];
1202                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1203                         && path->device_connector_id.id == link->link_id.id
1204                         && path->device_connector_id.type == link->link_id.type) {
1205
1206                         if (link->device_tag.acpi_device != 0
1207                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1208                                 link->ddi_channel_mapping = path->channel_mapping;
1209                                 link->chip_caps = path->caps;
1210                         } else if (path->device_tag ==
1211                                         link->device_tag.dev_id.raw_device_tag) {
1212                                 link->ddi_channel_mapping = path->channel_mapping;
1213                                 link->chip_caps = path->caps;
1214                         }
1215                         break;
1216                 }
1217         }
1218
1219         /*
1220          * TODO check if GPIO programmed correctly
1221          *
1222          * If GPIO isn't programmed correctly HPD might not rise or drain
1223          * fast enough, leading to bounces.
1224          */
1225         program_hpd_filter(link);
1226
1227         return true;
1228 device_tag_fail:
1229         link->link_enc->funcs->destroy(&link->link_enc);
1230 link_enc_create_fail:
1231         dal_ddc_service_destroy(&link->ddc);
1232 ddc_create_fail:
1233 create_fail:
1234
1235         if (hpd_gpio != NULL) {
1236                 dal_gpio_destroy_irq(&hpd_gpio);
1237         }
1238
1239         return false;
1240 }
1241
1242 /*******************************************************************************
1243  * Public functions
1244  ******************************************************************************/
1245 struct dc_link *link_create(const struct link_init_data *init_params)
1246 {
1247         struct dc_link *link =
1248                         kzalloc(sizeof(*link), GFP_KERNEL);
1249
1250         if (NULL == link)
1251                 goto alloc_fail;
1252
1253         if (false == construct(link, init_params))
1254                 goto construct_fail;
1255
1256         return link;
1257
1258 construct_fail:
1259         kfree(link);
1260
1261 alloc_fail:
1262         return NULL;
1263 }
1264
1265 void link_destroy(struct dc_link **link)
1266 {
1267         destruct(*link);
1268         kfree(*link);
1269         *link = NULL;
1270 }
1271
1272 static void dpcd_configure_panel_mode(
1273         struct dc_link *link,
1274         enum dp_panel_mode panel_mode)
1275 {
1276         union dpcd_edp_config edp_config_set;
1277         bool panel_mode_edp = false;
1278         DC_LOGGER_INIT(link->ctx->logger);
1279
1280         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1281
1282         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1283
1284                 switch (panel_mode) {
1285                 case DP_PANEL_MODE_EDP:
1286                 case DP_PANEL_MODE_SPECIAL:
1287                         panel_mode_edp = true;
1288                         break;
1289
1290                 default:
1291                         break;
1292                 }
1293
1294                 /*set edp panel mode in receiver*/
1295                 core_link_read_dpcd(
1296                         link,
1297                         DP_EDP_CONFIGURATION_SET,
1298                         &edp_config_set.raw,
1299                         sizeof(edp_config_set.raw));
1300
1301                 if (edp_config_set.bits.PANEL_MODE_EDP
1302                         != panel_mode_edp) {
1303                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1304
1305                         edp_config_set.bits.PANEL_MODE_EDP =
1306                         panel_mode_edp;
1307                         result = core_link_write_dpcd(
1308                                 link,
1309                                 DP_EDP_CONFIGURATION_SET,
1310                                 &edp_config_set.raw,
1311                                 sizeof(edp_config_set.raw));
1312
1313                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1314                 }
1315         }
1316         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1317                         "eDP panel mode enabled: %d \n",
1318                         link->link_index,
1319                         link->dpcd_caps.panel_mode_edp,
1320                         panel_mode_edp);
1321 }
1322
1323 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1324 {
1325         struct dc_stream_state *stream = pipe_ctx->stream;
1326         struct dc_link *link = stream->sink->link;
1327         union down_spread_ctrl old_downspread;
1328         union down_spread_ctrl new_downspread;
1329
1330         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1331                         &old_downspread.raw, sizeof(old_downspread));
1332
1333         new_downspread.raw = old_downspread.raw;
1334
1335         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1336                         (stream->ignore_msa_timing_param) ? 1 : 0;
1337
1338         if (new_downspread.raw != old_downspread.raw) {
1339                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1340                         &new_downspread.raw, sizeof(new_downspread));
1341         }
1342 }
1343
1344 static enum dc_status enable_link_dp(
1345                 struct dc_state *state,
1346                 struct pipe_ctx *pipe_ctx)
1347 {
1348         struct dc_stream_state *stream = pipe_ctx->stream;
1349         enum dc_status status;
1350         bool skip_video_pattern;
1351         struct dc_link *link = stream->sink->link;
1352         struct dc_link_settings link_settings = {0};
1353         enum dp_panel_mode panel_mode;
1354         enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
1355
1356         /* get link settings for video mode timing */
1357         decide_link_settings(stream, &link_settings);
1358
1359         /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
1360          * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
1361          */
1362         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1363                 max_link_rate = LINK_RATE_HIGH3;
1364
1365         if (link_settings.link_rate == max_link_rate) {
1366                 struct dc_clocks clocks = state->bw.dcn.clk;
1367
1368                 /* dce/dcn compat, do not update dispclk */
1369                 clocks.dispclk_khz = 0;
1370                 /* 27mhz = 27000000hz= 27000khz */
1371                 clocks.phyclk_khz = link_settings.link_rate * 27000;
1372
1373                 state->dis_clk->funcs->update_clocks(
1374                                 state->dis_clk, &clocks, false);
1375         }
1376
1377         dp_enable_link_phy(
1378                 link,
1379                 pipe_ctx->stream->signal,
1380                 pipe_ctx->clock_source->id,
1381                 &link_settings);
1382
1383         if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1384                 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1385
1386                 msleep(delay_dp_power_up_in_ms);
1387         }
1388
1389         panel_mode = dp_get_panel_mode(link);
1390         dpcd_configure_panel_mode(link, panel_mode);
1391
1392         skip_video_pattern = true;
1393
1394         if (link_settings.link_rate == LINK_RATE_LOW)
1395                         skip_video_pattern = false;
1396
1397         if (perform_link_training_with_retries(
1398                         link,
1399                         &link_settings,
1400                         skip_video_pattern,
1401                         LINK_TRAINING_ATTEMPTS)) {
1402                 link->cur_link_settings = link_settings;
1403                 status = DC_OK;
1404         }
1405         else
1406                 status = DC_FAIL_DP_LINK_TRAINING;
1407
1408         enable_stream_features(pipe_ctx);
1409
1410         return status;
1411 }
1412
1413 static enum dc_status enable_link_edp(
1414                 struct dc_state *state,
1415                 struct pipe_ctx *pipe_ctx)
1416 {
1417         enum dc_status status;
1418         struct dc_stream_state *stream = pipe_ctx->stream;
1419         struct dc_link *link = stream->sink->link;
1420         /*in case it is not on*/
1421         link->dc->hwss.edp_power_control(link, true);
1422         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1423
1424         status = enable_link_dp(state, pipe_ctx);
1425
1426
1427         return status;
1428 }
1429
1430 static enum dc_status enable_link_dp_mst(
1431                 struct dc_state *state,
1432                 struct pipe_ctx *pipe_ctx)
1433 {
1434         struct dc_link *link = pipe_ctx->stream->sink->link;
1435
1436         /* sink signal type after MST branch is MST. Multiple MST sinks
1437          * share one link. Link DP PHY is enable or training only once.
1438          */
1439         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1440                 return DC_OK;
1441
1442         /* clear payload table */
1443         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1444
1445         /* set the sink to MST mode before enabling the link */
1446         dp_enable_mst_on_sink(link, true);
1447
1448         return enable_link_dp(state, pipe_ctx);
1449 }
1450
1451 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1452                 enum engine_id eng_id,
1453                 struct ext_hdmi_settings *settings)
1454 {
1455         bool result = false;
1456         int i = 0;
1457         struct integrated_info *integrated_info =
1458                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1459
1460         if (integrated_info == NULL)
1461                 return false;
1462
1463         /*
1464          * Get retimer settings from sbios for passing SI eye test for DCE11
1465          * The setting values are varied based on board revision and port id
1466          * Therefore the setting values of each ports is passed by sbios.
1467          */
1468
1469         // Check if current bios contains ext Hdmi settings
1470         if (integrated_info->gpu_cap_info & 0x20) {
1471                 switch (eng_id) {
1472                 case ENGINE_ID_DIGA:
1473                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1474                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1475                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1476                         memmove(settings->reg_settings,
1477                                         integrated_info->dp0_ext_hdmi_reg_settings,
1478                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1479                         memmove(settings->reg_settings_6g,
1480                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1481                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1482                         result = true;
1483                         break;
1484                 case ENGINE_ID_DIGB:
1485                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1486                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1487                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1488                         memmove(settings->reg_settings,
1489                                         integrated_info->dp1_ext_hdmi_reg_settings,
1490                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1491                         memmove(settings->reg_settings_6g,
1492                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1493                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1494                         result = true;
1495                         break;
1496                 case ENGINE_ID_DIGC:
1497                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1498                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1499                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1500                         memmove(settings->reg_settings,
1501                                         integrated_info->dp2_ext_hdmi_reg_settings,
1502                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1503                         memmove(settings->reg_settings_6g,
1504                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1505                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1506                         result = true;
1507                         break;
1508                 case ENGINE_ID_DIGD:
1509                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1510                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1511                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1512                         memmove(settings->reg_settings,
1513                                         integrated_info->dp3_ext_hdmi_reg_settings,
1514                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1515                         memmove(settings->reg_settings_6g,
1516                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1517                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1518                         result = true;
1519                         break;
1520                 default:
1521                         break;
1522                 }
1523
1524                 if (result == true) {
1525                         // Validate settings from bios integrated info table
1526                         if (settings->slv_addr == 0)
1527                                 return false;
1528                         if (settings->reg_num > 9)
1529                                 return false;
1530                         if (settings->reg_num_6g > 3)
1531                                 return false;
1532
1533                         for (i = 0; i < settings->reg_num; i++) {
1534                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1535                                         return false;
1536                         }
1537
1538                         for (i = 0; i < settings->reg_num_6g; i++) {
1539                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1540                                         return false;
1541                         }
1542                 }
1543         }
1544
1545         return result;
1546 }
1547
1548 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1549                 uint8_t address, uint8_t *buffer, uint32_t length)
1550 {
1551         struct i2c_command cmd = {0};
1552         struct i2c_payload payload = {0};
1553
1554         memset(&payload, 0, sizeof(payload));
1555         memset(&cmd, 0, sizeof(cmd));
1556
1557         cmd.number_of_payloads = 1;
1558         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1559         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1560
1561         payload.address = address;
1562         payload.data = buffer;
1563         payload.length = length;
1564         payload.write = true;
1565         cmd.payloads = &payload;
1566
1567         if (dc_submit_i2c(pipe_ctx->stream->ctx->dc,
1568                         pipe_ctx->stream->sink->link->link_index, &cmd))
1569                 return true;
1570
1571         return false;
1572 }
1573
1574 static void write_i2c_retimer_setting(
1575                 struct pipe_ctx *pipe_ctx,
1576                 bool is_vga_mode,
1577                 bool is_over_340mhz,
1578                 struct ext_hdmi_settings *settings)
1579 {
1580         uint8_t slave_address = (settings->slv_addr >> 1);
1581         uint8_t buffer[2];
1582         const uint8_t apply_rx_tx_change = 0x4;
1583         uint8_t offset = 0xA;
1584         uint8_t value = 0;
1585         int i = 0;
1586         bool i2c_success = false;
1587
1588         memset(&buffer, 0, sizeof(buffer));
1589
1590         /* Start Ext-Hdmi programming*/
1591
1592         for (i = 0; i < settings->reg_num; i++) {
1593                 /* Apply 3G settings */
1594                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1595
1596                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1597                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1598                         i2c_success = i2c_write(pipe_ctx, slave_address,
1599                                                 buffer, sizeof(buffer));
1600
1601                         if (!i2c_success)
1602                                 goto i2c_write_fail;
1603
1604                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1605                          * needs to be set to 1 on every 0xA-0xC write.
1606                          */
1607                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1608                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1609                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1610
1611                                 /* Query current value from offset 0xA */
1612                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1613                                         value = settings->reg_settings[i].i2c_reg_val;
1614                                 else {
1615                                         i2c_success =
1616                                                 dal_ddc_service_query_ddc_data(
1617                                                 pipe_ctx->stream->sink->link->ddc,
1618                                                 slave_address, &offset, 1, &value, 1);
1619                                         if (!i2c_success)
1620                                                 goto i2c_write_fail;
1621                                 }
1622
1623                                 buffer[0] = offset;
1624                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1625                                 buffer[1] = value | apply_rx_tx_change;
1626                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1627                                                 buffer, sizeof(buffer));
1628                                 if (!i2c_success)
1629                                         goto i2c_write_fail;
1630                         }
1631                 }
1632         }
1633
1634         /* Apply 3G settings */
1635         if (is_over_340mhz) {
1636                 for (i = 0; i < settings->reg_num_6g; i++) {
1637                         /* Apply 3G settings */
1638                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1639
1640                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1641                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1642                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1643                                                         buffer, sizeof(buffer));
1644
1645                                 if (!i2c_success)
1646                                         goto i2c_write_fail;
1647
1648                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1649                                  * needs to be set to 1 on every 0xA-0xC write.
1650                                  */
1651                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1652                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1653                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1654
1655                                         /* Query current value from offset 0xA */
1656                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1657                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1658                                         else {
1659                                                 i2c_success =
1660                                                                 dal_ddc_service_query_ddc_data(
1661                                                                 pipe_ctx->stream->sink->link->ddc,
1662                                                                 slave_address, &offset, 1, &value, 1);
1663                                                 if (!i2c_success)
1664                                                         goto i2c_write_fail;
1665                                         }
1666
1667                                         buffer[0] = offset;
1668                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1669                                         buffer[1] = value | apply_rx_tx_change;
1670                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1671                                                         buffer, sizeof(buffer));
1672                                         if (!i2c_success)
1673                                                 goto i2c_write_fail;
1674                                 }
1675                         }
1676                 }
1677         }
1678
1679         if (is_vga_mode) {
1680                 /* Program additional settings if using 640x480 resolution */
1681
1682                 /* Write offset 0xFF to 0x01 */
1683                 buffer[0] = 0xff;
1684                 buffer[1] = 0x01;
1685                 i2c_success = i2c_write(pipe_ctx, slave_address,
1686                                 buffer, sizeof(buffer));
1687                 if (!i2c_success)
1688                         goto i2c_write_fail;
1689
1690                 /* Write offset 0x00 to 0x23 */
1691                 buffer[0] = 0x00;
1692                 buffer[1] = 0x23;
1693                 i2c_success = i2c_write(pipe_ctx, slave_address,
1694                                 buffer, sizeof(buffer));
1695                 if (!i2c_success)
1696                         goto i2c_write_fail;
1697
1698                 /* Write offset 0xff to 0x00 */
1699                 buffer[0] = 0xff;
1700                 buffer[1] = 0x00;
1701                 i2c_success = i2c_write(pipe_ctx, slave_address,
1702                                 buffer, sizeof(buffer));
1703                 if (!i2c_success)
1704                         goto i2c_write_fail;
1705
1706         }
1707
1708         return;
1709
1710 i2c_write_fail:
1711         DC_LOG_DEBUG("Set retimer failed");
1712 }
1713
1714 static void write_i2c_default_retimer_setting(
1715                 struct pipe_ctx *pipe_ctx,
1716                 bool is_vga_mode,
1717                 bool is_over_340mhz)
1718 {
1719         uint8_t slave_address = (0xBA >> 1);
1720         uint8_t buffer[2];
1721         bool i2c_success = false;
1722
1723         memset(&buffer, 0, sizeof(buffer));
1724
1725         /* Program Slave Address for tuning single integrity */
1726         /* Write offset 0x0A to 0x13 */
1727         buffer[0] = 0x0A;
1728         buffer[1] = 0x13;
1729         i2c_success = i2c_write(pipe_ctx, slave_address,
1730                         buffer, sizeof(buffer));
1731         if (!i2c_success)
1732                 goto i2c_write_fail;
1733
1734         /* Write offset 0x0A to 0x17 */
1735         buffer[0] = 0x0A;
1736         buffer[1] = 0x17;
1737         i2c_success = i2c_write(pipe_ctx, slave_address,
1738                         buffer, sizeof(buffer));
1739         if (!i2c_success)
1740                 goto i2c_write_fail;
1741
1742         /* Write offset 0x0B to 0xDA or 0xD8 */
1743         buffer[0] = 0x0B;
1744         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1745         i2c_success = i2c_write(pipe_ctx, slave_address,
1746                         buffer, sizeof(buffer));
1747         if (!i2c_success)
1748                 goto i2c_write_fail;
1749
1750         /* Write offset 0x0A to 0x17 */
1751         buffer[0] = 0x0A;
1752         buffer[1] = 0x17;
1753         i2c_success = i2c_write(pipe_ctx, slave_address,
1754                         buffer, sizeof(buffer));
1755         if (!i2c_success)
1756                 goto i2c_write_fail;
1757
1758         /* Write offset 0x0C to 0x1D or 0x91 */
1759         buffer[0] = 0x0C;
1760         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1761         i2c_success = i2c_write(pipe_ctx, slave_address,
1762                         buffer, sizeof(buffer));
1763         if (!i2c_success)
1764                 goto i2c_write_fail;
1765
1766         /* Write offset 0x0A to 0x17 */
1767         buffer[0] = 0x0A;
1768         buffer[1] = 0x17;
1769         i2c_success = i2c_write(pipe_ctx, slave_address,
1770                         buffer, sizeof(buffer));
1771         if (!i2c_success)
1772                 goto i2c_write_fail;
1773
1774
1775         if (is_vga_mode) {
1776                 /* Program additional settings if using 640x480 resolution */
1777
1778                 /* Write offset 0xFF to 0x01 */
1779                 buffer[0] = 0xff;
1780                 buffer[1] = 0x01;
1781                 i2c_success = i2c_write(pipe_ctx, slave_address,
1782                                 buffer, sizeof(buffer));
1783                 if (!i2c_success)
1784                         goto i2c_write_fail;
1785
1786                 /* Write offset 0x00 to 0x23 */
1787                 buffer[0] = 0x00;
1788                 buffer[1] = 0x23;
1789                 i2c_success = i2c_write(pipe_ctx, slave_address,
1790                                 buffer, sizeof(buffer));
1791                 if (!i2c_success)
1792                         goto i2c_write_fail;
1793
1794                 /* Write offset 0xff to 0x00 */
1795                 buffer[0] = 0xff;
1796                 buffer[1] = 0x00;
1797                 i2c_success = i2c_write(pipe_ctx, slave_address,
1798                                 buffer, sizeof(buffer));
1799                 if (!i2c_success)
1800                         goto i2c_write_fail;
1801         }
1802
1803         return;
1804
1805 i2c_write_fail:
1806         DC_LOG_DEBUG("Set default retimer failed");
1807 }
1808
1809 static void write_i2c_redriver_setting(
1810                 struct pipe_ctx *pipe_ctx,
1811                 bool is_over_340mhz)
1812 {
1813         uint8_t slave_address = (0xF0 >> 1);
1814         uint8_t buffer[16];
1815         bool i2c_success = false;
1816
1817         memset(&buffer, 0, sizeof(buffer));
1818
1819         // Program Slave Address for tuning single integrity
1820         buffer[3] = 0x4E;
1821         buffer[4] = 0x4E;
1822         buffer[5] = 0x4E;
1823         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1824
1825         i2c_success = i2c_write(pipe_ctx, slave_address,
1826                                         buffer, sizeof(buffer));
1827
1828         if (!i2c_success)
1829                 DC_LOG_DEBUG("Set redriver failed");
1830 }
1831
1832 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1833 {
1834         struct dc_stream_state *stream = pipe_ctx->stream;
1835         struct dc_link *link = stream->sink->link;
1836         enum dc_color_depth display_color_depth;
1837         enum engine_id eng_id;
1838         struct ext_hdmi_settings settings = {0};
1839         bool is_over_340mhz = false;
1840         bool is_vga_mode = (stream->timing.h_addressable == 640)
1841                         && (stream->timing.v_addressable == 480);
1842
1843         if (stream->phy_pix_clk == 0)
1844                 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1845         if (stream->phy_pix_clk > 340000)
1846                 is_over_340mhz = true;
1847
1848         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1849                 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1850                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1851                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1852                         /* DP159, Retimer settings */
1853                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1854
1855                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1856                                 write_i2c_retimer_setting(pipe_ctx,
1857                                                 is_vga_mode, is_over_340mhz, &settings);
1858                         } else {
1859                                 write_i2c_default_retimer_setting(pipe_ctx,
1860                                                 is_vga_mode, is_over_340mhz);
1861                         }
1862                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1863                         /* PI3EQX1204, Redriver settings */
1864                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1865                 }
1866         }
1867
1868         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1869                 dal_ddc_service_write_scdc_data(
1870                         stream->sink->link->ddc,
1871                         stream->phy_pix_clk,
1872                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1873
1874         memset(&stream->sink->link->cur_link_settings, 0,
1875                         sizeof(struct dc_link_settings));
1876
1877         display_color_depth = stream->timing.display_color_depth;
1878         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1879                 display_color_depth = COLOR_DEPTH_888;
1880
1881         link->link_enc->funcs->enable_tmds_output(
1882                         link->link_enc,
1883                         pipe_ctx->clock_source->id,
1884                         display_color_depth,
1885                         pipe_ctx->stream->signal,
1886                         stream->phy_pix_clk);
1887
1888         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1889                 dal_ddc_service_read_scdc_data(link->ddc);
1890 }
1891
1892 /****************************enable_link***********************************/
1893 static enum dc_status enable_link(
1894                 struct dc_state *state,
1895                 struct pipe_ctx *pipe_ctx)
1896 {
1897         enum dc_status status = DC_ERROR_UNEXPECTED;
1898         switch (pipe_ctx->stream->signal) {
1899         case SIGNAL_TYPE_DISPLAY_PORT:
1900                 status = enable_link_dp(state, pipe_ctx);
1901                 break;
1902         case SIGNAL_TYPE_EDP:
1903                 status = enable_link_edp(state, pipe_ctx);
1904                 break;
1905         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1906                 status = enable_link_dp_mst(state, pipe_ctx);
1907                 msleep(200);
1908                 break;
1909         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1910         case SIGNAL_TYPE_DVI_DUAL_LINK:
1911         case SIGNAL_TYPE_HDMI_TYPE_A:
1912                 enable_link_hdmi(pipe_ctx);
1913                 status = DC_OK;
1914                 break;
1915         case SIGNAL_TYPE_VIRTUAL:
1916                 status = DC_OK;
1917                 break;
1918         default:
1919                 break;
1920         }
1921
1922         return status;
1923 }
1924
1925 static void disable_link(struct dc_link *link, enum signal_type signal)
1926 {
1927         /*
1928          * TODO: implement call for dp_set_hw_test_pattern
1929          * it is needed for compliance testing
1930          */
1931
1932         /* here we need to specify that encoder output settings
1933          * need to be calculated as for the set mode,
1934          * it will lead to querying dynamic link capabilities
1935          * which should be done before enable output */
1936
1937         if (dc_is_dp_signal(signal)) {
1938                 /* SST DP, eDP */
1939                 if (dc_is_dp_sst_signal(signal))
1940                         dp_disable_link_phy(link, signal);
1941                 else
1942                         dp_disable_link_phy_mst(link, signal);
1943         } else
1944                 link->link_enc->funcs->disable_output(link->link_enc, signal);
1945 }
1946
1947 static bool dp_active_dongle_validate_timing(
1948                 const struct dc_crtc_timing *timing,
1949                 const struct dpcd_caps *dpcd_caps)
1950 {
1951         unsigned int required_pix_clk = timing->pix_clk_khz;
1952         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
1953
1954         switch (dpcd_caps->dongle_type) {
1955         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
1956         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
1957         case DISPLAY_DONGLE_DP_DVI_DONGLE:
1958                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
1959                         return true;
1960                 else
1961                         return false;
1962         default:
1963                 break;
1964         }
1965
1966         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
1967                 dongle_caps->extendedCapValid == false)
1968                 return true;
1969
1970         /* Check Pixel Encoding */
1971         switch (timing->pixel_encoding) {
1972         case PIXEL_ENCODING_RGB:
1973         case PIXEL_ENCODING_YCBCR444:
1974                 break;
1975         case PIXEL_ENCODING_YCBCR422:
1976                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
1977                         return false;
1978                 break;
1979         case PIXEL_ENCODING_YCBCR420:
1980                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
1981                         return false;
1982                 break;
1983         default:
1984                 /* Invalid Pixel Encoding*/
1985                 return false;
1986         }
1987
1988
1989         /* Check Color Depth and Pixel Clock */
1990         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1991                 required_pix_clk /= 2;
1992         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1993                 required_pix_clk = required_pix_clk * 2 / 3;
1994
1995         switch (timing->display_color_depth) {
1996         case COLOR_DEPTH_666:
1997         case COLOR_DEPTH_888:
1998                 /*888 and 666 should always be supported*/
1999                 break;
2000         case COLOR_DEPTH_101010:
2001                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2002                         return false;
2003                 required_pix_clk = required_pix_clk * 10 / 8;
2004                 break;
2005         case COLOR_DEPTH_121212:
2006                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2007                         return false;
2008                 required_pix_clk = required_pix_clk * 12 / 8;
2009                 break;
2010
2011         case COLOR_DEPTH_141414:
2012         case COLOR_DEPTH_161616:
2013         default:
2014                 /* These color depths are currently not supported */
2015                 return false;
2016         }
2017
2018         if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
2019                 return false;
2020
2021         return true;
2022 }
2023
2024 enum dc_status dc_link_validate_mode_timing(
2025                 const struct dc_stream_state *stream,
2026                 struct dc_link *link,
2027                 const struct dc_crtc_timing *timing)
2028 {
2029         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
2030         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2031
2032         /* A hack to avoid failing any modes for EDID override feature on
2033          * topology change such as lower quality cable for DP or different dongle
2034          */
2035         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2036                 return DC_OK;
2037
2038         /* Passive Dongle */
2039         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
2040                 return DC_EXCEED_DONGLE_CAP;
2041
2042         /* Active Dongle*/
2043         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2044                 return DC_EXCEED_DONGLE_CAP;
2045
2046         switch (stream->signal) {
2047         case SIGNAL_TYPE_EDP:
2048         case SIGNAL_TYPE_DISPLAY_PORT:
2049                 if (!dp_validate_mode_timing(
2050                                 link,
2051                                 timing))
2052                         return DC_NO_DP_LINK_BANDWIDTH;
2053                 break;
2054
2055         default:
2056                 break;
2057         }
2058
2059         return DC_OK;
2060 }
2061
2062 int dc_link_get_backlight_level(const struct dc_link *link)
2063 {
2064         struct abm *abm = link->ctx->dc->res_pool->abm;
2065
2066         if (abm == NULL || abm->funcs->get_current_backlight_8_bit == NULL)
2067                 return DC_ERROR_UNEXPECTED;
2068
2069         return (int) abm->funcs->get_current_backlight_8_bit(abm);
2070 }
2071
2072 bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
2073                 uint32_t frame_ramp, const struct dc_stream_state *stream)
2074 {
2075         struct dc  *core_dc = link->ctx->dc;
2076         struct abm *abm = core_dc->res_pool->abm;
2077         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2078         unsigned int controller_id = 0;
2079         bool use_smooth_brightness = true;
2080         int i;
2081         DC_LOGGER_INIT(link->ctx->logger);
2082
2083         if ((dmcu == NULL) ||
2084                 (abm == NULL) ||
2085                 (abm->funcs->set_backlight_level == NULL))
2086                 return false;
2087
2088         if (stream) {
2089                 if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
2090                         frame_ramp = 0;
2091
2092                 ((struct dc_stream_state *)stream)->bl_pwm_level = level;
2093         }
2094
2095         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2096
2097         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", level, level);
2098
2099         if (dc_is_embedded_signal(link->connector_signal)) {
2100                 if (stream != NULL) {
2101                         for (i = 0; i < MAX_PIPES; i++) {
2102                                 if (core_dc->current_state->res_ctx.
2103                                                 pipe_ctx[i].stream
2104                                                 == stream)
2105                                         /* DMCU -1 for all controller id values,
2106                                          * therefore +1 here
2107                                          */
2108                                         controller_id =
2109                                                 core_dc->current_state->
2110                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2111                                                 1;
2112                         }
2113                 }
2114                 abm->funcs->set_backlight_level(
2115                                 abm,
2116                                 level,
2117                                 frame_ramp,
2118                                 controller_id,
2119                                 use_smooth_brightness);
2120         }
2121
2122         return true;
2123 }
2124
2125 bool dc_link_set_abm_disable(const struct dc_link *link)
2126 {
2127         struct dc  *core_dc = link->ctx->dc;
2128         struct abm *abm = core_dc->res_pool->abm;
2129
2130         if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
2131                 return false;
2132
2133         abm->funcs->set_abm_immediate_disable(abm);
2134
2135         return true;
2136 }
2137
2138 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2139 {
2140         struct dc  *core_dc = link->ctx->dc;
2141         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2142
2143         if (dmcu != NULL && link->psr_enabled)
2144                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2145
2146         return true;
2147 }
2148
2149 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2150 {
2151         return &link->link_status;
2152 }
2153
2154 void core_link_resume(struct dc_link *link)
2155 {
2156         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2157                 program_hpd_filter(link);
2158 }
2159
2160 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2161 {
2162         struct dc_link_settings *link_settings =
2163                         &stream->sink->link->cur_link_settings;
2164         uint32_t link_rate_in_mbps =
2165                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2166         struct fixed31_32 mbps = dc_fixpt_from_int(
2167                         link_rate_in_mbps * link_settings->lane_count);
2168
2169         return dc_fixpt_div_int(mbps, 54);
2170 }
2171
2172 static int get_color_depth(enum dc_color_depth color_depth)
2173 {
2174         switch (color_depth) {
2175         case COLOR_DEPTH_666: return 6;
2176         case COLOR_DEPTH_888: return 8;
2177         case COLOR_DEPTH_101010: return 10;
2178         case COLOR_DEPTH_121212: return 12;
2179         case COLOR_DEPTH_141414: return 14;
2180         case COLOR_DEPTH_161616: return 16;
2181         default: return 0;
2182         }
2183 }
2184
2185 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2186 {
2187         uint32_t bpc;
2188         uint64_t kbps;
2189         struct fixed31_32 peak_kbps;
2190         uint32_t numerator;
2191         uint32_t denominator;
2192
2193         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2194         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2195
2196         /*
2197          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2198          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2199          * common multiplier to render an integer PBN for all link rate/lane
2200          * counts combinations
2201          * calculate
2202          * peak_kbps *= (1006/1000)
2203          * peak_kbps *= (64/54)
2204          * peak_kbps *= 8    convert to bytes
2205          */
2206
2207         numerator = 64 * PEAK_FACTOR_X1000;
2208         denominator = 54 * 8 * 1000 * 1000;
2209         kbps *= numerator;
2210         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2211
2212         return peak_kbps;
2213 }
2214
2215 static void update_mst_stream_alloc_table(
2216         struct dc_link *link,
2217         struct stream_encoder *stream_enc,
2218         const struct dp_mst_stream_allocation_table *proposed_table)
2219 {
2220         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2221                         { 0 } };
2222         struct link_mst_stream_allocation *dc_alloc;
2223
2224         int i;
2225         int j;
2226
2227         /* if DRM proposed_table has more than one new payload */
2228         ASSERT(proposed_table->stream_count -
2229                         link->mst_stream_alloc_table.stream_count < 2);
2230
2231         /* copy proposed_table to link, add stream encoder */
2232         for (i = 0; i < proposed_table->stream_count; i++) {
2233
2234                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2235                         dc_alloc =
2236                         &link->mst_stream_alloc_table.stream_allocations[j];
2237
2238                         if (dc_alloc->vcp_id ==
2239                                 proposed_table->stream_allocations[i].vcp_id) {
2240
2241                                 work_table[i] = *dc_alloc;
2242                                 break; /* exit j loop */
2243                         }
2244                 }
2245
2246                 /* new vcp_id */
2247                 if (j == link->mst_stream_alloc_table.stream_count) {
2248                         work_table[i].vcp_id =
2249                                 proposed_table->stream_allocations[i].vcp_id;
2250                         work_table[i].slot_count =
2251                                 proposed_table->stream_allocations[i].slot_count;
2252                         work_table[i].stream_enc = stream_enc;
2253                 }
2254         }
2255
2256         /* update link->mst_stream_alloc_table with work_table */
2257         link->mst_stream_alloc_table.stream_count =
2258                         proposed_table->stream_count;
2259         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2260                 link->mst_stream_alloc_table.stream_allocations[i] =
2261                                 work_table[i];
2262 }
2263
2264 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2265  * because stream_encoder is not exposed to dm
2266  */
2267 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2268 {
2269         struct dc_stream_state *stream = pipe_ctx->stream;
2270         struct dc_link *link = stream->sink->link;
2271         struct link_encoder *link_encoder = link->link_enc;
2272         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2273         struct dp_mst_stream_allocation_table proposed_table = {0};
2274         struct fixed31_32 avg_time_slots_per_mtp;
2275         struct fixed31_32 pbn;
2276         struct fixed31_32 pbn_per_slot;
2277         uint8_t i;
2278         DC_LOGGER_INIT(link->ctx->logger);
2279
2280         /* enable_link_dp_mst already check link->enabled_stream_count
2281          * and stream is in link->stream[]. This is called during set mode,
2282          * stream_enc is available.
2283          */
2284
2285         /* get calculate VC payload for stream: stream_alloc */
2286         if (dm_helpers_dp_mst_write_payload_allocation_table(
2287                 stream->ctx,
2288                 stream,
2289                 &proposed_table,
2290                 true)) {
2291                 update_mst_stream_alloc_table(
2292                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2293         }
2294         else
2295                 DC_LOG_WARNING("Failed to update"
2296                                 "MST allocation table for"
2297                                 "pipe idx:%d\n",
2298                                 pipe_ctx->pipe_idx);
2299
2300         DC_LOG_MST("%s  "
2301                         "stream_count: %d: \n ",
2302                         __func__,
2303                         link->mst_stream_alloc_table.stream_count);
2304
2305         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2306                 DC_LOG_MST("stream_enc[%d]: %p      "
2307                 "stream[%d].vcp_id: %d      "
2308                 "stream[%d].slot_count: %d\n",
2309                 i,
2310                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2311                 i,
2312                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2313                 i,
2314                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2315         }
2316
2317         ASSERT(proposed_table.stream_count > 0);
2318
2319         /* program DP source TX for payload */
2320         link_encoder->funcs->update_mst_stream_allocation_table(
2321                 link_encoder,
2322                 &link->mst_stream_alloc_table);
2323
2324         /* send down message */
2325         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2326                         stream->ctx,
2327                         stream);
2328
2329         dm_helpers_dp_mst_send_payload_allocation(
2330                         stream->ctx,
2331                         stream,
2332                         true);
2333
2334         /* slot X.Y for only current stream */
2335         pbn_per_slot = get_pbn_per_slot(stream);
2336         pbn = get_pbn_from_timing(pipe_ctx);
2337         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2338
2339         stream_encoder->funcs->set_mst_bandwidth(
2340                 stream_encoder,
2341                 avg_time_slots_per_mtp);
2342
2343         return DC_OK;
2344
2345 }
2346
2347 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2348 {
2349         struct dc_stream_state *stream = pipe_ctx->stream;
2350         struct dc_link *link = stream->sink->link;
2351         struct link_encoder *link_encoder = link->link_enc;
2352         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2353         struct dp_mst_stream_allocation_table proposed_table = {0};
2354         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2355         uint8_t i;
2356         bool mst_mode = (link->type == dc_connection_mst_branch);
2357         DC_LOGGER_INIT(link->ctx->logger);
2358
2359         /* deallocate_mst_payload is called before disable link. When mode or
2360          * disable/enable monitor, new stream is created which is not in link
2361          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2362          * should not done. For new mode set, map_resources will get engine
2363          * for new stream, so stream_enc->id should be validated until here.
2364          */
2365
2366         /* slot X.Y */
2367         stream_encoder->funcs->set_mst_bandwidth(
2368                 stream_encoder,
2369                 avg_time_slots_per_mtp);
2370
2371         /* TODO: which component is responsible for remove payload table? */
2372         if (mst_mode) {
2373                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2374                                 stream->ctx,
2375                                 stream,
2376                                 &proposed_table,
2377                                 false)) {
2378
2379                         update_mst_stream_alloc_table(
2380                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2381                 }
2382                 else {
2383                                 DC_LOG_WARNING("Failed to update"
2384                                                 "MST allocation table for"
2385                                                 "pipe idx:%d\n",
2386                                                 pipe_ctx->pipe_idx);
2387                 }
2388         }
2389
2390         DC_LOG_MST("%s"
2391                         "stream_count: %d: ",
2392                         __func__,
2393                         link->mst_stream_alloc_table.stream_count);
2394
2395         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2396                 DC_LOG_MST("stream_enc[%d]: %p      "
2397                 "stream[%d].vcp_id: %d      "
2398                 "stream[%d].slot_count: %d\n",
2399                 i,
2400                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2401                 i,
2402                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2403                 i,
2404                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2405         }
2406
2407         link_encoder->funcs->update_mst_stream_allocation_table(
2408                 link_encoder,
2409                 &link->mst_stream_alloc_table);
2410
2411         if (mst_mode) {
2412                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2413                         stream->ctx,
2414                         stream);
2415
2416                 dm_helpers_dp_mst_send_payload_allocation(
2417                         stream->ctx,
2418                         stream,
2419                         false);
2420         }
2421
2422         return DC_OK;
2423 }
2424
2425 void core_link_enable_stream(
2426                 struct dc_state *state,
2427                 struct pipe_ctx *pipe_ctx)
2428 {
2429         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2430         enum dc_status status;
2431         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2432
2433         /* eDP lit up by bios already, no need to enable again. */
2434         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2435                 core_dc->apply_edp_fast_boot_optimization) {
2436                 core_dc->apply_edp_fast_boot_optimization = false;
2437                 pipe_ctx->stream->dpms_off = false;
2438                 return;
2439         }
2440
2441         if (pipe_ctx->stream->dpms_off)
2442                 return;
2443
2444         status = enable_link(state, pipe_ctx);
2445
2446         if (status != DC_OK) {
2447                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2448                         pipe_ctx->stream->sink->link->link_index,
2449                         status);
2450
2451                         /* Abort stream enable *unless* the failure was due to
2452                          * DP link training - some DP monitors will recover and
2453                          * show the stream anyway. But MST displays can't proceed
2454                          * without link training.
2455                          */
2456                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2457                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2458                                 BREAK_TO_DEBUGGER();
2459                                 return;
2460                         }
2461         }
2462
2463         core_dc->hwss.enable_audio_stream(pipe_ctx);
2464
2465         /* turn off otg test pattern if enable */
2466         if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2467                 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2468                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2469                                 COLOR_DEPTH_UNDEFINED);
2470
2471         core_dc->hwss.enable_stream(pipe_ctx);
2472
2473         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2474                 allocate_mst_payload(pipe_ctx);
2475
2476         core_dc->hwss.unblank_stream(pipe_ctx,
2477                 &pipe_ctx->stream->sink->link->cur_link_settings);
2478 }
2479
2480 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2481 {
2482         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2483
2484         core_dc->hwss.blank_stream(pipe_ctx);
2485
2486         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2487                 deallocate_mst_payload(pipe_ctx);
2488
2489         core_dc->hwss.disable_stream(pipe_ctx, option);
2490
2491         disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2492 }
2493
2494 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2495 {
2496         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2497
2498         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2499                 return;
2500
2501         core_dc->hwss.set_avmute(pipe_ctx, enable);
2502 }
2503
2504 /**
2505  *****************************************************************************
2506  *  Function: dc_link_enable_hpd_filter
2507  *
2508  *  @brief
2509  *     If enable is true, programs HPD filter on associated HPD line using
2510  *     delay_on_disconnect/delay_on_connect values dependent on
2511  *     link->connector_signal
2512  *
2513  *     If enable is false, programs HPD filter on associated HPD line with no
2514  *     delays on connect or disconnect
2515  *
2516  *  @param [in] link: pointer to the dc link
2517  *  @param [in] enable: boolean specifying whether to enable hbd
2518  *****************************************************************************
2519  */
2520 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2521 {
2522         struct gpio *hpd;
2523
2524         if (enable) {
2525                 link->is_hpd_filter_disabled = false;
2526                 program_hpd_filter(link);
2527         } else {
2528                 link->is_hpd_filter_disabled = true;
2529                 /* Obtain HPD handle */
2530                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2531
2532                 if (!hpd)
2533                         return;
2534
2535                 /* Setup HPD filtering */
2536                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2537                         struct gpio_hpd_config config;
2538
2539                         config.delay_on_connect = 0;
2540                         config.delay_on_disconnect = 0;
2541
2542                         dal_irq_setup_hpd_filter(hpd, &config);
2543
2544                         dal_gpio_close(hpd);
2545                 } else {
2546                         ASSERT_CRITICAL(false);
2547                 }
2548                 /* Release HPD handle */
2549                 dal_gpio_destroy_irq(&hpd);
2550         }
2551 }
2552