drivers/gpu/drm/amd/display/dc/dc_hw_types.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_HW_TYPES_H
  27 #define DC_HW_TYPES_H
  28
  29 #include "os_types.h"
  30 #include "fixed31_32.h"
  31 #include "signal_types.h"
  32
  33 /******************************************************************************
  34  * Data types for Virtual HW Layer of DAL3.
  35  * (see DAL3 design documents for HW Layer definition)
  36  *
  37  * The intended uses are:
  38  * 1. Generation pseudocode sequences for HW programming.
  39  * 2. Implementation of real HW programming by HW Sequencer of DAL3.
  40  *
  41  * Note: do *not* add any types which are *not* used for HW programming - this
  42  * will ensure separation of Logic layer from HW layer.
  43  ******************************************************************************/
  44
  45 union large_integer {
  46         struct {
  47                 uint32_t low_part;
  48                 int32_t high_part;
  49         };
  50
  51         struct {
  52                 uint32_t low_part;
  53                 int32_t high_part;
  54         } u;
  55
  56         int64_t quad_part;
  57 };
  58
  59 #define PHYSICAL_ADDRESS_LOC union large_integer
  60
  61 enum dc_plane_addr_type {
  62         PLN_ADDR_TYPE_GRAPHICS = 0,
  63         PLN_ADDR_TYPE_GRPH_STEREO,
  64         PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
  65 };
  66
  67 struct dc_plane_address {
  68         enum dc_plane_addr_type type;
  69         bool tmz_surface;
  70         union {
  71                 struct{
  72                         PHYSICAL_ADDRESS_LOC addr;
  73                         PHYSICAL_ADDRESS_LOC meta_addr;
  74                         union large_integer dcc_const_color;
  75                 } grph;
  76
  77                 /*stereo*/
  78                 struct {
  79                         PHYSICAL_ADDRESS_LOC left_addr;
  80                         PHYSICAL_ADDRESS_LOC left_meta_addr;
  81                         union large_integer left_dcc_const_color;
  82
  83                         PHYSICAL_ADDRESS_LOC right_addr;
  84                         PHYSICAL_ADDRESS_LOC right_meta_addr;
  85                         union large_integer right_dcc_const_color;
  86
  87                 } grph_stereo;
  88
  89                 /*video  progressive*/
  90                 struct {
  91                         PHYSICAL_ADDRESS_LOC luma_addr;
  92                         PHYSICAL_ADDRESS_LOC luma_meta_addr;
  93                         union large_integer luma_dcc_const_color;
  94
  95                         PHYSICAL_ADDRESS_LOC chroma_addr;
  96                         PHYSICAL_ADDRESS_LOC chroma_meta_addr;
  97                         union large_integer chroma_dcc_const_color;
  98                 } video_progressive;
  99         };
 100 };
 101
 102 struct dc_size {
 103         int width;
 104         int height;
 105 };
 106
 107 struct rect {
 108         int x;
 109         int y;
 110         int width;
 111         int height;
 112 };
 113
 114 union plane_size {
 115         /* Grph or Video will be selected
 116          * based on format above:
 117          * Use Video structure if
 118          * format >= DalPixelFormat_VideoBegin
 119          * else use Grph structure
 120          */
 121         struct {
 122                 struct rect surface_size;
 123                 /* Graphic surface pitch in pixels.
 124                  * In LINEAR_GENERAL mode, pitch
 125                  * is 32 pixel aligned.
 126                  */
 127                 int surface_pitch;
 128         } grph;
 129
 130         struct {
 131                 struct rect luma_size;
 132                 /* Graphic surface pitch in pixels.
 133                  * In LINEAR_GENERAL mode, pitch is
 134                  * 32 pixel aligned.
 135                  */
 136                 int luma_pitch;
 137
 138                 struct rect chroma_size;
 139                 /* Graphic surface pitch in pixels.
 140                  * In LINEAR_GENERAL mode, pitch is
 141                  * 32 pixel aligned.
 142                  */
 143                 int chroma_pitch;
 144         } video;
 145 };
 146
 147 struct dc_plane_dcc_param {
 148         bool enable;
 149
 150         union {
 151                 struct {
 152                         int meta_pitch;
 153                         bool independent_64b_blks;
 154                 } grph;
 155
 156                 struct {
 157                         int meta_pitch_l;
 158                         bool independent_64b_blks_l;
 159
 160                         int meta_pitch_c;
 161                         bool independent_64b_blks_c;
 162                 } video;
 163         };
 164 };
 165
 166 /*Displayable pixel format in fb*/
 167 enum surface_pixel_format {
 168         SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
 169         /*TOBE REMOVED paletta 256 colors*/
 170         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
 171                 SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
 172         /*16 bpp*/
 173         SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
 174         /*16 bpp*/
 175         SURFACE_PIXEL_FORMAT_GRPH_RGB565,
 176         /*32 bpp*/
 177         SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
 178         /*32 bpp swaped*/
 179         SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
 180
 181         SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
 182         /*swaped*/
 183         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
 184         /*TOBE REMOVED swaped, XR_BIAS has no differance
 185          * for pixel layout than previous and we can
 186          * delete this after discusion*/
 187         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
 188         /*64 bpp */
 189         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
 190         /*float*/
 191         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
 192         /*swaped & float*/
 193         SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
 194         /*grow graphics here if necessary */
 195         SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
 196         SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 197         SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
 198                 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 199         SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
 200         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
 201         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
 202                 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
 203         SURFACE_PIXEL_FORMAT_INVALID
 204
 205         /*grow 444 video here if necessary */
 206 };
 207
 208
 209
 210 /* Pixel format */
 211 enum pixel_format {
 212         /*graph*/
 213         PIXEL_FORMAT_UNINITIALIZED,
 214         PIXEL_FORMAT_INDEX8,
 215         PIXEL_FORMAT_RGB565,
 216         PIXEL_FORMAT_ARGB8888,
 217         PIXEL_FORMAT_ARGB2101010,
 218         PIXEL_FORMAT_ARGB2101010_XRBIAS,
 219         PIXEL_FORMAT_FP16,
 220         /*video*/
 221         PIXEL_FORMAT_420BPP8,
 222         PIXEL_FORMAT_420BPP10,
 223         /*end of pixel format definition*/
 224         PIXEL_FORMAT_INVALID,
 225
 226         PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
 227         PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
 228         PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
 229         PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
 230         PIXEL_FORMAT_UNKNOWN
 231 };
 232
 233 enum tile_split_values {
 234         DC_DISPLAY_MICRO_TILING = 0x0,
 235         DC_THIN_MICRO_TILING = 0x1,
 236         DC_DEPTH_MICRO_TILING = 0x2,
 237         DC_ROTATED_MICRO_TILING = 0x3,
 238 };
 239
 240 /* TODO: These values come from hardware spec. We need to readdress this
 241  * if they ever change.
 242  */
 243 enum array_mode_values {
 244         DC_ARRAY_LINEAR_GENERAL = 0,
 245         DC_ARRAY_LINEAR_ALLIGNED,
 246         DC_ARRAY_1D_TILED_THIN1,
 247         DC_ARRAY_1D_TILED_THICK,
 248         DC_ARRAY_2D_TILED_THIN1,
 249         DC_ARRAY_PRT_TILED_THIN1,
 250         DC_ARRAY_PRT_2D_TILED_THIN1,
 251         DC_ARRAY_2D_TILED_THICK,
 252         DC_ARRAY_2D_TILED_X_THICK,
 253         DC_ARRAY_PRT_TILED_THICK,
 254         DC_ARRAY_PRT_2D_TILED_THICK,
 255         DC_ARRAY_PRT_3D_TILED_THIN1,
 256         DC_ARRAY_3D_TILED_THIN1,
 257         DC_ARRAY_3D_TILED_THICK,
 258         DC_ARRAY_3D_TILED_X_THICK,
 259         DC_ARRAY_PRT_3D_TILED_THICK,
 260 };
 261
 262 enum tile_mode_values {
 263         DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
 264         DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
 265 };
 266
 267 enum swizzle_mode_values {
 268         DC_SW_LINEAR = 0,
 269         DC_SW_256B_S = 1,
 270         DC_SW_256_D = 2,
 271         DC_SW_256_R = 3,
 272         DC_SW_4KB_S = 5,
 273         DC_SW_4KB_D = 6,
 274         DC_SW_4KB_R = 7,
 275         DC_SW_64KB_S = 9,
 276         DC_SW_64KB_D = 10,
 277         DC_SW_64KB_R = 11,
 278         DC_SW_VAR_S = 13,
 279         DC_SW_VAR_D = 14,
 280         DC_SW_VAR_R = 15,
 281         DC_SW_64KB_S_T = 17,
 282         DC_SW_64KB_D_T = 18,
 283         DC_SW_4KB_S_X = 21,
 284         DC_SW_4KB_D_X = 22,
 285         DC_SW_4KB_R_X = 23,
 286         DC_SW_64KB_S_X = 25,
 287         DC_SW_64KB_D_X = 26,
 288         DC_SW_64KB_R_X = 27,
 289         DC_SW_VAR_S_X = 29,
 290         DC_SW_VAR_D_X = 30,
 291         DC_SW_VAR_R_X = 31,
 292         DC_SW_MAX
 293 };
 294
 295 union dc_tiling_info {
 296
 297         struct {
 298                 /* Specifies the number of memory banks for tiling
 299                  *      purposes.
 300                  * Only applies to 2D and 3D tiling modes.
 301                  *      POSSIBLE VALUES: 2,4,8,16
 302                  */
 303                 unsigned int num_banks;
 304                 /* Specifies the number of tiles in the x direction
 305                  *      to be incorporated into the same bank.
 306                  * Only applies to 2D and 3D tiling modes.
 307                  *      POSSIBLE VALUES: 1,2,4,8
 308                  */
 309                 unsigned int bank_width;
 310                 unsigned int bank_width_c;
 311                 /* Specifies the number of tiles in the y direction to
 312                  *      be incorporated into the same bank.
 313                  * Only applies to 2D and 3D tiling modes.
 314                  *      POSSIBLE VALUES: 1,2,4,8
 315                  */
 316                 unsigned int bank_height;
 317                 unsigned int bank_height_c;
 318                 /* Specifies the macro tile aspect ratio. Only applies
 319                  * to 2D and 3D tiling modes.
 320                  */
 321                 unsigned int tile_aspect;
 322                 unsigned int tile_aspect_c;
 323                 /* Specifies the number of bytes that will be stored
 324                  *      contiguously for each tile.
 325                  * If the tile data requires more storage than this
 326                  *      amount, it is split into multiple slices.
 327                  * This field must not be larger than
 328                  *      GB_ADDR_CONFIG.DRAM_ROW_SIZE.
 329                  * Only applies to 2D and 3D tiling modes.
 330                  * For color render targets, TILE_SPLIT >= 256B.
 331                  */
 332                 enum tile_split_values tile_split;
 333                 enum tile_split_values tile_split_c;
 334                 /* Specifies the addressing within a tile.
 335                  *      0x0 - DISPLAY_MICRO_TILING
 336                  *      0x1 - THIN_MICRO_TILING
 337                  *      0x2 - DEPTH_MICRO_TILING
 338                  *      0x3 - ROTATED_MICRO_TILING
 339                  */
 340                 enum tile_mode_values tile_mode;
 341                 enum tile_mode_values tile_mode_c;
 342                 /* Specifies the number of pipes and how they are
 343                  *      interleaved in the surface.
 344                  * Refer to memory addressing document for complete
 345                  *      details and constraints.
 346                  */
 347                 unsigned int pipe_config;
 348                 /* Specifies the tiling mode of the surface.
 349                  * THIN tiles use an 8x8x1 tile size.
 350                  * THICK tiles use an 8x8x4 tile size.
 351                  * 2D tiling modes rotate banks for successive Z slices
 352                  * 3D tiling modes rotate pipes and banks for Z slices
 353                  * Refer to memory addressing document for complete
 354                  *      details and constraints.
 355                  */
 356                 enum array_mode_values array_mode;
 357         } gfx8;
 358
 359         struct {
 360                 unsigned int num_pipes;
 361                 unsigned int num_banks;
 362                 unsigned int pipe_interleave;
 363                 unsigned int num_shader_engines;
 364                 unsigned int num_rb_per_se;
 365                 unsigned int max_compressed_frags;
 366                 bool shaderEnable;
 367
 368                 enum swizzle_mode_values swizzle;
 369                 bool meta_linear;
 370                 bool rb_aligned;
 371                 bool pipe_aligned;
 372         } gfx9;
 373 };
 374
 375 /* Rotation angle */
 376 enum dc_rotation_angle {
 377         ROTATION_ANGLE_0 = 0,
 378         ROTATION_ANGLE_90,
 379         ROTATION_ANGLE_180,
 380         ROTATION_ANGLE_270,
 381         ROTATION_ANGLE_COUNT
 382 };
 383
 384 enum dc_scan_direction {
 385         SCAN_DIRECTION_UNKNOWN = 0,
 386         SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
 387         SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
 388 };
 389
 390 struct dc_cursor_position {
 391         uint32_t x;
 392         uint32_t y;
 393
 394         uint32_t x_hotspot;
 395         uint32_t y_hotspot;
 396
 397         /*
 398          * This parameter indicates whether HW cursor should be enabled
 399          */
 400         bool enable;
 401
 402 };
 403
 404 struct dc_cursor_mi_param {
 405         unsigned int pixel_clk_khz;
 406         unsigned int ref_clk_khz;
 407         struct rect viewport;
 408         struct fixed31_32 h_scale_ratio;
 409         struct fixed31_32 v_scale_ratio;
 410         enum dc_rotation_angle rotation;
 411         bool mirror;
 412 };
 413
 414 /* IPP related types */
 415
 416 enum {
 417         GAMMA_RGB_256_ENTRIES = 256,
 418         GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
 419         GAMMA_CS_TFM_1D_ENTRIES = 4096,
 420         GAMMA_CUSTOM_ENTRIES = 4096,
 421         GAMMA_MAX_ENTRIES = 4096
 422 };
 423
 424 enum dc_gamma_type {
 425         GAMMA_RGB_256 = 1,
 426         GAMMA_RGB_FLOAT_1024 = 2,
 427         GAMMA_CS_TFM_1D = 3,
 428         GAMMA_CUSTOM = 4,
 429 };
 430
 431 struct dc_csc_transform {
 432         uint16_t matrix[12];
 433         bool enable_adjustment;
 434 };
 435
 436 struct dc_gamma {
 437         struct kref refcount;
 438         enum dc_gamma_type type;
 439         unsigned int num_entries;
 440
 441         struct dc_gamma_entries {
 442                 struct fixed31_32 red[GAMMA_MAX_ENTRIES];
 443                 struct fixed31_32 green[GAMMA_MAX_ENTRIES];
 444                 struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
 445         } entries;
 446
 447         /* private to DC core */
 448         struct dc_context *ctx;
 449
 450         bool is_identity;
 451 };
 452
 453 /* Used by both ipp amd opp functions*/
 454 /* TODO: to be consolidated with enum color_space */
 455
 456 /*
 457  * This enum is for programming CURSOR_MODE register field. What this register
 458  * should be programmed to depends on OS requested cursor shape flags and what
 459  * we stored in the cursor surface.
 460  */
 461 enum dc_cursor_color_format {
 462         CURSOR_MODE_MONO,
 463         CURSOR_MODE_COLOR_1BIT_AND,
 464         CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
 465         CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
 466 };
 467
 468 /*
 469  * This is all the parameters required by DAL in order to update the cursor
 470  * attributes, including the new cursor image surface address, size, hotspot
 471  * location, color format, etc.
 472  */
 473
 474 union dc_cursor_attribute_flags {
 475         struct {
 476                 uint32_t ENABLE_MAGNIFICATION:1;
 477                 uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
 478                 uint32_t HORIZONTAL_MIRROR:1;
 479                 uint32_t VERTICAL_MIRROR:1;
 480                 uint32_t INVERT_PIXEL_DATA:1;
 481                 uint32_t ZERO_EXPANSION:1;
 482                 uint32_t MIN_MAX_INVERT:1;
 483                 uint32_t RESERVED:25;
 484         } bits;
 485         uint32_t value;
 486 };
 487
 488 struct dc_cursor_attributes {
 489         PHYSICAL_ADDRESS_LOC address;
 490         uint32_t pitch;
 491
 492         /* Width and height should correspond to cursor surface width x heigh */
 493         uint32_t width;
 494         uint32_t height;
 495
 496         enum dc_cursor_color_format color_format;
 497         uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
 498
 499         /* In case we support HW Cursor rotation in the future */
 500         enum dc_rotation_angle rotation_angle;
 501
 502         union dc_cursor_attribute_flags attribute_flags;
 503 };
 504
 505 struct dpp_cursor_attributes {
 506         int bias;
 507         int scale;
 508 };
 509
 510 /* OPP */
 511
 512 enum dc_color_space {
 513         COLOR_SPACE_UNKNOWN,
 514         COLOR_SPACE_SRGB,
 515         COLOR_SPACE_XR_RGB,
 516         COLOR_SPACE_SRGB_LIMITED,
 517         COLOR_SPACE_MSREF_SCRGB,
 518         COLOR_SPACE_YCBCR601,
 519         COLOR_SPACE_YCBCR709,
 520         COLOR_SPACE_XV_YCC_709,
 521         COLOR_SPACE_XV_YCC_601,
 522         COLOR_SPACE_YCBCR601_LIMITED,
 523         COLOR_SPACE_YCBCR709_LIMITED,
 524         COLOR_SPACE_2020_RGB_FULLRANGE,
 525         COLOR_SPACE_2020_RGB_LIMITEDRANGE,
 526         COLOR_SPACE_2020_YCBCR,
 527         COLOR_SPACE_ADOBERGB,
 528         COLOR_SPACE_DCIP3,
 529         COLOR_SPACE_DISPLAYNATIVE,
 530         COLOR_SPACE_DOLBYVISION,
 531         COLOR_SPACE_APPCTRL,
 532         COLOR_SPACE_CUSTOMPOINTS,
 533 };
 534
 535 enum dc_dither_option {
 536         DITHER_OPTION_DEFAULT,
 537         DITHER_OPTION_DISABLE,
 538         DITHER_OPTION_FM6,
 539         DITHER_OPTION_FM8,
 540         DITHER_OPTION_FM10,
 541         DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
 542         DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
 543         DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
 544         DITHER_OPTION_SPATIAL6,
 545         DITHER_OPTION_SPATIAL8,
 546         DITHER_OPTION_SPATIAL10,
 547         DITHER_OPTION_TRUN6,
 548         DITHER_OPTION_TRUN8,
 549         DITHER_OPTION_TRUN10,
 550         DITHER_OPTION_TRUN10_SPATIAL8,
 551         DITHER_OPTION_TRUN10_SPATIAL6,
 552         DITHER_OPTION_TRUN10_FM8,
 553         DITHER_OPTION_TRUN10_FM6,
 554         DITHER_OPTION_TRUN10_SPATIAL8_FM6,
 555         DITHER_OPTION_SPATIAL10_FM8,
 556         DITHER_OPTION_SPATIAL10_FM6,
 557         DITHER_OPTION_TRUN8_SPATIAL6,
 558         DITHER_OPTION_TRUN8_FM6,
 559         DITHER_OPTION_SPATIAL8_FM6,
 560         DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
 561         DITHER_OPTION_INVALID
 562 };
 563
 564 enum dc_quantization_range {
 565         QUANTIZATION_RANGE_UNKNOWN,
 566         QUANTIZATION_RANGE_FULL,
 567         QUANTIZATION_RANGE_LIMITED
 568 };
 569
 570 /* XFM */
 571
 572 /* used in  struct dc_plane_state */
 573 struct scaling_taps {
 574         uint32_t v_taps;
 575         uint32_t h_taps;
 576         uint32_t v_taps_c;
 577         uint32_t h_taps_c;
 578 };
 579
 580 enum dc_timing_standard {
 581         DC_TIMING_STANDARD_UNDEFINED,
 582         DC_TIMING_STANDARD_DMT,
 583         DC_TIMING_STANDARD_GTF,
 584         DC_TIMING_STANDARD_CVT,
 585         DC_TIMING_STANDARD_CVT_RB,
 586         DC_TIMING_STANDARD_CEA770,
 587         DC_TIMING_STANDARD_CEA861,
 588         DC_TIMING_STANDARD_HDMI,
 589         DC_TIMING_STANDARD_TV_NTSC,
 590         DC_TIMING_STANDARD_TV_NTSC_J,
 591         DC_TIMING_STANDARD_TV_PAL,
 592         DC_TIMING_STANDARD_TV_PAL_M,
 593         DC_TIMING_STANDARD_TV_PAL_CN,
 594         DC_TIMING_STANDARD_TV_SECAM,
 595         DC_TIMING_STANDARD_EXPLICIT,
 596         /*!< For explicit timings from EDID, VBIOS, etc.*/
 597         DC_TIMING_STANDARD_USER_OVERRIDE,
 598         /*!< For mode timing override by user*/
 599         DC_TIMING_STANDARD_MAX
 600 };
 601
 602 enum dc_color_depth {
 603         COLOR_DEPTH_UNDEFINED,
 604         COLOR_DEPTH_666,
 605         COLOR_DEPTH_888,
 606         COLOR_DEPTH_101010,
 607         COLOR_DEPTH_121212,
 608         COLOR_DEPTH_141414,
 609         COLOR_DEPTH_161616,
 610         COLOR_DEPTH_COUNT
 611 };
 612
 613 enum dc_pixel_encoding {
 614         PIXEL_ENCODING_UNDEFINED,
 615         PIXEL_ENCODING_RGB,
 616         PIXEL_ENCODING_YCBCR422,
 617         PIXEL_ENCODING_YCBCR444,
 618         PIXEL_ENCODING_YCBCR420,
 619         PIXEL_ENCODING_COUNT
 620 };
 621
 622 enum dc_aspect_ratio {
 623         ASPECT_RATIO_NO_DATA,
 624         ASPECT_RATIO_4_3,
 625         ASPECT_RATIO_16_9,
 626         ASPECT_RATIO_64_27,
 627         ASPECT_RATIO_256_135,
 628         ASPECT_RATIO_FUTURE
 629 };
 630
 631 enum scanning_type {
 632         SCANNING_TYPE_NODATA = 0,
 633         SCANNING_TYPE_OVERSCAN,
 634         SCANNING_TYPE_UNDERSCAN,
 635         SCANNING_TYPE_FUTURE,
 636         SCANNING_TYPE_UNDEFINED
 637 };
 638
 639 struct dc_crtc_timing_flags {
 640         uint32_t INTERLACE :1;
 641         uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 642          it is positive polarity --reversed with dal1 or video bios define*/
 643         uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 644          it is positive polarity --reversed with dal1 or video bios define*/
 645
 646         uint32_t HORZ_COUNT_BY_TWO:1;
 647
 648         uint32_t EXCLUSIVE_3D :1; /* if this bit set,
 649          timing can be driven in 3D format only
 650          and there is no corresponding 2D timing*/
 651         uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
 652          (right eye = '1', left eye = '0') */
 653         uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
 654          when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
 655         uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
 656          because corresponding 2D timing also present in the list*/
 657         uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
 658          and we want to match priority of corresponding 3D timing*/
 659         uint32_t Y_ONLY :1;
 660
 661         uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
 662         uint32_t DTD_COUNTER :5; /* values 1 to 16 */
 663
 664         uint32_t FORCE_HDR :1;
 665
 666         /* HDMI 2.0 - Support scrambling for TMDS character
 667          * rates less than or equal to 340Mcsc */
 668         uint32_t LTE_340MCSC_SCRAMBLE:1;
 669
 670 };
 671
 672 enum dc_timing_3d_format {
 673         TIMING_3D_FORMAT_NONE,
 674         TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
 675         TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
 676         TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
 677         /* for active DP-HDMI dongle*/
 678         TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
 679         TIMING_3D_FORMAT_HW_FRAME_PACKING,
 680         TIMING_3D_FORMAT_SW_FRAME_PACKING,
 681         TIMING_3D_FORMAT_ROW_INTERLEAVE,
 682         TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
 683         TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
 684         TIMING_3D_FORMAT_SIDE_BY_SIDE,
 685         TIMING_3D_FORMAT_TOP_AND_BOTTOM,
 686         TIMING_3D_FORMAT_SBS_SW_PACKED,
 687         /* Side-by-side, packed by application/driver into 2D frame*/
 688         TIMING_3D_FORMAT_TB_SW_PACKED,
 689         /* Top-and-bottom, packed by application/driver into 2D frame*/
 690
 691         TIMING_3D_FORMAT_MAX,
 692 };
 693
 694 enum trigger_delay {
 695         TRIGGER_DELAY_NEXT_PIXEL = 0,
 696         TRIGGER_DELAY_NEXT_LINE,
 697 };
 698
 699 enum crtc_event {
 700         CRTC_EVENT_VSYNC_RISING = 0,
 701         CRTC_EVENT_VSYNC_FALLING
 702 };
 703
 704 struct crtc_trigger_info {
 705         bool enabled;
 706         struct dc_stream_state *event_source;
 707         enum crtc_event event;
 708         enum trigger_delay delay;
 709 };
 710
 711 enum vrr_state {
 712         VRR_STATE_OFF = 0,
 713         VRR_STATE_VARIABLE,
 714         VRR_STATE_FIXED,
 715 };
 716
 717 struct dc_crtc_timing_adjust {
 718         uint32_t v_total_min;
 719         uint32_t v_total_max;
 720 };
 721
 722 struct dc_crtc_timing {
 723         uint32_t h_total;
 724         uint32_t h_border_left;
 725         uint32_t h_addressable;
 726         uint32_t h_border_right;
 727         uint32_t h_front_porch;
 728         uint32_t h_sync_width;
 729
 730         uint32_t v_total;
 731         uint32_t v_border_top;
 732         uint32_t v_addressable;
 733         uint32_t v_border_bottom;
 734         uint32_t v_front_porch;
 735         uint32_t v_sync_width;
 736
 737         uint32_t pix_clk_khz;
 738
 739         uint32_t vic;
 740         uint32_t hdmi_vic;
 741         enum dc_timing_3d_format timing_3d_format;
 742         enum dc_color_depth display_color_depth;
 743         enum dc_pixel_encoding pixel_encoding;
 744         enum dc_aspect_ratio aspect_ratio;
 745         enum scanning_type scan_type;
 746
 747         struct dc_crtc_timing_flags flags;
 748 };
 749
 750 #define MAX_TG_COLOR_VALUE 0x3FF
 751 struct tg_color {
 752         /* Maximum 10 bits color value */
 753         uint16_t color_r_cr;
 754         uint16_t color_g_y;
 755         uint16_t color_b_cb;
 756 };
 757
 758 #endif /* DC_HW_TYPES_H */
 759