2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #include "fixed31_32.h"
30 #include "irq_types.h"
31 #include "dc_dp_types.h"
32 #include "dc_hw_types.h"
33 #include "dal_types.h"
34 #include "grph_object_defs.h"
36 /* forward declarations */
37 struct dc_plane_state;
38 struct dc_stream_state;
43 /********************************
44 * Environment definitions
45 ********************************/
46 enum dce_environment {
47 DCE_ENV_PRODUCTION_DRV = 0,
48 /* Emulation on FPGA, in "Maximus" System.
49 * This environment enforces that *only* DC registers accessed.
50 * (access to non-DC registers will hang FPGA) */
52 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
53 * requirements of Diagnostics team. */
57 /* Note: use these macro definitions instead of direct comparison! */
58 #define IS_FPGA_MAXIMUS_DC(dce_environment) \
59 (dce_environment == DCE_ENV_FPGA_MAXIMUS)
61 #define IS_DIAG_DC(dce_environment) \
62 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
67 uint32_t pci_revision_id;
68 uint32_t hw_internal_rev;
71 uint32_t feature_flags;
72 uint32_t fake_paths_num;
73 void *atombios_base_address;
79 void *driver_context; /* e.g. amdgpu_device */
82 enum dce_environment dce_environment;
83 struct hw_asic_id asic_id;
85 /* todo: below should probably move to dc. to facilitate removal
86 * of AS we will store these here
88 enum dce_version dce_version;
89 struct dc_bios *dc_bios;
91 struct gpio_service *gpio_service;
92 struct i2caux *i2caux;
93 uint32_t dc_sink_id_count;
94 uint64_t fbc_gpu_addr;
98 #define DC_MAX_EDID_BUFFER_SIZE 512
99 #define EDID_BLOCK_SIZE 128
100 #define MAX_SURFACE_NUM 4
101 #define NUM_PIXEL_FORMATS 10
103 #include "dc_ddc_types.h"
112 enum view_3d_format {
113 VIEW_3D_FORMAT_NONE = 0,
114 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
115 VIEW_3D_FORMAT_SIDE_BY_SIDE,
116 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
117 VIEW_3D_FORMAT_COUNT,
118 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
121 enum plane_stereo_format {
122 PLANE_STEREO_FORMAT_NONE = 0,
123 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
124 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
125 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
126 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
127 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
128 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
131 /* TODO: Find way to calculate number of bits
132 * Please increase if pixel_format enum increases
133 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
136 enum dc_edid_connector_type {
137 DC_EDID_CONNECTOR_UNKNOWN = 0,
138 DC_EDID_CONNECTOR_ANALOG = 1,
139 DC_EDID_CONNECTOR_DIGITAL = 10,
140 DC_EDID_CONNECTOR_DVI = 11,
141 DC_EDID_CONNECTOR_HDMIA = 12,
142 DC_EDID_CONNECTOR_MDDI = 14,
143 DC_EDID_CONNECTOR_DISPLAYPORT = 15
146 enum dc_edid_status {
154 /* audio capability from EDID*/
155 struct dc_cea_audio_mode {
156 uint8_t format_code; /* ucData[0] [6:3]*/
157 uint8_t channel_count; /* ucData[0] [2:0]*/
158 uint8_t sample_rate; /* ucData[1]*/
160 uint8_t sample_size; /* for LPCM*/
161 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
162 uint8_t max_bit_rate;
163 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
169 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
172 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
173 * is used. In this case we assume speaker location are: front left, front
174 * right and front center. */
175 #define DEFAULT_SPEAKER_LOCATION 5
177 #define DC_MAX_AUDIO_DESC_COUNT 16
179 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
181 union display_content_support {
184 unsigned int valid_content_type :1;
185 unsigned int game_content :1;
186 unsigned int cinema_content :1;
187 unsigned int photo_content :1;
188 unsigned int graphics_content :1;
189 unsigned int reserved :27;
193 struct dc_panel_patch {
194 unsigned int dppowerup_delay;
195 unsigned int extra_t12_ms;
198 struct dc_edid_caps {
199 /* sink identification */
200 uint16_t manufacturer_id;
202 uint32_t serial_number;
203 uint8_t manufacture_week;
204 uint8_t manufacture_year;
205 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
208 uint8_t speaker_flags;
209 uint32_t audio_mode_count;
210 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
211 uint32_t audio_latency;
212 uint32_t video_latency;
214 union display_content_support content_support;
220 bool lte_340mcsc_scramble;
225 struct dc_panel_patch panel_patch;
233 struct dc_mode_flags {
234 /* note: part of refresh rate flag*/
235 uint32_t INTERLACE :1;
236 /* native display timing*/
238 /* preferred is the recommended mode, one per display */
239 uint32_t PREFERRED :1;
240 /* true if this mode should use reduced blanking timings
241 *_not_ related to the Reduced Blanking adjustment*/
242 uint32_t REDUCED_BLANKING :1;
243 /* note: part of refreshrate flag*/
244 uint32_t VIDEO_OPTIMIZED_RATE :1;
245 /* should be reported to upper layers as mode_flags*/
246 uint32_t PACKED_PIXEL_FORMAT :1;
248 uint32_t PREFERRED_VIEW :1;
249 /* this timing should be used only in tiled mode*/
250 uint32_t TILED_MODE :1;
251 uint32_t DSE_MODE :1;
252 /* Refresh rate divider when Miracast sink is using a
253 different rate than the output display device
254 Must be zero for wired displays and non-zero for
256 uint32_t MIRACAST_REFRESH_DIVIDER;
260 enum dc_timing_source {
261 TIMING_SOURCE_UNDEFINED,
263 /* explicitly specifed by user, most important*/
264 TIMING_SOURCE_USER_FORCED,
265 TIMING_SOURCE_USER_OVERRIDE,
266 TIMING_SOURCE_CUSTOM,
267 TIMING_SOURCE_EXPLICIT,
269 /* explicitly specified by the display device, more important*/
270 TIMING_SOURCE_EDID_CEA_SVD_3D,
271 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
272 TIMING_SOURCE_EDID_CEA_SVD_420,
273 TIMING_SOURCE_EDID_DETAILED,
274 TIMING_SOURCE_EDID_ESTABLISHED,
275 TIMING_SOURCE_EDID_STANDARD,
276 TIMING_SOURCE_EDID_CEA_SVD,
277 TIMING_SOURCE_EDID_CVT_3BYTE,
278 TIMING_SOURCE_EDID_4BYTE,
282 TIMING_SOURCE_HDMI_VIC,
284 /* implicitly specified by display device, still safe but less important*/
285 TIMING_SOURCE_DEFAULT,
287 /* only used for custom base modes */
288 TIMING_SOURCE_CUSTOM_BASE,
290 /* these timing might not work, least important*/
291 TIMING_SOURCE_RANGELIMIT,
292 TIMING_SOURCE_OS_FORCED,
293 TIMING_SOURCE_IMPLICIT,
295 /* only used by default mode list*/
296 TIMING_SOURCE_BASICMODE,
302 struct stereo_3d_features {
307 bool singleFrameSWPacked;
310 enum dc_timing_support_method {
311 TIMING_SUPPORT_METHOD_UNDEFINED,
312 TIMING_SUPPORT_METHOD_EXPLICIT,
313 TIMING_SUPPORT_METHOD_IMPLICIT,
314 TIMING_SUPPORT_METHOD_NATIVE
317 struct dc_mode_info {
318 uint32_t pixel_width;
319 uint32_t pixel_height;
321 /* Vertical refresh rate for progressive modes.
322 * Field rate for interlaced modes.*/
324 enum dc_timing_standard timing_standard;
325 enum dc_timing_source timing_source;
326 struct dc_mode_flags flags;
329 enum dc_power_state {
330 DC_POWER_STATE_ON = 1,
331 DC_POWER_STATE_STANDBY,
332 DC_POWER_STATE_SUSPEND,
337 enum dc_video_power_state {
338 DC_VIDEO_POWER_UNSPECIFIED = 0,
339 DC_VIDEO_POWER_ON = 1,
340 DC_VIDEO_POWER_STANDBY,
341 DC_VIDEO_POWER_SUSPEND,
343 DC_VIDEO_POWER_HIBERNATE,
344 DC_VIDEO_POWER_SHUTDOWN,
345 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
346 DC_VIDEO_POWER_AFTER_RESET,
347 DC_VIDEO_POWER_MAXIMUM
350 enum dc_acpi_cm_power_state {
351 DC_ACPI_CM_POWER_STATE_D0 = 1,
352 DC_ACPI_CM_POWER_STATE_D1 = 2,
353 DC_ACPI_CM_POWER_STATE_D2 = 4,
354 DC_ACPI_CM_POWER_STATE_D3 = 8
357 enum dc_connection_type {
359 dc_connection_single,
360 dc_connection_mst_branch,
361 dc_connection_active_dongle
364 struct dc_csc_adjustments {
365 struct fixed31_32 contrast;
366 struct fixed31_32 saturation;
367 struct fixed31_32 brightness;
368 struct fixed31_32 hue;
371 enum dpcd_downstream_port_max_bpc {
372 DOWN_STREAM_MAX_8BPC = 0,
373 DOWN_STREAM_MAX_10BPC,
374 DOWN_STREAM_MAX_12BPC,
375 DOWN_STREAM_MAX_16BPC
377 struct dc_dongle_caps {
378 /* dongle type (DP converter, CV smart dongle) */
379 enum display_dongle_type dongle_type;
380 bool extendedCapValid;
381 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
382 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
383 bool is_dp_hdmi_s3d_converter;
384 bool is_dp_hdmi_ycbcr422_pass_through;
385 bool is_dp_hdmi_ycbcr420_pass_through;
386 bool is_dp_hdmi_ycbcr422_converter;
387 bool is_dp_hdmi_ycbcr420_converter;
388 uint32_t dp_hdmi_max_bpc;
389 uint32_t dp_hdmi_max_pixel_clk;
392 enum scaling_transformation {
393 SCALING_TRANSFORMATION_UNINITIALIZED,
394 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
395 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
396 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
397 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
398 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
399 SCALING_TRANSFORMATION_INVALID = 0x80000000,
401 /* Flag the first and last */
402 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
403 SCALING_TRANSFORMATION_END =
404 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
407 enum display_content_type {
408 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
409 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
410 DISPLAY_CONTENT_TYPE_PHOTO = 2,
411 DISPLAY_CONTENT_TYPE_CINEMA = 4,
412 DISPLAY_CONTENT_TYPE_GAME = 8
417 union audio_sample_rates {
418 struct sample_rates {
424 uint8_t RATE_176_4:1;
431 struct audio_speaker_flags {
439 uint32_t SUPPORT_AI:1;
442 struct audio_speaker_info {
443 uint32_t ALLSPEAKERS:7;
444 uint32_t SUPPORT_AI:1;
448 struct audio_info_flags {
452 struct audio_speaker_flags speaker_flags;
453 struct audio_speaker_info info;
459 enum audio_format_code {
460 AUDIO_FORMAT_CODE_FIRST = 1,
461 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
463 AUDIO_FORMAT_CODE_AC3,
465 AUDIO_FORMAT_CODE_MPEG1,
467 AUDIO_FORMAT_CODE_MP3,
469 AUDIO_FORMAT_CODE_MPEG2,
470 AUDIO_FORMAT_CODE_AAC,
471 AUDIO_FORMAT_CODE_DTS,
472 AUDIO_FORMAT_CODE_ATRAC,
473 AUDIO_FORMAT_CODE_1BITAUDIO,
474 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
475 AUDIO_FORMAT_CODE_DTS_HD,
476 AUDIO_FORMAT_CODE_MAT_MLP,
477 AUDIO_FORMAT_CODE_DST,
478 AUDIO_FORMAT_CODE_WMAPRO,
479 AUDIO_FORMAT_CODE_LAST,
480 AUDIO_FORMAT_CODE_COUNT =
481 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
485 /* ucData[0] [6:3] */
486 enum audio_format_code format_code;
487 /* ucData[0] [2:0] */
488 uint8_t channel_count;
490 union audio_sample_rates sample_rates;
494 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
495 uint8_t max_bit_rate;
496 /* for Audio Formats 9-15 */
497 uint8_t vendor_specific;
502 struct audio_info_flags flags;
503 uint32_t video_latency;
504 uint32_t audio_latency;
505 uint32_t display_index;
506 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
507 uint32_t manufacture_id;
509 /* PortID used for ContainerID when defined */
512 /* this field must be last in this struct */
513 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
517 enum vrr_state state;
520 uint32_t inserted_frame_duration_in_us;
521 uint32_t frames_to_insert;
522 uint32_t frame_counter;
525 struct dc_info_packet {
534 #define DC_PLANE_UPDATE_TIMES_MAX 10
536 struct dc_plane_flip_time {
537 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
539 unsigned int prev_update_time_in_us;
542 // Will combine with vrr_params at some point.
543 struct freesync_context {
548 unsigned int min_refresh_in_micro_hz;
549 unsigned int nominal_refresh_in_micro_hz;
553 unsigned char psr_version;
554 unsigned int psr_rfb_setup_time;
555 bool psr_exit_link_training_required;
557 bool psr_frame_capture_indication_req;
558 unsigned int psr_sdp_transmit_line_num_deadline;
561 union dmcu_psr_level {
563 unsigned int SKIP_CRC:1;
564 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
565 unsigned int SKIP_PHY_POWER_DOWN:1;
566 unsigned int SKIP_AUX_ACK_CHECK:1;
567 unsigned int SKIP_CRTC_DISABLE:1;
568 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
569 unsigned int SKIP_SMU_NOTIFICATION:1;
570 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
571 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
572 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
573 unsigned int RESERVED:22;
578 enum physical_phy_id {
590 PHYLD_UNKNOWN = (-1L)
594 PHY_TYPE_UNKNOWN = 1,
595 PHY_TYPE_PCIE_PHY = 2,
601 enum channel_id channel;
603 enum transmitter transmitterId;
604 /* Engine Id is used for Dig Be source select */
605 enum engine_id engineId;
606 /* Controller Id used for Dig Fe source select */
607 enum controller_id controllerId;
609 enum phy_type phyType;
610 /* Physical PHY Id used by SMU interpretation */
611 enum physical_phy_id smuPhyId;
612 /* Vertical total pixels from crtc timing.
613 * This is used for static screen detection.
614 * ie. If we want to detect half a frame,
615 * we use this to determine the hyst lines.
617 unsigned int crtcTimingVerticalTotal;
618 /* PSR supported from panel capabilities and
619 * current display configuration
621 bool psrSupportedDisplayConfig;
622 /* Whether fast link training is supported by the panel */
623 bool psrExitLinkTrainingRequired;
624 /* If RFB setup time is greater than the total VBLANK time,
625 * it is not possible for the sink to capture the video frame
626 * in the same frame the SDP is sent. In this case,
627 * the frame capture indication bit should be set and an extra
628 * static frame should be transmitted to the sink.
630 bool psrFrameCaptureIndicationReq;
631 /* Set the last possible line SDP may be transmitted without violating
632 * the RFB setup time or entering the active video frame.
634 unsigned int sdpTransmitLineNumDeadline;
635 /* The VSync rate in Hz used to calculate the
636 * step size for smooth brightness feature
638 unsigned int vsyncRateHz;
639 unsigned int skipPsrWaitForPllLock;
640 unsigned int numberOfControllers;
641 /* Unused, for future use. To indicate that first changed frame from
642 * state3 shouldn't result in psr_inactive, but rather to perform
643 * an automatic single frame rfb_update.
645 bool rfb_update_auto_en;
646 /* Number of frame before entering static screen */
647 unsigned int timehyst_frames;
648 /* Partial frames before entering static screen */
649 unsigned int hyst_lines;
650 /* # of repeated AUX transaction attempts to make before
651 * indicating failure to the driver
653 unsigned int aux_repeats;
654 /* Controls hw blocks to power down during PSR active state */
655 union dmcu_psr_level psr_level;
656 /* Controls additional delay after remote frame capture before
657 * continuing powerd own
659 unsigned int frame_delay;
662 struct colorspace_transform {
663 struct fixed31_32 matrix[12];
673 #endif /* DC_TYPES_H_ */