drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include "dm_services.h"
  28 #include "core_types.h"
  29 #include "resource.h"
  30 #include "custom_float.h"
  31 #include "dcn10_hw_sequencer.h"
  32 #include "dce110/dce110_hw_sequencer.h"
  33 #include "dce/dce_hwseq.h"
  34 #include "abm.h"
  35 #include "dmcu.h"
  36 #include "dcn10_optc.h"
  37 #include "dcn10/dcn10_dpp.h"
  38 #include "dcn10/dcn10_mpc.h"
  39 #include "timing_generator.h"
  40 #include "opp.h"
  41 #include "ipp.h"
  42 #include "mpc.h"
  43 #include "reg_helper.h"
  44 #include "custom_float.h"
  45 #include "dcn10_hubp.h"
  46 #include "dcn10_hubbub.h"
  47 #include "dcn10_cm_common.h"
  48
  49 #define DC_LOGGER_INIT(logger)
  50
  51 #define CTX \
  52         hws->ctx
  53 #define REG(reg)\
  54         hws->regs->reg
  55
  56 #undef FN
  57 #define FN(reg_name, field_name) \
  58         hws->shifts->field_name, hws->masks->field_name
  59
  60 /*print is 17 wide, first two characters are spaces*/
  61 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  62         print_microsec(dc_ctx, ref_cycle)
  63
  64 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
  65 {
  66         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
  67         static const unsigned int frac = 1000;
  68         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  69
  70         DTN_INFO("  %11d.%03d",
  71                         us_x10 / frac,
  72                         us_x10 % frac);
  73 }
  74
  75
  76 static void log_mpc_crc(struct dc *dc)
  77 {
  78         struct dc_context *dc_ctx = dc->ctx;
  79         struct dce_hwseq *hws = dc->hwseq;
  80
  81         if (REG(MPC_CRC_RESULT_GB))
  82                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  83                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  84         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  85                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  86                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  87 }
  88
  89 void dcn10_log_hubbub_state(struct dc *dc)
  90 {
  91         struct dc_context *dc_ctx = dc->ctx;
  92         struct dcn_hubbub_wm wm;
  93         int i;
  94
  95         hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
  96
  97         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
  98                         "         sr_enter          sr_exit  dram_clk_change\n");
  99
 100         for (i = 0; i < 4; i++) {
 101                 struct dcn_hubbub_wm_set *s;
 102
 103                 s = &wm.sets[i];
 104                 DTN_INFO("WM_Set[%d]:", s->wm_set);
 105                 DTN_INFO_MICRO_SEC(s->data_urgent);
 106                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 107                 DTN_INFO_MICRO_SEC(s->sr_enter);
 108                 DTN_INFO_MICRO_SEC(s->sr_exit);
 109                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 110                 DTN_INFO("\n");
 111         }
 112
 113         DTN_INFO("\n");
 114 }
 115
 116 static void dcn10_log_hubp_states(struct dc *dc)
 117 {
 118         struct dc_context *dc_ctx = dc->ctx;
 119         struct resource_pool *pool = dc->res_pool;
 120         int i;
 121
 122         DTN_INFO("HUBP:  format  addr_hi  width  height"
 123                         "  rot  mir  sw_mode  dcc_en  blank_en  ttu_dis  underflow"
 124                         "   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 125         for (i = 0; i < pool->pipe_count; i++) {
 126                 struct hubp *hubp = pool->hubps[i];
 127                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
 128
 129                 hubp->funcs->hubp_read_state(hubp);
 130
 131                 if (!s->blank_en) {
 132                         DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
 133                                         "  %6d  %8d  %7d  %8xh",
 134                                         hubp->inst,
 135                                         s->pixel_format,
 136                                         s->inuse_addr_hi,
 137                                         s->viewport_width,
 138                                         s->viewport_height,
 139                                         s->rotation_angle,
 140                                         s->h_mirror_en,
 141                                         s->sw_mode,
 142                                         s->dcc_en,
 143                                         s->blank_en,
 144                                         s->ttu_disable,
 145                                         s->underflow_status);
 146                         DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
 147                         DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
 148                         DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
 149                         DTN_INFO("\n");
 150                 }
 151         }
 152
 153         DTN_INFO("\n=========RQ========\n");
 154         DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"
 155                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"
 156                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h\n");
 157         for (i = 0; i < pool->pipe_count; i++) {
 158                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 159                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 160
 161                 if (!s->blank_en)
 162                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 163                                 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
 164                                 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
 165                                 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
 166                                 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
 167                                 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
 168                                 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
 169                                 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
 170                                 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
 171                                 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
 172         }
 173
 174         DTN_INFO("========DLG========\n");
 175         DTN_INFO("HUBP:  rc_hbe     dlg_vbe    min_d_y_n  rc_per_ht  rc_x_a_s "
 176                         "  dst_y_a_s  dst_y_pf   dst_y_vvb  dst_y_rvb  dst_y_vfl  dst_y_rfl  rf_pix_fq"
 177                         "  vratio_pf  vrat_pf_c  rc_pg_vbl  rc_pg_vbc  rc_mc_vbl  rc_mc_vbc  rc_pg_fll"
 178                         "  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "
 179                         "  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "
 180                         "  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"
 181                         "  x_rp_dlay  x_rr_sfl\n");
 182         for (i = 0; i < pool->pipe_count; i++) {
 183                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 184                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 185
 186                 if (!s->blank_en)
 187                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 188                                 "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 189                                 "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 190                                 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
 191                                 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
 192                                 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
 193                                 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
 194                                 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
 195                                 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
 196                                 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
 197                                 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
 198                                 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
 199                                 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
 200                                 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
 201                                 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
 202                                 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
 203                                 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
 204                                 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
 205                                 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
 206                                 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
 207                                 dlg_regs->xfc_reg_remote_surface_flip_latency);
 208         }
 209
 210         DTN_INFO("========TTU========\n");
 211         DTN_INFO("HUBP:  qos_ll_wm  qos_lh_wm  mn_ttu_vb  qos_l_flp  rc_rd_p_l  rc_rd_l    rc_rd_p_c"
 212                         "  rc_rd_c    rc_rd_c0   rc_rd_pc0  rc_rd_c1   rc_rd_pc1  qos_lf_l   qos_rds_l"
 213                         "  qos_lf_c   qos_rds_c  qos_lf_c0  qos_rds_c0 qos_lf_c1  qos_rds_c1\n");
 214         for (i = 0; i < pool->pipe_count; i++) {
 215                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 216                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 217
 218                 if (!s->blank_en)
 219                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 220                                 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
 221                                 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
 222                                 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
 223                                 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
 224                                 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
 225                                 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
 226                                 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
 227         }
 228         DTN_INFO("\n");
 229 }
 230
 231 void dcn10_log_hw_state(struct dc *dc)
 232 {
 233         struct dc_context *dc_ctx = dc->ctx;
 234         struct resource_pool *pool = dc->res_pool;
 235         int i;
 236
 237         DTN_INFO_BEGIN();
 238
 239         dcn10_log_hubbub_state(dc);
 240
 241         dcn10_log_hubp_states(dc);
 242
 243         DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
 244                         "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
 245                         "C31 C32   C33 C34\n");
 246         for (i = 0; i < pool->pipe_count; i++) {
 247                 struct dpp *dpp = pool->dpps[i];
 248                 struct dcn_dpp_state s;
 249
 250                 dpp->funcs->dpp_read_state(dpp, &s);
 251
 252                 DTN_INFO("[%2d]:  %11xh  %-11s  %-11s  %-11s"
 253                                 "%8x    %08xh %08xh %08xh %08xh %08xh %08xh",
 254                                 dpp->inst,
 255                                 s.igam_input_format,
 256                                 (s.igam_lut_mode == 0) ? "BypassFixed" :
 257                                         ((s.igam_lut_mode == 1) ? "BypassFloat" :
 258                                         ((s.igam_lut_mode == 2) ? "RAM" :
 259                                         ((s.igam_lut_mode == 3) ? "RAM" :
 260                                                                  "Unknown"))),
 261                                 (s.dgam_lut_mode == 0) ? "Bypass" :
 262                                         ((s.dgam_lut_mode == 1) ? "sRGB" :
 263                                         ((s.dgam_lut_mode == 2) ? "Ycc" :
 264                                         ((s.dgam_lut_mode == 3) ? "RAM" :
 265                                         ((s.dgam_lut_mode == 4) ? "RAM" :
 266                                                                  "Unknown")))),
 267                                 (s.rgam_lut_mode == 0) ? "Bypass" :
 268                                         ((s.rgam_lut_mode == 1) ? "sRGB" :
 269                                         ((s.rgam_lut_mode == 2) ? "Ycc" :
 270                                         ((s.rgam_lut_mode == 3) ? "RAM" :
 271                                         ((s.rgam_lut_mode == 4) ? "RAM" :
 272                                                                  "Unknown")))),
 273                                 s.gamut_remap_mode,
 274                                 s.gamut_remap_c11_c12,
 275                                 s.gamut_remap_c13_c14,
 276                                 s.gamut_remap_c21_c22,
 277                                 s.gamut_remap_c23_c24,
 278                                 s.gamut_remap_c31_c32,
 279                                 s.gamut_remap_c33_c34);
 280                 DTN_INFO("\n");
 281         }
 282         DTN_INFO("\n");
 283
 284         DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 285         for (i = 0; i < pool->pipe_count; i++) {
 286                 struct mpcc_state s = {0};
 287
 288                 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
 289                 if (s.opp_id != 0xf)
 290                         DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
 291                                 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
 292                                 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
 293                                 s.idle);
 294         }
 295         DTN_INFO("\n");
 296
 297         DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel"
 298                         "  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow\n");
 299
 300         for (i = 0; i < pool->timing_generator_count; i++) {
 301                 struct timing_generator *tg = pool->timing_generators[i];
 302                 struct dcn_otg_state s = {0};
 303
 304                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 305
 306                 //only print if OTG master is enabled
 307                 if ((s.otg_enabled & 1) == 0)
 308                         continue;
 309
 310                 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
 311                                 " %5d %5d %5d %5d  %9d\n",
 312                                 tg->inst,
 313                                 s.v_blank_start,
 314                                 s.v_blank_end,
 315                                 s.v_sync_a_start,
 316                                 s.v_sync_a_end,
 317                                 s.v_sync_a_pol,
 318                                 s.v_total_max,
 319                                 s.v_total_min,
 320                                 s.v_total_max_sel,
 321                                 s.v_total_min_sel,
 322                                 s.h_blank_start,
 323                                 s.h_blank_end,
 324                                 s.h_sync_a_start,
 325                                 s.h_sync_a_end,
 326                                 s.h_sync_a_pol,
 327                                 s.h_total,
 328                                 s.v_total,
 329                                 s.underflow_occurred_status);
 330
 331                 // Clear underflow for debug purposes
 332                 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
 333                 // This function is called only from Windows or Diags test environment, hence it's safe to clear
 334                 // it from here without affecting the original intent.
 335                 tg->funcs->clear_optc_underflow(tg);
 336         }
 337         DTN_INFO("\n");
 338
 339         DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
 340                 "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
 341                         dc->current_state->bw.dcn.clk.dcfclk_khz,
 342                         dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz,
 343                         dc->current_state->bw.dcn.clk.dispclk_khz,
 344                         dc->current_state->bw.dcn.clk.dppclk_khz,
 345                         dc->current_state->bw.dcn.clk.max_supported_dppclk_khz,
 346                         dc->current_state->bw.dcn.clk.fclk_khz,
 347                         dc->current_state->bw.dcn.clk.socclk_khz);
 348
 349         log_mpc_crc(dc);
 350
 351         DTN_INFO_END();
 352 }
 353
 354 static void enable_power_gating_plane(
 355         struct dce_hwseq *hws,
 356         bool enable)
 357 {
 358         bool force_on = 1; /* disable power gating */
 359
 360         if (enable)
 361                 force_on = 0;
 362
 363         /* DCHUBP0/1/2/3 */
 364         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 365         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 366         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 367         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 368
 369         /* DPP0/1/2/3 */
 370         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 371         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 372         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 373         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 374 }
 375
 376 static void disable_vga(
 377         struct dce_hwseq *hws)
 378 {
 379         unsigned int in_vga1_mode = 0;
 380         unsigned int in_vga2_mode = 0;
 381         unsigned int in_vga3_mode = 0;
 382         unsigned int in_vga4_mode = 0;
 383
 384         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 385         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 386         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 387         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 388
 389         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 390                         in_vga3_mode == 0 && in_vga4_mode == 0)
 391                 return;
 392
 393         REG_WRITE(D1VGA_CONTROL, 0);
 394         REG_WRITE(D2VGA_CONTROL, 0);
 395         REG_WRITE(D3VGA_CONTROL, 0);
 396         REG_WRITE(D4VGA_CONTROL, 0);
 397
 398         /* HW Engineer's Notes:
 399          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 400          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 401          *
 402          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 403          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 404          */
 405         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 406         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 407 }
 408
 409 static void dpp_pg_control(
 410                 struct dce_hwseq *hws,
 411                 unsigned int dpp_inst,
 412                 bool power_on)
 413 {
 414         uint32_t power_gate = power_on ? 0 : 1;
 415         uint32_t pwr_status = power_on ? 0 : 2;
 416
 417         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 418                 return;
 419         if (REG(DOMAIN1_PG_CONFIG) == 0)
 420                 return;
 421
 422         switch (dpp_inst) {
 423         case 0: /* DPP0 */
 424                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 425                                 DOMAIN1_POWER_GATE, power_gate);
 426
 427                 REG_WAIT(DOMAIN1_PG_STATUS,
 428                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 429                                 1, 1000);
 430                 break;
 431         case 1: /* DPP1 */
 432                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 433                                 DOMAIN3_POWER_GATE, power_gate);
 434
 435                 REG_WAIT(DOMAIN3_PG_STATUS,
 436                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 437                                 1, 1000);
 438                 break;
 439         case 2: /* DPP2 */
 440                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 441                                 DOMAIN5_POWER_GATE, power_gate);
 442
 443                 REG_WAIT(DOMAIN5_PG_STATUS,
 444                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 445                                 1, 1000);
 446                 break;
 447         case 3: /* DPP3 */
 448                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 449                                 DOMAIN7_POWER_GATE, power_gate);
 450
 451                 REG_WAIT(DOMAIN7_PG_STATUS,
 452                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 453                                 1, 1000);
 454                 break;
 455         default:
 456                 BREAK_TO_DEBUGGER();
 457                 break;
 458         }
 459 }
 460
 461 static void hubp_pg_control(
 462                 struct dce_hwseq *hws,
 463                 unsigned int hubp_inst,
 464                 bool power_on)
 465 {
 466         uint32_t power_gate = power_on ? 0 : 1;
 467         uint32_t pwr_status = power_on ? 0 : 2;
 468
 469         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 470                 return;
 471         if (REG(DOMAIN0_PG_CONFIG) == 0)
 472                 return;
 473
 474         switch (hubp_inst) {
 475         case 0: /* DCHUBP0 */
 476                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 477                                 DOMAIN0_POWER_GATE, power_gate);
 478
 479                 REG_WAIT(DOMAIN0_PG_STATUS,
 480                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 481                                 1, 1000);
 482                 break;
 483         case 1: /* DCHUBP1 */
 484                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 485                                 DOMAIN2_POWER_GATE, power_gate);
 486
 487                 REG_WAIT(DOMAIN2_PG_STATUS,
 488                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 489                                 1, 1000);
 490                 break;
 491         case 2: /* DCHUBP2 */
 492                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 493                                 DOMAIN4_POWER_GATE, power_gate);
 494
 495                 REG_WAIT(DOMAIN4_PG_STATUS,
 496                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 497                                 1, 1000);
 498                 break;
 499         case 3: /* DCHUBP3 */
 500                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 501                                 DOMAIN6_POWER_GATE, power_gate);
 502
 503                 REG_WAIT(DOMAIN6_PG_STATUS,
 504                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 505                                 1, 1000);
 506                 break;
 507         default:
 508                 BREAK_TO_DEBUGGER();
 509                 break;
 510         }
 511 }
 512
 513 static void power_on_plane(
 514         struct dce_hwseq *hws,
 515         int plane_id)
 516 {
 517         DC_LOGGER_INIT(hws->ctx->logger);
 518         if (REG(DC_IP_REQUEST_CNTL)) {
 519                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 520                                 IP_REQUEST_EN, 1);
 521                 dpp_pg_control(hws, plane_id, true);
 522                 hubp_pg_control(hws, plane_id, true);
 523                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 524                                 IP_REQUEST_EN, 0);
 525                 DC_LOG_DEBUG(
 526                                 "Un-gated front end for pipe %d\n", plane_id);
 527         }
 528 }
 529
 530 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 531 {
 532         struct dce_hwseq *hws = dc->hwseq;
 533         struct hubp *hubp = dc->res_pool->hubps[0];
 534
 535         if (!hws->wa_state.DEGVIDCN10_253_applied)
 536                 return;
 537
 538         hubp->funcs->set_blank(hubp, true);
 539
 540         REG_SET(DC_IP_REQUEST_CNTL, 0,
 541                         IP_REQUEST_EN, 1);
 542
 543         hubp_pg_control(hws, 0, false);
 544         REG_SET(DC_IP_REQUEST_CNTL, 0,
 545                         IP_REQUEST_EN, 0);
 546
 547         hws->wa_state.DEGVIDCN10_253_applied = false;
 548 }
 549
 550 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 551 {
 552         struct dce_hwseq *hws = dc->hwseq;
 553         struct hubp *hubp = dc->res_pool->hubps[0];
 554         int i;
 555
 556         if (dc->debug.disable_stutter)
 557                 return;
 558
 559         if (!hws->wa.DEGVIDCN10_253)
 560                 return;
 561
 562         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 563                 if (!dc->res_pool->hubps[i]->power_gated)
 564                         return;
 565         }
 566
 567         /* all pipe power gated, apply work around to enable stutter. */
 568
 569         REG_SET(DC_IP_REQUEST_CNTL, 0,
 570                         IP_REQUEST_EN, 1);
 571
 572         hubp_pg_control(hws, 0, true);
 573         REG_SET(DC_IP_REQUEST_CNTL, 0,
 574                         IP_REQUEST_EN, 0);
 575
 576         hubp->funcs->set_hubp_blank_en(hubp, false);
 577         hws->wa_state.DEGVIDCN10_253_applied = true;
 578 }
 579
 580 static void bios_golden_init(struct dc *dc)
 581 {
 582         struct dc_bios *bp = dc->ctx->dc_bios;
 583         int i;
 584
 585         /* initialize dcn global */
 586         bp->funcs->enable_disp_power_gating(bp,
 587                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 588
 589         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 590                 /* initialize dcn per pipe */
 591                 bp->funcs->enable_disp_power_gating(bp,
 592                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 593         }
 594 }
 595
 596 static void false_optc_underflow_wa(
 597                 struct dc *dc,
 598                 const struct dc_stream_state *stream,
 599                 struct timing_generator *tg)
 600 {
 601         int i;
 602         bool underflow;
 603
 604         if (!dc->hwseq->wa.false_optc_underflow)
 605                 return;
 606
 607         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 608
 609         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 610                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 611
 612                 if (old_pipe_ctx->stream != stream)
 613                         continue;
 614
 615                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 616         }
 617
 618         tg->funcs->set_blank_data_double_buffer(tg, true);
 619
 620         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 621                 tg->funcs->clear_optc_underflow(tg);
 622 }
 623
 624 static enum dc_status dcn10_enable_stream_timing(
 625                 struct pipe_ctx *pipe_ctx,
 626                 struct dc_state *context,
 627                 struct dc *dc)
 628 {
 629         struct dc_stream_state *stream = pipe_ctx->stream;
 630         enum dc_color_space color_space;
 631         struct tg_color black_color = {0};
 632
 633         /* by upper caller loop, pipe0 is parent pipe and be called first.
 634          * back end is set up by for pipe0. Other children pipe share back end
 635          * with pipe 0. No program is needed.
 636          */
 637         if (pipe_ctx->top_pipe != NULL)
 638                 return DC_OK;
 639
 640         /* TODO check if timing_changed, disable stream if timing changed */
 641
 642         /* HW program guide assume display already disable
 643          * by unplug sequence. OTG assume stop.
 644          */
 645         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 646
 647         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 648                         pipe_ctx->clock_source,
 649                         &pipe_ctx->stream_res.pix_clk_params,
 650                         &pipe_ctx->pll_settings)) {
 651                 BREAK_TO_DEBUGGER();
 652                 return DC_ERROR_UNEXPECTED;
 653         }
 654         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 655         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 656         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 657         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 658
 659         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 660
 661         pipe_ctx->stream_res.tg->funcs->program_timing(
 662                         pipe_ctx->stream_res.tg,
 663                         &stream->timing,
 664                         true);
 665
 666 #if 0 /* move to after enable_crtc */
 667         /* TODO: OPP FMT, ABM. etc. should be done here. */
 668         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 669
 670         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 671
 672         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 673                                 pipe_ctx->stream_res.opp,
 674                                 &stream->bit_depth_params,
 675                                 &stream->clamping);
 676 #endif
 677         /* program otg blank color */
 678         color_space = stream->output_color_space;
 679         color_space_to_black_color(dc, color_space, &black_color);
 680
 681         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 682                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 683                                 pipe_ctx->stream_res.tg,
 684                                 &black_color);
 685
 686         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 687                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 688                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 689                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 690                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 691         }
 692
 693         /* VTG is  within DCHUB command block. DCFCLK is always on */
 694         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 695                 BREAK_TO_DEBUGGER();
 696                 return DC_ERROR_UNEXPECTED;
 697         }
 698
 699         /* TODO program crtc source select for non-virtual signal*/
 700         /* TODO program FMT */
 701         /* TODO setup link_enc */
 702         /* TODO set stream attributes */
 703         /* TODO program audio */
 704         /* TODO enable stream if timing changed */
 705         /* TODO unblank stream if DP */
 706
 707         return DC_OK;
 708 }
 709
 710 static void reset_back_end_for_pipe(
 711                 struct dc *dc,
 712                 struct pipe_ctx *pipe_ctx,
 713                 struct dc_state *context)
 714 {
 715         int i;
 716         DC_LOGGER_INIT(dc->ctx->logger);
 717         if (pipe_ctx->stream_res.stream_enc == NULL) {
 718                 pipe_ctx->stream = NULL;
 719                 return;
 720         }
 721
 722         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 723                 /* DPMS may already disable */
 724                 if (!pipe_ctx->stream->dpms_off)
 725                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 726                 else if (pipe_ctx->stream_res.audio) {
 727                         dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 728                 }
 729
 730         }
 731
 732         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 733          * back end share by all pipes and will be disable only when disable
 734          * parent pipe.
 735          */
 736         if (pipe_ctx->top_pipe == NULL) {
 737                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 738
 739                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 740         }
 741
 742         for (i = 0; i < dc->res_pool->pipe_count; i++)
 743                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 744                         break;
 745
 746         if (i == dc->res_pool->pipe_count)
 747                 return;
 748
 749         pipe_ctx->stream = NULL;
 750         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 751                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 752 }
 753
 754 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 755 {
 756         struct hubp *hubp ;
 757         unsigned int i;
 758         bool need_recover = true;
 759
 760         if (!dc->debug.recovery_enabled)
 761                 return false;
 762
 763         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 764                 struct pipe_ctx *pipe_ctx =
 765                         &dc->current_state->res_ctx.pipe_ctx[i];
 766                 if (pipe_ctx != NULL) {
 767                         hubp = pipe_ctx->plane_res.hubp;
 768                         if (hubp != NULL) {
 769                                 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
 770                                         /* one pipe underflow, we will reset all the pipes*/
 771                                         need_recover = true;
 772                                 }
 773                         }
 774                 }
 775         }
 776         if (!need_recover)
 777                 return false;
 778         /*
 779         DCHUBP_CNTL:HUBP_BLANK_EN=1
 780         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
 781         DCHUBP_CNTL:HUBP_DISABLE=1
 782         DCHUBP_CNTL:HUBP_DISABLE=0
 783         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
 784         DCSURF_PRIMARY_SURFACE_ADDRESS
 785         DCHUBP_CNTL:HUBP_BLANK_EN=0
 786         */
 787
 788         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 789                 struct pipe_ctx *pipe_ctx =
 790                         &dc->current_state->res_ctx.pipe_ctx[i];
 791                 if (pipe_ctx != NULL) {
 792                         hubp = pipe_ctx->plane_res.hubp;
 793                         /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
 794                         if (hubp != NULL)
 795                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 796                 }
 797         }
 798         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
 799         hubbub1_soft_reset(dc->res_pool->hubbub, true);
 800
 801         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 802                 struct pipe_ctx *pipe_ctx =
 803                         &dc->current_state->res_ctx.pipe_ctx[i];
 804                 if (pipe_ctx != NULL) {
 805                         hubp = pipe_ctx->plane_res.hubp;
 806                         /*DCHUBP_CNTL:HUBP_DISABLE=1*/
 807                         if (hubp != NULL)
 808                                 hubp->funcs->hubp_disable_control(hubp, true);
 809                 }
 810         }
 811         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 812                 struct pipe_ctx *pipe_ctx =
 813                         &dc->current_state->res_ctx.pipe_ctx[i];
 814                 if (pipe_ctx != NULL) {
 815                         hubp = pipe_ctx->plane_res.hubp;
 816                         /*DCHUBP_CNTL:HUBP_DISABLE=0*/
 817                         if (hubp != NULL)
 818                                 hubp->funcs->hubp_disable_control(hubp, true);
 819                 }
 820         }
 821         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
 822         hubbub1_soft_reset(dc->res_pool->hubbub, false);
 823         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 824                 struct pipe_ctx *pipe_ctx =
 825                         &dc->current_state->res_ctx.pipe_ctx[i];
 826                 if (pipe_ctx != NULL) {
 827                         hubp = pipe_ctx->plane_res.hubp;
 828                         /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
 829                         if (hubp != NULL)
 830                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 831                 }
 832         }
 833         return true;
 834
 835 }
 836
 837
 838 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 839 {
 840         static bool should_log_hw_state; /* prevent hw state log by default */
 841
 842         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 843                 if (should_log_hw_state) {
 844                         dcn10_log_hw_state(dc);
 845                 }
 846                 BREAK_TO_DEBUGGER();
 847                 if (dcn10_hw_wa_force_recovery(dc)) {
 848                 /*check again*/
 849                         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
 850                                 BREAK_TO_DEBUGGER();
 851                 }
 852         }
 853 }
 854
 855 /* trigger HW to start disconnect plane from stream on the next vsync */
 856 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 857 {
 858         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 859         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 860         struct mpc *mpc = dc->res_pool->mpc;
 861         struct mpc_tree *mpc_tree_params;
 862         struct mpcc *mpcc_to_remove = NULL;
 863         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
 864
 865         mpc_tree_params = &(opp->mpc_tree_params);
 866         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
 867
 868         /*Already reset*/
 869         if (mpcc_to_remove == NULL)
 870                 return;
 871
 872         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 873         if (opp != NULL)
 874                 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 875
 876         dc->optimized_required = true;
 877
 878         if (hubp->funcs->hubp_disconnect)
 879                 hubp->funcs->hubp_disconnect(hubp);
 880
 881         if (dc->debug.sanity_checks)
 882                 dcn10_verify_allow_pstate_change_high(dc);
 883 }
 884
 885 static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
 886 {
 887         struct dce_hwseq *hws = dc->hwseq;
 888         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 889         DC_LOGGER_INIT(dc->ctx->logger);
 890
 891         if (REG(DC_IP_REQUEST_CNTL)) {
 892                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 893                                 IP_REQUEST_EN, 1);
 894                 dpp_pg_control(hws, dpp->inst, false);
 895                 hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
 896                 dpp->funcs->dpp_reset(dpp);
 897                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 898                                 IP_REQUEST_EN, 0);
 899                 DC_LOG_DEBUG(
 900                                 "Power gated front end %d\n", pipe_ctx->pipe_idx);
 901         }
 902 }
 903
 904 /* disable HW used by plane.
 905  * note:  cannot disable until disconnect is complete
 906  */
 907 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 908 {
 909         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 910         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 911         int opp_id = hubp->opp_id;
 912
 913         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 914
 915         hubp->funcs->hubp_clk_cntl(hubp, false);
 916
 917         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 918
 919         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
 920                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 921                                 pipe_ctx->stream_res.opp,
 922                                 false);
 923
 924         hubp->power_gated = true;
 925         dc->optimized_required = false; /* We're powering off, no need to optimize */
 926
 927         plane_atomic_power_down(dc, pipe_ctx);
 928
 929         pipe_ctx->stream = NULL;
 930         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 931         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 932         pipe_ctx->top_pipe = NULL;
 933         pipe_ctx->bottom_pipe = NULL;
 934         pipe_ctx->plane_state = NULL;
 935 }
 936
 937 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 938 {
 939         DC_LOGGER_INIT(dc->ctx->logger);
 940
 941         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 942                 return;
 943
 944         plane_atomic_disable(dc, pipe_ctx);
 945
 946         apply_DEGVIDCN10_253_wa(dc);
 947
 948         DC_LOG_DC("Power down front end %d\n",
 949                                         pipe_ctx->pipe_idx);
 950 }
 951
 952 static void dcn10_init_hw(struct dc *dc)
 953 {
 954         int i;
 955         struct abm *abm = dc->res_pool->abm;
 956         struct dmcu *dmcu = dc->res_pool->dmcu;
 957         struct dce_hwseq *hws = dc->hwseq;
 958         struct dc_bios *dcb = dc->ctx->dc_bios;
 959         struct dc_state  *context = dc->current_state;
 960
 961         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 962                 REG_WRITE(REFCLK_CNTL, 0);
 963                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 964                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 965
 966                 if (!dc->debug.disable_clock_gate) {
 967                         /* enable all DCN clock gating */
 968                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 969
 970                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 971
 972                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 973                 }
 974
 975                 enable_power_gating_plane(dc->hwseq, true);
 976         } else {
 977
 978                 if (!dcb->funcs->is_accelerated_mode(dcb)) {
 979                         bios_golden_init(dc);
 980                         disable_vga(dc->hwseq);
 981                 }
 982
 983                 for (i = 0; i < dc->link_count; i++) {
 984                         /* Power up AND update implementation according to the
 985                          * required signal (which may be different from the
 986                          * default signal on connector).
 987                          */
 988                         struct dc_link *link = dc->links[i];
 989
 990                         if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
 991                                 dc->hwss.edp_power_control(link, true);
 992
 993                         link->link_enc->funcs->hw_init(link->link_enc);
 994                 }
 995         }
 996
 997         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 998                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 999
1000                 if (tg->funcs->is_tg_enabled(tg))
1001                         tg->funcs->lock(tg);
1002         }
1003
1004         /* Blank controller using driver code instead of
1005          * command table.
1006          */
1007         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1008                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1009
1010                 if (tg->funcs->is_tg_enabled(tg)) {
1011                         tg->funcs->set_blank(tg, true);
1012                         hwss_wait_for_blank_complete(tg);
1013                 }
1014         }
1015
1016         /* Reset all MPCC muxes */
1017         dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
1018
1019         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1020                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1021                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1022                 struct hubp *hubp = dc->res_pool->hubps[i];
1023                 struct dpp *dpp = dc->res_pool->dpps[i];
1024
1025                 pipe_ctx->stream_res.tg = tg;
1026                 pipe_ctx->pipe_idx = i;
1027
1028                 pipe_ctx->plane_res.hubp = hubp;
1029                 pipe_ctx->plane_res.dpp = dpp;
1030                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1031                 hubp->mpcc_id = dpp->inst;
1032                 hubp->opp_id = 0xf;
1033                 hubp->power_gated = false;
1034
1035                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1036                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1037                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1038                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1039
1040                 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
1041         }
1042
1043         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1044                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1045
1046                 if (tg->funcs->is_tg_enabled(tg))
1047                         tg->funcs->unlock(tg);
1048         }
1049
1050         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1051                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1052                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1053
1054                 dcn10_disable_plane(dc, pipe_ctx);
1055
1056                 pipe_ctx->stream_res.tg = NULL;
1057                 pipe_ctx->plane_res.hubp = NULL;
1058
1059                 tg->funcs->tg_init(tg);
1060         }
1061
1062         /* end of FPGA. Below if real ASIC */
1063         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1064                 return;
1065
1066         for (i = 0; i < dc->res_pool->audio_count; i++) {
1067                 struct audio *audio = dc->res_pool->audios[i];
1068
1069                 audio->funcs->hw_init(audio);
1070         }
1071
1072         if (abm != NULL) {
1073                 abm->funcs->init_backlight(abm);
1074                 abm->funcs->abm_init(abm);
1075         }
1076
1077         if (dmcu != NULL)
1078                 dmcu->funcs->dmcu_init(dmcu);
1079
1080         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1081         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1082
1083         if (!dc->debug.disable_clock_gate) {
1084                 /* enable all DCN clock gating */
1085                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1086
1087                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1088
1089                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1090         }
1091
1092         enable_power_gating_plane(dc->hwseq, true);
1093
1094         memset(&dc->res_pool->dccg->clks, 0, sizeof(dc->res_pool->dccg->clks));
1095 }
1096
1097 static void reset_hw_ctx_wrap(
1098                 struct dc *dc,
1099                 struct dc_state *context)
1100 {
1101         int i;
1102
1103         /* Reset Back End*/
1104         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1105                 struct pipe_ctx *pipe_ctx_old =
1106                         &dc->current_state->res_ctx.pipe_ctx[i];
1107                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1108
1109                 if (!pipe_ctx_old->stream)
1110                         continue;
1111
1112                 if (pipe_ctx_old->top_pipe)
1113                         continue;
1114
1115                 if (!pipe_ctx->stream ||
1116                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1117                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1118
1119                         reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1120                         if (old_clk)
1121                                 old_clk->funcs->cs_power_down(old_clk);
1122                 }
1123         }
1124
1125 }
1126
1127 static bool patch_address_for_sbs_tb_stereo(
1128                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1129 {
1130         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1131         bool sec_split = pipe_ctx->top_pipe &&
1132                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1133         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1134                 (pipe_ctx->stream->timing.timing_3d_format ==
1135                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1136                  pipe_ctx->stream->timing.timing_3d_format ==
1137                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1138                 *addr = plane_state->address.grph_stereo.left_addr;
1139                 plane_state->address.grph_stereo.left_addr =
1140                 plane_state->address.grph_stereo.right_addr;
1141                 return true;
1142         } else {
1143                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1144                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1145                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1146                         plane_state->address.grph_stereo.right_addr =
1147                         plane_state->address.grph_stereo.left_addr;
1148                 }
1149         }
1150         return false;
1151 }
1152
1153
1154
1155 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1156 {
1157         bool addr_patched = false;
1158         PHYSICAL_ADDRESS_LOC addr;
1159         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1160
1161         if (plane_state == NULL)
1162                 return;
1163
1164         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1165
1166         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1167                         pipe_ctx->plane_res.hubp,
1168                         &plane_state->address,
1169                         plane_state->flip_immediate);
1170
1171         plane_state->status.requested_address = plane_state->address;
1172
1173         if (plane_state->flip_immediate)
1174                 plane_state->status.current_address = plane_state->address;
1175
1176         if (addr_patched)
1177                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1178 }
1179
1180 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
1181                                           const struct dc_plane_state *plane_state)
1182 {
1183         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1184         const struct dc_transfer_func *tf = NULL;
1185         bool result = true;
1186
1187         if (dpp_base == NULL)
1188                 return false;
1189
1190         if (plane_state->in_transfer_func)
1191                 tf = plane_state->in_transfer_func;
1192
1193         if (plane_state->gamma_correction &&
1194                 !dpp_base->ctx->dc->debug.always_use_regamma
1195                 && !plane_state->gamma_correction->is_identity
1196                         && dce_use_lut(plane_state->format))
1197                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1198
1199         if (tf == NULL)
1200                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1201         else if (tf->type == TF_TYPE_PREDEFINED) {
1202                 switch (tf->tf) {
1203                 case TRANSFER_FUNCTION_SRGB:
1204                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1205                         break;
1206                 case TRANSFER_FUNCTION_BT709:
1207                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1208                         break;
1209                 case TRANSFER_FUNCTION_LINEAR:
1210                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1211                         break;
1212                 case TRANSFER_FUNCTION_PQ:
1213                 default:
1214                         result = false;
1215                         break;
1216                 }
1217         } else if (tf->type == TF_TYPE_BYPASS) {
1218                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1219         } else {
1220                 cm_helper_translate_curve_to_degamma_hw_format(tf,
1221                                         &dpp_base->degamma_params);
1222                 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1223                                 &dpp_base->degamma_params);
1224                 result = true;
1225         }
1226
1227         return result;
1228 }
1229
1230
1231
1232
1233
1234 static bool
1235 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1236                                const struct dc_stream_state *stream)
1237 {
1238         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1239
1240         if (dpp == NULL)
1241                 return false;
1242
1243         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1244
1245         if (stream->out_transfer_func &&
1246             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1247             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1248                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1249
1250         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1251          * update.
1252          */
1253         else if (cm_helper_translate_curve_to_hw_format(
1254                         stream->out_transfer_func,
1255                         &dpp->regamma_params, false)) {
1256                 dpp->funcs->dpp_program_regamma_pwl(
1257                                 dpp,
1258                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1259         } else
1260                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1261
1262         return true;
1263 }
1264
1265 static void dcn10_pipe_control_lock(
1266         struct dc *dc,
1267         struct pipe_ctx *pipe,
1268         bool lock)
1269 {
1270         /* use TG master update lock to lock everything on the TG
1271          * therefore only top pipe need to lock
1272          */
1273         if (pipe->top_pipe)
1274                 return;
1275
1276         if (dc->debug.sanity_checks)
1277                 dcn10_verify_allow_pstate_change_high(dc);
1278
1279         if (lock)
1280                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1281         else
1282                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1283
1284         if (dc->debug.sanity_checks)
1285                 dcn10_verify_allow_pstate_change_high(dc);
1286 }
1287
1288 static bool wait_for_reset_trigger_to_occur(
1289         struct dc_context *dc_ctx,
1290         struct timing_generator *tg)
1291 {
1292         bool rc = false;
1293
1294         /* To avoid endless loop we wait at most
1295          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1296         const uint32_t frames_to_wait_on_triggered_reset = 10;
1297         int i;
1298
1299         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1300
1301                 if (!tg->funcs->is_counter_moving(tg)) {
1302                         DC_ERROR("TG counter is not moving!\n");
1303                         break;
1304                 }
1305
1306                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1307                         rc = true;
1308                         /* usually occurs at i=1 */
1309                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1310                                         i);
1311                         break;
1312                 }
1313
1314                 /* Wait for one frame. */
1315                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1316                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1317         }
1318
1319         if (false == rc)
1320                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1321
1322         return rc;
1323 }
1324
1325 static void dcn10_enable_timing_synchronization(
1326         struct dc *dc,
1327         int group_index,
1328         int group_size,
1329         struct pipe_ctx *grouped_pipes[])
1330 {
1331         struct dc_context *dc_ctx = dc->ctx;
1332         int i;
1333
1334         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1335
1336         for (i = 1; i < group_size; i++)
1337                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1338                                 grouped_pipes[i]->stream_res.tg,
1339                                 grouped_pipes[0]->stream_res.tg->inst);
1340
1341         DC_SYNC_INFO("Waiting for trigger\n");
1342
1343         /* Need to get only check 1 pipe for having reset as all the others are
1344          * synchronized. Look at last pipe programmed to reset.
1345          */
1346
1347         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1348         for (i = 1; i < group_size; i++)
1349                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1350                                 grouped_pipes[i]->stream_res.tg);
1351
1352         DC_SYNC_INFO("Sync complete\n");
1353 }
1354
1355 static void dcn10_enable_per_frame_crtc_position_reset(
1356         struct dc *dc,
1357         int group_size,
1358         struct pipe_ctx *grouped_pipes[])
1359 {
1360         struct dc_context *dc_ctx = dc->ctx;
1361         int i;
1362
1363         DC_SYNC_INFO("Setting up\n");
1364         for (i = 0; i < group_size; i++)
1365                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1366                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1367                                         grouped_pipes[i]->stream_res.tg,
1368                                         grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1369                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
1370
1371         DC_SYNC_INFO("Waiting for trigger\n");
1372
1373         for (i = 0; i < group_size; i++)
1374                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1375
1376         DC_SYNC_INFO("Multi-display sync is complete\n");
1377 }
1378
1379 /*static void print_rq_dlg_ttu(
1380                 struct dc *core_dc,
1381                 struct pipe_ctx *pipe_ctx)
1382 {
1383         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1384                         "\n============== DML TTU Output parameters [%d] ==============\n"
1385                         "qos_level_low_wm: %d, \n"
1386                         "qos_level_high_wm: %d, \n"
1387                         "min_ttu_vblank: %d, \n"
1388                         "qos_level_flip: %d, \n"
1389                         "refcyc_per_req_delivery_l: %d, \n"
1390                         "qos_level_fixed_l: %d, \n"
1391                         "qos_ramp_disable_l: %d, \n"
1392                         "refcyc_per_req_delivery_pre_l: %d, \n"
1393                         "refcyc_per_req_delivery_c: %d, \n"
1394                         "qos_level_fixed_c: %d, \n"
1395                         "qos_ramp_disable_c: %d, \n"
1396                         "refcyc_per_req_delivery_pre_c: %d\n"
1397                         "=============================================================\n",
1398                         pipe_ctx->pipe_idx,
1399                         pipe_ctx->ttu_regs.qos_level_low_wm,
1400                         pipe_ctx->ttu_regs.qos_level_high_wm,
1401                         pipe_ctx->ttu_regs.min_ttu_vblank,
1402                         pipe_ctx->ttu_regs.qos_level_flip,
1403                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1404                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1405                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1406                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1407                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1408                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1409                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1410                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1411                         );
1412
1413         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1414                         "\n============== DML DLG Output parameters [%d] ==============\n"
1415                         "refcyc_h_blank_end: %d, \n"
1416                         "dlg_vblank_end: %d, \n"
1417                         "min_dst_y_next_start: %d, \n"
1418                         "refcyc_per_htotal: %d, \n"
1419                         "refcyc_x_after_scaler: %d, \n"
1420                         "dst_y_after_scaler: %d, \n"
1421                         "dst_y_prefetch: %d, \n"
1422                         "dst_y_per_vm_vblank: %d, \n"
1423                         "dst_y_per_row_vblank: %d, \n"
1424                         "ref_freq_to_pix_freq: %d, \n"
1425                         "vratio_prefetch: %d, \n"
1426                         "refcyc_per_pte_group_vblank_l: %d, \n"
1427                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1428                         "dst_y_per_pte_row_nom_l: %d, \n"
1429                         "refcyc_per_pte_group_nom_l: %d, \n",
1430                         pipe_ctx->pipe_idx,
1431                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1432                         pipe_ctx->dlg_regs.dlg_vblank_end,
1433                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1434                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1435                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1436                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1437                         pipe_ctx->dlg_regs.dst_y_prefetch,
1438                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1439                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1440                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1441                         pipe_ctx->dlg_regs.vratio_prefetch,
1442                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1443                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1444                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1445                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1446                         );
1447
1448         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1449                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1450                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1451                         "refcyc_per_line_delivery_pre_l: %d, \n"
1452                         "refcyc_per_line_delivery_l: %d, \n"
1453                         "vratio_prefetch_c: %d, \n"
1454                         "refcyc_per_pte_group_vblank_c: %d, \n"
1455                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1456                         "dst_y_per_pte_row_nom_c: %d, \n"
1457                         "refcyc_per_pte_group_nom_c: %d, \n"
1458                         "dst_y_per_meta_row_nom_c: %d, \n"
1459                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1460                         "refcyc_per_line_delivery_pre_c: %d, \n"
1461                         "refcyc_per_line_delivery_c: %d \n"
1462                         "========================================================\n",
1463                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1464                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1465                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1466                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1467                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1468                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1469                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1470                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1471                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1472                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1473                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1474                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1475                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1476                         );
1477
1478         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1479                         "\n============== DML RQ Output parameters [%d] ==============\n"
1480                         "chunk_size: %d \n"
1481                         "min_chunk_size: %d \n"
1482                         "meta_chunk_size: %d \n"
1483                         "min_meta_chunk_size: %d \n"
1484                         "dpte_group_size: %d \n"
1485                         "mpte_group_size: %d \n"
1486                         "swath_height: %d \n"
1487                         "pte_row_height_linear: %d \n"
1488                         "========================================================\n",
1489                         pipe_ctx->pipe_idx,
1490                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1491                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1492                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1493                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1494                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1495                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1496                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1497                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1498                         );
1499 }
1500 */
1501
1502 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1503                 struct vm_system_aperture_param *apt,
1504                 struct dce_hwseq *hws)
1505 {
1506         PHYSICAL_ADDRESS_LOC physical_page_number;
1507         uint32_t logical_addr_low;
1508         uint32_t logical_addr_high;
1509
1510         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1511                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1512         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1513                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1514
1515         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1516                         LOGICAL_ADDR, &logical_addr_low);
1517
1518         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1519                         LOGICAL_ADDR, &logical_addr_high);
1520
1521         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1522         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1523         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1524 }
1525
1526 /* Temporary read settings, future will get values from kmd directly */
1527 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1528                 struct vm_context0_param *vm0,
1529                 struct dce_hwseq *hws)
1530 {
1531         PHYSICAL_ADDRESS_LOC fb_base;
1532         PHYSICAL_ADDRESS_LOC fb_offset;
1533         uint32_t fb_base_value;
1534         uint32_t fb_offset_value;
1535
1536         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1537         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1538
1539         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1540                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1541         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1542                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1543
1544         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1545                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1546         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1547                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1548
1549         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1550                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1551         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1552                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1553
1554         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1555                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1556         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1557                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1558
1559         /*
1560          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1561          * Therefore we need to do
1562          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1563          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1564          */
1565         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1566         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1567         vm0->pte_base.quad_part += fb_base.quad_part;
1568         vm0->pte_base.quad_part -= fb_offset.quad_part;
1569 }
1570
1571
1572 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1573 {
1574         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1575         struct vm_system_aperture_param apt = { {{ 0 } } };
1576         struct vm_context0_param vm0 = { { { 0 } } };
1577
1578         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1579         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1580
1581         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1582         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1583 }
1584
1585 static void dcn10_enable_plane(
1586         struct dc *dc,
1587         struct pipe_ctx *pipe_ctx,
1588         struct dc_state *context)
1589 {
1590         struct dce_hwseq *hws = dc->hwseq;
1591
1592         if (dc->debug.sanity_checks) {
1593                 dcn10_verify_allow_pstate_change_high(dc);
1594         }
1595
1596         undo_DEGVIDCN10_253_wa(dc);
1597
1598         power_on_plane(dc->hwseq,
1599                 pipe_ctx->plane_res.hubp->inst);
1600
1601         /* enable DCFCLK current DCHUB */
1602         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1603
1604         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1605         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1606                         pipe_ctx->stream_res.opp,
1607                         true);
1608
1609 /* TODO: enable/disable in dm as per update type.
1610         if (plane_state) {
1611                 DC_LOG_DC(dc->ctx->logger,
1612                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1613                                 "addr low:0x%x, "
1614                                 "src: %d, %d, %d,"
1615                                 " %d; dst: %d, %d, %d, %d;\n",
1616                                 pipe_ctx->pipe_idx,
1617                                 plane_state,
1618                                 plane_state->address.grph.addr.high_part,
1619                                 plane_state->address.grph.addr.low_part,
1620                                 plane_state->src_rect.x,
1621                                 plane_state->src_rect.y,
1622                                 plane_state->src_rect.width,
1623                                 plane_state->src_rect.height,
1624                                 plane_state->dst_rect.x,
1625                                 plane_state->dst_rect.y,
1626                                 plane_state->dst_rect.width,
1627                                 plane_state->dst_rect.height);
1628
1629                 DC_LOG_DC(dc->ctx->logger,
1630                                 "Pipe %d: width, height, x, y         format:%d\n"
1631                                 "viewport:%d, %d, %d, %d\n"
1632                                 "recout:  %d, %d, %d, %d\n",
1633                                 pipe_ctx->pipe_idx,
1634                                 plane_state->format,
1635                                 pipe_ctx->plane_res.scl_data.viewport.width,
1636                                 pipe_ctx->plane_res.scl_data.viewport.height,
1637                                 pipe_ctx->plane_res.scl_data.viewport.x,
1638                                 pipe_ctx->plane_res.scl_data.viewport.y,
1639                                 pipe_ctx->plane_res.scl_data.recout.width,
1640                                 pipe_ctx->plane_res.scl_data.recout.height,
1641                                 pipe_ctx->plane_res.scl_data.recout.x,
1642                                 pipe_ctx->plane_res.scl_data.recout.y);
1643                 print_rq_dlg_ttu(dc, pipe_ctx);
1644         }
1645 */
1646         if (dc->config.gpu_vm_support)
1647                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1648
1649         if (dc->debug.sanity_checks) {
1650                 dcn10_verify_allow_pstate_change_high(dc);
1651         }
1652 }
1653
1654 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1655 {
1656         int i = 0;
1657         struct dpp_grph_csc_adjustment adjust;
1658         memset(&adjust, 0, sizeof(adjust));
1659         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1660
1661
1662         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1663                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1664                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1665                         adjust.temperature_matrix[i] =
1666                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1667         }
1668
1669         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1670 }
1671
1672
1673 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1674                 enum dc_color_space colorspace,
1675                 uint16_t *matrix)
1676 {
1677         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1678                         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1679                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1680         } else {
1681                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1682                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1683         }
1684 }
1685
1686 static void dcn10_program_output_csc(struct dc *dc,
1687                 struct pipe_ctx *pipe_ctx,
1688                 enum dc_color_space colorspace,
1689                 uint16_t *matrix,
1690                 int opp_id)
1691 {
1692         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1693                 program_csc_matrix(pipe_ctx,
1694                                 colorspace,
1695                                 matrix);
1696 }
1697
1698 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1699 {
1700         if (pipe_ctx->plane_state->visible)
1701                 return true;
1702         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1703                 return true;
1704         return false;
1705 }
1706
1707 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1708 {
1709         if (pipe_ctx->plane_state->visible)
1710                 return true;
1711         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1712                 return true;
1713         return false;
1714 }
1715
1716 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1717 {
1718         if (pipe_ctx->plane_state->visible)
1719                 return true;
1720         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1721                 return true;
1722         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1723                 return true;
1724         return false;
1725 }
1726
1727 bool is_rgb_cspace(enum dc_color_space output_color_space)
1728 {
1729         switch (output_color_space) {
1730         case COLOR_SPACE_SRGB:
1731         case COLOR_SPACE_SRGB_LIMITED:
1732         case COLOR_SPACE_2020_RGB_FULLRANGE:
1733         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1734         case COLOR_SPACE_ADOBERGB:
1735                 return true;
1736         case COLOR_SPACE_YCBCR601:
1737         case COLOR_SPACE_YCBCR709:
1738         case COLOR_SPACE_YCBCR601_LIMITED:
1739         case COLOR_SPACE_YCBCR709_LIMITED:
1740         case COLOR_SPACE_2020_YCBCR:
1741                 return false;
1742         default:
1743                 /* Add a case to switch */
1744                 BREAK_TO_DEBUGGER();
1745                 return false;
1746         }
1747 }
1748
1749 static void dcn10_get_surface_visual_confirm_color(
1750                 const struct pipe_ctx *pipe_ctx,
1751                 struct tg_color *color)
1752 {
1753         uint32_t color_value = MAX_TG_COLOR_VALUE;
1754
1755         switch (pipe_ctx->plane_res.scl_data.format) {
1756         case PIXEL_FORMAT_ARGB8888:
1757                 /* set boarder color to red */
1758                 color->color_r_cr = color_value;
1759                 break;
1760
1761         case PIXEL_FORMAT_ARGB2101010:
1762                 /* set boarder color to blue */
1763                 color->color_b_cb = color_value;
1764                 break;
1765         case PIXEL_FORMAT_420BPP8:
1766                 /* set boarder color to green */
1767                 color->color_g_y = color_value;
1768                 break;
1769         case PIXEL_FORMAT_420BPP10:
1770                 /* set boarder color to yellow */
1771                 color->color_g_y = color_value;
1772                 color->color_r_cr = color_value;
1773                 break;
1774         case PIXEL_FORMAT_FP16:
1775                 /* set boarder color to white */
1776                 color->color_r_cr = color_value;
1777                 color->color_b_cb = color_value;
1778                 color->color_g_y = color_value;
1779                 break;
1780         default:
1781                 break;
1782         }
1783 }
1784
1785 static void dcn10_get_hdr_visual_confirm_color(
1786                 struct pipe_ctx *pipe_ctx,
1787                 struct tg_color *color)
1788 {
1789         uint32_t color_value = MAX_TG_COLOR_VALUE;
1790
1791         // Determine the overscan color based on the top-most (desktop) plane's context
1792         struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
1793
1794         while (top_pipe_ctx->top_pipe != NULL)
1795                 top_pipe_ctx = top_pipe_ctx->top_pipe;
1796
1797         switch (top_pipe_ctx->plane_res.scl_data.format) {
1798         case PIXEL_FORMAT_ARGB2101010:
1799                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_UNITY) {
1800                         /* HDR10, ARGB2101010 - set boarder color to red */
1801                         color->color_r_cr = color_value;
1802                 }
1803                 break;
1804         case PIXEL_FORMAT_FP16:
1805                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1806                         /* HDR10, FP16 - set boarder color to blue */
1807                         color->color_b_cb = color_value;
1808                 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
1809                         /* FreeSync 2 HDR - set boarder color to green */
1810                         color->color_g_y = color_value;
1811                 }
1812                 break;
1813         default:
1814                 /* SDR - set boarder color to Gray */
1815                 color->color_r_cr = color_value/2;
1816                 color->color_b_cb = color_value/2;
1817                 color->color_g_y = color_value/2;
1818                 break;
1819         }
1820 }
1821
1822 static uint16_t fixed_point_to_int_frac(
1823         struct fixed31_32 arg,
1824         uint8_t integer_bits,
1825         uint8_t fractional_bits)
1826 {
1827         int32_t numerator;
1828         int32_t divisor = 1 << fractional_bits;
1829
1830         uint16_t result;
1831
1832         uint16_t d = (uint16_t)dc_fixpt_floor(
1833                 dc_fixpt_abs(
1834                         arg));
1835
1836         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1837                 numerator = (uint16_t)dc_fixpt_floor(
1838                         dc_fixpt_mul_int(
1839                                 arg,
1840                                 divisor));
1841         else {
1842                 numerator = dc_fixpt_floor(
1843                         dc_fixpt_sub(
1844                                 dc_fixpt_from_int(
1845                                         1LL << integer_bits),
1846                                 dc_fixpt_recip(
1847                                         dc_fixpt_from_int(
1848                                                 divisor))));
1849         }
1850
1851         if (numerator >= 0)
1852                 result = (uint16_t)numerator;
1853         else
1854                 result = (uint16_t)(
1855                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1856
1857         if ((result != 0) && dc_fixpt_lt(
1858                 arg, dc_fixpt_zero))
1859                 result |= 1 << (integer_bits + fractional_bits);
1860
1861         return result;
1862 }
1863
1864 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1865                 const struct dc_plane_state *plane_state)
1866 {
1867         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1868                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1869                         && plane_state->input_csc_color_matrix.enable_adjustment
1870                         && plane_state->coeff_reduction_factor.value != 0) {
1871                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1872                         dc_fixpt_mul(plane_state->coeff_reduction_factor,
1873                                         dc_fixpt_from_fraction(256, 255)),
1874                                 2,
1875                                 13);
1876                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1877                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1878         } else {
1879                 bias_and_scale->scale_blue = 0x2000;
1880                 bias_and_scale->scale_red = 0x2000;
1881                 bias_and_scale->scale_green = 0x2000;
1882         }
1883 }
1884
1885 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1886 {
1887         struct dc_bias_and_scale bns_params = {0};
1888
1889         // program the input csc
1890         dpp->funcs->dpp_setup(dpp,
1891                         plane_state->format,
1892                         EXPANSION_MODE_ZERO,
1893                         plane_state->input_csc_color_matrix,
1894                         plane_state->color_space);
1895
1896         //set scale and bias registers
1897         build_prescale_params(&bns_params, plane_state);
1898         if (dpp->funcs->dpp_program_bias_and_scale)
1899                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1900 }
1901
1902 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1903 {
1904         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1905         struct mpcc_blnd_cfg blnd_cfg = {0};
1906         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1907         int mpcc_id;
1908         struct mpcc *new_mpcc;
1909         struct mpc *mpc = dc->res_pool->mpc;
1910         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1911
1912
1913
1914         /* TODO: proper fix once fpga works */
1915
1916         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1917                 dcn10_get_hdr_visual_confirm_color(
1918                                 pipe_ctx, &blnd_cfg.black_color);
1919         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1920                 dcn10_get_surface_visual_confirm_color(
1921                                 pipe_ctx, &blnd_cfg.black_color);
1922         } else {
1923                 color_space_to_black_color(
1924                                 dc, pipe_ctx->stream->output_color_space,
1925                                 &blnd_cfg.black_color);
1926         }
1927
1928         if (per_pixel_alpha)
1929                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1930         else
1931                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1932
1933         blnd_cfg.overlap_only = false;
1934         blnd_cfg.global_alpha = 0xff;
1935         blnd_cfg.global_gain = 0xff;
1936
1937         /* DCN1.0 has output CM before MPC which seems to screw with
1938          * pre-multiplied alpha.
1939          */
1940         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1941                         pipe_ctx->stream->output_color_space)
1942                                         && per_pixel_alpha;
1943
1944
1945         /*
1946          * TODO: remove hack
1947          * Note: currently there is a bug in init_hw such that
1948          * on resume from hibernate, BIOS sets up MPCC0, and
1949          * we do mpcc_remove but the mpcc cannot go to idle
1950          * after remove. This cause us to pick mpcc1 here,
1951          * which causes a pstate hang for yet unknown reason.
1952          */
1953         mpcc_id = hubp->inst;
1954
1955         /* If there is no full update, don't need to touch MPC tree*/
1956         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
1957                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
1958                 return;
1959         }
1960
1961         /* check if this MPCC is already being used */
1962         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1963         /* remove MPCC if being used */
1964         if (new_mpcc != NULL)
1965                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1966         else
1967                 if (dc->debug.sanity_checks)
1968                         mpc->funcs->assert_mpcc_idle_before_connect(
1969                                         dc->res_pool->mpc, mpcc_id);
1970
1971         /* Call MPC to insert new plane */
1972         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1973                         mpc_tree_params,
1974                         &blnd_cfg,
1975                         NULL,
1976                         NULL,
1977                         hubp->inst,
1978                         mpcc_id);
1979
1980         ASSERT(new_mpcc != NULL);
1981
1982         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1983         hubp->mpcc_id = mpcc_id;
1984 }
1985
1986 static void update_scaler(struct pipe_ctx *pipe_ctx)
1987 {
1988         bool per_pixel_alpha =
1989                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1990
1991         /* TODO: proper fix once fpga works */
1992
1993         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1994         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1995         /* scaler configuration */
1996         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1997                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1998 }
1999
2000 static void update_dchubp_dpp(
2001         struct dc *dc,
2002         struct pipe_ctx *pipe_ctx,
2003         struct dc_state *context)
2004 {
2005         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2006         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2007         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2008         union plane_size size = plane_state->plane_size;
2009
2010         /* depends on DML calculation, DPP clock value may change dynamically */
2011         /* If request max dpp clk is lower than current dispclk, no need to
2012          * divided by 2
2013          */
2014         if (plane_state->update_flags.bits.full_update) {
2015                 bool should_divided_by_2 = context->bw.dcn.clk.dppclk_khz <=
2016                                 dc->res_pool->dccg->clks.dispclk_khz / 2;
2017
2018                 dpp->funcs->dpp_dppclk_control(
2019                                 dpp,
2020                                 should_divided_by_2,
2021                                 true);
2022
2023                 dc->res_pool->dccg->clks.dppclk_khz = should_divided_by_2 ?
2024                                                 dc->res_pool->dccg->clks.dispclk_khz / 2 :
2025                                                         dc->res_pool->dccg->clks.dispclk_khz;
2026         }
2027
2028         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2029          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2030          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2031          */
2032         if (plane_state->update_flags.bits.full_update) {
2033                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2034
2035                 hubp->funcs->hubp_setup(
2036                         hubp,
2037                         &pipe_ctx->dlg_regs,
2038                         &pipe_ctx->ttu_regs,
2039                         &pipe_ctx->rq_regs,
2040                         &pipe_ctx->pipe_dlg_param);
2041         }
2042
2043         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2044
2045         if (plane_state->update_flags.bits.full_update ||
2046                 plane_state->update_flags.bits.bpp_change)
2047                 update_dpp(dpp, plane_state);
2048
2049         if (plane_state->update_flags.bits.full_update ||
2050                 plane_state->update_flags.bits.per_pixel_alpha_change)
2051                 dc->hwss.update_mpcc(dc, pipe_ctx);
2052
2053         if (plane_state->update_flags.bits.full_update ||
2054                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2055                 plane_state->update_flags.bits.scaling_change ||
2056                 plane_state->update_flags.bits.position_change) {
2057                 update_scaler(pipe_ctx);
2058         }
2059
2060         if (plane_state->update_flags.bits.full_update ||
2061                 plane_state->update_flags.bits.scaling_change ||
2062                 plane_state->update_flags.bits.position_change) {
2063                 hubp->funcs->mem_program_viewport(
2064                         hubp,
2065                         &pipe_ctx->plane_res.scl_data.viewport,
2066                         &pipe_ctx->plane_res.scl_data.viewport_c);
2067         }
2068
2069         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2070                 dc->hwss.set_cursor_position(pipe_ctx);
2071                 dc->hwss.set_cursor_attribute(pipe_ctx);
2072         }
2073
2074         if (plane_state->update_flags.bits.full_update) {
2075                 /*gamut remap*/
2076                 program_gamut_remap(pipe_ctx);
2077
2078                 dc->hwss.program_output_csc(dc,
2079                                 pipe_ctx,
2080                                 pipe_ctx->stream->output_color_space,
2081                                 pipe_ctx->stream->csc_color_matrix.matrix,
2082                                 hubp->opp_id);
2083         }
2084
2085         if (plane_state->update_flags.bits.full_update ||
2086                 plane_state->update_flags.bits.pixel_format_change ||
2087                 plane_state->update_flags.bits.horizontal_mirror_change ||
2088                 plane_state->update_flags.bits.rotation_change ||
2089                 plane_state->update_flags.bits.swizzle_change ||
2090                 plane_state->update_flags.bits.dcc_change ||
2091                 plane_state->update_flags.bits.bpp_change ||
2092                 plane_state->update_flags.bits.scaling_change) {
2093                 hubp->funcs->hubp_program_surface_config(
2094                         hubp,
2095                         plane_state->format,
2096                         &plane_state->tiling_info,
2097                         &size,
2098                         plane_state->rotation,
2099                         &plane_state->dcc,
2100                         plane_state->horizontal_mirror);
2101         }
2102
2103         hubp->power_gated = false;
2104
2105         dc->hwss.update_plane_addr(dc, pipe_ctx);
2106
2107         if (is_pipe_tree_visible(pipe_ctx))
2108                 hubp->funcs->set_blank(hubp, false);
2109 }
2110
2111 static void dcn10_blank_pixel_data(
2112                 struct dc *dc,
2113                 struct pipe_ctx *pipe_ctx,
2114                 bool blank)
2115 {
2116         enum dc_color_space color_space;
2117         struct tg_color black_color = {0};
2118         struct stream_resource *stream_res = &pipe_ctx->stream_res;
2119         struct dc_stream_state *stream = pipe_ctx->stream;
2120
2121         /* program otg blank color */
2122         color_space = stream->output_color_space;
2123         color_space_to_black_color(dc, color_space, &black_color);
2124
2125         /*
2126          * The way 420 is packed, 2 channels carry Y component, 1 channel
2127          * alternate between Cb and Cr, so both channels need the pixel
2128          * value for Y
2129          */
2130         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2131                 black_color.color_r_cr = black_color.color_g_y;
2132
2133
2134         if (stream_res->tg->funcs->set_blank_color)
2135                 stream_res->tg->funcs->set_blank_color(
2136                                 stream_res->tg,
2137                                 &black_color);
2138
2139         if (!blank) {
2140                 if (stream_res->tg->funcs->set_blank)
2141                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2142                 if (stream_res->abm)
2143                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2144         } else if (blank) {
2145                 if (stream_res->abm)
2146                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2147                 if (stream_res->tg->funcs->set_blank)
2148                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2149         }
2150 }
2151
2152 static void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2153 {
2154         struct fixed31_32 multiplier = dc_fixpt_from_fraction(
2155                         pipe_ctx->plane_state->sdr_white_level, 80);
2156         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2157         struct custom_float_format fmt;
2158
2159         fmt.exponenta_bits = 6;
2160         fmt.mantissa_bits = 12;
2161         fmt.sign = true;
2162
2163         if (pipe_ctx->plane_state->sdr_white_level > 80)
2164                 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2165
2166         pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2167                         pipe_ctx->plane_res.dpp, hw_mult);
2168 }
2169
2170 void dcn10_program_pipe(
2171                 struct dc *dc,
2172                 struct pipe_ctx *pipe_ctx,
2173                 struct dc_state *context)
2174 {
2175         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2176                 dcn10_enable_plane(dc, pipe_ctx, context);
2177
2178         update_dchubp_dpp(dc, pipe_ctx, context);
2179
2180         set_hdr_multiplier(pipe_ctx);
2181
2182         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2183                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2184                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2185                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2186
2187         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2188          * only do gamma programming for full update.
2189          * TODO: This can be further optimized/cleaned up
2190          * Always call this for now since it does memcmp inside before
2191          * doing heavy calculation and programming
2192          */
2193         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2194                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2195 }
2196
2197 static void program_all_pipe_in_tree(
2198                 struct dc *dc,
2199                 struct pipe_ctx *pipe_ctx,
2200                 struct dc_state *context)
2201 {
2202         if (pipe_ctx->top_pipe == NULL) {
2203                 bool blank = !is_pipe_tree_visible(pipe_ctx);
2204
2205                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2206                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2207                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2208                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2209                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
2210
2211                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2212                                 pipe_ctx->stream_res.tg);
2213
2214                 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2215
2216         }
2217
2218         if (pipe_ctx->plane_state != NULL) {
2219                 dcn10_program_pipe(dc, pipe_ctx, context);
2220         }
2221
2222         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) {
2223                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2224         }
2225 }
2226
2227 static void dcn10_pplib_apply_display_requirements(
2228         struct dc *dc,
2229         struct dc_state *context)
2230 {
2231         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2232
2233         pp_display_cfg->min_engine_clock_khz = dc->res_pool->dccg->clks.dcfclk_khz;
2234         pp_display_cfg->min_memory_clock_khz = dc->res_pool->dccg->clks.fclk_khz;
2235         pp_display_cfg->min_engine_clock_deep_sleep_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;
2236         pp_display_cfg->min_dcfc_deep_sleep_clock_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;
2237         pp_display_cfg->min_dcfclock_khz = dc->res_pool->dccg->clks.dcfclk_khz;
2238         pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;
2239         dce110_fill_display_configs(context, pp_display_cfg);
2240
2241         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2242                         struct dm_pp_display_configuration)) !=  0)
2243                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2244
2245         dc->prev_display_config = *pp_display_cfg;
2246 }
2247
2248 static void optimize_shared_resources(struct dc *dc)
2249 {
2250         if (dc->current_state->stream_count == 0) {
2251                 /* S0i2 message */
2252                 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
2253         }
2254
2255         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2256                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2257 }
2258
2259 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
2260 {
2261         /* S0i2 message */
2262         if (dc->current_state->stream_count == 0 &&
2263                         context->stream_count != 0)
2264                 dcn10_pplib_apply_display_requirements(dc, context);
2265 }
2266
2267 static struct pipe_ctx *find_top_pipe_for_stream(
2268                 struct dc *dc,
2269                 struct dc_state *context,
2270                 const struct dc_stream_state *stream)
2271 {
2272         int i;
2273
2274         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2275                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2276                 struct pipe_ctx *old_pipe_ctx =
2277                                 &dc->current_state->res_ctx.pipe_ctx[i];
2278
2279                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2280                         continue;
2281
2282                 if (pipe_ctx->stream != stream)
2283                         continue;
2284
2285                 if (!pipe_ctx->top_pipe)
2286                         return pipe_ctx;
2287         }
2288         return NULL;
2289 }
2290
2291 static void dcn10_apply_ctx_for_surface(
2292                 struct dc *dc,
2293                 const struct dc_stream_state *stream,
2294                 int num_planes,
2295                 struct dc_state *context)
2296 {
2297         int i;
2298         struct timing_generator *tg;
2299         bool removed_pipe[4] = { false };
2300         struct pipe_ctx *top_pipe_to_program =
2301                         find_top_pipe_for_stream(dc, context, stream);
2302         DC_LOGGER_INIT(dc->ctx->logger);
2303
2304         if (!top_pipe_to_program)
2305                 return;
2306
2307         tg = top_pipe_to_program->stream_res.tg;
2308
2309         dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2310
2311         if (num_planes == 0) {
2312                 /* OTG blank before remove all front end */
2313                 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2314         }
2315
2316         /* Disconnect unused mpcc */
2317         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2318                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2319                 struct pipe_ctx *old_pipe_ctx =
2320                                 &dc->current_state->res_ctx.pipe_ctx[i];
2321                 /*
2322                  * Powergate reused pipes that are not powergated
2323                  * fairly hacky right now, using opp_id as indicator
2324                  * TODO: After move dc_post to dc_update, this will
2325                  * be removed.
2326                  */
2327                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2328                         if (old_pipe_ctx->stream_res.tg == tg &&
2329                                 old_pipe_ctx->plane_res.hubp &&
2330                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
2331                                 dcn10_disable_plane(dc, old_pipe_ctx);
2332                                 /*
2333                                  * power down fe will unlock when calling reset, need
2334                                  * to lock it back here. Messy, need rework.
2335                                  */
2336                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
2337                         }
2338                 }
2339
2340                 if ((!pipe_ctx->plane_state ||
2341                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2342                     old_pipe_ctx->plane_state &&
2343                     old_pipe_ctx->stream_res.tg == tg) {
2344
2345                         dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2346                         removed_pipe[i] = true;
2347
2348                         DC_LOG_DC("Reset mpcc for pipe %d\n",
2349                                         old_pipe_ctx->pipe_idx);
2350                 }
2351         }
2352
2353         if (num_planes > 0)
2354                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2355
2356         dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2357
2358         if (num_planes == 0)
2359                 false_optc_underflow_wa(dc, stream, tg);
2360
2361         for (i = 0; i < dc->res_pool->pipe_count; i++)
2362                 if (removed_pipe[i])
2363                         dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2364
2365         if (dc->hwseq->wa.DEGVIDCN10_254)
2366                 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2367 }
2368
2369 static void dcn10_set_bandwidth(
2370                 struct dc *dc,
2371                 struct dc_state *context,
2372                 bool safe_to_lower)
2373 {
2374         if (dc->debug.sanity_checks)
2375                 dcn10_verify_allow_pstate_change_high(dc);
2376
2377         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2378                 if (context->stream_count == 0)
2379                         context->bw.dcn.clk.phyclk_khz = 0;
2380
2381                 dc->res_pool->dccg->funcs->update_clocks(
2382                                 dc->res_pool->dccg,
2383                                 &context->bw.dcn.clk,
2384                                 safe_to_lower);
2385
2386                 dcn10_pplib_apply_display_requirements(dc, context);
2387         }
2388
2389         hubbub1_program_watermarks(dc->res_pool->hubbub,
2390                         &context->bw.dcn.watermarks,
2391                         dc->res_pool->ref_clock_inKhz / 1000,
2392                         true);
2393
2394         if (dc->debug.sanity_checks)
2395                 dcn10_verify_allow_pstate_change_high(dc);
2396 }
2397
2398 static void set_drr(struct pipe_ctx **pipe_ctx,
2399                 int num_pipes, int vmin, int vmax)
2400 {
2401         int i = 0;
2402         struct drr_params params = {0};
2403
2404         params.vertical_total_max = vmax;
2405         params.vertical_total_min = vmin;
2406
2407         /* TODO: If multiple pipes are to be supported, you need
2408          * some GSL stuff
2409          */
2410         for (i = 0; i < num_pipes; i++) {
2411                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
2412         }
2413 }
2414
2415 static void get_position(struct pipe_ctx **pipe_ctx,
2416                 int num_pipes,
2417                 struct crtc_position *position)
2418 {
2419         int i = 0;
2420
2421         /* TODO: handle pipes > 1
2422          */
2423         for (i = 0; i < num_pipes; i++)
2424                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2425 }
2426
2427 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2428                 int num_pipes, const struct dc_static_screen_events *events)
2429 {
2430         unsigned int i;
2431         unsigned int value = 0;
2432
2433         if (events->surface_update)
2434                 value |= 0x80;
2435         if (events->cursor_update)
2436                 value |= 0x2;
2437         if (events->force_trigger)
2438                 value |= 0x1;
2439
2440         for (i = 0; i < num_pipes; i++)
2441                 pipe_ctx[i]->stream_res.tg->funcs->
2442                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2443 }
2444
2445 static void dcn10_config_stereo_parameters(
2446                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2447 {
2448         enum view_3d_format view_format = stream->view_format;
2449         enum dc_timing_3d_format timing_3d_format =\
2450                         stream->timing.timing_3d_format;
2451         bool non_stereo_timing = false;
2452
2453         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2454                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2455                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2456                 non_stereo_timing = true;
2457
2458         if (non_stereo_timing == false &&
2459                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2460
2461                 flags->PROGRAM_STEREO         = 1;
2462                 flags->PROGRAM_POLARITY       = 1;
2463                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2464                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2465                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2466                         enum display_dongle_type dongle = \
2467                                         stream->sink->link->ddc->dongle_type;
2468                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2469                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2470                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2471                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2472                 }
2473                 flags->RIGHT_EYE_POLARITY =\
2474                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2475                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2476                         flags->FRAME_PACKED = 1;
2477         }
2478
2479         return;
2480 }
2481
2482 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2483 {
2484         struct crtc_stereo_flags flags = { 0 };
2485         struct dc_stream_state *stream = pipe_ctx->stream;
2486
2487         dcn10_config_stereo_parameters(stream, &flags);
2488
2489         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2490                 pipe_ctx->stream_res.opp,
2491                 flags.PROGRAM_STEREO == 1 ? true:false,
2492                 &stream->timing);
2493
2494         pipe_ctx->stream_res.tg->funcs->program_stereo(
2495                 pipe_ctx->stream_res.tg,
2496                 &stream->timing,
2497                 &flags);
2498
2499         return;
2500 }
2501
2502 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2503 {
2504         int i;
2505
2506         for (i = 0; i < res_pool->pipe_count; i++) {
2507                 if (res_pool->hubps[i]->inst == mpcc_inst)
2508                         return res_pool->hubps[i];
2509         }
2510         ASSERT(false);
2511         return NULL;
2512 }
2513
2514 static void dcn10_wait_for_mpcc_disconnect(
2515                 struct dc *dc,
2516                 struct resource_pool *res_pool,
2517                 struct pipe_ctx *pipe_ctx)
2518 {
2519         int mpcc_inst;
2520
2521         if (dc->debug.sanity_checks) {
2522                 dcn10_verify_allow_pstate_change_high(dc);
2523         }
2524
2525         if (!pipe_ctx->stream_res.opp)
2526                 return;
2527
2528         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2529                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2530                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2531
2532                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2533                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2534                         hubp->funcs->set_blank(hubp, true);
2535                         /*DC_LOG_ERROR(dc->ctx->logger,
2536                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2537                                         i);*/
2538                 }
2539         }
2540
2541         if (dc->debug.sanity_checks) {
2542                 dcn10_verify_allow_pstate_change_high(dc);
2543         }
2544
2545 }
2546
2547 static bool dcn10_dummy_display_power_gating(
2548         struct dc *dc,
2549         uint8_t controller_id,
2550         struct dc_bios *dcb,
2551         enum pipe_gating_control power_gating)
2552 {
2553         return true;
2554 }
2555
2556 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2557 {
2558         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2559         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2560         bool flip_pending;
2561
2562         if (plane_state == NULL)
2563                 return;
2564
2565         flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2566                                         pipe_ctx->plane_res.hubp);
2567
2568         plane_state->status.is_flip_pending = flip_pending;
2569
2570         if (!flip_pending)
2571                 plane_state->status.current_address = plane_state->status.requested_address;
2572
2573         if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2574                         tg->funcs->is_stereo_left_eye) {
2575                 plane_state->status.is_right_eye =
2576                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2577         }
2578 }
2579
2580 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2581 {
2582         if (hws->ctx->dc->res_pool->hubbub != NULL) {
2583                 struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
2584
2585                 if (hubp->funcs->hubp_update_dchub)
2586                         hubp->funcs->hubp_update_dchub(hubp, dh_data);
2587                 else
2588                         hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2589         }
2590 }
2591
2592 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2593 {
2594         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2595         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2596         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2597         struct dc_cursor_mi_param param = {
2598                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2599                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2600                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2601                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2602                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2603                 .rotation = pipe_ctx->plane_state->rotation,
2604                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2605         };
2606
2607         if (pipe_ctx->plane_state->address.type
2608                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2609                 pos_cpy.enable = false;
2610
2611         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2612                 pos_cpy.enable = false;
2613
2614         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2615         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
2616 }
2617
2618 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2619 {
2620         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2621
2622         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2623                         pipe_ctx->plane_res.hubp, attributes);
2624         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2625                 pipe_ctx->plane_res.dpp, attributes->color_format);
2626 }
2627
2628 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
2629 {
2630         uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
2631         struct fixed31_32 multiplier;
2632         struct dpp_cursor_attributes opt_attr = { 0 };
2633         uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
2634         struct custom_float_format fmt;
2635
2636         if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
2637                 return;
2638
2639         fmt.exponenta_bits = 5;
2640         fmt.mantissa_bits = 10;
2641         fmt.sign = true;
2642
2643         if (sdr_white_level > 80) {
2644                 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
2645                 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
2646         }
2647
2648         opt_attr.scale = hw_scale;
2649         opt_attr.bias = 0;
2650
2651         pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
2652                         pipe_ctx->plane_res.dpp, &opt_attr);
2653 }
2654
2655 static const struct hw_sequencer_funcs dcn10_funcs = {
2656         .program_gamut_remap = program_gamut_remap,
2657         .program_csc_matrix = program_csc_matrix,
2658         .init_hw = dcn10_init_hw,
2659         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2660         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2661         .update_plane_addr = dcn10_update_plane_addr,
2662         .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
2663         .update_dchub = dcn10_update_dchub,
2664         .update_mpcc = dcn10_update_mpcc,
2665         .update_pending_status = dcn10_update_pending_status,
2666         .set_input_transfer_func = dcn10_set_input_transfer_func,
2667         .set_output_transfer_func = dcn10_set_output_transfer_func,
2668         .program_output_csc = dcn10_program_output_csc,
2669         .power_down = dce110_power_down,
2670         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2671         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2672         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2673         .update_info_frame = dce110_update_info_frame,
2674         .enable_stream = dce110_enable_stream,
2675         .disable_stream = dce110_disable_stream,
2676         .unblank_stream = dce110_unblank_stream,
2677         .blank_stream = dce110_blank_stream,
2678         .enable_audio_stream = dce110_enable_audio_stream,
2679         .disable_audio_stream = dce110_disable_audio_stream,
2680         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2681         .disable_plane = dcn10_disable_plane,
2682         .blank_pixel_data = dcn10_blank_pixel_data,
2683         .pipe_control_lock = dcn10_pipe_control_lock,
2684         .set_bandwidth = dcn10_set_bandwidth,
2685         .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2686         .enable_stream_timing = dcn10_enable_stream_timing,
2687         .set_drr = set_drr,
2688         .get_position = get_position,
2689         .set_static_screen_control = set_static_screen_control,
2690         .setup_stereo = dcn10_setup_stereo,
2691         .set_avmute = dce110_set_avmute,
2692         .log_hw_state = dcn10_log_hw_state,
2693         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2694         .ready_shared_resources = ready_shared_resources,
2695         .optimize_shared_resources = optimize_shared_resources,
2696         .pplib_apply_display_requirements =
2697                         dcn10_pplib_apply_display_requirements,
2698         .edp_backlight_control = hwss_edp_backlight_control,
2699         .edp_power_control = hwss_edp_power_control,
2700         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2701         .set_cursor_position = dcn10_set_cursor_position,
2702         .set_cursor_attribute = dcn10_set_cursor_attribute,
2703         .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level
2704 };
2705
2706
2707 void dcn10_hw_sequencer_construct(struct dc *dc)
2708 {
2709         dc->hwss = dcn10_funcs;
2710 }
2711