2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "reg_helper.h"
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dcn10_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "i2caux_interface.h"
33 #include "dc_bios_types.h"
35 #include "gpio_service_interface.h"
40 enc10->base.ctx->logger
43 (enc10->link_regs->reg)
46 #define FN(reg_name, field_name) \
47 enc10->link_shift->field_name, enc10->link_mask->field_name
52 * Trigger Source Select
53 * ASIC-dependent, actual values for register programming
55 #define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
56 #define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
57 #define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
58 #define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
59 #define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
60 #define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
61 #define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
62 #define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
65 DP_MST_UPDATE_MAX_RETRY = 50
68 static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
69 .validate_output_with_stream =
70 dcn10_link_encoder_validate_output_with_stream,
71 .hw_init = dcn10_link_encoder_hw_init,
72 .setup = dcn10_link_encoder_setup,
73 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
74 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
75 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
76 .disable_output = dcn10_link_encoder_disable_output,
77 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
78 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
79 .update_mst_stream_allocation_table =
80 dcn10_link_encoder_update_mst_stream_allocation_table,
81 .psr_program_dp_dphy_fast_training =
82 dcn10_psr_program_dp_dphy_fast_training,
83 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
84 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
85 .enable_hpd = dcn10_link_encoder_enable_hpd,
86 .disable_hpd = dcn10_link_encoder_disable_hpd,
87 .is_dig_enabled = dcn10_is_dig_enabled,
88 .destroy = dcn10_link_encoder_destroy
91 static enum bp_result link_transmitter_control(
92 struct dcn10_link_encoder *enc10,
93 struct bp_transmitter_control *cntl)
95 enum bp_result result;
96 struct dc_bios *bp = enc10->base.ctx->dc_bios;
98 result = bp->funcs->transmitter_control(bp, cntl);
103 static void enable_phy_bypass_mode(
104 struct dcn10_link_encoder *enc10,
107 /* This register resides in DP back end block;
108 * transmitter is used for the offset
110 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
114 static void disable_prbs_symbols(
115 struct dcn10_link_encoder *enc10,
118 /* This register resides in DP back end block;
119 * transmitter is used for the offset
121 REG_UPDATE_4(DP_DPHY_CNTL,
122 DPHY_ATEST_SEL_LANE0, disable,
123 DPHY_ATEST_SEL_LANE1, disable,
124 DPHY_ATEST_SEL_LANE2, disable,
125 DPHY_ATEST_SEL_LANE3, disable);
128 static void disable_prbs_mode(
129 struct dcn10_link_encoder *enc10)
131 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
134 static void program_pattern_symbols(
135 struct dcn10_link_encoder *enc10,
136 uint16_t pattern_symbols[8])
138 /* This register resides in DP back end block;
139 * transmitter is used for the offset
141 REG_SET_3(DP_DPHY_SYM0, 0,
142 DPHY_SYM1, pattern_symbols[0],
143 DPHY_SYM2, pattern_symbols[1],
144 DPHY_SYM3, pattern_symbols[2]);
146 /* This register resides in DP back end block;
147 * transmitter is used for the offset
149 REG_SET_3(DP_DPHY_SYM1, 0,
150 DPHY_SYM4, pattern_symbols[3],
151 DPHY_SYM5, pattern_symbols[4],
152 DPHY_SYM6, pattern_symbols[5]);
154 /* This register resides in DP back end block;
155 * transmitter is used for the offset
157 REG_SET_2(DP_DPHY_SYM2, 0,
158 DPHY_SYM7, pattern_symbols[6],
159 DPHY_SYM8, pattern_symbols[7]);
162 static void set_dp_phy_pattern_d102(
163 struct dcn10_link_encoder *enc10)
165 /* Disable PHY Bypass mode to setup the test pattern */
166 enable_phy_bypass_mode(enc10, false);
168 /* For 10-bit PRBS or debug symbols
169 * please use the following sequence:
171 * Enable debug symbols on the lanes
173 disable_prbs_symbols(enc10, true);
175 /* Disable PRBS mode */
176 disable_prbs_mode(enc10);
178 /* Program debug symbols to be output */
180 uint16_t pattern_symbols[8] = {
181 0x2AA, 0x2AA, 0x2AA, 0x2AA,
182 0x2AA, 0x2AA, 0x2AA, 0x2AA
185 program_pattern_symbols(enc10, pattern_symbols);
188 /* Enable phy bypass mode to enable the test pattern */
190 enable_phy_bypass_mode(enc10, true);
193 static void set_link_training_complete(
194 struct dcn10_link_encoder *enc10,
197 /* This register resides in DP back end block;
198 * transmitter is used for the offset
200 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
204 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
205 struct link_encoder *enc,
208 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
209 /* Write Training Pattern */
211 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
213 /* Set HW Register Training Complete to false */
215 set_link_training_complete(enc10, false);
217 /* Disable PHY Bypass mode to output Training Pattern */
219 enable_phy_bypass_mode(enc10, false);
221 /* Disable PRBS mode */
222 disable_prbs_mode(enc10);
225 static void setup_panel_mode(
226 struct dcn10_link_encoder *enc10,
227 enum dp_panel_mode panel_mode)
231 ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
232 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
234 switch (panel_mode) {
235 case DP_PANEL_MODE_EDP:
238 case DP_PANEL_MODE_SPECIAL:
246 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
249 static void set_dp_phy_pattern_symbol_error(
250 struct dcn10_link_encoder *enc10)
252 /* Disable PHY Bypass mode to setup the test pattern */
253 enable_phy_bypass_mode(enc10, false);
255 /* program correct panel mode*/
256 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
258 /* A PRBS23 pattern is used for most DP electrical measurements. */
260 /* Enable PRBS symbols on the lanes */
261 disable_prbs_symbols(enc10, false);
263 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
264 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
268 /* Enable phy bypass mode to enable the test pattern */
269 enable_phy_bypass_mode(enc10, true);
272 static void set_dp_phy_pattern_prbs7(
273 struct dcn10_link_encoder *enc10)
275 /* Disable PHY Bypass mode to setup the test pattern */
276 enable_phy_bypass_mode(enc10, false);
278 /* A PRBS7 pattern is used for most DP electrical measurements. */
280 /* Enable PRBS symbols on the lanes */
281 disable_prbs_symbols(enc10, false);
283 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
284 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
288 /* Enable phy bypass mode to enable the test pattern */
289 enable_phy_bypass_mode(enc10, true);
292 static void set_dp_phy_pattern_80bit_custom(
293 struct dcn10_link_encoder *enc10,
294 const uint8_t *pattern)
296 /* Disable PHY Bypass mode to setup the test pattern */
297 enable_phy_bypass_mode(enc10, false);
299 /* Enable debug symbols on the lanes */
301 disable_prbs_symbols(enc10, true);
303 /* Enable PHY bypass mode to enable the test pattern */
304 /* TODO is it really needed ? */
306 enable_phy_bypass_mode(enc10, true);
308 /* Program 80 bit custom pattern */
310 uint16_t pattern_symbols[8];
313 ((pattern[1] & 0x03) << 8) | pattern[0];
315 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
317 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
319 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
321 ((pattern[6] & 0x03) << 8) | pattern[5];
323 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
325 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
327 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
329 program_pattern_symbols(enc10, pattern_symbols);
332 /* Enable phy bypass mode to enable the test pattern */
334 enable_phy_bypass_mode(enc10, true);
337 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
338 struct dcn10_link_encoder *enc10,
339 unsigned int cp2520_pattern)
342 /* previously there is a register DP_HBR2_EYE_PATTERN
343 * that is enabled to get the pattern.
344 * But it does not work with the latest spec change,
345 * so we are programming the following registers manually.
347 * The following settings have been confirmed
348 * by Nick Chorney and Sandra Liu
351 /* Disable PHY Bypass mode to setup the test pattern */
353 enable_phy_bypass_mode(enc10, false);
355 /* Setup DIG encoder in DP SST mode */
356 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
358 /* ensure normal panel mode. */
359 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
361 /* no vbid after BS (SR)
362 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
363 * 11000260 / 11000104 / 110000FC
365 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
366 DP_IDLE_BS_INTERVAL, 0xFC,
368 DP_VID_ENHANCED_FRAME_MODE, 1);
370 /* swap every BS with SR */
371 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
373 /* select cp2520 patterns */
374 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
375 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
376 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
378 /* pre-DCE11 can only generate CP2520 pattern 2 */
379 ASSERT(cp2520_pattern == 2);
381 /* set link training complete */
382 set_link_training_complete(enc10, true);
384 /* disable video stream */
385 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
387 /* Disable PHY Bypass mode to setup the test pattern */
388 enable_phy_bypass_mode(enc10, false);
391 static void set_dp_phy_pattern_passthrough_mode(
392 struct dcn10_link_encoder *enc10,
393 enum dp_panel_mode panel_mode)
395 /* program correct panel mode */
396 setup_panel_mode(enc10, panel_mode);
398 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
399 * in case we were doing HBR2 compliance pattern before
401 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
402 DP_IDLE_BS_INTERVAL, 0x2000,
404 DP_VID_ENHANCED_FRAME_MODE, 1);
406 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
408 /* set link training complete */
409 set_link_training_complete(enc10, true);
411 /* Disable PHY Bypass mode to setup the test pattern */
412 enable_phy_bypass_mode(enc10, false);
414 /* Disable PRBS mode */
415 disable_prbs_mode(enc10);
418 /* return value is bit-vector */
419 static uint8_t get_frontend_source(
420 enum engine_id engine)
424 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
426 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
428 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
430 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
432 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
434 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
436 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
438 ASSERT_CRITICAL(false);
439 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
443 void configure_encoder(
444 struct dcn10_link_encoder *enc10,
445 const struct dc_link_settings *link_settings)
447 /* set number of lanes */
448 REG_SET(DP_CONFIG, 0,
449 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
451 /* setup scrambler */
452 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
455 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
456 bool exit_link_training_required)
458 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
460 if (exit_link_training_required)
461 REG_UPDATE(DP_DPHY_FAST_TRAINING,
462 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
464 REG_UPDATE(DP_DPHY_FAST_TRAINING,
465 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
466 /*In DCE 11, we are able to pre-program a Force SR register
467 * to be able to trigger SR symbol after 5 idle patterns
468 * transmitted. Upon PSR Exit, DMCU can trigger
469 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
470 * DPHY_LOAD_BS_COUNT_START and the internal counter
471 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
472 * replaced by SR symbol once.
475 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
479 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
480 unsigned int sdp_transmit_line_num_deadline)
482 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
484 REG_UPDATE_2(DP_SEC_CNTL1,
485 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
486 DP_SEC_GSP0_PRIORITY, 1);
489 bool dcn10_is_dig_enabled(struct link_encoder *enc)
491 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
494 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
498 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
500 /* reset training pattern */
501 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
502 DPHY_TRAINING_PATTERN_SEL, 0);
504 /* reset training complete */
505 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
507 /* reset panel mode */
508 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
511 static void hpd_initialize(
512 struct dcn10_link_encoder *enc10)
514 /* Associate HPD with DIG_BE */
515 enum hpd_source_id hpd_source = enc10->base.hpd_source;
517 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
520 bool dcn10_link_encoder_validate_dvi_output(
521 const struct dcn10_link_encoder *enc10,
522 enum signal_type connector_signal,
523 enum signal_type signal,
524 const struct dc_crtc_timing *crtc_timing)
526 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
528 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
529 max_pixel_clock *= 2;
531 /* This handles the case of HDMI downgrade to DVI we don't want to
532 * we don't want to cap the pixel clock if the DDI is not DVI.
534 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
535 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
536 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
538 /* DVI only support RGB pixel encoding */
539 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
542 /*connect DVI via adpater's HDMI connector*/
543 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
544 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
545 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
546 crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
548 if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
551 if (crtc_timing->pix_clk_khz > max_pixel_clock)
554 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
555 switch (crtc_timing->display_color_depth) {
556 case COLOR_DEPTH_666:
557 case COLOR_DEPTH_888:
559 case COLOR_DEPTH_101010:
560 case COLOR_DEPTH_161616:
561 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
571 static bool dcn10_link_encoder_validate_hdmi_output(
572 const struct dcn10_link_encoder *enc10,
573 const struct dc_crtc_timing *crtc_timing,
574 int adjusted_pix_clk_khz)
576 enum dc_color_depth max_deep_color =
577 enc10->base.features.max_hdmi_deep_color;
579 if (max_deep_color < crtc_timing->display_color_depth)
582 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
584 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
587 if ((adjusted_pix_clk_khz == 0) ||
588 (adjusted_pix_clk_khz > enc10->base.features.max_hdmi_pixel_clock))
591 /* DCE11 HW does not support 420 */
592 if (!enc10->base.features.ycbcr420_supported &&
593 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
596 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
597 adjusted_pix_clk_khz >= 300000)
599 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
600 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
605 bool dcn10_link_encoder_validate_dp_output(
606 const struct dcn10_link_encoder *enc10,
607 const struct dc_crtc_timing *crtc_timing)
609 /* default RGB only */
610 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
613 if (enc10->base.features.flags.bits.IS_YCBCR_CAPABLE)
616 /* for DCE 8.x or later DP Y-only feature,
617 * we need ASIC cap + FeatureSupportDPYonly, not support 666
619 if (crtc_timing->flags.Y_ONLY &&
620 enc10->base.features.flags.bits.IS_YCBCR_CAPABLE &&
621 crtc_timing->display_color_depth != COLOR_DEPTH_666)
627 void dcn10_link_encoder_construct(
628 struct dcn10_link_encoder *enc10,
629 const struct encoder_init_data *init_data,
630 const struct encoder_feature_support *enc_features,
631 const struct dcn10_link_enc_registers *link_regs,
632 const struct dcn10_link_enc_aux_registers *aux_regs,
633 const struct dcn10_link_enc_hpd_registers *hpd_regs,
634 const struct dcn10_link_enc_shift *link_shift,
635 const struct dcn10_link_enc_mask *link_mask)
637 struct bp_encoder_cap_info bp_cap_info = {0};
638 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
639 enum bp_result result = BP_RESULT_OK;
641 enc10->base.funcs = &dcn10_lnk_enc_funcs;
642 enc10->base.ctx = init_data->ctx;
643 enc10->base.id = init_data->encoder;
645 enc10->base.hpd_source = init_data->hpd_source;
646 enc10->base.connector = init_data->connector;
648 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
650 enc10->base.features = *enc_features;
652 enc10->base.transmitter = init_data->transmitter;
654 /* set the flag to indicate whether driver poll the I2C data pin
655 * while doing the DP sink detect
658 /* if (dal_adapter_service_is_feature_supported(as,
659 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
660 enc10->base.features.flags.bits.
661 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
663 enc10->base.output_signals =
664 SIGNAL_TYPE_DVI_SINGLE_LINK |
665 SIGNAL_TYPE_DVI_DUAL_LINK |
667 SIGNAL_TYPE_DISPLAY_PORT |
668 SIGNAL_TYPE_DISPLAY_PORT_MST |
670 SIGNAL_TYPE_HDMI_TYPE_A;
672 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
673 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
674 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
675 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
676 * Prefer DIG assignment is decided by board design.
677 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
678 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
679 * By this, adding DIGG should not hurt DCE 8.0.
680 * This will let DCE 8.1 share DCE 8.0 as much as possible
683 enc10->link_regs = link_regs;
684 enc10->aux_regs = aux_regs;
685 enc10->hpd_regs = hpd_regs;
686 enc10->link_shift = link_shift;
687 enc10->link_mask = link_mask;
689 switch (enc10->base.transmitter) {
690 case TRANSMITTER_UNIPHY_A:
691 enc10->base.preferred_engine = ENGINE_ID_DIGA;
693 case TRANSMITTER_UNIPHY_B:
694 enc10->base.preferred_engine = ENGINE_ID_DIGB;
696 case TRANSMITTER_UNIPHY_C:
697 enc10->base.preferred_engine = ENGINE_ID_DIGC;
699 case TRANSMITTER_UNIPHY_D:
700 enc10->base.preferred_engine = ENGINE_ID_DIGD;
702 case TRANSMITTER_UNIPHY_E:
703 enc10->base.preferred_engine = ENGINE_ID_DIGE;
705 case TRANSMITTER_UNIPHY_F:
706 enc10->base.preferred_engine = ENGINE_ID_DIGF;
708 case TRANSMITTER_UNIPHY_G:
709 enc10->base.preferred_engine = ENGINE_ID_DIGG;
712 ASSERT_CRITICAL(false);
713 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
716 /* default to one to mirror Windows behavior */
717 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
719 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
720 enc10->base.id, &bp_cap_info);
722 /* Override features with DCE-specific values */
723 if (result == BP_RESULT_OK) {
724 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
725 bp_cap_info.DP_HBR2_EN;
726 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
727 bp_cap_info.DP_HBR3_EN;
728 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
730 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
734 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
735 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
739 bool dcn10_link_encoder_validate_output_with_stream(
740 struct link_encoder *enc,
741 const struct dc_stream_state *stream)
743 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
746 switch (stream->signal) {
747 case SIGNAL_TYPE_DVI_SINGLE_LINK:
748 case SIGNAL_TYPE_DVI_DUAL_LINK:
749 is_valid = dcn10_link_encoder_validate_dvi_output(
751 stream->sink->link->connector_signal,
755 case SIGNAL_TYPE_HDMI_TYPE_A:
756 is_valid = dcn10_link_encoder_validate_hdmi_output(
759 stream->phy_pix_clk);
761 case SIGNAL_TYPE_DISPLAY_PORT:
762 case SIGNAL_TYPE_DISPLAY_PORT_MST:
763 is_valid = dcn10_link_encoder_validate_dp_output(
764 enc10, &stream->timing);
766 case SIGNAL_TYPE_EDP:
767 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
769 case SIGNAL_TYPE_VIRTUAL:
780 void dcn10_link_encoder_hw_init(
781 struct link_encoder *enc)
783 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
784 struct bp_transmitter_control cntl = { 0 };
785 enum bp_result result;
787 cntl.action = TRANSMITTER_CONTROL_INIT;
788 cntl.engine_id = ENGINE_ID_UNKNOWN;
789 cntl.transmitter = enc10->base.transmitter;
790 cntl.connector_obj_id = enc10->base.connector;
791 cntl.lanes_number = LANE_COUNT_FOUR;
792 cntl.coherent = false;
793 cntl.hpd_sel = enc10->base.hpd_source;
795 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
796 cntl.signal = SIGNAL_TYPE_EDP;
798 result = link_transmitter_control(enc10, &cntl);
800 if (result != BP_RESULT_OK) {
801 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
807 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
808 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
810 result = link_transmitter_control(enc10, &cntl);
812 ASSERT(result == BP_RESULT_OK);
815 dcn10_aux_initialize(enc10);
818 * hpd_initialize() will pass DIG_FE id to HW context.
819 * All other routine within HW context will use fe_engine_offset
820 * as DIG_FE id even caller pass DIG_FE id.
821 * So this routine must be called first.
823 hpd_initialize(enc10);
826 void dcn10_link_encoder_destroy(struct link_encoder **enc)
828 kfree(TO_DCN10_LINK_ENC(*enc));
832 void dcn10_link_encoder_setup(
833 struct link_encoder *enc,
834 enum signal_type signal)
836 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
839 case SIGNAL_TYPE_EDP:
840 case SIGNAL_TYPE_DISPLAY_PORT:
842 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
844 case SIGNAL_TYPE_LVDS:
846 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
848 case SIGNAL_TYPE_DVI_SINGLE_LINK:
849 case SIGNAL_TYPE_DVI_DUAL_LINK:
851 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
853 case SIGNAL_TYPE_HDMI_TYPE_A:
855 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
857 case SIGNAL_TYPE_DISPLAY_PORT_MST:
859 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
862 ASSERT_CRITICAL(false);
869 /* TODO: still need depth or just pass in adjusted pixel clock? */
870 void dcn10_link_encoder_enable_tmds_output(
871 struct link_encoder *enc,
872 enum clock_source_id clock_source,
873 enum dc_color_depth color_depth,
874 enum signal_type signal,
875 uint32_t pixel_clock)
877 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
878 struct bp_transmitter_control cntl = { 0 };
879 enum bp_result result;
883 cntl.action = TRANSMITTER_CONTROL_ENABLE;
884 cntl.engine_id = enc->preferred_engine;
885 cntl.transmitter = enc10->base.transmitter;
886 cntl.pll_id = clock_source;
887 cntl.signal = signal;
888 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
889 cntl.lanes_number = 8;
891 cntl.lanes_number = 4;
893 cntl.hpd_sel = enc10->base.hpd_source;
895 cntl.pixel_clock = pixel_clock;
896 cntl.color_depth = color_depth;
898 result = link_transmitter_control(enc10, &cntl);
900 if (result != BP_RESULT_OK) {
901 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
907 /* enables DP PHY output */
908 void dcn10_link_encoder_enable_dp_output(
909 struct link_encoder *enc,
910 const struct dc_link_settings *link_settings,
911 enum clock_source_id clock_source)
913 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
914 struct bp_transmitter_control cntl = { 0 };
915 enum bp_result result;
919 /* number_of_lanes is used for pixel clock adjust,
920 * but it's not passed to asic_control.
921 * We need to set number of lanes manually.
923 configure_encoder(enc10, link_settings);
925 cntl.action = TRANSMITTER_CONTROL_ENABLE;
926 cntl.engine_id = enc->preferred_engine;
927 cntl.transmitter = enc10->base.transmitter;
928 cntl.pll_id = clock_source;
929 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
930 cntl.lanes_number = link_settings->lane_count;
931 cntl.hpd_sel = enc10->base.hpd_source;
932 cntl.pixel_clock = link_settings->link_rate
933 * LINK_RATE_REF_FREQ_IN_KHZ;
934 /* TODO: check if undefined works */
935 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
937 result = link_transmitter_control(enc10, &cntl);
939 if (result != BP_RESULT_OK) {
940 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
946 /* enables DP PHY output in MST mode */
947 void dcn10_link_encoder_enable_dp_mst_output(
948 struct link_encoder *enc,
949 const struct dc_link_settings *link_settings,
950 enum clock_source_id clock_source)
952 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
953 struct bp_transmitter_control cntl = { 0 };
954 enum bp_result result;
958 /* number_of_lanes is used for pixel clock adjust,
959 * but it's not passed to asic_control.
960 * We need to set number of lanes manually.
962 configure_encoder(enc10, link_settings);
964 cntl.action = TRANSMITTER_CONTROL_ENABLE;
965 cntl.engine_id = ENGINE_ID_UNKNOWN;
966 cntl.transmitter = enc10->base.transmitter;
967 cntl.pll_id = clock_source;
968 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
969 cntl.lanes_number = link_settings->lane_count;
970 cntl.hpd_sel = enc10->base.hpd_source;
971 cntl.pixel_clock = link_settings->link_rate
972 * LINK_RATE_REF_FREQ_IN_KHZ;
973 /* TODO: check if undefined works */
974 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
976 result = link_transmitter_control(enc10, &cntl);
978 if (result != BP_RESULT_OK) {
979 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
986 * Disable transmitter and its encoder
988 void dcn10_link_encoder_disable_output(
989 struct link_encoder *enc,
990 enum signal_type signal)
992 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
993 struct bp_transmitter_control cntl = { 0 };
994 enum bp_result result;
996 if (!dcn10_is_dig_enabled(enc)) {
997 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
998 /*in DP_Alt_No_Connect case, we turn off the dig already,
999 after excuation the PHY w/a sequence, not allow touch PHY any more*/
1002 /* Power-down RX and disable GPU PHY should be paired.
1003 * Disabling PHY without powering down RX may cause
1004 * symbol lock loss, on which we will get DP Sink interrupt.
1007 /* There is a case for the DP active dongles
1008 * where we want to disable the PHY but keep RX powered,
1009 * for those we need to ignore DP Sink interrupt
1010 * by checking lane count that has been set
1011 * on the last do_enable_output().
1014 /* disable transmitter */
1015 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1016 cntl.transmitter = enc10->base.transmitter;
1017 cntl.hpd_sel = enc10->base.hpd_source;
1018 cntl.signal = signal;
1019 cntl.connector_obj_id = enc10->base.connector;
1021 result = link_transmitter_control(enc10, &cntl);
1023 if (result != BP_RESULT_OK) {
1024 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1026 BREAK_TO_DEBUGGER();
1030 /* disable encoder */
1031 if (dc_is_dp_signal(signal))
1032 link_encoder_disable(enc10);
1035 void dcn10_link_encoder_dp_set_lane_settings(
1036 struct link_encoder *enc,
1037 const struct link_training_settings *link_settings)
1039 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1040 union dpcd_training_lane_set training_lane_set = { { 0 } };
1042 struct bp_transmitter_control cntl = { 0 };
1044 if (!link_settings) {
1045 BREAK_TO_DEBUGGER();
1049 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1050 cntl.transmitter = enc10->base.transmitter;
1051 cntl.connector_obj_id = enc10->base.connector;
1052 cntl.lanes_number = link_settings->link_settings.lane_count;
1053 cntl.hpd_sel = enc10->base.hpd_source;
1054 cntl.pixel_clock = link_settings->link_settings.link_rate *
1055 LINK_RATE_REF_FREQ_IN_KHZ;
1057 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1058 /* translate lane settings */
1060 training_lane_set.bits.VOLTAGE_SWING_SET =
1061 link_settings->lane_settings[lane].VOLTAGE_SWING;
1062 training_lane_set.bits.PRE_EMPHASIS_SET =
1063 link_settings->lane_settings[lane].PRE_EMPHASIS;
1065 /* post cursor 2 setting only applies to HBR2 link rate */
1066 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1067 /* this is passed to VBIOS
1068 * to program post cursor 2 level
1070 training_lane_set.bits.POST_CURSOR2_SET =
1071 link_settings->lane_settings[lane].POST_CURSOR2;
1074 cntl.lane_select = lane;
1075 cntl.lane_settings = training_lane_set.raw;
1077 /* call VBIOS table to set voltage swing and pre-emphasis */
1078 link_transmitter_control(enc10, &cntl);
1082 /* set DP PHY test and training patterns */
1083 void dcn10_link_encoder_dp_set_phy_pattern(
1084 struct link_encoder *enc,
1085 const struct encoder_set_dp_phy_pattern_param *param)
1087 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1089 switch (param->dp_phy_pattern) {
1090 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1091 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1093 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1094 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1096 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1097 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1099 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1100 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1102 case DP_TEST_PATTERN_D102:
1103 set_dp_phy_pattern_d102(enc10);
1105 case DP_TEST_PATTERN_SYMBOL_ERROR:
1106 set_dp_phy_pattern_symbol_error(enc10);
1108 case DP_TEST_PATTERN_PRBS7:
1109 set_dp_phy_pattern_prbs7(enc10);
1111 case DP_TEST_PATTERN_80BIT_CUSTOM:
1112 set_dp_phy_pattern_80bit_custom(
1113 enc10, param->custom_pattern);
1115 case DP_TEST_PATTERN_CP2520_1:
1116 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1118 case DP_TEST_PATTERN_CP2520_2:
1119 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1121 case DP_TEST_PATTERN_CP2520_3:
1122 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1124 case DP_TEST_PATTERN_VIDEO_MODE: {
1125 set_dp_phy_pattern_passthrough_mode(
1126 enc10, param->dp_panel_mode);
1131 /* invalid phy pattern */
1132 ASSERT_CRITICAL(false);
1137 static void fill_stream_allocation_row_info(
1138 const struct link_mst_stream_allocation *stream_allocation,
1142 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1145 *src = stream_enc->id;
1146 *slots = stream_allocation->slot_count;
1153 /* programs DP MST VC payload allocation */
1154 void dcn10_link_encoder_update_mst_stream_allocation_table(
1155 struct link_encoder *enc,
1156 const struct link_mst_stream_allocation_table *table)
1158 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1159 uint32_t value0 = 0;
1160 uint32_t value1 = 0;
1161 uint32_t value2 = 0;
1164 uint32_t retries = 0;
1166 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1168 /* --- Set MSE Stream Attribute -
1169 * Setup VC Payload Table on Tx Side,
1170 * Issue allocation change trigger
1171 * to commit payload on both tx and rx side
1174 /* we should clean-up table each time */
1176 if (table->stream_count >= 1) {
1177 fill_stream_allocation_row_info(
1178 &table->stream_allocations[0],
1186 REG_UPDATE_2(DP_MSE_SAT0,
1187 DP_MSE_SAT_SRC0, src,
1188 DP_MSE_SAT_SLOT_COUNT0, slots);
1190 if (table->stream_count >= 2) {
1191 fill_stream_allocation_row_info(
1192 &table->stream_allocations[1],
1200 REG_UPDATE_2(DP_MSE_SAT0,
1201 DP_MSE_SAT_SRC1, src,
1202 DP_MSE_SAT_SLOT_COUNT1, slots);
1204 if (table->stream_count >= 3) {
1205 fill_stream_allocation_row_info(
1206 &table->stream_allocations[2],
1214 REG_UPDATE_2(DP_MSE_SAT1,
1215 DP_MSE_SAT_SRC2, src,
1216 DP_MSE_SAT_SLOT_COUNT2, slots);
1218 if (table->stream_count >= 4) {
1219 fill_stream_allocation_row_info(
1220 &table->stream_allocations[3],
1228 REG_UPDATE_2(DP_MSE_SAT1,
1229 DP_MSE_SAT_SRC3, src,
1230 DP_MSE_SAT_SLOT_COUNT3, slots);
1232 /* --- wait for transaction finish */
1234 /* send allocation change trigger (ACT) ?
1235 * this step first sends the ACT,
1236 * then double buffers the SAT into the hardware
1237 * making the new allocation active on the DP MST mode link
1240 /* DP_MSE_SAT_UPDATE:
1242 * 1 - Update SAT with trigger
1243 * 2 - Update SAT without trigger
1245 REG_UPDATE(DP_MSE_SAT_UPDATE,
1246 DP_MSE_SAT_UPDATE, 1);
1248 /* wait for update to complete
1249 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1250 * then wait for the transmission
1251 * of at least 16 MTP headers on immediate local link.
1252 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1253 * a value of 1 indicates that DP MST mode
1254 * is in the 16 MTP keepout region after a VC has been added.
1255 * MST stream bandwidth (VC rate) can be configured
1256 * after this bit is cleared
1261 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1263 REG_GET(DP_MSE_SAT_UPDATE,
1264 DP_MSE_SAT_UPDATE, &value1);
1266 REG_GET(DP_MSE_SAT_UPDATE,
1267 DP_MSE_16_MTP_KEEPOUT, &value2);
1269 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1270 if (!value1 && !value2)
1273 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1276 void dcn10_link_encoder_connect_dig_be_to_fe(
1277 struct link_encoder *enc,
1278 enum engine_id engine,
1281 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1284 if (engine != ENGINE_ID_UNKNOWN) {
1286 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1289 field |= get_frontend_source(engine);
1291 field &= ~get_frontend_source(engine);
1293 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1298 #define HPD_REG(reg)\
1299 (enc10->hpd_regs->reg)
1301 #define HPD_REG_READ(reg_name) \
1302 dm_read_reg(CTX, HPD_REG(reg_name))
1304 #define HPD_REG_UPDATE_N(reg_name, n, ...) \
1305 generic_reg_update_ex(CTX, \
1306 HPD_REG(reg_name), \
1307 HPD_REG_READ(reg_name), \
1310 #define HPD_REG_UPDATE(reg_name, field, val) \
1311 HPD_REG_UPDATE_N(reg_name, 1, \
1312 FN(reg_name, field), val)
1314 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1316 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1318 HPD_REG_UPDATE(DC_HPD_CONTROL,
1322 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1324 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1326 HPD_REG_UPDATE(DC_HPD_CONTROL,
1331 #define AUX_REG(reg)\
1332 (enc10->aux_regs->reg)
1334 #define AUX_REG_READ(reg_name) \
1335 dm_read_reg(CTX, AUX_REG(reg_name))
1337 #define AUX_REG_UPDATE_N(reg_name, n, ...) \
1338 generic_reg_update_ex(CTX, \
1339 AUX_REG(reg_name), \
1340 AUX_REG_READ(reg_name), \
1343 #define AUX_REG_UPDATE(reg_name, field, val) \
1344 AUX_REG_UPDATE_N(reg_name, 1, \
1345 FN(reg_name, field), val)
1347 #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1348 AUX_REG_UPDATE_N(reg, 2,\
1352 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1354 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1356 AUX_REG_UPDATE_2(AUX_CONTROL,
1357 AUX_HPD_SEL, hpd_source,
1360 /* 1/4 window (the maximum allowed) */
1361 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1362 AUX_RX_RECEIVE_WINDOW, 1);