drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "reg_helper.h"
  28 #include "dcn10_optc.h"
  29 #include "dc.h"
  30
  31 #define REG(reg)\
  32         optc1->tg_regs->reg
  33
  34 #define CTX \
  35         optc1->base.ctx
  36
  37 #undef FN
  38 #define FN(reg_name, field_name) \
  39         optc1->tg_shift->field_name, optc1->tg_mask->field_name
  40
  41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
  42
  43 /**
  44 * apply_front_porch_workaround  TODO FPGA still need?
  45 *
  46 * This is a workaround for a bug that has existed since R5xx and has not been
  47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
  48 */
  49 static void optc1_apply_front_porch_workaround(
  50         struct timing_generator *optc,
  51         struct dc_crtc_timing *timing)
  52 {
  53         if (timing->flags.INTERLACE == 1) {
  54                 if (timing->v_front_porch < 2)
  55                         timing->v_front_porch = 2;
  56         } else {
  57                 if (timing->v_front_porch < 1)
  58                         timing->v_front_porch = 1;
  59         }
  60 }
  61
  62 void optc1_program_global_sync(
  63                 struct timing_generator *optc)
  64 {
  65         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  66
  67         if (optc->dlg_otg_param.vstartup_start == 0) {
  68                 BREAK_TO_DEBUGGER();
  69                 return;
  70         }
  71
  72         REG_SET(OTG_VSTARTUP_PARAM, 0,
  73                 VSTARTUP_START, optc->dlg_otg_param.vstartup_start);
  74
  75         REG_SET_2(OTG_VUPDATE_PARAM, 0,
  76                         VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset,
  77                         VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width);
  78
  79         REG_SET(OTG_VREADY_PARAM, 0,
  80                         VREADY_OFFSET, optc->dlg_otg_param.vready_offset);
  81 }
  82
  83 static void optc1_disable_stereo(struct timing_generator *optc)
  84 {
  85         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  86
  87         REG_SET(OTG_STEREO_CONTROL, 0,
  88                 OTG_STEREO_EN, 0);
  89
  90         REG_SET_3(OTG_3D_STRUCTURE_CONTROL, 0,
  91                 OTG_3D_STRUCTURE_EN, 0,
  92                 OTG_3D_STRUCTURE_V_UPDATE_MODE, 0,
  93                 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
  94 }
  95
  96 static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing)
  97 {
  98         struct dc_crtc_timing patched_crtc_timing;
  99         int vesa_sync_start;
 100         int asic_blank_end;
 101         int interlace_factor;
 102         int vertical_line_start;
 103
 104         patched_crtc_timing = *dc_crtc_timing;
 105         optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
 106
 107         vesa_sync_start = patched_crtc_timing.h_addressable +
 108                         patched_crtc_timing.h_border_right +
 109                         patched_crtc_timing.h_front_porch;
 110
 111         asic_blank_end = patched_crtc_timing.h_total -
 112                         vesa_sync_start -
 113                         patched_crtc_timing.h_border_left;
 114
 115         interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
 116
 117         vesa_sync_start = patched_crtc_timing.v_addressable +
 118                         patched_crtc_timing.v_border_bottom +
 119                         patched_crtc_timing.v_front_porch;
 120
 121         asic_blank_end = (patched_crtc_timing.v_total -
 122                         vesa_sync_start -
 123                         patched_crtc_timing.v_border_top)
 124                         * interlace_factor;
 125
 126         vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
 127         if (vertical_line_start < 0) {
 128                 ASSERT(0);
 129                 vertical_line_start = 0;
 130         }
 131
 132         return vertical_line_start;
 133 }
 134
 135 void optc1_program_vline_interrupt(
 136                 struct timing_generator *optc,
 137                 const struct dc_crtc_timing *dc_crtc_timing,
 138                 unsigned long long vsync_delta)
 139 {
 140
 141         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 142
 143         unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
 144         unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
 145         uint32_t req_delta_lines = (uint32_t) div64_u64(
 146                         (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
 147                                                                 dc_crtc_timing->h_total);
 148
 149         uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);
 150         uint32_t start_line = 0;
 151         uint32_t endLine = 0;
 152
 153         if (req_delta_lines != 0)
 154                 req_delta_lines--;
 155
 156         if (req_delta_lines > vsync_line)
 157                 start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1;
 158         else
 159                 start_line = vsync_line - req_delta_lines;
 160
 161         endLine = start_line + 2;
 162
 163         if (endLine >= dc_crtc_timing->v_total)
 164                 endLine = 2;
 165
 166         REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
 167                         OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
 168                         OTG_VERTICAL_INTERRUPT0_LINE_END, endLine);
 169 }
 170
 171 /**
 172  * program_timing_generator   used by mode timing set
 173  * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
 174  * Including SYNC. Call BIOS command table to program Timings.
 175  */
 176 void optc1_program_timing(
 177         struct timing_generator *optc,
 178         const struct dc_crtc_timing *dc_crtc_timing,
 179         bool use_vbios)
 180 {
 181         struct dc_crtc_timing patched_crtc_timing;
 182         uint32_t vesa_sync_start;
 183         uint32_t asic_blank_end;
 184         uint32_t asic_blank_start;
 185         uint32_t v_total;
 186         uint32_t v_sync_end;
 187         uint32_t v_init, v_fp2;
 188         uint32_t h_sync_polarity, v_sync_polarity;
 189         uint32_t interlace_factor;
 190         uint32_t start_point = 0;
 191         uint32_t field_num = 0;
 192         uint32_t h_div_2;
 193         int32_t vertical_line_start;
 194
 195         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 196
 197         patched_crtc_timing = *dc_crtc_timing;
 198         optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
 199
 200         /* Load horizontal timing */
 201
 202         /* CRTC_H_TOTAL = vesa.h_total - 1 */
 203         REG_SET(OTG_H_TOTAL, 0,
 204                         OTG_H_TOTAL,  patched_crtc_timing.h_total - 1);
 205
 206         /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
 207         REG_UPDATE_2(OTG_H_SYNC_A,
 208                         OTG_H_SYNC_A_START, 0,
 209                         OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
 210
 211         /* asic_h_blank_end = HsyncWidth + HbackPorch =
 212          * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart -
 213          * vesa.h_left_border
 214          */
 215         vesa_sync_start = patched_crtc_timing.h_addressable +
 216                         patched_crtc_timing.h_border_right +
 217                         patched_crtc_timing.h_front_porch;
 218
 219         asic_blank_end = patched_crtc_timing.h_total -
 220                         vesa_sync_start -
 221                         patched_crtc_timing.h_border_left;
 222
 223         /* h_blank_start = v_blank_end + v_active */
 224         asic_blank_start = asic_blank_end +
 225                         patched_crtc_timing.h_border_left +
 226                         patched_crtc_timing.h_addressable +
 227                         patched_crtc_timing.h_border_right;
 228
 229         REG_UPDATE_2(OTG_H_BLANK_START_END,
 230                         OTG_H_BLANK_START, asic_blank_start,
 231                         OTG_H_BLANK_END, asic_blank_end);
 232
 233         /* h_sync polarity */
 234         h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
 235                         0 : 1;
 236
 237         REG_UPDATE(OTG_H_SYNC_A_CNTL,
 238                         OTG_H_SYNC_A_POL, h_sync_polarity);
 239
 240         /* Load vertical timing */
 241
 242         /* CRTC_V_TOTAL = v_total - 1 */
 243         if (patched_crtc_timing.flags.INTERLACE) {
 244                 interlace_factor = 2;
 245                 v_total = 2 * patched_crtc_timing.v_total;
 246         } else {
 247                 interlace_factor = 1;
 248                 v_total = patched_crtc_timing.v_total - 1;
 249         }
 250         REG_SET(OTG_V_TOTAL, 0,
 251                         OTG_V_TOTAL, v_total);
 252
 253         /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
 254          * OTG_V_TOTAL_MIN are equal to V_TOTAL.
 255          */
 256         REG_SET(OTG_V_TOTAL_MAX, 0,
 257                 OTG_V_TOTAL_MAX, v_total);
 258         REG_SET(OTG_V_TOTAL_MIN, 0,
 259                 OTG_V_TOTAL_MIN, v_total);
 260
 261         /* v_sync_start = 0, v_sync_end = v_sync_width */
 262         v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;
 263
 264         REG_UPDATE_2(OTG_V_SYNC_A,
 265                         OTG_V_SYNC_A_START, 0,
 266                         OTG_V_SYNC_A_END, v_sync_end);
 267
 268         vesa_sync_start = patched_crtc_timing.v_addressable +
 269                         patched_crtc_timing.v_border_bottom +
 270                         patched_crtc_timing.v_front_porch;
 271
 272         asic_blank_end = (patched_crtc_timing.v_total -
 273                         vesa_sync_start -
 274                         patched_crtc_timing.v_border_top)
 275                         * interlace_factor;
 276
 277         /* v_blank_start = v_blank_end + v_active */
 278         asic_blank_start = asic_blank_end +
 279                         (patched_crtc_timing.v_border_top +
 280                         patched_crtc_timing.v_addressable +
 281                         patched_crtc_timing.v_border_bottom)
 282                         * interlace_factor;
 283
 284         REG_UPDATE_2(OTG_V_BLANK_START_END,
 285                         OTG_V_BLANK_START, asic_blank_start,
 286                         OTG_V_BLANK_END, asic_blank_end);
 287
 288         /* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt,
 289          * program the reg for interrupt postition.
 290          */
 291         vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
 292         if (vertical_line_start < 0) {
 293                 ASSERT(0);
 294                 vertical_line_start = 0;
 295         }
 296         REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
 297                         OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start);
 298
 299         /* v_sync polarity */
 300         v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
 301                         0 : 1;
 302
 303         REG_UPDATE(OTG_V_SYNC_A_CNTL,
 304                         OTG_V_SYNC_A_POL, v_sync_polarity);
 305
 306         v_init = asic_blank_start;
 307         if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
 308                 optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
 309                 optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {
 310                 start_point = 1;
 311                 if (patched_crtc_timing.flags.INTERLACE == 1)
 312                         field_num = 1;
 313         }
 314         v_fp2 = 0;
 315         if (optc->dlg_otg_param.vstartup_start > asic_blank_end)
 316                 v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end;
 317
 318         /* Interlace */
 319         if (patched_crtc_timing.flags.INTERLACE == 1) {
 320                 REG_UPDATE(OTG_INTERLACE_CONTROL,
 321                                 OTG_INTERLACE_ENABLE, 1);
 322                 v_init = v_init / 2;
 323                 if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
 324                         v_fp2 = v_fp2 / 2;
 325         } else
 326                 REG_UPDATE(OTG_INTERLACE_CONTROL,
 327                                 OTG_INTERLACE_ENABLE, 0);
 328
 329
 330         /* VTG enable set to 0 first VInit */
 331         REG_UPDATE(CONTROL,
 332                         VTG0_ENABLE, 0);
 333
 334         REG_UPDATE_2(CONTROL,
 335                         VTG0_FP2, v_fp2,
 336                         VTG0_VCOUNT_INIT, v_init);
 337
 338         /* original code is using VTG offset to address OTG reg, seems wrong */
 339         REG_UPDATE_2(OTG_CONTROL,
 340                         OTG_START_POINT_CNTL, start_point,
 341                         OTG_FIELD_NUMBER_CNTL, field_num);
 342
 343         optc1_program_global_sync(optc);
 344
 345         /* TODO
 346          * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
 347          * program_horz_count_by_2
 348          * for DVI 30bpp mode, 0 otherwise
 349          * program_horz_count_by_2(optc, &patched_crtc_timing);
 350          */
 351
 352         /* Enable stereo - only when we need to pack 3D frame. Other types
 353          * of stereo handled in explicit call
 354          */
 355         h_div_2 = (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ?
 356                         1 : 0;
 357
 358         REG_UPDATE(OTG_H_TIMING_CNTL,
 359                         OTG_H_TIMING_DIV_BY2, h_div_2);
 360
 361 }
 362
 363 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
 364 {
 365         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 366
 367         uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
 368
 369         REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
 370                         OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
 371 }
 372
 373 /**
 374  * unblank_crtc
 375  * Call ASIC Control Object to UnBlank CRTC.
 376  */
 377 static void optc1_unblank_crtc(struct timing_generator *optc)
 378 {
 379         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 380         uint32_t vertical_interrupt_enable = 0;
 381
 382         REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
 383                         OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable);
 384
 385         /* temporary work around for vertical interrupt, once vertical interrupt enabled,
 386          * this check will be removed.
 387          */
 388         if (vertical_interrupt_enable)
 389                 optc1_set_blank_data_double_buffer(optc, true);
 390
 391         REG_UPDATE_2(OTG_BLANK_CONTROL,
 392                         OTG_BLANK_DATA_EN, 0,
 393                         OTG_BLANK_DE_MODE, 0);
 394 }
 395
 396 /**
 397  * blank_crtc
 398  * Call ASIC Control Object to Blank CRTC.
 399  */
 400
 401 static void optc1_blank_crtc(struct timing_generator *optc)
 402 {
 403         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 404
 405         REG_UPDATE_2(OTG_BLANK_CONTROL,
 406                         OTG_BLANK_DATA_EN, 1,
 407                         OTG_BLANK_DE_MODE, 0);
 408
 409         optc1_set_blank_data_double_buffer(optc, false);
 410 }
 411
 412 void optc1_set_blank(struct timing_generator *optc,
 413                 bool enable_blanking)
 414 {
 415         if (enable_blanking)
 416                 optc1_blank_crtc(optc);
 417         else
 418                 optc1_unblank_crtc(optc);
 419 }
 420
 421 bool optc1_is_blanked(struct timing_generator *optc)
 422 {
 423         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 424         uint32_t blank_en;
 425         uint32_t blank_state;
 426
 427         REG_GET_2(OTG_BLANK_CONTROL,
 428                         OTG_BLANK_DATA_EN, &blank_en,
 429                         OTG_CURRENT_BLANK_STATE, &blank_state);
 430
 431         return blank_en && blank_state;
 432 }
 433
 434 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
 435 {
 436         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 437
 438         if (enable) {
 439                 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 440                                 OPTC_INPUT_CLK_EN, 1,
 441                                 OPTC_INPUT_CLK_GATE_DIS, 1);
 442
 443                 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
 444                                 OPTC_INPUT_CLK_ON, 1,
 445                                 1, 1000);
 446
 447                 /* Enable clock */
 448                 REG_UPDATE_2(OTG_CLOCK_CONTROL,
 449                                 OTG_CLOCK_EN, 1,
 450                                 OTG_CLOCK_GATE_DIS, 1);
 451                 REG_WAIT(OTG_CLOCK_CONTROL,
 452                                 OTG_CLOCK_ON, 1,
 453                                 1, 1000);
 454         } else  {
 455
 456                 //last chance to clear underflow, otherwise, it will always there due to clock is off.
 457                 if (optc->funcs->is_optc_underflow_occurred(optc) == true)
 458                         optc->funcs->clear_optc_underflow(optc);
 459
 460                 REG_UPDATE_2(OTG_CLOCK_CONTROL,
 461                                 OTG_CLOCK_GATE_DIS, 0,
 462                                 OTG_CLOCK_EN, 0);
 463
 464                 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 465                                 OPTC_INPUT_CLK_GATE_DIS, 0,
 466                                 OPTC_INPUT_CLK_EN, 0);
 467         }
 468 }
 469
 470 /**
 471  * Enable CRTC
 472  * Enable CRTC - call ASIC Control Object to enable Timing generator.
 473  */
 474 static bool optc1_enable_crtc(struct timing_generator *optc)
 475 {
 476         /* TODO FPGA wait for answer
 477          * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
 478          * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
 479          */
 480         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 481
 482         /* opp instance for OTG. For DCN1.0, ODM is remoed.
 483          * OPP and OPTC should 1:1 mapping
 484          */
 485         REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
 486                         OPTC_SRC_SEL, optc->inst);
 487
 488         /* VTG enable first is for HW workaround */
 489         REG_UPDATE(CONTROL,
 490                         VTG0_ENABLE, 1);
 491
 492         /* Enable CRTC */
 493         REG_UPDATE_2(OTG_CONTROL,
 494                         OTG_DISABLE_POINT_CNTL, 3,
 495                         OTG_MASTER_EN, 1);
 496
 497         return true;
 498 }
 499
 500 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
 501 bool optc1_disable_crtc(struct timing_generator *optc)
 502 {
 503         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 504
 505         /* disable otg request until end of the first line
 506          * in the vertical blank region
 507          */
 508         REG_UPDATE_2(OTG_CONTROL,
 509                         OTG_DISABLE_POINT_CNTL, 3,
 510                         OTG_MASTER_EN, 0);
 511
 512         REG_UPDATE(CONTROL,
 513                         VTG0_ENABLE, 0);
 514
 515         /* CRTC disabled, so disable  clock. */
 516         REG_WAIT(OTG_CLOCK_CONTROL,
 517                         OTG_BUSY, 0,
 518                         1, 100000);
 519
 520         return true;
 521 }
 522
 523
 524 void optc1_program_blank_color(
 525                 struct timing_generator *optc,
 526                 const struct tg_color *black_color)
 527 {
 528         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 529
 530         REG_SET_3(OTG_BLACK_COLOR, 0,
 531                         OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
 532                         OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
 533                         OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
 534 }
 535
 536 bool optc1_validate_timing(
 537         struct timing_generator *optc,
 538         const struct dc_crtc_timing *timing)
 539 {
 540         uint32_t interlace_factor;
 541         uint32_t v_blank;
 542         uint32_t h_blank;
 543         uint32_t min_v_blank;
 544         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 545
 546         ASSERT(timing != NULL);
 547
 548         interlace_factor = timing->flags.INTERLACE ? 2 : 1;
 549         v_blank = (timing->v_total - timing->v_addressable -
 550                                         timing->v_border_top - timing->v_border_bottom) *
 551                                         interlace_factor;
 552
 553         h_blank = (timing->h_total - timing->h_addressable -
 554                 timing->h_border_right -
 555                 timing->h_border_left);
 556
 557         if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
 558                 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
 559                 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
 560                 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
 561                 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
 562                 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
 563                 return false;
 564
 565         /* Temporarily blocking interlacing mode until it's supported */
 566         if (timing->flags.INTERLACE == 1)
 567                 return false;
 568
 569         /* Check maximum number of pixels supported by Timing Generator
 570          * (Currently will never fail, in order to fail needs display which
 571          * needs more than 8192 horizontal and
 572          * more than 8192 vertical total pixels)
 573          */
 574         if (timing->h_total > optc1->max_h_total ||
 575                 timing->v_total > optc1->max_v_total)
 576                 return false;
 577
 578
 579         if (h_blank < optc1->min_h_blank)
 580                 return false;
 581
 582         if (timing->h_sync_width  < optc1->min_h_sync_width ||
 583                  timing->v_sync_width  < optc1->min_v_sync_width)
 584                 return false;
 585
 586         min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
 587
 588         if (v_blank < min_v_blank)
 589                 return false;
 590
 591         return true;
 592
 593 }
 594
 595 /*
 596  * get_vblank_counter
 597  *
 598  * @brief
 599  * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
 600  * holds the counter of frames.
 601  *
 602  * @param
 603  * struct timing_generator *optc - [in] timing generator which controls the
 604  * desired CRTC
 605  *
 606  * @return
 607  * Counter of frames, which should equal to number of vblanks.
 608  */
 609 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
 610 {
 611         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 612         uint32_t frame_count;
 613
 614         REG_GET(OTG_STATUS_FRAME_COUNT,
 615                 OTG_FRAME_COUNT, &frame_count);
 616
 617         return frame_count;
 618 }
 619
 620 void optc1_lock(struct timing_generator *optc)
 621 {
 622         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 623
 624         REG_SET(OTG_GLOBAL_CONTROL0, 0,
 625                         OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
 626         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 627                         OTG_MASTER_UPDATE_LOCK, 1);
 628
 629         /* Should be fast, status does not update on maximus */
 630         if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
 631                 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
 632                                 UPDATE_LOCK_STATUS, 1,
 633                                 1, 10);
 634 }
 635
 636 void optc1_unlock(struct timing_generator *optc)
 637 {
 638         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 639
 640         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 641                         OTG_MASTER_UPDATE_LOCK, 0);
 642 }
 643
 644 void optc1_get_position(struct timing_generator *optc,
 645                 struct crtc_position *position)
 646 {
 647         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 648
 649         REG_GET_2(OTG_STATUS_POSITION,
 650                         OTG_HORZ_COUNT, &position->horizontal_count,
 651                         OTG_VERT_COUNT, &position->vertical_count);
 652
 653         REG_GET(OTG_NOM_VERT_POSITION,
 654                         OTG_VERT_COUNT_NOM, &position->nominal_vcount);
 655 }
 656
 657 bool optc1_is_counter_moving(struct timing_generator *optc)
 658 {
 659         struct crtc_position position1, position2;
 660
 661         optc->funcs->get_position(optc, &position1);
 662         optc->funcs->get_position(optc, &position2);
 663
 664         if (position1.horizontal_count == position2.horizontal_count &&
 665                 position1.vertical_count == position2.vertical_count)
 666                 return false;
 667         else
 668                 return true;
 669 }
 670
 671 bool optc1_did_triggered_reset_occur(
 672         struct timing_generator *optc)
 673 {
 674         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 675         uint32_t occurred_force, occurred_vsync;
 676
 677         REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
 678                 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
 679
 680         REG_GET(OTG_VERT_SYNC_CONTROL,
 681                 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
 682
 683         return occurred_vsync != 0 || occurred_force != 0;
 684 }
 685
 686 void optc1_disable_reset_trigger(struct timing_generator *optc)
 687 {
 688         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 689
 690         REG_WRITE(OTG_TRIGA_CNTL, 0);
 691
 692         REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 693                 OTG_FORCE_COUNT_NOW_CLEAR, 1);
 694
 695         REG_SET(OTG_VERT_SYNC_CONTROL, 0,
 696                 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
 697 }
 698
 699 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
 700 {
 701         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 702         uint32_t falling_edge;
 703
 704         REG_GET(OTG_V_SYNC_A_CNTL,
 705                         OTG_V_SYNC_A_POL, &falling_edge);
 706
 707         if (falling_edge)
 708                 REG_SET_3(OTG_TRIGA_CNTL, 0,
 709                                 /* vsync signal from selected OTG pipe based
 710                                  * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 711                                  */
 712                                 OTG_TRIGA_SOURCE_SELECT, 20,
 713                                 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 714                                 /* always detect falling edge */
 715                                 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
 716         else
 717                 REG_SET_3(OTG_TRIGA_CNTL, 0,
 718                                 /* vsync signal from selected OTG pipe based
 719                                  * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 720                                  */
 721                                 OTG_TRIGA_SOURCE_SELECT, 20,
 722                                 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 723                                 /* always detect rising edge */
 724                                 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
 725
 726         REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 727                         /* force H count to H_TOTAL and V count to V_TOTAL in
 728                          * progressive mode and V_TOTAL-1 in interlaced mode
 729                          */
 730                         OTG_FORCE_COUNT_NOW_MODE, 2);
 731 }
 732
 733 void optc1_enable_crtc_reset(
 734                 struct timing_generator *optc,
 735                 int source_tg_inst,
 736                 struct crtc_trigger_info *crtc_tp)
 737 {
 738         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 739         uint32_t falling_edge = 0;
 740         uint32_t rising_edge = 0;
 741
 742         switch (crtc_tp->event) {
 743
 744         case CRTC_EVENT_VSYNC_RISING:
 745                 rising_edge = 1;
 746                 break;
 747
 748         case CRTC_EVENT_VSYNC_FALLING:
 749                 falling_edge = 1;
 750                 break;
 751         }
 752
 753         REG_SET_4(OTG_TRIGA_CNTL, 0,
 754                  /* vsync signal from selected OTG pipe based
 755                   * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 756                   */
 757                   OTG_TRIGA_SOURCE_SELECT, 20,
 758                   OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 759                   /* always detect falling edge */
 760                   OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
 761                   OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
 762
 763         switch (crtc_tp->delay) {
 764         case TRIGGER_DELAY_NEXT_LINE:
 765                 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
 766                                 OTG_AUTO_FORCE_VSYNC_MODE, 1);
 767                 break;
 768         case TRIGGER_DELAY_NEXT_PIXEL:
 769                 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 770                         /* force H count to H_TOTAL and V count to V_TOTAL in
 771                          * progressive mode and V_TOTAL-1 in interlaced mode
 772                          */
 773                         OTG_FORCE_COUNT_NOW_MODE, 2);
 774                 break;
 775         }
 776 }
 777
 778 void optc1_wait_for_state(struct timing_generator *optc,
 779                 enum crtc_state state)
 780 {
 781         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 782
 783         switch (state) {
 784         case CRTC_STATE_VBLANK:
 785                 REG_WAIT(OTG_STATUS,
 786                                 OTG_V_BLANK, 1,
 787                                 1, 100000); /* 1 vupdate at 10hz */
 788                 break;
 789
 790         case CRTC_STATE_VACTIVE:
 791                 REG_WAIT(OTG_STATUS,
 792                                 OTG_V_ACTIVE_DISP, 1,
 793                                 1, 100000); /* 1 vupdate at 10hz */
 794                 break;
 795
 796         default:
 797                 break;
 798         }
 799 }
 800
 801 void optc1_set_early_control(
 802         struct timing_generator *optc,
 803         uint32_t early_cntl)
 804 {
 805         /* asic design change, do not need this control
 806          * empty for share caller logic
 807          */
 808 }
 809
 810
 811 void optc1_set_static_screen_control(
 812         struct timing_generator *optc,
 813         uint32_t value)
 814 {
 815         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 816
 817         /* Bit 8 is no longer applicable in RV for PSR case,
 818          * set bit 8 to 0 if given
 819          */
 820         if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
 821                         != 0)
 822                 value = value &
 823                 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
 824
 825         REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
 826                         OTG_STATIC_SCREEN_EVENT_MASK, value,
 827                         OTG_STATIC_SCREEN_FRAME_COUNT, 2);
 828 }
 829
 830
 831 /**
 832  *****************************************************************************
 833  *  Function: set_drr
 834  *
 835  *  @brief
 836  *     Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
 837  *
 838  *****************************************************************************
 839  */
 840 void optc1_set_drr(
 841         struct timing_generator *optc,
 842         const struct drr_params *params)
 843 {
 844         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 845
 846         if (params != NULL &&
 847                 params->vertical_total_max > 0 &&
 848                 params->vertical_total_min > 0) {
 849
 850                 REG_SET(OTG_V_TOTAL_MAX, 0,
 851                         OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
 852
 853                 REG_SET(OTG_V_TOTAL_MIN, 0,
 854                         OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
 855
 856                 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
 857                                 OTG_V_TOTAL_MIN_SEL, 1,
 858                                 OTG_V_TOTAL_MAX_SEL, 1,
 859                                 OTG_FORCE_LOCK_ON_EVENT, 0,
 860                                 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
 861                                 OTG_SET_V_TOTAL_MIN_MASK, 0);
 862         } else {
 863                 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
 864                                 OTG_SET_V_TOTAL_MIN_MASK, 0,
 865                                 OTG_V_TOTAL_MIN_SEL, 0,
 866                                 OTG_V_TOTAL_MAX_SEL, 0,
 867                                 OTG_FORCE_LOCK_ON_EVENT, 0);
 868
 869                 REG_SET(OTG_V_TOTAL_MIN, 0,
 870                         OTG_V_TOTAL_MIN, 0);
 871
 872                 REG_SET(OTG_V_TOTAL_MAX, 0,
 873                         OTG_V_TOTAL_MAX, 0);
 874         }
 875 }
 876
 877 static void optc1_set_test_pattern(
 878         struct timing_generator *optc,
 879         /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
 880          * because this is not DP-specific (which is probably somewhere in DP
 881          * encoder) */
 882         enum controller_dp_test_pattern test_pattern,
 883         enum dc_color_depth color_depth)
 884 {
 885         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 886         enum test_pattern_color_format bit_depth;
 887         enum test_pattern_dyn_range dyn_range;
 888         enum test_pattern_mode mode;
 889         uint32_t pattern_mask;
 890         uint32_t pattern_data;
 891         /* color ramp generator mixes 16-bits color */
 892         uint32_t src_bpc = 16;
 893         /* requested bpc */
 894         uint32_t dst_bpc;
 895         uint32_t index;
 896         /* RGB values of the color bars.
 897          * Produce two RGB colors: RGB0 - white (all Fs)
 898          * and RGB1 - black (all 0s)
 899          * (three RGB components for two colors)
 900          */
 901         uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
 902                                                 0x0000, 0x0000};
 903         /* dest color (converted to the specified color format) */
 904         uint16_t dst_color[6];
 905         uint32_t inc_base;
 906
 907         /* translate to bit depth */
 908         switch (color_depth) {
 909         case COLOR_DEPTH_666:
 910                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
 911         break;
 912         case COLOR_DEPTH_888:
 913                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
 914         break;
 915         case COLOR_DEPTH_101010:
 916                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
 917         break;
 918         case COLOR_DEPTH_121212:
 919                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
 920         break;
 921         default:
 922                 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
 923         break;
 924         }
 925
 926         switch (test_pattern) {
 927         case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
 928         case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
 929         {
 930                 dyn_range = (test_pattern ==
 931                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
 932                                 TEST_PATTERN_DYN_RANGE_CEA :
 933                                 TEST_PATTERN_DYN_RANGE_VESA);
 934                 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
 935
 936                 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
 937                                 OTG_TEST_PATTERN_VRES, 6,
 938                                 OTG_TEST_PATTERN_HRES, 6);
 939
 940                 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
 941                                 OTG_TEST_PATTERN_EN, 1,
 942                                 OTG_TEST_PATTERN_MODE, mode,
 943                                 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
 944                                 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
 945         }
 946         break;
 947
 948         case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
 949         case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
 950         {
 951                 mode = (test_pattern ==
 952                         CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
 953                         TEST_PATTERN_MODE_VERTICALBARS :
 954                         TEST_PATTERN_MODE_HORIZONTALBARS);
 955
 956                 switch (bit_depth) {
 957                 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
 958                         dst_bpc = 6;
 959                 break;
 960                 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
 961                         dst_bpc = 8;
 962                 break;
 963                 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
 964                         dst_bpc = 10;
 965                 break;
 966                 default:
 967                         dst_bpc = 8;
 968                 break;
 969                 }
 970
 971                 /* adjust color to the required colorFormat */
 972                 for (index = 0; index < 6; index++) {
 973                         /* dst = 2^dstBpc * src / 2^srcBpc = src >>
 974                          * (srcBpc - dstBpc);
 975                          */
 976                         dst_color[index] =
 977                                 src_color[index] >> (src_bpc - dst_bpc);
 978                 /* CRTC_TEST_PATTERN_DATA has 16 bits,
 979                  * lowest 6 are hardwired to ZERO
 980                  * color bits should be left aligned aligned to MSB
 981                  * XXXXXXXXXX000000 for 10 bit,
 982                  * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
 983                  */
 984                         dst_color[index] <<= (16 - dst_bpc);
 985                 }
 986
 987                 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
 988
 989                 /* We have to write the mask before data, similar to pipeline.
 990                  * For example, for 8 bpc, if we want RGB0 to be magenta,
 991                  * and RGB1 to be cyan,
 992                  * we need to make 7 writes:
 993                  * MASK   DATA
 994                  * 000001 00000000 00000000                     set mask to R0
 995                  * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
 996                  * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
 997                  * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
 998                  * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
 999                  * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
1000                  * 100000 11111111 00000000     B1 255, 0xFF00
1001                  *
1002                  * we will make a loop of 6 in which we prepare the mask,
1003                  * then write, then prepare the color for next write.
1004                  * first iteration will write mask only,
1005                  * but each next iteration color prepared in
1006                  * previous iteration will be written within new mask,
1007                  * the last component will written separately,
1008                  * mask is not changing between 6th and 7th write
1009                  * and color will be prepared by last iteration
1010                  */
1011
1012                 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1013                  * is B1, G1, R1, B0, G0, R0
1014                  */
1015                 pattern_data = 0;
1016                 for (index = 0; index < 6; index++) {
1017                         /* prepare color mask, first write PATTERN_DATA
1018                          * will have all zeros
1019                          */
1020                         pattern_mask = (1 << index);
1021
1022                         /* write color component */
1023                         REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1024                                         OTG_TEST_PATTERN_MASK, pattern_mask,
1025                                         OTG_TEST_PATTERN_DATA, pattern_data);
1026
1027                         /* prepare next color component,
1028                          * will be written in the next iteration
1029                          */
1030                         pattern_data = dst_color[index];
1031                 }
1032                 /* write last color component,
1033                  * it's been already prepared in the loop
1034                  */
1035                 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1036                                 OTG_TEST_PATTERN_MASK, pattern_mask,
1037                                 OTG_TEST_PATTERN_DATA, pattern_data);
1038
1039                 /* enable test pattern */
1040                 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1041                                 OTG_TEST_PATTERN_EN, 1,
1042                                 OTG_TEST_PATTERN_MODE, mode,
1043                                 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1044                                 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1045         }
1046         break;
1047
1048         case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1049         {
1050                 mode = (bit_depth ==
1051                         TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1052                         TEST_PATTERN_MODE_DUALRAMP_RGB :
1053                         TEST_PATTERN_MODE_SINGLERAMP_RGB);
1054
1055                 switch (bit_depth) {
1056                 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1057                         dst_bpc = 6;
1058                 break;
1059                 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1060                         dst_bpc = 8;
1061                 break;
1062                 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1063                         dst_bpc = 10;
1064                 break;
1065                 default:
1066                         dst_bpc = 8;
1067                 break;
1068                 }
1069
1070                 /* increment for the first ramp for one color gradation
1071                  * 1 gradation for 6-bit color is 2^10
1072                  * gradations in 16-bit color
1073                  */
1074                 inc_base = (src_bpc - dst_bpc);
1075
1076                 switch (bit_depth) {
1077                 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1078                 {
1079                         REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1080                                         OTG_TEST_PATTERN_INC0, inc_base,
1081                                         OTG_TEST_PATTERN_INC1, 0,
1082                                         OTG_TEST_PATTERN_HRES, 6,
1083                                         OTG_TEST_PATTERN_VRES, 6,
1084                                         OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1085                 }
1086                 break;
1087                 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1088                 {
1089                         REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1090                                         OTG_TEST_PATTERN_INC0, inc_base,
1091                                         OTG_TEST_PATTERN_INC1, 0,
1092                                         OTG_TEST_PATTERN_HRES, 8,
1093                                         OTG_TEST_PATTERN_VRES, 6,
1094                                         OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1095                 }
1096                 break;
1097                 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1098                 {
1099                         REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1100                                         OTG_TEST_PATTERN_INC0, inc_base,
1101                                         OTG_TEST_PATTERN_INC1, inc_base + 2,
1102                                         OTG_TEST_PATTERN_HRES, 8,
1103                                         OTG_TEST_PATTERN_VRES, 5,
1104                                         OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1105                 }
1106                 break;
1107                 default:
1108                 break;
1109                 }
1110
1111                 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1112
1113                 /* enable test pattern */
1114                 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1115
1116                 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1117                                 OTG_TEST_PATTERN_EN, 1,
1118                                 OTG_TEST_PATTERN_MODE, mode,
1119                                 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1120                                 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1121         }
1122         break;
1123         case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1124         {
1125                 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1126                 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1127                 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1128         }
1129         break;
1130         default:
1131                 break;
1132
1133         }
1134 }
1135
1136 void optc1_get_crtc_scanoutpos(
1137         struct timing_generator *optc,
1138         uint32_t *v_blank_start,
1139         uint32_t *v_blank_end,
1140         uint32_t *h_position,
1141         uint32_t *v_position)
1142 {
1143         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1144         struct crtc_position position;
1145
1146         REG_GET_2(OTG_V_BLANK_START_END,
1147                         OTG_V_BLANK_START, v_blank_start,
1148                         OTG_V_BLANK_END, v_blank_end);
1149
1150         optc1_get_position(optc, &position);
1151
1152         *h_position = position.horizontal_count;
1153         *v_position = position.vertical_count;
1154 }
1155
1156 static void optc1_enable_stereo(struct timing_generator *optc,
1157         const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1158 {
1159         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1160
1161         if (flags) {
1162                 uint32_t stereo_en;
1163                 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1164
1165                 if (flags->PROGRAM_STEREO)
1166                         REG_UPDATE_3(OTG_STEREO_CONTROL,
1167                                 OTG_STEREO_EN, stereo_en,
1168                                 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1169                                 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
1170
1171                 if (flags->PROGRAM_POLARITY)
1172                         REG_UPDATE(OTG_STEREO_CONTROL,
1173                                 OTG_STEREO_EYE_FLAG_POLARITY,
1174                                 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1175
1176                 if (flags->DISABLE_STEREO_DP_SYNC)
1177                         REG_UPDATE(OTG_STEREO_CONTROL,
1178                                 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1179
1180                 if (flags->PROGRAM_STEREO)
1181                         REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL,
1182                                 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1183                                 OTG_3D_STRUCTURE_V_UPDATE_MODE, flags->FRAME_PACKED,
1184                                 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1185
1186         }
1187 }
1188
1189 void optc1_program_stereo(struct timing_generator *optc,
1190         const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1191 {
1192         if (flags->PROGRAM_STEREO)
1193                 optc1_enable_stereo(optc, timing, flags);
1194         else
1195                 optc1_disable_stereo(optc);
1196 }
1197
1198
1199 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1200 {
1201         bool ret = false;
1202         uint32_t left_eye = 0;
1203         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1204
1205         REG_GET(OTG_STEREO_STATUS,
1206                 OTG_STEREO_CURRENT_EYE, &left_eye);
1207         if (left_eye == 1)
1208                 ret = true;
1209         else
1210                 ret = false;
1211
1212         return ret;
1213 }
1214
1215 void optc1_read_otg_state(struct optc *optc1,
1216                 struct dcn_otg_state *s)
1217 {
1218         REG_GET(OTG_CONTROL,
1219                         OTG_MASTER_EN, &s->otg_enabled);
1220
1221         REG_GET_2(OTG_V_BLANK_START_END,
1222                         OTG_V_BLANK_START, &s->v_blank_start,
1223                         OTG_V_BLANK_END, &s->v_blank_end);
1224
1225         REG_GET(OTG_V_SYNC_A_CNTL,
1226                         OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1227
1228         REG_GET(OTG_V_TOTAL,
1229                         OTG_V_TOTAL, &s->v_total);
1230
1231         REG_GET(OTG_V_TOTAL_MAX,
1232                         OTG_V_TOTAL_MAX, &s->v_total_max);
1233
1234         REG_GET(OTG_V_TOTAL_MIN,
1235                         OTG_V_TOTAL_MIN, &s->v_total_min);
1236
1237         REG_GET(OTG_V_TOTAL_CONTROL,
1238                         OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1239
1240         REG_GET(OTG_V_TOTAL_CONTROL,
1241                         OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1242
1243         REG_GET_2(OTG_V_SYNC_A,
1244                         OTG_V_SYNC_A_START, &s->v_sync_a_start,
1245                         OTG_V_SYNC_A_END, &s->v_sync_a_end);
1246
1247         REG_GET_2(OTG_H_BLANK_START_END,
1248                         OTG_H_BLANK_START, &s->h_blank_start,
1249                         OTG_H_BLANK_END, &s->h_blank_end);
1250
1251         REG_GET_2(OTG_H_SYNC_A,
1252                         OTG_H_SYNC_A_START, &s->h_sync_a_start,
1253                         OTG_H_SYNC_A_END, &s->h_sync_a_end);
1254
1255         REG_GET(OTG_H_SYNC_A_CNTL,
1256                         OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1257
1258         REG_GET(OTG_H_TOTAL,
1259                         OTG_H_TOTAL, &s->h_total);
1260
1261         REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1262                         OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1263 }
1264
1265 bool optc1_get_otg_active_size(struct timing_generator *optc,
1266                 uint32_t *otg_active_width,
1267                 uint32_t *otg_active_height)
1268 {
1269         uint32_t otg_enabled;
1270         uint32_t v_blank_start;
1271         uint32_t v_blank_end;
1272         uint32_t h_blank_start;
1273         uint32_t h_blank_end;
1274         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1275
1276
1277         REG_GET(OTG_CONTROL,
1278                         OTG_MASTER_EN, &otg_enabled);
1279
1280         if (otg_enabled == 0)
1281                 return false;
1282
1283         REG_GET_2(OTG_V_BLANK_START_END,
1284                         OTG_V_BLANK_START, &v_blank_start,
1285                         OTG_V_BLANK_END, &v_blank_end);
1286
1287         REG_GET_2(OTG_H_BLANK_START_END,
1288                         OTG_H_BLANK_START, &h_blank_start,
1289                         OTG_H_BLANK_END, &h_blank_end);
1290
1291         *otg_active_width = v_blank_start - v_blank_end;
1292         *otg_active_height = h_blank_start - h_blank_end;
1293         return true;
1294 }
1295
1296 void optc1_clear_optc_underflow(struct timing_generator *optc)
1297 {
1298         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1299
1300         REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1301 }
1302
1303 void optc1_tg_init(struct timing_generator *optc)
1304 {
1305         optc1_set_blank_data_double_buffer(optc, true);
1306         optc1_clear_optc_underflow(optc);
1307 }
1308
1309 bool optc1_is_tg_enabled(struct timing_generator *optc)
1310 {
1311         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1312         uint32_t otg_enabled = 0;
1313
1314         REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1315
1316         return (otg_enabled != 0);
1317
1318 }
1319
1320 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1321 {
1322         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1323         uint32_t underflow_occurred = 0;
1324
1325         REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1326                         OPTC_UNDERFLOW_OCCURRED_STATUS,
1327                         &underflow_occurred);
1328
1329         return (underflow_occurred == 1);
1330 }
1331
1332 bool optc1_configure_crc(struct timing_generator *optc,
1333                           const struct crc_params *params)
1334 {
1335         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1336
1337         /* Cannot configure crc on a CRTC that is disabled */
1338         if (!optc1_is_tg_enabled(optc))
1339                 return false;
1340
1341         REG_WRITE(OTG_CRC_CNTL, 0);
1342
1343         if (!params->enable)
1344                 return true;
1345
1346         /* Program frame boundaries */
1347         /* Window A x axis start and end. */
1348         REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1349                         OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1350                         OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1351
1352         /* Window A y axis start and end. */
1353         REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1354                         OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1355                         OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1356
1357         /* Window B x axis start and end. */
1358         REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1359                         OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1360                         OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1361
1362         /* Window B y axis start and end. */
1363         REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1364                         OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1365                         OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1366
1367         /* Set crc mode and selection, and enable. Only using CRC0*/
1368         REG_UPDATE_3(OTG_CRC_CNTL,
1369                         OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1370                         OTG_CRC0_SELECT, params->selection,
1371                         OTG_CRC_EN, 1);
1372
1373         return true;
1374 }
1375
1376 bool optc1_get_crc(struct timing_generator *optc,
1377                     uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1378 {
1379         uint32_t field = 0;
1380         struct optc *optc1 = DCN10TG_FROM_TG(optc);
1381
1382         REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1383
1384         /* Early return if CRC is not enabled for this CRTC */
1385         if (!field)
1386                 return false;
1387
1388         REG_GET_2(OTG_CRC0_DATA_RG,
1389                         CRC0_R_CR, r_cr,
1390                         CRC0_G_Y, g_y);
1391
1392         REG_GET(OTG_CRC0_DATA_B,
1393                         CRC0_B_CB, b_cb);
1394
1395         return true;
1396 }
1397
1398 static const struct timing_generator_funcs dcn10_tg_funcs = {
1399                 .validate_timing = optc1_validate_timing,
1400                 .program_timing = optc1_program_timing,
1401                 .program_vline_interrupt = optc1_program_vline_interrupt,
1402                 .program_global_sync = optc1_program_global_sync,
1403                 .enable_crtc = optc1_enable_crtc,
1404                 .disable_crtc = optc1_disable_crtc,
1405                 /* used by enable_timing_synchronization. Not need for FPGA */
1406                 .is_counter_moving = optc1_is_counter_moving,
1407                 .get_position = optc1_get_position,
1408                 .get_frame_count = optc1_get_vblank_counter,
1409                 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1410                 .get_otg_active_size = optc1_get_otg_active_size,
1411                 .set_early_control = optc1_set_early_control,
1412                 /* used by enable_timing_synchronization. Not need for FPGA */
1413                 .wait_for_state = optc1_wait_for_state,
1414                 .set_blank = optc1_set_blank,
1415                 .is_blanked = optc1_is_blanked,
1416                 .set_blank_color = optc1_program_blank_color,
1417                 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1418                 .enable_reset_trigger = optc1_enable_reset_trigger,
1419                 .enable_crtc_reset = optc1_enable_crtc_reset,
1420                 .disable_reset_trigger = optc1_disable_reset_trigger,
1421                 .lock = optc1_lock,
1422                 .unlock = optc1_unlock,
1423                 .enable_optc_clock = optc1_enable_optc_clock,
1424                 .set_drr = optc1_set_drr,
1425                 .set_static_screen_control = optc1_set_static_screen_control,
1426                 .set_test_pattern = optc1_set_test_pattern,
1427                 .program_stereo = optc1_program_stereo,
1428                 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1429                 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1430                 .tg_init = optc1_tg_init,
1431                 .is_tg_enabled = optc1_is_tg_enabled,
1432                 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1433                 .clear_optc_underflow = optc1_clear_optc_underflow,
1434                 .get_crc = optc1_get_crc,
1435                 .configure_crc = optc1_configure_crc,
1436 };
1437
1438 void dcn10_timing_generator_init(struct optc *optc1)
1439 {
1440         optc1->base.funcs = &dcn10_tg_funcs;
1441
1442         optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1443         optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1444
1445         optc1->min_h_blank = 32;
1446         optc1->min_v_blank = 3;
1447         optc1->min_v_blank_interlace = 5;
1448         optc1->min_h_sync_width = 8;
1449         optc1->min_v_sync_width = 1;
1450 }