2 * Copyright 2013-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 * Pre-requisites: headers required by header of this unit
30 #include "hw_translate_dcn10.h"
32 #include "dm_services.h"
33 #include "include/gpio_types.h"
34 #include "../hw_translate.h"
36 #include "dcn/dcn_1_0_offset.h"
37 #include "dcn/dcn_1_0_sh_mask.h"
38 #include "soc15_hw_ip.h"
39 #include "vega10_ip_offset.h"
41 /* begin *********************
42 * macros to expend register list macro defined in HW object header file */
44 #define BASE_INNER(seg) \
45 DCE_BASE__INST0_SEG ## seg
47 /* compile time expand base address. */
51 #define REG(reg_name)\
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
54 #define REGI(reg_name, block, id)\
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
56 mm ## block ## id ## _ ## reg_name
58 /* macros to expend register list macro defined in HW object header file
59 * end *********************/
61 static bool offset_to_id(
69 case REG(DC_GPIO_GENERIC_A):
70 *id = GPIO_ID_GENERIC;
72 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
75 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
78 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
81 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
84 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
87 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
90 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
94 ASSERT_CRITICAL(false);
99 case REG(DC_GPIO_HPD_A):
102 case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
105 case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
108 case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
111 case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
114 case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
117 case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
121 ASSERT_CRITICAL(false);
126 case REG(DC_GPIO_SYNCA_A):
129 case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
130 *en = GPIO_SYNC_HSYNC_A;
132 case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
133 *en = GPIO_SYNC_VSYNC_A;
136 ASSERT_CRITICAL(false);
140 /* REG(DC_GPIO_GENLK_MASK */
141 case REG(DC_GPIO_GENLK_A):
144 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
145 *en = GPIO_GSL_GENLOCK_CLOCK;
147 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
148 *en = GPIO_GSL_GENLOCK_VSYNC;
150 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
151 *en = GPIO_GSL_SWAPLOCK_A;
153 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
154 *en = GPIO_GSL_SWAPLOCK_B;
157 ASSERT_CRITICAL(false);
162 /* we don't care about the GPIO_ID for DDC
163 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
164 * directly in the create method */
165 case REG(DC_GPIO_DDC1_A):
166 *en = GPIO_DDC_LINE_DDC1;
168 case REG(DC_GPIO_DDC2_A):
169 *en = GPIO_DDC_LINE_DDC2;
171 case REG(DC_GPIO_DDC3_A):
172 *en = GPIO_DDC_LINE_DDC3;
174 case REG(DC_GPIO_DDC4_A):
175 *en = GPIO_DDC_LINE_DDC4;
177 case REG(DC_GPIO_DDC5_A):
178 *en = GPIO_DDC_LINE_DDC5;
180 case REG(DC_GPIO_DDC6_A):
181 *en = GPIO_DDC_LINE_DDC6;
183 case REG(DC_GPIO_DDCVGA_A):
184 *en = GPIO_DDC_LINE_DDC_VGA;
187 case REG(DC_GPIO_I2CPAD_A):
188 *en = GPIO_DDC_LINE_I2C_PAD;
190 /* Not implemented */
191 case REG(DC_GPIO_PWRSEQ_A):
192 case REG(DC_GPIO_PAD_STRENGTH_1):
193 case REG(DC_GPIO_PAD_STRENGTH_2):
194 case REG(DC_GPIO_DEBUG):
198 ASSERT_CRITICAL(false);
203 static bool id_to_offset(
206 struct gpio_pin_info *info)
211 case GPIO_ID_DDC_DATA:
212 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
214 case GPIO_DDC_LINE_DDC1:
215 info->offset = REG(DC_GPIO_DDC1_A);
217 case GPIO_DDC_LINE_DDC2:
218 info->offset = REG(DC_GPIO_DDC2_A);
220 case GPIO_DDC_LINE_DDC3:
221 info->offset = REG(DC_GPIO_DDC3_A);
223 case GPIO_DDC_LINE_DDC4:
224 info->offset = REG(DC_GPIO_DDC4_A);
226 case GPIO_DDC_LINE_DDC5:
227 info->offset = REG(DC_GPIO_DDC5_A);
229 case GPIO_DDC_LINE_DDC6:
230 info->offset = REG(DC_GPIO_DDC6_A);
232 case GPIO_DDC_LINE_DDC_VGA:
233 info->offset = REG(DC_GPIO_DDCVGA_A);
235 case GPIO_DDC_LINE_I2C_PAD:
236 info->offset = REG(DC_GPIO_I2CPAD_A);
239 ASSERT_CRITICAL(false);
243 case GPIO_ID_DDC_CLOCK:
244 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
246 case GPIO_DDC_LINE_DDC1:
247 info->offset = REG(DC_GPIO_DDC1_A);
249 case GPIO_DDC_LINE_DDC2:
250 info->offset = REG(DC_GPIO_DDC2_A);
252 case GPIO_DDC_LINE_DDC3:
253 info->offset = REG(DC_GPIO_DDC3_A);
255 case GPIO_DDC_LINE_DDC4:
256 info->offset = REG(DC_GPIO_DDC4_A);
258 case GPIO_DDC_LINE_DDC5:
259 info->offset = REG(DC_GPIO_DDC5_A);
261 case GPIO_DDC_LINE_DDC6:
262 info->offset = REG(DC_GPIO_DDC6_A);
264 case GPIO_DDC_LINE_DDC_VGA:
265 info->offset = REG(DC_GPIO_DDCVGA_A);
267 case GPIO_DDC_LINE_I2C_PAD:
268 info->offset = REG(DC_GPIO_I2CPAD_A);
271 ASSERT_CRITICAL(false);
275 case GPIO_ID_GENERIC:
276 info->offset = REG(DC_GPIO_GENERIC_A);
279 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
282 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
285 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
288 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
291 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
294 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
297 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
300 ASSERT_CRITICAL(false);
305 info->offset = REG(DC_GPIO_HPD_A);
308 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
311 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
314 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
317 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
320 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
323 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
326 ASSERT_CRITICAL(false);
332 case GPIO_SYNC_HSYNC_A:
333 info->offset = REG(DC_GPIO_SYNCA_A);
334 info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
336 case GPIO_SYNC_VSYNC_A:
337 info->offset = REG(DC_GPIO_SYNCA_A);
338 info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
340 case GPIO_SYNC_HSYNC_B:
341 case GPIO_SYNC_VSYNC_B:
343 ASSERT_CRITICAL(false);
349 case GPIO_GSL_GENLOCK_CLOCK:
350 info->offset = REG(DC_GPIO_GENLK_A);
351 info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
353 case GPIO_GSL_GENLOCK_VSYNC:
354 info->offset = REG(DC_GPIO_GENLK_A);
356 DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
358 case GPIO_GSL_SWAPLOCK_A:
359 info->offset = REG(DC_GPIO_GENLK_A);
360 info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
362 case GPIO_GSL_SWAPLOCK_B:
363 info->offset = REG(DC_GPIO_GENLK_A);
364 info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
367 ASSERT_CRITICAL(false);
371 case GPIO_ID_VIP_PAD:
373 ASSERT_CRITICAL(false);
378 info->offset_y = info->offset + 2;
379 info->offset_en = info->offset + 1;
380 info->offset_mask = info->offset - 1;
382 info->mask_y = info->mask;
383 info->mask_en = info->mask;
384 info->mask_mask = info->mask;
391 static const struct hw_translate_funcs funcs = {
392 .offset_to_id = offset_to_id,
393 .id_to_offset = id_to_offset,
397 * dal_hw_translate_dcn10_init
400 * Initialize Hw translate function pointers.
403 * struct hw_translate *tr - [out] struct of function pointers
406 void dal_hw_translate_dcn10_init(struct hw_translate *tr)