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26 #include "dm_services.h"
29 * Pre-requisites: headers required by header of this unit
31 #include "include/i2caux_interface.h"
32 #include "dc_bios_types.h"
41 * Post-requisites: headers required by this unit
45 #include "i2c_engine.h"
46 #include "aux_engine.h"
52 #include "dce80/i2caux_dce80.h"
54 #include "dce100/i2caux_dce100.h"
56 #include "dce110/i2caux_dce110.h"
58 #include "dce112/i2caux_dce112.h"
60 #include "dce120/i2caux_dce120.h"
62 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
63 #include "dcn10/i2caux_dcn10.h"
66 #include "diagnostics/i2caux_diag.h"
70 * Plain API, available publicly
73 struct i2caux *dal_i2caux_create(
74 struct dc_context *ctx)
76 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
77 return dal_i2caux_diag_fpga_create(ctx);
80 switch (ctx->dce_version) {
84 return dal_i2caux_dce80_create(ctx);
85 case DCE_VERSION_11_2:
86 case DCE_VERSION_11_22:
87 return dal_i2caux_dce112_create(ctx);
88 case DCE_VERSION_11_0:
89 return dal_i2caux_dce110_create(ctx);
90 case DCE_VERSION_10_0:
91 return dal_i2caux_dce100_create(ctx);
92 case DCE_VERSION_12_0:
93 return dal_i2caux_dce120_create(ctx);
94 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
96 return dal_i2caux_dcn10_create(ctx);
105 bool dal_i2caux_submit_i2c_command(
106 struct i2caux *i2caux,
108 struct i2c_command *cmd)
110 struct i2c_engine *engine;
111 uint8_t index_of_payload = 0;
125 * default will be SW, however there is a feature flag in adapter
126 * service that determines whether SW i2c_engine will be available or
127 * not, if sw i2c is not available we will fallback to hw. This feature
128 * flag is set to not creating sw i2c engine for every dce except dce80
131 switch (cmd->engine) {
132 case I2C_COMMAND_ENGINE_DEFAULT:
133 case I2C_COMMAND_ENGINE_SW:
134 /* try to acquire SW engine first,
135 * acquire HW engine if SW engine not available */
136 engine = i2caux->funcs->acquire_i2c_sw_engine(i2caux, ddc);
139 engine = i2caux->funcs->acquire_i2c_hw_engine(
142 case I2C_COMMAND_ENGINE_HW:
144 /* try to acquire HW engine first,
145 * acquire SW engine if HW engine not available */
146 engine = i2caux->funcs->acquire_i2c_hw_engine(i2caux, ddc);
149 engine = i2caux->funcs->acquire_i2c_sw_engine(
156 engine->funcs->set_speed(engine, cmd->speed);
160 while (index_of_payload < cmd->number_of_payloads) {
161 bool mot = (index_of_payload != cmd->number_of_payloads - 1);
163 struct i2c_payload *payload = cmd->payloads + index_of_payload;
165 struct i2caux_transaction_request request = { 0 };
167 request.operation = payload->write ?
168 I2CAUX_TRANSACTION_WRITE :
169 I2CAUX_TRANSACTION_READ;
171 request.payload.address_space =
172 I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
173 request.payload.address = (payload->address << 1) |
175 request.payload.length = payload->length;
176 request.payload.data = payload->data;
178 if (!engine->base.funcs->submit_request(
179 &engine->base, &request, mot)) {
187 i2caux->funcs->release_engine(i2caux, &engine->base);
192 bool dal_i2caux_submit_aux_command(
193 struct i2caux *i2caux,
195 struct aux_command *cmd)
197 struct aux_engine *engine;
198 uint8_t index_of_payload = 0;
212 engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc);
217 engine->delay = cmd->defer_delay;
218 engine->max_defer_write_retry = cmd->max_defer_write_retry;
222 while (index_of_payload < cmd->number_of_payloads) {
223 struct aux_payload *payload = cmd->payloads + index_of_payload;
224 struct i2caux_transaction_request request = { 0 };
226 if (cmd->mot == I2C_MOT_UNDEF)
227 mot = (index_of_payload != cmd->number_of_payloads - 1);
229 mot = (cmd->mot == I2C_MOT_TRUE);
231 request.operation = payload->write ?
232 I2CAUX_TRANSACTION_WRITE :
233 I2CAUX_TRANSACTION_READ;
235 if (payload->i2c_over_aux) {
236 request.payload.address_space =
237 I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
239 request.payload.address = (payload->address << 1) |
242 request.payload.address_space =
243 I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD;
245 request.payload.address = payload->address;
248 request.payload.length = payload->length;
249 request.payload.data = payload->data;
251 if (!engine->base.funcs->submit_request(
252 &engine->base, &request, mot)) {
260 i2caux->funcs->release_engine(i2caux, &engine->base);
265 static bool get_hw_supported_ddc_line(
267 enum gpio_ddc_line *line)
269 enum gpio_ddc_line line_found;
271 *line = GPIO_DDC_LINE_UNKNOWN;
278 if (!ddc->hw_info.hw_supported)
281 line_found = dal_ddc_get_line(ddc);
283 if (line_found >= GPIO_DDC_LINE_COUNT)
291 void dal_i2caux_configure_aux(
292 struct i2caux *i2caux,
294 union aux_config cfg)
296 struct aux_engine *engine =
297 i2caux->funcs->acquire_aux_engine(i2caux, ddc);
302 engine->funcs->configure(engine, cfg);
304 i2caux->funcs->release_engine(i2caux, &engine->base);
307 void dal_i2caux_destroy(
308 struct i2caux **i2caux)
310 if (!i2caux || !*i2caux) {
315 (*i2caux)->funcs->destroy(i2caux);
322 * An utility function used by 'struct i2caux' and its descendants
325 uint32_t dal_i2caux_get_reference_clock(
326 struct dc_bios *bios)
328 struct dc_firmware_info info = { { 0 } };
330 if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
333 return info.pll_info.crystal_frequency;
342 /* following are expressed in KHz */
343 DEFAULT_I2C_SW_SPEED = 50,
344 DEFAULT_I2C_HW_SPEED = 50,
346 DEFAULT_I2C_SW_SPEED_100KHZ = 100,
347 DEFAULT_I2C_HW_SPEED_100KHZ = 100,
349 /* This is the timeout as defined in DP 1.2a,
350 * 2.3.4 "Detailed uPacket TX AUX CH State Description". */
351 AUX_TIMEOUT_PERIOD = 400,
353 /* Ideally, the SW timeout should be just above 550usec
354 * which is programmed in HW.
355 * But the SW timeout of 600usec is not reliable,
356 * because on some systems, delay_in_microseconds()
357 * returns faster than it should.
358 * EPR #379763: by trial-and-error on different systems,
359 * 700usec is the minimum reliable SW timeout for polling
360 * the AUX_SW_STATUS.AUX_SW_DONE bit.
361 * This timeout expires *only* when there is
362 * AUX Error or AUX Timeout conditions - not during normal operation.
363 * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
364 * at most within ~240usec. That means,
365 * increasing this timeout will not affect normal operation,
366 * and we'll timeout after
367 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
368 * This timeout is especially important for
369 * resume from S3 and CTS. */
370 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
373 struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
374 struct i2caux *i2caux,
377 enum gpio_ddc_line line;
378 struct i2c_engine *engine = NULL;
380 if (get_hw_supported_ddc_line(ddc, &line))
381 engine = i2caux->i2c_sw_engines[line];
384 engine = i2caux->i2c_generic_sw_engine;
389 if (!engine->base.funcs->acquire(&engine->base, ddc))
395 struct aux_engine *dal_i2caux_acquire_aux_engine(
396 struct i2caux *i2caux,
399 enum gpio_ddc_line line;
400 struct aux_engine *engine;
402 if (!get_hw_supported_ddc_line(ddc, &line))
405 engine = i2caux->aux_engines[line];
410 if (!engine->base.funcs->acquire(&engine->base, ddc))
416 void dal_i2caux_release_engine(
417 struct i2caux *i2caux,
418 struct engine *engine)
420 engine->funcs->release_engine(engine);
422 dal_ddc_close(engine->ddc);
427 void dal_i2caux_construct(
428 struct i2caux *i2caux,
429 struct dc_context *ctx)
435 i2caux->i2c_sw_engines[i] = NULL;
436 i2caux->i2c_hw_engines[i] = NULL;
437 i2caux->aux_engines[i] = NULL;
440 } while (i < GPIO_DDC_LINE_COUNT);
442 i2caux->i2c_generic_sw_engine = NULL;
443 i2caux->i2c_generic_hw_engine = NULL;
445 i2caux->aux_timeout_period =
446 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD;
448 if (ctx->dce_version >= DCE_VERSION_11_2) {
449 i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED_100KHZ;
450 i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED_100KHZ;
452 i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED;
453 i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED;
457 void dal_i2caux_destruct(
458 struct i2caux *i2caux)
462 if (i2caux->i2c_generic_hw_engine)
463 i2caux->i2c_generic_hw_engine->funcs->destroy(
464 &i2caux->i2c_generic_hw_engine);
466 if (i2caux->i2c_generic_sw_engine)
467 i2caux->i2c_generic_sw_engine->funcs->destroy(
468 &i2caux->i2c_generic_sw_engine);
471 if (i2caux->aux_engines[i])
472 i2caux->aux_engines[i]->funcs->destroy(
473 &i2caux->aux_engines[i]);
475 if (i2caux->i2c_hw_engines[i])
476 i2caux->i2c_hw_engines[i]->funcs->destroy(
477 &i2caux->i2c_hw_engines[i]);
479 if (i2caux->i2c_sw_engines[i])
480 i2caux->i2c_sw_engines[i]->funcs->destroy(
481 &i2caux->i2c_sw_engines[i]);
484 } while (i < GPIO_DDC_LINE_COUNT);