2 * Copyright 2016 Advanced Micro Devices, Inc.
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11 * The above copyright notice and this permission notice shall be included in
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25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
28 #include "dm_services.h"
30 /* macro for register read/write
31 * user of macro need to define
33 * CTX ==> macro to ptr to dc_context
34 * eg. aud110->base.ctx
36 * REG ==> macro to location of register offset
37 * eg. aud110->regs->reg
39 #define REG_READ(reg_name) \
40 dm_read_reg(CTX, REG(reg_name))
42 #define REG_WRITE(reg_name, value) \
43 dm_write_reg(CTX, REG(reg_name), value)
53 /* macro to set register fields. */
54 #define REG_SET_N(reg_name, n, initial_val, ...) \
55 generic_reg_update_ex(CTX, \
60 #define FN(reg_name, field) \
61 FD(reg_name##__##field)
63 #define REG_SET(reg_name, initial_val, field, val) \
64 REG_SET_N(reg_name, 1, initial_val, \
65 FN(reg_name, field), val)
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
68 REG_SET_N(reg, 2, init_value, \
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
73 REG_SET_N(reg, 3, init_value, \
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
79 REG_SET_N(reg, 4, init_value, \
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
87 REG_SET_N(reg, 5, init_value, \
94 #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
96 REG_SET_N(reg, 6, init_value, \
104 #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
105 f5, v5, f6, v6, f7, v7) \
106 REG_SET_N(reg, 7, init_value, \
115 #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
116 f5, v5, f6, v6, f7, v7, f8, v8) \
117 REG_SET_N(reg, 8, init_value, \
127 #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \
129 REG_SET_N(reg, 9, init_value, \
140 #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
142 REG_SET_N(reg, 10, init_value, \
154 /* macro to get register fields
155 * read given register and fill in field value in output parameter */
156 #define REG_GET(reg_name, field, val) \
157 generic_reg_get(CTX, REG(reg_name), \
158 FN(reg_name, field), val)
160 #define REG_GET_2(reg_name, f1, v1, f2, v2) \
161 generic_reg_get2(CTX, REG(reg_name), \
162 FN(reg_name, f1), v1, \
163 FN(reg_name, f2), v2)
165 #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \
166 generic_reg_get3(CTX, REG(reg_name), \
167 FN(reg_name, f1), v1, \
168 FN(reg_name, f2), v2, \
169 FN(reg_name, f3), v3)
171 #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \
172 generic_reg_get4(CTX, REG(reg_name), \
173 FN(reg_name, f1), v1, \
174 FN(reg_name, f2), v2, \
175 FN(reg_name, f3), v3, \
176 FN(reg_name, f4), v4)
178 #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
179 generic_reg_get5(CTX, REG(reg_name), \
180 FN(reg_name, f1), v1, \
181 FN(reg_name, f2), v2, \
182 FN(reg_name, f3), v3, \
183 FN(reg_name, f4), v4, \
184 FN(reg_name, f5), v5)
186 #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
187 generic_reg_get6(CTX, REG(reg_name), \
188 FN(reg_name, f1), v1, \
189 FN(reg_name, f2), v2, \
190 FN(reg_name, f3), v3, \
191 FN(reg_name, f4), v4, \
192 FN(reg_name, f5), v5, \
193 FN(reg_name, f6), v6)
195 #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
196 generic_reg_get7(CTX, REG(reg_name), \
197 FN(reg_name, f1), v1, \
198 FN(reg_name, f2), v2, \
199 FN(reg_name, f3), v3, \
200 FN(reg_name, f4), v4, \
201 FN(reg_name, f5), v5, \
202 FN(reg_name, f6), v6, \
203 FN(reg_name, f7), v7)
205 #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
206 generic_reg_get8(CTX, REG(reg_name), \
207 FN(reg_name, f1), v1, \
208 FN(reg_name, f2), v2, \
209 FN(reg_name, f3), v3, \
210 FN(reg_name, f4), v4, \
211 FN(reg_name, f5), v5, \
212 FN(reg_name, f6), v6, \
213 FN(reg_name, f7), v7, \
214 FN(reg_name, f8), v8)
216 /* macro to poll and wait for a register field to read back given value */
218 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
219 generic_reg_wait(CTX, \
220 REG(reg_name), FN(reg_name, field), val,\
221 delay_between_poll_us, max_try, __func__, __LINE__)
223 /* macro to update (read, modify, write) register fields
225 #define REG_UPDATE_N(reg_name, n, ...) \
226 generic_reg_update_ex(CTX, \
228 REG_READ(reg_name), \
231 #define REG_UPDATE(reg_name, field, val) \
232 REG_UPDATE_N(reg_name, 1, \
233 FN(reg_name, field), val)
235 #define REG_UPDATE_2(reg, f1, v1, f2, v2) \
236 REG_UPDATE_N(reg, 2,\
240 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
241 REG_UPDATE_N(reg, 3, \
246 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
247 REG_UPDATE_N(reg, 4, \
253 #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
254 REG_UPDATE_N(reg, 5, \
261 #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
262 REG_UPDATE_N(reg, 6, \
270 #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
271 REG_UPDATE_N(reg, 7, \
280 #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
281 REG_UPDATE_N(reg, 8, \
291 #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \
292 REG_UPDATE_N(reg, 9, \
303 #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
304 REG_UPDATE_N(reg, 10, \
316 #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
317 v10, f11, v11, f12, v12, f13, v13, f14, v14)\
318 REG_UPDATE_N(reg, 14, \
334 #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
335 v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19)\
336 REG_UPDATE_N(reg, 19, \
357 #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
358 v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20)\
359 REG_UPDATE_N(reg, 20, \
380 /* macro to update a register field to specified values in given sequences.
381 * useful when toggling bits
383 #define REG_UPDATE_SEQ(reg, field, value1, value2) \
384 { uint32_t val = REG_UPDATE(reg, field, value1); \
385 REG_SET(reg, val, field, value2); }
387 /* macro to update fields in register 1 field at a time in given order */
388 #define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
389 { uint32_t val = REG_UPDATE(reg, f1, v1); \
390 REG_SET(reg, val, f2, v2); }
392 #define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
393 { uint32_t val = REG_UPDATE(reg, f1, v1); \
394 val = REG_SET(reg, val, f2, v2); \
395 REG_SET(reg, val, f3, v3); }
397 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
398 uint8_t shift, uint32_t mask, uint32_t *field_value);
400 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
401 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
402 uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
404 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
405 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
406 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
407 uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
409 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
410 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
411 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
412 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
413 uint8_t shift4, uint32_t mask4, uint32_t *field_value4);
415 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
416 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
417 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
418 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
419 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
420 uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
422 uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
423 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
424 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
425 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
426 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
427 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
428 uint8_t shift6, uint32_t mask6, uint32_t *field_value6);
430 uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
431 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
432 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
433 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
434 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
435 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
436 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
437 uint8_t shift7, uint32_t mask7, uint32_t *field_value7);
439 uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
440 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
441 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
442 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
443 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
444 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
445 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
446 uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
447 uint8_t shift8, uint32_t mask8, uint32_t *field_value8);
450 /* indirect register access */
452 #define IX_REG_SET_N(index_reg_name, data_reg_name, index, n, initial_val, ...) \
453 generic_indirect_reg_update_ex(CTX, \
454 REG(index_reg_name), REG(data_reg_name), IND_REG(index), \
458 #define IX_REG_SET_2(index_reg_name, data_reg_name, index, init_value, f1, v1, f2, v2) \
459 IX_REG_SET_N(index_reg_name, data_reg_name, index, 2, init_value, \
464 #define IX_REG_READ(index_reg_name, data_reg_name, index) \
465 generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))
469 #define IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, n, ...) \
470 generic_indirect_reg_update_ex(CTX, \
471 REG(index_reg_name), REG(data_reg_name), IND_REG(index), \
472 IX_REG_READ(index_reg_name, data_reg_name, index), \
475 #define IX_REG_UPDATE_2(index_reg_name, data_reg_name, index, f1, v1, f2, v2) \
476 IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, 2,\
480 void generic_write_indirect_reg(const struct dc_context *ctx,
481 uint32_t addr_index, uint32_t addr_data,
482 uint32_t index, uint32_t data);
484 uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
485 uint32_t addr_index, uint32_t addr_data,
488 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
489 uint32_t addr_index, uint32_t addr_data,
490 uint32_t index, uint32_t reg_val, int n,
491 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
494 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */