drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "include/logger_interface.h"
  29
  30 #include "../dce110/irq_service_dce110.h"
  31
  32 #include "dcn/dcn_1_0_offset.h"
  33 #include "dcn/dcn_1_0_sh_mask.h"
  34 #include "soc15_hw_ip.h"
  35 #include "vega10_ip_offset.h"
  36
  37 #include "irq_service_dcn10.h"
  38
  39 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  40
  41 enum dc_irq_source to_dal_irq_source_dcn10(
  42                 struct irq_service *irq_service,
  43                 uint32_t src_id,
  44                 uint32_t ext_id)
  45 {
  46         switch (src_id) {
  47         case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
  48                 return DC_IRQ_SOURCE_VBLANK1;
  49         case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
  50                 return DC_IRQ_SOURCE_VBLANK2;
  51         case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
  52                 return DC_IRQ_SOURCE_VBLANK3;
  53         case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
  54                 return DC_IRQ_SOURCE_VBLANK4;
  55         case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
  56                 return DC_IRQ_SOURCE_VBLANK5;
  57         case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
  58                 return DC_IRQ_SOURCE_VBLANK6;
  59         case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
  60                 return DC_IRQ_SOURCE_PFLIP1;
  61         case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
  62                 return DC_IRQ_SOURCE_PFLIP2;
  63         case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
  64                 return DC_IRQ_SOURCE_PFLIP3;
  65         case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
  66                 return DC_IRQ_SOURCE_PFLIP4;
  67         case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
  68                 return DC_IRQ_SOURCE_PFLIP5;
  69         case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
  70                 return DC_IRQ_SOURCE_PFLIP6;
  71
  72         case DCN_1_0__SRCID__DC_HPD1_INT:
  73                 /* generic src_id for all HPD and HPDRX interrupts */
  74                 switch (ext_id) {
  75                 case DCN_1_0__CTXID__DC_HPD1_INT:
  76                         return DC_IRQ_SOURCE_HPD1;
  77                 case DCN_1_0__CTXID__DC_HPD2_INT:
  78                         return DC_IRQ_SOURCE_HPD2;
  79                 case DCN_1_0__CTXID__DC_HPD3_INT:
  80                         return DC_IRQ_SOURCE_HPD3;
  81                 case DCN_1_0__CTXID__DC_HPD4_INT:
  82                         return DC_IRQ_SOURCE_HPD4;
  83                 case DCN_1_0__CTXID__DC_HPD5_INT:
  84                         return DC_IRQ_SOURCE_HPD5;
  85                 case DCN_1_0__CTXID__DC_HPD6_INT:
  86                         return DC_IRQ_SOURCE_HPD6;
  87                 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
  88                         return DC_IRQ_SOURCE_HPD1RX;
  89                 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
  90                         return DC_IRQ_SOURCE_HPD2RX;
  91                 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
  92                         return DC_IRQ_SOURCE_HPD3RX;
  93                 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
  94                         return DC_IRQ_SOURCE_HPD4RX;
  95                 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
  96                         return DC_IRQ_SOURCE_HPD5RX;
  97                 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
  98                         return DC_IRQ_SOURCE_HPD6RX;
  99                 default:
 100                         return DC_IRQ_SOURCE_INVALID;
 101                 }
 102                 break;
 103
 104         default:
 105                 return DC_IRQ_SOURCE_INVALID;
 106         }
 107 }
 108
 109 static bool hpd_ack(
 110         struct irq_service *irq_service,
 111         const struct irq_source_info *info)
 112 {
 113         uint32_t addr = info->status_reg;
 114         uint32_t value = dm_read_reg(irq_service->ctx, addr);
 115         uint32_t current_status =
 116                 get_reg_field_value(
 117                         value,
 118                         HPD0_DC_HPD_INT_STATUS,
 119                         DC_HPD_SENSE_DELAYED);
 120
 121         dal_irq_service_ack_generic(irq_service, info);
 122
 123         value = dm_read_reg(irq_service->ctx, info->enable_reg);
 124
 125         set_reg_field_value(
 126                 value,
 127                 current_status ? 0 : 1,
 128                 HPD0_DC_HPD_INT_CONTROL,
 129                 DC_HPD_INT_POLARITY);
 130
 131         dm_write_reg(irq_service->ctx, info->enable_reg, value);
 132
 133         return true;
 134 }
 135
 136 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
 137         .set = NULL,
 138         .ack = hpd_ack
 139 };
 140
 141 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 142         .set = NULL,
 143         .ack = NULL
 144 };
 145
 146 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
 147         .set = NULL,
 148         .ack = NULL
 149 };
 150
 151 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 152         .set = NULL,
 153         .ack = NULL
 154 };
 155
 156 #define BASE_INNER(seg) \
 157         DCE_BASE__INST0_SEG ## seg
 158
 159 #define BASE(seg) \
 160         BASE_INNER(seg)
 161
 162 #define SRI(reg_name, block, id)\
 163         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 164                         mm ## block ## id ## _ ## reg_name
 165
 166
 167 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 168         .enable_reg = SRI(reg1, block, reg_num),\
 169         .enable_mask = \
 170                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 171         .enable_value = {\
 172                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 173                 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
 174         },\
 175         .ack_reg = SRI(reg2, block, reg_num),\
 176         .ack_mask = \
 177                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
 178         .ack_value = \
 179                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 180
 181 #define hpd_int_entry(reg_num)\
 182         [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 183                 IRQ_REG_ENTRY(HPD, reg_num,\
 184                         DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
 185                         DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
 186                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 187                 .funcs = &hpd_irq_info_funcs\
 188         }
 189
 190 #define hpd_rx_int_entry(reg_num)\
 191         [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
 192                 IRQ_REG_ENTRY(HPD, reg_num,\
 193                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
 194                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
 195                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 196                 .funcs = &hpd_rx_irq_info_funcs\
 197         }
 198 #define pflip_int_entry(reg_num)\
 199         [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
 200                 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
 201                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
 202                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
 203                 .funcs = &pflip_irq_info_funcs\
 204         }
 205
 206 #define vupdate_int_entry(reg_num)\
 207         [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
 208                 IRQ_REG_ENTRY(OTG, reg_num,\
 209                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
 210                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
 211                 .funcs = &vblank_irq_info_funcs\
 212         }
 213
 214 #define vblank_int_entry(reg_num)\
 215         [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
 216                 IRQ_REG_ENTRY(OTG, reg_num,\
 217                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
 218                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
 219                 .funcs = &vblank_irq_info_funcs\
 220         }
 221
 222 #define dummy_irq_entry() \
 223         {\
 224                 .funcs = &dummy_irq_info_funcs\
 225         }
 226
 227 #define i2c_int_entry(reg_num) \
 228         [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
 229
 230 #define dp_sink_int_entry(reg_num) \
 231         [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
 232
 233 #define gpio_pad_int_entry(reg_num) \
 234         [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
 235
 236 #define dc_underflow_int_entry(reg_num) \
 237         [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
 238
 239 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
 240         .set = dal_irq_service_dummy_set,
 241         .ack = dal_irq_service_dummy_ack
 242 };
 243
 244 static const struct irq_source_info
 245 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
 246         [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
 247         hpd_int_entry(0),
 248         hpd_int_entry(1),
 249         hpd_int_entry(2),
 250         hpd_int_entry(3),
 251         hpd_int_entry(4),
 252         hpd_int_entry(5),
 253         hpd_rx_int_entry(0),
 254         hpd_rx_int_entry(1),
 255         hpd_rx_int_entry(2),
 256         hpd_rx_int_entry(3),
 257         hpd_rx_int_entry(4),
 258         hpd_rx_int_entry(5),
 259         i2c_int_entry(1),
 260         i2c_int_entry(2),
 261         i2c_int_entry(3),
 262         i2c_int_entry(4),
 263         i2c_int_entry(5),
 264         i2c_int_entry(6),
 265         dp_sink_int_entry(1),
 266         dp_sink_int_entry(2),
 267         dp_sink_int_entry(3),
 268         dp_sink_int_entry(4),
 269         dp_sink_int_entry(5),
 270         dp_sink_int_entry(6),
 271         [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
 272         pflip_int_entry(0),
 273         pflip_int_entry(1),
 274         pflip_int_entry(2),
 275         pflip_int_entry(3),
 276         [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
 277         [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
 278         [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
 279         gpio_pad_int_entry(0),
 280         gpio_pad_int_entry(1),
 281         gpio_pad_int_entry(2),
 282         gpio_pad_int_entry(3),
 283         gpio_pad_int_entry(4),
 284         gpio_pad_int_entry(5),
 285         gpio_pad_int_entry(6),
 286         gpio_pad_int_entry(7),
 287         gpio_pad_int_entry(8),
 288         gpio_pad_int_entry(9),
 289         gpio_pad_int_entry(10),
 290         gpio_pad_int_entry(11),
 291         gpio_pad_int_entry(12),
 292         gpio_pad_int_entry(13),
 293         gpio_pad_int_entry(14),
 294         gpio_pad_int_entry(15),
 295         gpio_pad_int_entry(16),
 296         gpio_pad_int_entry(17),
 297         gpio_pad_int_entry(18),
 298         gpio_pad_int_entry(19),
 299         gpio_pad_int_entry(20),
 300         gpio_pad_int_entry(21),
 301         gpio_pad_int_entry(22),
 302         gpio_pad_int_entry(23),
 303         gpio_pad_int_entry(24),
 304         gpio_pad_int_entry(25),
 305         gpio_pad_int_entry(26),
 306         gpio_pad_int_entry(27),
 307         gpio_pad_int_entry(28),
 308         gpio_pad_int_entry(29),
 309         gpio_pad_int_entry(30),
 310         dc_underflow_int_entry(1),
 311         dc_underflow_int_entry(2),
 312         dc_underflow_int_entry(3),
 313         dc_underflow_int_entry(4),
 314         dc_underflow_int_entry(5),
 315         dc_underflow_int_entry(6),
 316         [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
 317         [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
 318         vupdate_int_entry(0),
 319         vupdate_int_entry(1),
 320         vupdate_int_entry(2),
 321         vupdate_int_entry(3),
 322         vupdate_int_entry(4),
 323         vupdate_int_entry(5),
 324         vblank_int_entry(0),
 325         vblank_int_entry(1),
 326         vblank_int_entry(2),
 327         vblank_int_entry(3),
 328         vblank_int_entry(4),
 329         vblank_int_entry(5),
 330 };
 331
 332 static const struct irq_service_funcs irq_service_funcs_dcn10 = {
 333                 .to_dal_irq_source = to_dal_irq_source_dcn10
 334 };
 335
 336 static void construct(
 337         struct irq_service *irq_service,
 338         struct irq_service_init_data *init_data)
 339 {
 340         dal_irq_service_construct(irq_service, init_data);
 341
 342         irq_service->info = irq_source_info_dcn10;
 343         irq_service->funcs = &irq_service_funcs_dcn10;
 344 }
 345
 346 struct irq_service *dal_irq_service_dcn10_create(
 347         struct irq_service_init_data *init_data)
 348 {
 349         struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
 350                                                   GFP_KERNEL);
 351
 352         if (!irq_service)
 353                 return NULL;
 354
 355         construct(irq_service, init_data);
 356         return irq_service;
 357 }