2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef _mp_9_0_SH_MASK_HEADER
22 #define _mp_9_0_SH_MASK_HEADER
25 // addressBlock: mp_SmuMp0_SmnDec
27 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
28 #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
30 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
31 #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
33 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
34 #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
36 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
37 #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
39 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
40 #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
42 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
43 #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
45 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
46 #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
48 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
49 #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
51 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
52 #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
54 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
55 #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
57 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
58 #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
60 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
61 #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
63 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
64 #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
66 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
67 #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
69 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
70 #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
72 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
73 #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
75 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
76 #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
78 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
79 #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
81 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
82 #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
84 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
85 #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
87 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
88 #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
90 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
91 #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
93 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
94 #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
96 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
97 #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
99 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
100 #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
102 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
103 #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
105 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
106 #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
108 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
109 #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
111 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
112 #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
114 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
115 #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
117 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
118 #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
120 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
121 #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
123 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
124 #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
126 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
127 #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
129 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
130 #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
132 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
133 #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
135 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
136 #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
138 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
139 #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
141 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
142 #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
144 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
145 #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
147 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
148 #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
150 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
151 #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
153 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
154 #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
156 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
157 #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
159 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
160 #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
162 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
163 #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
165 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
166 #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
168 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
169 #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
171 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
172 #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
174 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
175 #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
177 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
178 #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
180 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
181 #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
183 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
184 #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
186 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
187 #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
189 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
190 #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
192 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
193 #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
195 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
196 #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
198 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
199 #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
201 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
202 #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
204 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
205 #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
207 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
208 #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
210 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
211 #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
213 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
214 #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
216 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
217 #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
219 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
220 #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
222 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
223 #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
225 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
226 #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
228 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
229 #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
231 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
232 #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
234 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
235 #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
237 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
238 #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
240 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
241 #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
242 //MP0_SMN_ACTIVE_FCN_ID
243 #define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
244 #define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
245 #define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
246 #define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
248 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
249 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
250 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
251 #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
253 #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0
254 #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1
255 #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L
256 #define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL
257 //MP0_SMN_IH_SW_INT_CTRL
258 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
259 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
260 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
261 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
264 // addressBlock: mp_SmuMp1_SmnDec
265 //MP1_SMN_ACP2MP_RESP
266 #define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0
267 #define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
269 #define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0
270 #define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
271 //MP1_SMN_UVD2MP_RESP
272 #define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0
273 #define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
274 //MP1_SMN_VCE2MP_RESP
275 #define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0
276 #define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
277 //MP1_SMN_RLC2MP_RESP
278 #define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0
279 #define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
281 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
282 #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
284 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
285 #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
287 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
288 #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
290 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
291 #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
293 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
294 #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
296 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
297 #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
299 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
300 #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
302 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
303 #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
305 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
306 #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
308 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
309 #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
311 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
312 #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
314 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
315 #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
317 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
318 #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
320 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
321 #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
323 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
324 #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
326 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
327 #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
329 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
330 #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
332 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
333 #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
335 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
336 #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
338 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
339 #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
341 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
342 #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
344 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
345 #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
347 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
348 #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
350 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
351 #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
353 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
354 #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
356 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
357 #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
359 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
360 #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
362 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
363 #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
365 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
366 #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
368 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
369 #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
371 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
372 #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
374 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
375 #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
377 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
378 #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
380 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
381 #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
383 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
384 #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
386 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
387 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
389 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
390 #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
392 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
393 #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
395 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
396 #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
398 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
399 #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
401 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
402 #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
404 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
405 #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
407 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
408 #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
410 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
411 #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
413 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
414 #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
416 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
417 #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
419 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
420 #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
422 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
423 #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
425 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
426 #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
428 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
429 #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
431 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
432 #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
434 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
435 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
437 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
438 #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
440 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
441 #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
443 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
444 #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
446 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
447 #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
449 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
450 #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
452 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
453 #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
455 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
456 #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
458 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
459 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
461 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
462 #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
464 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
465 #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
467 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
468 #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
470 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
471 #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
473 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
474 #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
476 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
477 #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
479 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
480 #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
482 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
483 #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
485 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
486 #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
488 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
489 #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
491 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
492 #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
494 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
495 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
496 //MP1_SMN_ACTIVE_FCN_ID
497 #define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
498 #define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
499 #define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
500 #define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
502 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
503 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
504 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
505 #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
507 #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0
508 #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1
509 #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L
510 #define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL
511 //MP1_SMN_IH_SW_INT_CTRL
512 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
513 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
514 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
515 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
517 #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
518 #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
519 //MP1_SMN_EXT_SCRATCH0
520 #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
521 #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
522 //MP1_SMN_EXT_SCRATCH1
523 #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
524 #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
525 //MP1_SMN_EXT_SCRATCH2
526 #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
527 #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
528 //MP1_SMN_EXT_SCRATCH3
529 #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
530 #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
531 //MP1_SMN_EXT_SCRATCH4
532 #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
533 #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
534 //MP1_SMN_EXT_SCRATCH5
535 #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
536 #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
537 //MP1_SMN_EXT_SCRATCH6
538 #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
539 #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
540 //MP1_SMN_EXT_SCRATCH7
541 #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
542 #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
543 //MP1_SMN_EXT_SCRATCH8
544 #define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
545 #define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
550 // addressBlock: mp_SmuMp0Pub_CruDec
552 #define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0
553 #define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2
554 #define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L
555 #define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL
557 #define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0
558 #define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
560 #define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0
561 #define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
563 #define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0
564 #define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
566 #define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0
567 #define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
569 #define MP0_FW_INTF__SS_SECURE__SHIFT 0x13
570 #define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L
572 #define MP0_C2PMSG_0__CONTENT__SHIFT 0x0
573 #define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
575 #define MP0_C2PMSG_1__CONTENT__SHIFT 0x0
576 #define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
578 #define MP0_C2PMSG_2__CONTENT__SHIFT 0x0
579 #define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
581 #define MP0_C2PMSG_3__CONTENT__SHIFT 0x0
582 #define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
584 #define MP0_C2PMSG_4__CONTENT__SHIFT 0x0
585 #define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
587 #define MP0_C2PMSG_5__CONTENT__SHIFT 0x0
588 #define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
590 #define MP0_C2PMSG_6__CONTENT__SHIFT 0x0
591 #define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
593 #define MP0_C2PMSG_7__CONTENT__SHIFT 0x0
594 #define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
596 #define MP0_C2PMSG_8__CONTENT__SHIFT 0x0
597 #define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
599 #define MP0_C2PMSG_9__CONTENT__SHIFT 0x0
600 #define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
602 #define MP0_C2PMSG_10__CONTENT__SHIFT 0x0
603 #define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
605 #define MP0_C2PMSG_11__CONTENT__SHIFT 0x0
606 #define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
608 #define MP0_C2PMSG_12__CONTENT__SHIFT 0x0
609 #define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
611 #define MP0_C2PMSG_13__CONTENT__SHIFT 0x0
612 #define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
614 #define MP0_C2PMSG_14__CONTENT__SHIFT 0x0
615 #define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
617 #define MP0_C2PMSG_15__CONTENT__SHIFT 0x0
618 #define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
620 #define MP0_C2PMSG_16__CONTENT__SHIFT 0x0
621 #define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
623 #define MP0_C2PMSG_17__CONTENT__SHIFT 0x0
624 #define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
626 #define MP0_C2PMSG_18__CONTENT__SHIFT 0x0
627 #define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
629 #define MP0_C2PMSG_19__CONTENT__SHIFT 0x0
630 #define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
632 #define MP0_C2PMSG_20__CONTENT__SHIFT 0x0
633 #define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
635 #define MP0_C2PMSG_21__CONTENT__SHIFT 0x0
636 #define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
638 #define MP0_C2PMSG_22__CONTENT__SHIFT 0x0
639 #define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
641 #define MP0_C2PMSG_23__CONTENT__SHIFT 0x0
642 #define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
644 #define MP0_C2PMSG_24__CONTENT__SHIFT 0x0
645 #define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
647 #define MP0_C2PMSG_25__CONTENT__SHIFT 0x0
648 #define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
650 #define MP0_C2PMSG_26__CONTENT__SHIFT 0x0
651 #define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
653 #define MP0_C2PMSG_27__CONTENT__SHIFT 0x0
654 #define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
656 #define MP0_C2PMSG_28__CONTENT__SHIFT 0x0
657 #define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
659 #define MP0_C2PMSG_29__CONTENT__SHIFT 0x0
660 #define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
662 #define MP0_C2PMSG_30__CONTENT__SHIFT 0x0
663 #define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
665 #define MP0_C2PMSG_31__CONTENT__SHIFT 0x0
666 #define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
668 #define MP0_P2CMSG_0__CONTENT__SHIFT 0x0
669 #define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
671 #define MP0_P2CMSG_1__CONTENT__SHIFT 0x0
672 #define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
674 #define MP0_P2CMSG_2__CONTENT__SHIFT 0x0
675 #define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
677 #define MP0_P2CMSG_3__CONTENT__SHIFT 0x0
678 #define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
680 #define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0
681 #define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
683 #define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
684 #define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
685 #define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
686 #define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
687 #define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
688 #define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
689 #define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
690 #define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
692 #define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0
693 #define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL
695 #define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0
696 #define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL
698 #define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0
699 #define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL
701 #define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0
702 #define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL
704 #define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0
705 #define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL
707 #define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0
708 #define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL
710 #define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0
711 #define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL
713 #define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0
714 #define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
716 #define MP0_P2SMSG_0__CONTENT__SHIFT 0x0
717 #define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
719 #define MP0_P2SMSG_1__CONTENT__SHIFT 0x0
720 #define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
722 #define MP0_P2SMSG_2__CONTENT__SHIFT 0x0
723 #define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
725 #define MP0_P2SMSG_3__CONTENT__SHIFT 0x0
726 #define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
728 #define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0
729 #define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
731 #define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0
732 #define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L
734 #define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
735 #define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
736 #define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
737 #define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
738 #define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
739 #define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
740 #define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
741 #define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
743 #define MP0_S2PMSG_0__CONTENT__SHIFT 0x0
744 #define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
746 #define MP0_C2PMSG_32__CONTENT__SHIFT 0x0
747 #define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
749 #define MP0_C2PMSG_33__CONTENT__SHIFT 0x0
750 #define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
752 #define MP0_C2PMSG_34__CONTENT__SHIFT 0x0
753 #define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
755 #define MP0_C2PMSG_35__CONTENT__SHIFT 0x0
756 #define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
758 #define MP0_C2PMSG_36__CONTENT__SHIFT 0x0
759 #define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
761 #define MP0_C2PMSG_37__CONTENT__SHIFT 0x0
762 #define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
764 #define MP0_C2PMSG_38__CONTENT__SHIFT 0x0
765 #define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
767 #define MP0_C2PMSG_39__CONTENT__SHIFT 0x0
768 #define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
770 #define MP0_C2PMSG_40__CONTENT__SHIFT 0x0
771 #define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
773 #define MP0_C2PMSG_41__CONTENT__SHIFT 0x0
774 #define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
776 #define MP0_C2PMSG_42__CONTENT__SHIFT 0x0
777 #define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
779 #define MP0_C2PMSG_43__CONTENT__SHIFT 0x0
780 #define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
782 #define MP0_C2PMSG_44__CONTENT__SHIFT 0x0
783 #define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
785 #define MP0_C2PMSG_45__CONTENT__SHIFT 0x0
786 #define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
788 #define MP0_C2PMSG_46__CONTENT__SHIFT 0x0
789 #define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
791 #define MP0_C2PMSG_47__CONTENT__SHIFT 0x0
792 #define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
794 #define MP0_C2PMSG_48__CONTENT__SHIFT 0x0
795 #define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
797 #define MP0_C2PMSG_49__CONTENT__SHIFT 0x0
798 #define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
800 #define MP0_C2PMSG_50__CONTENT__SHIFT 0x0
801 #define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
803 #define MP0_C2PMSG_51__CONTENT__SHIFT 0x0
804 #define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
806 #define MP0_C2PMSG_52__CONTENT__SHIFT 0x0
807 #define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
809 #define MP0_C2PMSG_53__CONTENT__SHIFT 0x0
810 #define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
812 #define MP0_C2PMSG_54__CONTENT__SHIFT 0x0
813 #define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
815 #define MP0_C2PMSG_55__CONTENT__SHIFT 0x0
816 #define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
818 #define MP0_C2PMSG_56__CONTENT__SHIFT 0x0
819 #define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
821 #define MP0_C2PMSG_57__CONTENT__SHIFT 0x0
822 #define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
824 #define MP0_C2PMSG_58__CONTENT__SHIFT 0x0
825 #define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
827 #define MP0_C2PMSG_59__CONTENT__SHIFT 0x0
828 #define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
830 #define MP0_C2PMSG_60__CONTENT__SHIFT 0x0
831 #define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
833 #define MP0_C2PMSG_61__CONTENT__SHIFT 0x0
834 #define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
836 #define MP0_C2PMSG_62__CONTENT__SHIFT 0x0
837 #define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
839 #define MP0_C2PMSG_63__CONTENT__SHIFT 0x0
840 #define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
842 #define MP0_C2PMSG_64__CONTENT__SHIFT 0x0
843 #define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
845 #define MP0_C2PMSG_65__CONTENT__SHIFT 0x0
846 #define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
848 #define MP0_C2PMSG_66__CONTENT__SHIFT 0x0
849 #define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
851 #define MP0_C2PMSG_67__CONTENT__SHIFT 0x0
852 #define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
854 #define MP0_C2PMSG_68__CONTENT__SHIFT 0x0
855 #define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
857 #define MP0_C2PMSG_69__CONTENT__SHIFT 0x0
858 #define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
860 #define MP0_C2PMSG_70__CONTENT__SHIFT 0x0
861 #define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
863 #define MP0_C2PMSG_71__CONTENT__SHIFT 0x0
864 #define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
866 #define MP0_C2PMSG_72__CONTENT__SHIFT 0x0
867 #define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
869 #define MP0_C2PMSG_73__CONTENT__SHIFT 0x0
870 #define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
872 #define MP0_C2PMSG_74__CONTENT__SHIFT 0x0
873 #define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
875 #define MP0_C2PMSG_75__CONTENT__SHIFT 0x0
876 #define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
878 #define MP0_C2PMSG_76__CONTENT__SHIFT 0x0
879 #define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
881 #define MP0_C2PMSG_77__CONTENT__SHIFT 0x0
882 #define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
884 #define MP0_C2PMSG_78__CONTENT__SHIFT 0x0
885 #define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
887 #define MP0_C2PMSG_79__CONTENT__SHIFT 0x0
888 #define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
890 #define MP0_C2PMSG_80__CONTENT__SHIFT 0x0
891 #define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
893 #define MP0_C2PMSG_81__CONTENT__SHIFT 0x0
894 #define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
896 #define MP0_C2PMSG_82__CONTENT__SHIFT 0x0
897 #define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
899 #define MP0_C2PMSG_83__CONTENT__SHIFT 0x0
900 #define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
902 #define MP0_C2PMSG_84__CONTENT__SHIFT 0x0
903 #define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
905 #define MP0_C2PMSG_85__CONTENT__SHIFT 0x0
906 #define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
908 #define MP0_C2PMSG_86__CONTENT__SHIFT 0x0
909 #define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
911 #define MP0_C2PMSG_87__CONTENT__SHIFT 0x0
912 #define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
914 #define MP0_C2PMSG_88__CONTENT__SHIFT 0x0
915 #define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
917 #define MP0_C2PMSG_89__CONTENT__SHIFT 0x0
918 #define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
920 #define MP0_C2PMSG_90__CONTENT__SHIFT 0x0
921 #define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
923 #define MP0_C2PMSG_91__CONTENT__SHIFT 0x0
924 #define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
926 #define MP0_C2PMSG_92__CONTENT__SHIFT 0x0
927 #define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
929 #define MP0_C2PMSG_93__CONTENT__SHIFT 0x0
930 #define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
932 #define MP0_C2PMSG_94__CONTENT__SHIFT 0x0
933 #define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
935 #define MP0_C2PMSG_95__CONTENT__SHIFT 0x0
936 #define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
938 #define MP0_C2PMSG_96__CONTENT__SHIFT 0x0
939 #define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
941 #define MP0_C2PMSG_97__CONTENT__SHIFT 0x0
942 #define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
944 #define MP0_C2PMSG_98__CONTENT__SHIFT 0x0
945 #define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
947 #define MP0_C2PMSG_99__CONTENT__SHIFT 0x0
948 #define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
950 #define MP0_C2PMSG_100__CONTENT__SHIFT 0x0
951 #define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
953 #define MP0_C2PMSG_101__CONTENT__SHIFT 0x0
954 #define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
956 #define MP0_C2PMSG_102__CONTENT__SHIFT 0x0
957 #define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
959 #define MP0_C2PMSG_103__CONTENT__SHIFT 0x0
960 #define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
962 #define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
963 #define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
964 #define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
965 #define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
967 #define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
968 #define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10
969 #define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
970 #define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
972 #define MP0_IH_SW_INT__ID__SHIFT 0x0
973 #define MP0_IH_SW_INT__VALID__SHIFT 0x8
974 #define MP0_IH_SW_INT__ID_MASK 0x000000FFL
975 #define MP0_IH_SW_INT__VALID_MASK 0x00000100L
977 #define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
978 #define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
979 #define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
980 #define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
984 #define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
985 #define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
986 #define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc
987 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15
988 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16
989 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
990 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
991 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
992 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
993 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
994 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
995 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
996 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
997 #define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
998 #define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
999 #define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L
1000 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L
1001 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L
1002 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
1003 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
1004 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
1005 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
1006 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
1007 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
1008 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
1009 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
1010 //DRM_LIGHT_SLEEP_CTRL
1011 #define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0
1012 #define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L
1015 // addressBlock: mp_SmuMp1Pub_CruDec
1017 #define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0
1018 #define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L
1019 //MP1_FIRMWARE_FLAGS
1020 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
1021 #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
1022 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
1023 #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
1025 #define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0
1026 #define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
1028 #define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0
1029 #define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
1031 #define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0
1032 #define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
1034 #define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0
1035 #define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
1037 #define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
1038 #define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
1040 #define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
1041 #define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
1043 #define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
1044 #define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
1046 #define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
1047 #define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
1049 #define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
1050 #define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
1052 #define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
1053 #define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
1055 #define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
1056 #define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
1058 #define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
1059 #define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
1061 #define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
1062 #define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
1064 #define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
1065 #define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
1067 #define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
1068 #define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
1070 #define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
1071 #define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
1073 #define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
1074 #define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
1076 #define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
1077 #define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
1079 #define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
1080 #define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
1082 #define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
1083 #define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
1085 #define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
1086 #define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
1088 #define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
1089 #define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
1091 #define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
1092 #define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
1094 #define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
1095 #define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
1097 #define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
1098 #define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
1100 #define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
1101 #define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
1103 #define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
1104 #define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
1106 #define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
1107 #define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
1109 #define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
1110 #define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
1112 #define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
1113 #define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
1115 #define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
1116 #define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
1118 #define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
1119 #define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
1121 #define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
1122 #define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
1124 #define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
1125 #define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
1127 #define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
1128 #define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
1130 #define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
1131 #define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
1133 #define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
1134 #define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
1136 #define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
1137 #define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
1139 #define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
1140 #define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
1142 #define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
1143 #define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
1145 #define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
1146 #define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
1148 #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
1149 #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
1150 #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
1151 #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
1152 #define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
1153 #define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
1154 #define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
1155 #define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
1157 #define MP1_P2SMSG_0__CONTENT__SHIFT 0x0
1158 #define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
1160 #define MP1_P2SMSG_1__CONTENT__SHIFT 0x0
1161 #define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
1163 #define MP1_P2SMSG_2__CONTENT__SHIFT 0x0
1164 #define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
1166 #define MP1_P2SMSG_3__CONTENT__SHIFT 0x0
1167 #define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
1169 #define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
1170 #define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
1171 #define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
1172 #define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
1173 #define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
1174 #define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
1175 #define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
1176 #define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
1178 #define MP1_S2PMSG_0__CONTENT__SHIFT 0x0
1179 #define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
1181 #define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0
1182 #define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1184 #define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0
1185 #define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1187 #define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0
1188 #define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1190 #define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0
1191 #define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1193 #define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0
1194 #define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1196 #define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
1197 #define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
1199 #define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
1200 #define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
1202 #define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
1203 #define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
1205 #define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
1206 #define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
1208 #define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
1209 #define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
1211 #define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
1212 #define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
1214 #define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
1215 #define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
1217 #define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
1218 #define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
1220 #define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
1221 #define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
1223 #define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
1224 #define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
1226 #define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
1227 #define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
1229 #define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
1230 #define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
1232 #define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
1233 #define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
1235 #define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
1236 #define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
1238 #define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
1239 #define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
1241 #define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
1242 #define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
1244 #define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
1245 #define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
1247 #define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
1248 #define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
1250 #define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
1251 #define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
1253 #define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
1254 #define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
1256 #define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
1257 #define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
1259 #define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
1260 #define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
1262 #define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
1263 #define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
1265 #define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
1266 #define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
1268 #define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
1269 #define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
1271 #define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
1272 #define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
1274 #define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
1275 #define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
1277 #define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
1278 #define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
1280 #define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
1281 #define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
1283 #define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
1284 #define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
1286 #define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
1287 #define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
1289 #define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
1290 #define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
1292 #define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
1293 #define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
1295 #define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
1296 #define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
1298 #define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
1299 #define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
1301 #define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
1302 #define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
1304 #define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
1305 #define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
1307 #define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
1308 #define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
1310 #define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
1311 #define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
1313 #define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
1314 #define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
1316 #define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
1317 #define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
1319 #define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
1320 #define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
1322 #define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
1323 #define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
1325 #define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
1326 #define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
1328 #define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
1329 #define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
1331 #define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
1332 #define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
1334 #define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
1335 #define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
1337 #define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
1338 #define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
1340 #define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
1341 #define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
1343 #define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
1344 #define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
1346 #define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
1347 #define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
1349 #define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
1350 #define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
1352 #define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
1353 #define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
1355 #define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
1356 #define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
1358 #define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
1359 #define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
1361 #define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
1362 #define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
1364 #define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
1365 #define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
1367 #define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
1368 #define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
1370 #define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
1371 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
1373 #define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
1374 #define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
1376 #define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
1377 #define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
1379 #define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
1380 #define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
1382 #define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
1383 #define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
1385 #define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
1386 #define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
1388 #define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
1389 #define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
1391 #define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
1392 #define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
1394 #define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
1395 #define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
1397 #define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
1398 #define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
1400 #define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
1401 #define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
1403 #define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
1404 #define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
1406 #define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
1407 #define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
1409 #define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
1410 #define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
1412 #define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
1413 #define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
1414 #define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
1415 #define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
1417 #define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
1418 #define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
1419 #define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
1420 #define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
1422 #define MP1_IH_SW_INT__ID__SHIFT 0x0
1423 #define MP1_IH_SW_INT__VALID__SHIFT 0x8
1424 #define MP1_IH_SW_INT__ID_MASK 0x000000FFL
1425 #define MP1_IH_SW_INT__VALID_MASK 0x00000100L
1426 //MP1_IH_SW_INT_CTRL
1427 #define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
1428 #define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
1429 #define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
1430 #define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
1432 #define MP1_FPS_CNT__COUNT__SHIFT 0x0
1433 #define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
1435 #define MP1_PUB_CTRL__RESET__SHIFT 0x0
1436 #define MP1_PUB_CTRL__RESET_MASK 0x00000001L
1438 #define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0
1439 #define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
1441 #define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0
1442 #define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
1444 #define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0
1445 #define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
1447 #define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0
1448 #define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
1450 #define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0
1451 #define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
1453 #define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0
1454 #define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
1456 #define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0
1457 #define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
1459 #define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0
1460 #define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL