drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "ppatomfwctrl.h"
  25 #include "atomfirmware.h"
  26 #include "pp_debug.h"
  27
  28
  29 static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4(
  30                 const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table,
  31                 uint8_t voltage_type, uint8_t voltage_mode)
  32 {
  33         unsigned int size = le16_to_cpu(
  34                         voltage_object_info_table->table_header.structuresize);
  35         unsigned int offset =
  36                         offsetof(struct atom_voltage_objects_info_v4_1, voltage_object[0]);
  37         unsigned long start = (unsigned long)voltage_object_info_table;
  38
  39         while (offset < size) {
  40                 const union atom_voltage_object_v4 *voltage_object =
  41                                 (const union atom_voltage_object_v4 *)(start + offset);
  42
  43         if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&
  44             voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)
  45             return voltage_object;
  46
  47         offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
  48
  49     }
  50
  51     return NULL;
  52 }
  53
  54 static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table(
  55                 struct pp_hwmgr *hwmgr)
  56 {
  57     const void *table_address;
  58     uint16_t idx;
  59
  60     idx = GetIndexIntoMasterDataTable(voltageobject_info);
  61     table_address =     cgs_atom_get_data_table(hwmgr->device,
  62                 idx, NULL, NULL, NULL);
  63
  64     PP_ASSERT_WITH_CODE(
  65         table_address,
  66         "Error retrieving BIOS Table Address!",
  67         return NULL);
  68
  69     return (struct atom_voltage_objects_info_v4_1 *)table_address;
  70 }
  71
  72 /**
  73 * Returns TRUE if the given voltage type is controlled by GPIO pins.
  74 * voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC, SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
  75 * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
  76 */
  77 bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
  78                 uint8_t voltage_type, uint8_t voltage_mode)
  79 {
  80         struct atom_voltage_objects_info_v4_1 *voltage_info =
  81                         (struct atom_voltage_objects_info_v4_1 *)
  82                         pp_atomfwctrl_get_voltage_info_table(hwmgr);
  83         bool ret;
  84
  85         /* If we cannot find the table do NOT try to control this voltage. */
  86         PP_ASSERT_WITH_CODE(voltage_info,
  87                         "Could not find Voltage Table in BIOS.",
  88                         return false);
  89
  90         ret = (pp_atomfwctrl_lookup_voltage_type_v4(voltage_info,
  91                         voltage_type, voltage_mode)) ? true : false;
  92
  93         return ret;
  94 }
  95
  96 int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr,
  97                 uint8_t voltage_type, uint8_t voltage_mode,
  98                 struct pp_atomfwctrl_voltage_table *voltage_table)
  99 {
 100         struct atom_voltage_objects_info_v4_1 *voltage_info =
 101                         (struct atom_voltage_objects_info_v4_1 *)
 102                         pp_atomfwctrl_get_voltage_info_table(hwmgr);
 103         const union atom_voltage_object_v4 *voltage_object;
 104         unsigned int i;
 105         int result = 0;
 106
 107         PP_ASSERT_WITH_CODE(voltage_info,
 108                         "Could not find Voltage Table in BIOS.",
 109                         return -1);
 110
 111         voltage_object = pp_atomfwctrl_lookup_voltage_type_v4(voltage_info,
 112                         voltage_type, voltage_mode);
 113
 114         if (!voltage_object)
 115                 return -1;
 116
 117         voltage_table->count = 0;
 118         if (voltage_mode == VOLTAGE_OBJ_GPIO_LUT) {
 119                 PP_ASSERT_WITH_CODE(
 120                                 (voltage_object->gpio_voltage_obj.gpio_entry_num <=
 121                                 PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES),
 122                                 "Too many voltage entries!",
 123                                 result = -1);
 124
 125                 if (!result) {
 126                         for (i = 0; i < voltage_object->gpio_voltage_obj.
 127                                                         gpio_entry_num; i++) {
 128                                 voltage_table->entries[i].value =
 129                                                 le16_to_cpu(voltage_object->gpio_voltage_obj.
 130                                                 voltage_gpio_lut[i].voltage_level_mv);
 131                                 voltage_table->entries[i].smio_low =
 132                                                 le32_to_cpu(voltage_object->gpio_voltage_obj.
 133                                                 voltage_gpio_lut[i].voltage_gpio_reg_val);
 134                         }
 135                         voltage_table->count =
 136                                         voltage_object->gpio_voltage_obj.gpio_entry_num;
 137                         voltage_table->mask_low =
 138                                         le32_to_cpu(
 139                                         voltage_object->gpio_voltage_obj.gpio_mask_val);
 140                         voltage_table->phase_delay =
 141                                         voltage_object->gpio_voltage_obj.phase_delay_us;
 142                 }
 143         } else if (voltage_mode == VOLTAGE_OBJ_SVID2) {
 144                 voltage_table->psi1_enable =
 145                         (voltage_object->svid2_voltage_obj.loadline_psi1 & 0x20) >> 5;
 146                 voltage_table->psi0_enable =
 147                         voltage_object->svid2_voltage_obj.psi0_enable & 0x1;
 148                 voltage_table->max_vid_step =
 149                         voltage_object->svid2_voltage_obj.maxvstep;
 150                 voltage_table->telemetry_offset =
 151                         voltage_object->svid2_voltage_obj.telemetry_offset;
 152                 voltage_table->telemetry_slope =
 153                         voltage_object->svid2_voltage_obj.telemetry_gain;
 154         } else
 155                 PP_ASSERT_WITH_CODE(false,
 156                                 "Unsupported Voltage Object Mode!",
 157                                 result = -1);
 158
 159         return result;
 160 }
 161
 162
 163 static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table(
 164                 struct pp_hwmgr *hwmgr)
 165 {
 166         const void *table_address;
 167         uint16_t idx;
 168
 169         idx = GetIndexIntoMasterDataTable(gpio_pin_lut);
 170         table_address = cgs_atom_get_data_table(hwmgr->device,
 171                         idx, NULL, NULL, NULL);
 172         PP_ASSERT_WITH_CODE(table_address,
 173                         "Error retrieving BIOS Table Address!",
 174                         return NULL);
 175
 176         return (struct atom_gpio_pin_lut_v2_1 *)table_address;
 177 }
 178
 179 static bool pp_atomfwctrl_lookup_gpio_pin(
 180                 struct atom_gpio_pin_lut_v2_1 *gpio_lookup_table,
 181                 const uint32_t pin_id,
 182                 struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment)
 183 {
 184         unsigned int size = le16_to_cpu(
 185                         gpio_lookup_table->table_header.structuresize);
 186         unsigned int offset =
 187                         offsetof(struct atom_gpio_pin_lut_v2_1, gpio_pin[0]);
 188         unsigned long start = (unsigned long)gpio_lookup_table;
 189
 190         while (offset < size) {
 191                 const struct  atom_gpio_pin_assignment *pin_assignment =
 192                                 (const struct  atom_gpio_pin_assignment *)(start + offset);
 193
 194                 if (pin_id == pin_assignment->gpio_id)  {
 195                         gpio_pin_assignment->uc_gpio_pin_bit_shift =
 196                                         pin_assignment->gpio_bitshift;
 197                         gpio_pin_assignment->us_gpio_pin_aindex =
 198                                         le16_to_cpu(pin_assignment->data_a_reg_index);
 199                         return true;
 200                 }
 201                 offset += offsetof(struct atom_gpio_pin_assignment, gpio_id) + 1;
 202         }
 203         return false;
 204 }
 205
 206 /**
 207 * Returns TRUE if the given pin id find in lookup table.
 208 */
 209 bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr,
 210                 const uint32_t pin_id,
 211                 struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment)
 212 {
 213         bool ret = false;
 214         struct atom_gpio_pin_lut_v2_1 *gpio_lookup_table =
 215                         pp_atomfwctrl_get_gpio_lookup_table(hwmgr);
 216
 217         /* If we cannot find the table do NOT try to control this voltage. */
 218         PP_ASSERT_WITH_CODE(gpio_lookup_table,
 219                         "Could not find GPIO lookup Table in BIOS.",
 220                         return false);
 221
 222         ret = pp_atomfwctrl_lookup_gpio_pin(gpio_lookup_table,
 223                         pin_id, gpio_pin_assignment);
 224
 225         return ret;
 226 }
 227
 228 /**
 229 * Enter to SelfRefresh mode.
 230 * @param hwmgr
 231 */
 232 int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr)
 233 {
 234         /* 0 - no action
 235          * 1 - leave power to video memory always on
 236          */
 237         return 0;
 238 }
 239
 240 /** pp_atomfwctrl_get_gpu_pll_dividers_vega10().
 241  *
 242  * @param hwmgr       input parameter: pointer to HwMgr
 243  * @param clock_type  input parameter: Clock type: 1 - GFXCLK, 2 - UCLK, 0 - All other clocks
 244  * @param clock_value input parameter: Clock
 245  * @param dividers    output parameter:Clock dividers
 246  */
 247 int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
 248                 uint32_t clock_type, uint32_t clock_value,
 249                 struct pp_atomfwctrl_clock_dividers_soc15 *dividers)
 250 {
 251         struct compute_gpu_clock_input_parameter_v1_8 pll_parameters;
 252         struct compute_gpu_clock_output_parameter_v1_8 *pll_output;
 253         int result;
 254         uint32_t idx;
 255
 256         pll_parameters.gpuclock_10khz = (uint32_t)clock_value;
 257         pll_parameters.gpu_clock_type = clock_type;
 258
 259         idx = GetIndexIntoMasterCmdTable(computegpuclockparam);
 260         result = cgs_atom_exec_cmd_table(hwmgr->device, idx, &pll_parameters);
 261
 262         if (!result) {
 263                 pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)
 264                                 &pll_parameters;
 265                 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
 266                 dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
 267                 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
 268                 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
 269                 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
 270                 dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
 271         }
 272         return result;
 273 }
 274
 275 int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
 276                 struct pp_atomfwctrl_avfs_parameters *param)
 277 {
 278         uint16_t idx;
 279         uint8_t format_revision, content_revision;
 280
 281         struct atom_asic_profiling_info_v4_1 *profile;
 282         struct atom_asic_profiling_info_v4_2 *profile_v4_2;
 283
 284         idx = GetIndexIntoMasterDataTable(asic_profiling_info);
 285         profile = (struct atom_asic_profiling_info_v4_1 *)
 286                         cgs_atom_get_data_table(hwmgr->device,
 287                                         idx, NULL, NULL, NULL);
 288
 289         if (!profile)
 290                 return -1;
 291
 292         format_revision = ((struct atom_common_table_header *)profile)->format_revision;
 293         content_revision = ((struct atom_common_table_header *)profile)->content_revision;
 294
 295         if (format_revision == 4 && content_revision == 1) {
 296                 param->ulMaxVddc = le32_to_cpu(profile->maxvddc);
 297                 param->ulMinVddc = le32_to_cpu(profile->minvddc);
 298                 param->ulMeanNsigmaAcontant0 =
 299                                 le32_to_cpu(profile->avfs_meannsigma_acontant0);
 300                 param->ulMeanNsigmaAcontant1 =
 301                                 le32_to_cpu(profile->avfs_meannsigma_acontant1);
 302                 param->ulMeanNsigmaAcontant2 =
 303                                 le32_to_cpu(profile->avfs_meannsigma_acontant2);
 304                 param->usMeanNsigmaDcTolSigma =
 305                                 le16_to_cpu(profile->avfs_meannsigma_dc_tol_sigma);
 306                 param->usMeanNsigmaPlatformMean =
 307                                 le16_to_cpu(profile->avfs_meannsigma_platform_mean);
 308                 param->usMeanNsigmaPlatformSigma =
 309                                 le16_to_cpu(profile->avfs_meannsigma_platform_sigma);
 310                 param->ulGbVdroopTableCksoffA0 =
 311                                 le32_to_cpu(profile->gb_vdroop_table_cksoff_a0);
 312                 param->ulGbVdroopTableCksoffA1 =
 313                                 le32_to_cpu(profile->gb_vdroop_table_cksoff_a1);
 314                 param->ulGbVdroopTableCksoffA2 =
 315                                 le32_to_cpu(profile->gb_vdroop_table_cksoff_a2);
 316                 param->ulGbVdroopTableCksonA0 =
 317                                 le32_to_cpu(profile->gb_vdroop_table_ckson_a0);
 318                 param->ulGbVdroopTableCksonA1 =
 319                                 le32_to_cpu(profile->gb_vdroop_table_ckson_a1);
 320                 param->ulGbVdroopTableCksonA2 =
 321                                 le32_to_cpu(profile->gb_vdroop_table_ckson_a2);
 322                 param->ulGbFuseTableCksoffM1 =
 323                                 le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m1);
 324                 param->ulGbFuseTableCksoffM2 =
 325                                 le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m2);
 326                 param->ulGbFuseTableCksoffB =
 327                                 le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b);
 328                 param->ulGbFuseTableCksonM1 =
 329                                 le32_to_cpu(profile->avfsgb_fuse_table_ckson_m1);
 330                 param->ulGbFuseTableCksonM2 =
 331                                 le32_to_cpu(profile->avfsgb_fuse_table_ckson_m2);
 332                 param->ulGbFuseTableCksonB =
 333                                 le32_to_cpu(profile->avfsgb_fuse_table_ckson_b);
 334
 335                 param->ucEnableGbVdroopTableCkson =
 336                                 profile->enable_gb_vdroop_table_ckson;
 337                 param->ucEnableGbFuseTableCkson =
 338                                 profile->enable_gb_fuse_table_ckson;
 339                 param->usPsmAgeComfactor =
 340                                 le16_to_cpu(profile->psm_age_comfactor);
 341
 342                 param->ulDispclk2GfxclkM1 =
 343                                 le32_to_cpu(profile->dispclk2gfxclk_a);
 344                 param->ulDispclk2GfxclkM2 =
 345                                 le32_to_cpu(profile->dispclk2gfxclk_b);
 346                 param->ulDispclk2GfxclkB =
 347                                 le32_to_cpu(profile->dispclk2gfxclk_c);
 348                 param->ulDcefclk2GfxclkM1 =
 349                                 le32_to_cpu(profile->dcefclk2gfxclk_a);
 350                 param->ulDcefclk2GfxclkM2 =
 351                                 le32_to_cpu(profile->dcefclk2gfxclk_b);
 352                 param->ulDcefclk2GfxclkB =
 353                                 le32_to_cpu(profile->dcefclk2gfxclk_c);
 354                 param->ulPixelclk2GfxclkM1 =
 355                                 le32_to_cpu(profile->pixclk2gfxclk_a);
 356                 param->ulPixelclk2GfxclkM2 =
 357                                 le32_to_cpu(profile->pixclk2gfxclk_b);
 358                 param->ulPixelclk2GfxclkB =
 359                                 le32_to_cpu(profile->pixclk2gfxclk_c);
 360                 param->ulPhyclk2GfxclkM1 =
 361                                 le32_to_cpu(profile->phyclk2gfxclk_a);
 362                 param->ulPhyclk2GfxclkM2 =
 363                                 le32_to_cpu(profile->phyclk2gfxclk_b);
 364                 param->ulPhyclk2GfxclkB =
 365                                 le32_to_cpu(profile->phyclk2gfxclk_c);
 366                 param->ulAcgGbVdroopTableA0           = 0;
 367                 param->ulAcgGbVdroopTableA1           = 0;
 368                 param->ulAcgGbVdroopTableA2           = 0;
 369                 param->ulAcgGbFuseTableM1             = 0;
 370                 param->ulAcgGbFuseTableM2             = 0;
 371                 param->ulAcgGbFuseTableB              = 0;
 372                 param->ucAcgEnableGbVdroopTable       = 0;
 373                 param->ucAcgEnableGbFuseTable         = 0;
 374         } else if (format_revision == 4 && content_revision == 2) {
 375                 profile_v4_2 = (struct atom_asic_profiling_info_v4_2 *)profile;
 376                 param->ulMaxVddc = le32_to_cpu(profile_v4_2->maxvddc);
 377                 param->ulMinVddc = le32_to_cpu(profile_v4_2->minvddc);
 378                 param->ulMeanNsigmaAcontant0 =
 379                                 le32_to_cpu(profile_v4_2->avfs_meannsigma_acontant0);
 380                 param->ulMeanNsigmaAcontant1 =
 381                                 le32_to_cpu(profile_v4_2->avfs_meannsigma_acontant1);
 382                 param->ulMeanNsigmaAcontant2 =
 383                                 le32_to_cpu(profile_v4_2->avfs_meannsigma_acontant2);
 384                 param->usMeanNsigmaDcTolSigma =
 385                                 le16_to_cpu(profile_v4_2->avfs_meannsigma_dc_tol_sigma);
 386                 param->usMeanNsigmaPlatformMean =
 387                                 le16_to_cpu(profile_v4_2->avfs_meannsigma_platform_mean);
 388                 param->usMeanNsigmaPlatformSigma =
 389                                 le16_to_cpu(profile_v4_2->avfs_meannsigma_platform_sigma);
 390                 param->ulGbVdroopTableCksoffA0 =
 391                                 le32_to_cpu(profile_v4_2->gb_vdroop_table_cksoff_a0);
 392                 param->ulGbVdroopTableCksoffA1 =
 393                                 le32_to_cpu(profile_v4_2->gb_vdroop_table_cksoff_a1);
 394                 param->ulGbVdroopTableCksoffA2 =
 395                                 le32_to_cpu(profile_v4_2->gb_vdroop_table_cksoff_a2);
 396                 param->ulGbVdroopTableCksonA0 =
 397                                 le32_to_cpu(profile_v4_2->gb_vdroop_table_ckson_a0);
 398                 param->ulGbVdroopTableCksonA1 =
 399                                 le32_to_cpu(profile_v4_2->gb_vdroop_table_ckson_a1);
 400                 param->ulGbVdroopTableCksonA2 =
 401                                 le32_to_cpu(profile_v4_2->gb_vdroop_table_ckson_a2);
 402                 param->ulGbFuseTableCksoffM1 =
 403                                 le32_to_cpu(profile_v4_2->avfsgb_fuse_table_cksoff_m1);
 404                 param->ulGbFuseTableCksoffM2 =
 405                                 le32_to_cpu(profile_v4_2->avfsgb_fuse_table_cksoff_m2);
 406                 param->ulGbFuseTableCksoffB =
 407                                 le32_to_cpu(profile_v4_2->avfsgb_fuse_table_cksoff_b);
 408                 param->ulGbFuseTableCksonM1 =
 409                                 le32_to_cpu(profile_v4_2->avfsgb_fuse_table_ckson_m1);
 410                 param->ulGbFuseTableCksonM2 =
 411                                 le32_to_cpu(profile_v4_2->avfsgb_fuse_table_ckson_m2);
 412                 param->ulGbFuseTableCksonB =
 413                                 le32_to_cpu(profile_v4_2->avfsgb_fuse_table_ckson_b);
 414
 415                 param->ucEnableGbVdroopTableCkson =
 416                                 profile_v4_2->enable_gb_vdroop_table_ckson;
 417                 param->ucEnableGbFuseTableCkson =
 418                                 profile_v4_2->enable_gb_fuse_table_ckson;
 419                 param->usPsmAgeComfactor =
 420                                 le16_to_cpu(profile_v4_2->psm_age_comfactor);
 421
 422                 param->ulDispclk2GfxclkM1 =
 423                                 le32_to_cpu(profile_v4_2->dispclk2gfxclk_a);
 424                 param->ulDispclk2GfxclkM2 =
 425                                 le32_to_cpu(profile_v4_2->dispclk2gfxclk_b);
 426                 param->ulDispclk2GfxclkB =
 427                                 le32_to_cpu(profile_v4_2->dispclk2gfxclk_c);
 428                 param->ulDcefclk2GfxclkM1 =
 429                                 le32_to_cpu(profile_v4_2->dcefclk2gfxclk_a);
 430                 param->ulDcefclk2GfxclkM2 =
 431                                 le32_to_cpu(profile_v4_2->dcefclk2gfxclk_b);
 432                 param->ulDcefclk2GfxclkB =
 433                                 le32_to_cpu(profile_v4_2->dcefclk2gfxclk_c);
 434                 param->ulPixelclk2GfxclkM1 =
 435                                 le32_to_cpu(profile_v4_2->pixclk2gfxclk_a);
 436                 param->ulPixelclk2GfxclkM2 =
 437                                 le32_to_cpu(profile_v4_2->pixclk2gfxclk_b);
 438                 param->ulPixelclk2GfxclkB =
 439                                 le32_to_cpu(profile_v4_2->pixclk2gfxclk_c);
 440                 param->ulPhyclk2GfxclkM1 =
 441                                 le32_to_cpu(profile->phyclk2gfxclk_a);
 442                 param->ulPhyclk2GfxclkM2 =
 443                                 le32_to_cpu(profile_v4_2->phyclk2gfxclk_b);
 444                 param->ulPhyclk2GfxclkB =
 445                                 le32_to_cpu(profile_v4_2->phyclk2gfxclk_c);
 446                 param->ulAcgGbVdroopTableA0 = le32_to_cpu(profile_v4_2->acg_gb_vdroop_table_a0);
 447                 param->ulAcgGbVdroopTableA1 = le32_to_cpu(profile_v4_2->acg_gb_vdroop_table_a1);
 448                 param->ulAcgGbVdroopTableA2 = le32_to_cpu(profile_v4_2->acg_gb_vdroop_table_a2);
 449                 param->ulAcgGbFuseTableM1 = le32_to_cpu(profile_v4_2->acg_avfsgb_fuse_table_m1);
 450                 param->ulAcgGbFuseTableM2 = le32_to_cpu(profile_v4_2->acg_avfsgb_fuse_table_m2);
 451                 param->ulAcgGbFuseTableB = le32_to_cpu(profile_v4_2->acg_avfsgb_fuse_table_b);
 452                 param->ucAcgEnableGbVdroopTable = le32_to_cpu(profile_v4_2->enable_acg_gb_vdroop_table);
 453                 param->ucAcgEnableGbFuseTable = le32_to_cpu(profile_v4_2->enable_acg_gb_fuse_table);
 454         } else {
 455                 pr_info("Invalid VBIOS AVFS ProfilingInfo Revision!\n");
 456                 return -EINVAL;
 457         }
 458
 459         return 0;
 460 }
 461
 462 int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
 463                 struct pp_atomfwctrl_gpio_parameters *param)
 464 {
 465         struct atom_smu_info_v3_1 *info;
 466         uint16_t idx;
 467
 468         idx = GetIndexIntoMasterDataTable(smu_info);
 469         info = (struct atom_smu_info_v3_1 *)
 470                 cgs_atom_get_data_table(hwmgr->device,
 471                                 idx, NULL, NULL, NULL);
 472
 473         if (!info) {
 474                 pr_info("Error retrieving BIOS smu_info Table Address!");
 475                 return -1;
 476         }
 477
 478         param->ucAcDcGpio       = info->ac_dc_gpio_bit;
 479         param->ucAcDcPolarity   = info->ac_dc_polarity;
 480         param->ucVR0HotGpio     = info->vr0hot_gpio_bit;
 481         param->ucVR0HotPolarity = info->vr0hot_polarity;
 482         param->ucVR1HotGpio     = info->vr1hot_gpio_bit;
 483         param->ucVR1HotPolarity = info->vr1hot_polarity;
 484         param->ucFwCtfGpio      = info->fw_ctf_gpio_bit;
 485         param->ucFwCtfPolarity  = info->fw_ctf_polarity;
 486
 487         return 0;
 488 }
 489
 490 int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency)
 491 {
 492         struct atom_get_smu_clock_info_parameters_v3_1   parameters;
 493         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 494         uint32_t ix;
 495
 496         parameters.clk_id = id;
 497         parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 498
 499         ix = GetIndexIntoMasterCmdTable(getsmuclockinfo);
 500         if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, &parameters)) {
 501                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters;
 502                 *frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
 503         } else {
 504                 pr_info("Error execute_table getsmuclockinfo!");
 505                 return -1;
 506         }
 507
 508         return 0;
 509 }
 510
 511 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
 512                         struct pp_atomfwctrl_bios_boot_up_values *boot_values)
 513 {
 514         struct atom_firmware_info_v3_1 *info = NULL;
 515         uint16_t ix;
 516         uint32_t frequency = 0;
 517
 518         ix = GetIndexIntoMasterDataTable(firmwareinfo);
 519         info = (struct atom_firmware_info_v3_1 *)
 520                 cgs_atom_get_data_table(hwmgr->device,
 521                                 ix, NULL, NULL, NULL);
 522
 523         if (!info) {
 524                 pr_info("Error retrieving BIOS firmwareinfo!");
 525                 return -EINVAL;
 526         }
 527
 528         boot_values->ulRevision = info->firmware_revision;
 529         boot_values->ulGfxClk   = info->bootup_sclk_in10khz;
 530         boot_values->ulUClk     = info->bootup_mclk_in10khz;
 531         boot_values->usVddc     = info->bootup_vddc_mv;
 532         boot_values->usVddci    = info->bootup_vddci_mv;
 533         boot_values->usMvddc    = info->bootup_mvddc_mv;
 534         boot_values->usVddGfx   = info->bootup_vddgfx_mv;
 535         boot_values->ulSocClk   = 0;
 536         boot_values->ulDCEFClk   = 0;
 537
 538         if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency))
 539                 boot_values->ulSocClk   = frequency;
 540
 541         if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency))
 542                 boot_values->ulDCEFClk   = frequency;
 543
 544         return 0;
 545 }