2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef PP_ATOMFWCTRL_H
25 #define PP_ATOMFWCTRL_H
29 typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
31 #define GetIndexIntoMasterCmdTable(FieldName) \
32 (((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
33 #define GetIndexIntoMasterDataTable(FieldName) \
34 (((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
36 #define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
38 struct pp_atomfwctrl_voltage_table_entry {
43 struct pp_atomfwctrl_voltage_table {
50 uint8_t telemetry_offset;
51 uint8_t telemetry_slope;
52 struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
55 struct pp_atomfwctrl_gpio_pin_assignment {
56 uint16_t us_gpio_pin_aindex;
57 uint8_t uc_gpio_pin_bit_shift;
60 struct pp_atomfwctrl_clock_dividers_soc15 {
61 uint32_t ulClock; /* the actual clock */
62 uint32_t ulDid; /* DFS divider */
63 uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
64 uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
65 uint16_t usPll_ss_slew_frac;
66 uint8_t ucPll_ss_enable;
68 uint32_t ulReserve[2];
71 struct pp_atomfwctrl_avfs_parameters {
75 uint32_t ulMeanNsigmaAcontant0;
76 uint32_t ulMeanNsigmaAcontant1;
77 uint32_t ulMeanNsigmaAcontant2;
78 uint16_t usMeanNsigmaDcTolSigma;
79 uint16_t usMeanNsigmaPlatformMean;
80 uint16_t usMeanNsigmaPlatformSigma;
81 uint32_t ulGbVdroopTableCksoffA0;
82 uint32_t ulGbVdroopTableCksoffA1;
83 uint32_t ulGbVdroopTableCksoffA2;
84 uint32_t ulGbVdroopTableCksonA0;
85 uint32_t ulGbVdroopTableCksonA1;
86 uint32_t ulGbVdroopTableCksonA2;
88 uint32_t ulGbFuseTableCksoffM1;
89 uint32_t ulGbFuseTableCksoffM2;
90 uint32_t ulGbFuseTableCksoffB;
92 uint32_t ulGbFuseTableCksonM1;
93 uint32_t ulGbFuseTableCksonM2;
94 uint32_t ulGbFuseTableCksonB;
96 uint8_t ucEnableGbVdroopTableCkson;
97 uint8_t ucEnableGbFuseTableCkson;
98 uint16_t usPsmAgeComfactor;
100 uint32_t ulDispclk2GfxclkM1;
101 uint32_t ulDispclk2GfxclkM2;
102 uint32_t ulDispclk2GfxclkB;
103 uint32_t ulDcefclk2GfxclkM1;
104 uint32_t ulDcefclk2GfxclkM2;
105 uint32_t ulDcefclk2GfxclkB;
106 uint32_t ulPixelclk2GfxclkM1;
107 uint32_t ulPixelclk2GfxclkM2;
108 uint32_t ulPixelclk2GfxclkB;
109 uint32_t ulPhyclk2GfxclkM1;
110 uint32_t ulPhyclk2GfxclkM2;
111 uint32_t ulPhyclk2GfxclkB;
112 uint32_t ulAcgGbVdroopTableA0;
113 uint32_t ulAcgGbVdroopTableA1;
114 uint32_t ulAcgGbVdroopTableA2;
115 uint32_t ulAcgGbFuseTableM1;
116 uint32_t ulAcgGbFuseTableM2;
117 uint32_t ulAcgGbFuseTableB;
118 uint32_t ucAcgEnableGbVdroopTable;
119 uint32_t ucAcgEnableGbFuseTable;
122 struct pp_atomfwctrl_gpio_parameters {
124 uint8_t ucAcDcPolarity;
125 uint8_t ucVR0HotGpio;
126 uint8_t ucVR0HotPolarity;
127 uint8_t ucVR1HotGpio;
128 uint8_t ucVR1HotPolarity;
130 uint8_t ucFwCtfPolarity;
133 struct pp_atomfwctrl_bios_boot_up_values {
145 int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
146 uint32_t clock_type, uint32_t clock_value,
147 struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
148 int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
149 bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
150 struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
152 int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
153 uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
154 bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
155 uint8_t voltage_type, uint8_t voltage_mode);
157 int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
158 struct pp_atomfwctrl_avfs_parameters *param);
159 int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
160 struct pp_atomfwctrl_gpio_parameters *param);
162 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
163 struct pp_atomfwctrl_bios_boot_up_values *boot_values);