drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "vega10_thermal.h"
  25 #include "vega10_hwmgr.h"
  26 #include "vega10_smumgr.h"
  27 #include "vega10_ppsmc.h"
  28 #include "vega10_inc.h"
  29 #include "pp_soc15.h"
  30 #include "pp_debug.h"
  31
  32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
  33 {
  34         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
  35                                 PPSMC_MSG_GetCurrentRpm),
  36                         "Attempt to get current RPM from SMC Failed!",
  37                         return -1);
  38         PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
  39                         current_rpm),
  40                         "Attempt to read current RPM from SMC Failed!",
  41                         return -1);
  42         return 0;
  43 }
  44
  45 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
  46                 struct phm_fan_speed_info *fan_speed_info)
  47 {
  48
  49         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  50                 return 0;
  51
  52         fan_speed_info->supports_percent_read = true;
  53         fan_speed_info->supports_percent_write = true;
  54         fan_speed_info->min_percent = 0;
  55         fan_speed_info->max_percent = 100;
  56
  57         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  58                         PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
  59                 hwmgr->thermal_controller.fanInfo.
  60                 ucTachometerPulsesPerRevolution) {
  61                 fan_speed_info->supports_rpm_read = true;
  62                 fan_speed_info->supports_rpm_write = true;
  63                 fan_speed_info->min_rpm =
  64                                 hwmgr->thermal_controller.fanInfo.ulMinRPM;
  65                 fan_speed_info->max_rpm =
  66                                 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
  67         } else {
  68                 fan_speed_info->min_rpm = 0;
  69                 fan_speed_info->max_rpm = 0;
  70         }
  71
  72         return 0;
  73 }
  74
  75 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
  76                 uint32_t *speed)
  77 {
  78         uint32_t current_rpm;
  79         uint32_t percent = 0;
  80
  81         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  82                 return 0;
  83
  84         if (vega10_get_current_rpm(hwmgr, &current_rpm))
  85                 return -1;
  86
  87         if (hwmgr->thermal_controller.
  88                         advanceFanControlParameters.usMaxFanRPM != 0)
  89                 percent = current_rpm * 100 /
  90                         hwmgr->thermal_controller.
  91                         advanceFanControlParameters.usMaxFanRPM;
  92
  93         *speed = percent > 100 ? 100 : percent;
  94
  95         return 0;
  96 }
  97
  98 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
  99 {
 100         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 101         uint32_t tach_period;
 102         uint32_t crystal_clock_freq;
 103         int result = 0;
 104
 105         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 106                 return -1;
 107
 108         if (data->smu_features[GNLD_FAN_CONTROL].supported)
 109                 result = vega10_get_current_rpm(hwmgr, speed);
 110         else {
 111                 uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
 112                                 mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
 113                 tach_period = (cgs_read_register(hwmgr->device,
 114                                 reg) & CG_TACH_STATUS__TACH_PERIOD_MASK) >>
 115                                 CG_TACH_STATUS__TACH_PERIOD__SHIFT;
 116
 117                 if (tach_period == 0)
 118                         return -EINVAL;
 119
 120                 crystal_clock_freq = smu7_get_xclk(hwmgr);
 121
 122                 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
 123         }
 124
 125         return result;
 126 }
 127
 128 /**
 129 * Set Fan Speed Control to static mode,
 130 * so that the user can decide what speed to use.
 131 * @param    hwmgr  the address of the powerplay hardware manager.
 132 *           mode the fan control mode, 0 default, 1 by percent, 5, by RPM
 133 * @exception Should always succeed.
 134 */
 135 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 136 {
 137         uint32_t reg;
 138
 139         reg = soc15_get_register_offset(THM_HWID, 0,
 140                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 141
 142         if (hwmgr->fan_ctrl_is_in_default_mode) {
 143                 hwmgr->fan_ctrl_default_mode =
 144                                 (cgs_read_register(hwmgr->device, reg) &
 145                                 CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
 146                                 CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
 147                 hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
 148                                 CG_FDO_CTRL2__TMIN_MASK) >>
 149                                 CG_FDO_CTRL2__TMIN__SHIFT;
 150                 hwmgr->fan_ctrl_is_in_default_mode = false;
 151         }
 152
 153         cgs_write_register(hwmgr->device, reg,
 154                         (cgs_read_register(hwmgr->device, reg) &
 155                         ~CG_FDO_CTRL2__TMIN_MASK) |
 156                         (0 << CG_FDO_CTRL2__TMIN__SHIFT));
 157         cgs_write_register(hwmgr->device, reg,
 158                         (cgs_read_register(hwmgr->device, reg) &
 159                         ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
 160                         (mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
 161
 162         return 0;
 163 }
 164
 165 /**
 166 * Reset Fan Speed Control to default mode.
 167 * @param    hwmgr  the address of the powerplay hardware manager.
 168 * @exception Should always succeed.
 169 */
 170 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
 171 {
 172         uint32_t reg;
 173
 174         reg = soc15_get_register_offset(THM_HWID, 0,
 175                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 176
 177         if (!hwmgr->fan_ctrl_is_in_default_mode) {
 178                 cgs_write_register(hwmgr->device, reg,
 179                                 (cgs_read_register(hwmgr->device, reg) &
 180                                 ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
 181                                 (hwmgr->fan_ctrl_default_mode <<
 182                                 CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
 183                 cgs_write_register(hwmgr->device, reg,
 184                                 (cgs_read_register(hwmgr->device, reg) &
 185                                 ~CG_FDO_CTRL2__TMIN_MASK) |
 186                                 (hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
 187                 hwmgr->fan_ctrl_is_in_default_mode = true;
 188         }
 189
 190         return 0;
 191 }
 192
 193 /**
 194  * @fn vega10_enable_fan_control_feature
 195  * @brief Enables the SMC Fan Control Feature.
 196  *
 197  * @param    hwmgr - the address of the powerplay hardware manager.
 198  * @return   0 on success. -1 otherwise.
 199  */
 200 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
 201 {
 202         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 203
 204         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 205                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 206                                 hwmgr->smumgr, true,
 207                                 data->smu_features[GNLD_FAN_CONTROL].
 208                                 smu_feature_bitmap),
 209                                 "Attempt to Enable FAN CONTROL feature Failed!",
 210                                 return -1);
 211                 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
 218 {
 219         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 220
 221         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 222                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 223                                 hwmgr->smumgr, false,
 224                                 data->smu_features[GNLD_FAN_CONTROL].
 225                                 smu_feature_bitmap),
 226                                 "Attempt to Enable FAN CONTROL feature Failed!",
 227                                 return -1);
 228                 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
 229         }
 230
 231         return 0;
 232 }
 233
 234 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 235 {
 236         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 237                 return -1;
 238
 239         PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
 240                         "Attempt to Enable SMC FAN CONTROL Feature Failed!",
 241                         return -1);
 242
 243         return 0;
 244 }
 245
 246
 247 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
 248 {
 249         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 250
 251         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 252                 return -1;
 253
 254         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 255                 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
 256                                 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
 257                                 return -1);
 258         }
 259         return 0;
 260 }
 261
 262 /**
 263 * Set Fan Speed in percent.
 264 * @param    hwmgr  the address of the powerplay hardware manager.
 265 * @param    speed is the percentage value (0% - 100%) to be set.
 266 * @exception Fails is the 100% setting appears to be 0.
 267 */
 268 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
 269                 uint32_t speed)
 270 {
 271         uint32_t duty100;
 272         uint32_t duty;
 273         uint64_t tmp64;
 274         uint32_t reg;
 275
 276         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 277                 return 0;
 278
 279         if (speed > 100)
 280                 speed = 100;
 281
 282         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 283                         PHM_PlatformCaps_MicrocodeFanControl))
 284                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 285
 286         reg = soc15_get_register_offset(THM_HWID, 0,
 287                         mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
 288
 289         duty100 = (cgs_read_register(hwmgr->device, reg) &
 290                         CG_FDO_CTRL1__FMAX_DUTY100_MASK) >>
 291                         CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
 292
 293         if (duty100 == 0)
 294                 return -EINVAL;
 295
 296         tmp64 = (uint64_t)speed * duty100;
 297         do_div(tmp64, 100);
 298         duty = (uint32_t)tmp64;
 299
 300         reg = soc15_get_register_offset(THM_HWID, 0,
 301                         mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
 302         cgs_write_register(hwmgr->device, reg,
 303                         (cgs_read_register(hwmgr->device, reg) &
 304                         ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) |
 305                         (duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT));
 306
 307         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 308 }
 309
 310 /**
 311 * Reset Fan Speed to default.
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @exception Always succeeds.
 314 */
 315 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
 316 {
 317         int result;
 318
 319         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 320                 return 0;
 321
 322         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 323                         PHM_PlatformCaps_MicrocodeFanControl)) {
 324                 result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 325         } else
 326                 result = vega10_fan_ctrl_set_default_mode(hwmgr);
 327
 328         return result;
 329 }
 330
 331 /**
 332 * Set Fan Speed in RPM.
 333 * @param    hwmgr  the address of the powerplay hardware manager.
 334 * @param    speed is the percentage value (min - max) to be set.
 335 * @exception Fails is the speed not lie between min and max.
 336 */
 337 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
 338 {
 339         uint32_t tach_period;
 340         uint32_t crystal_clock_freq;
 341         int result = 0;
 342         uint32_t reg;
 343
 344         if (hwmgr->thermal_controller.fanInfo.bNoFan ||
 345                         (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
 346                         (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
 347                 return -1;
 348
 349         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 350                         PHM_PlatformCaps_MicrocodeFanControl))
 351                 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 352
 353         if (!result) {
 354                 crystal_clock_freq = smu7_get_xclk(hwmgr);
 355                 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
 356                 reg = soc15_get_register_offset(THM_HWID, 0,
 357                                 mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
 358                 cgs_write_register(hwmgr->device, reg,
 359                                 (cgs_read_register(hwmgr->device, reg) &
 360                                 ~CG_TACH_STATUS__TACH_PERIOD_MASK) |
 361                                 (tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT));
 362         }
 363         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 364 }
 365
 366 /**
 367 * Reads the remote temperature from the SIslands thermal controller.
 368 *
 369 * @param    hwmgr The address of the hardware manager.
 370 */
 371 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 372 {
 373         int temp;
 374         uint32_t reg;
 375
 376         reg = soc15_get_register_offset(THM_HWID, 0,
 377                         mmCG_TACH_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
 378
 379         temp = cgs_read_register(hwmgr->device, reg);
 380
 381         temp = (temp & CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK) >>
 382                         CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT;
 383
 384         temp = temp & 0x1ff;
 385
 386         temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 387
 388         return temp;
 389 }
 390
 391 /**
 392 * Set the requested temperature range for high and low alert signals
 393 *
 394 * @param    hwmgr The address of the hardware manager.
 395 * @param    range Temperature range to be programmed for
 396 *           high and low alert signals
 397 * @exception PP_Result_BadInput if the input data is not valid.
 398 */
 399 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 400                 struct PP_TemperatureRange *range)
 401 {
 402         uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
 403                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 404         uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
 405                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 406         uint32_t val, reg;
 407
 408         if (low < range->min)
 409                 low = range->min;
 410         if (high > range->max)
 411                 high = range->max;
 412
 413         if (low > high)
 414                 return -EINVAL;
 415
 416         reg = soc15_get_register_offset(THM_HWID, 0,
 417                         mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
 418
 419         val = cgs_read_register(hwmgr->device, reg);
 420
 421         val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
 422         val |=  (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
 423
 424         val &= (~THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK);
 425         val |= (1 << THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT);
 426
 427         val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
 428         val |= ((high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
 429                         << THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT);
 430
 431         val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
 432         val |= ((low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
 433                         << THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
 434
 435         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 436
 437         cgs_write_register(hwmgr->device, reg, val);
 438
 439         return 0;
 440 }
 441
 442 /**
 443 * Programs thermal controller one-time setting registers
 444 *
 445 * @param    hwmgr The address of the hardware manager.
 446 */
 447 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 448 {
 449         uint32_t reg;
 450
 451         if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
 452                 reg = soc15_get_register_offset(THM_HWID, 0,
 453                                 mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
 454                 cgs_write_register(hwmgr->device, reg,
 455                                 (cgs_read_register(hwmgr->device, reg) &
 456                                 ~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
 457                                 ((hwmgr->thermal_controller.fanInfo.
 458                                 ucTachometerPulsesPerRevolution - 1) <<
 459                                 CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
 460         }
 461
 462         reg = soc15_get_register_offset(THM_HWID, 0,
 463                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 464         cgs_write_register(hwmgr->device, reg,
 465                         (cgs_read_register(hwmgr->device, reg) &
 466                         ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) |
 467                         (0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
 468
 469         return 0;
 470 }
 471
 472 /**
 473 * Enable thermal alerts on the RV770 thermal controller.
 474 *
 475 * @param    hwmgr The address of the hardware manager.
 476 */
 477 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 478 {
 479         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 480         uint32_t val = 0;
 481         uint32_t reg;
 482
 483         if (data->smu_features[GNLD_FW_CTF].supported) {
 484                 if (data->smu_features[GNLD_FW_CTF].enabled)
 485                         printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
 486
 487                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
 488                                 true,
 489                                 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 490                                 "Attempt to Enable FW CTF feature Failed!",
 491                                 return -1);
 492                 data->smu_features[GNLD_FW_CTF].enabled = true;
 493         }
 494
 495         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
 496         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
 497         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
 498
 499         reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
 500         cgs_write_register(hwmgr->device, reg, val);
 501
 502         return 0;
 503 }
 504
 505 /**
 506 * Disable thermal alerts on the RV770 thermal controller.
 507 * @param    hwmgr The address of the hardware manager.
 508 */
 509 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
 510 {
 511         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 512         uint32_t reg;
 513
 514         if (data->smu_features[GNLD_FW_CTF].supported) {
 515                 if (!data->smu_features[GNLD_FW_CTF].enabled)
 516                         printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
 517
 518
 519                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
 520                         false,
 521                         data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 522                         "Attempt to disable FW CTF feature Failed!",
 523                         return -1);
 524                 data->smu_features[GNLD_FW_CTF].enabled = false;
 525         }
 526
 527         reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
 528         cgs_write_register(hwmgr->device, reg, 0);
 529
 530         return 0;
 531 }
 532
 533 /**
 534 * Uninitialize the thermal controller.
 535 * Currently just disables alerts.
 536 * @param    hwmgr The address of the hardware manager.
 537 */
 538 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 539 {
 540         int result = vega10_thermal_disable_alert(hwmgr);
 541
 542         if (!hwmgr->thermal_controller.fanInfo.bNoFan)
 543                 vega10_fan_ctrl_set_default_mode(hwmgr);
 544
 545         return result;
 546 }
 547
 548 /**
 549 * Set up the fan table to control the fan using the SMC.
 550 * @param    hwmgr  the address of the powerplay hardware manager.
 551 * @param    pInput the pointer to input data
 552 * @param    pOutput the pointer to output data
 553 * @param    pStorage the pointer to temporary storage
 554 * @param    Result the last failure code
 555 * @return   result from set temperature range routine
 556 */
 557 int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
 558                 void *input, void *output, void *storage, int result)
 559 {
 560         int ret;
 561         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 562         PPTable_t *table = &(data->smc_state_table.pp_table);
 563
 564         if (!data->smu_features[GNLD_FAN_CONTROL].supported)
 565                 return 0;
 566
 567         table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
 568                         advanceFanControlParameters.usMaxFanRPM;
 569         table->FanThrottlingRpm = hwmgr->thermal_controller.
 570                         advanceFanControlParameters.usFanRPMMaxLimit;
 571         table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
 572                         advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
 573         table->FanTargetTemperature = hwmgr->thermal_controller.
 574                         advanceFanControlParameters.usTMax;
 575
 576         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 577                                 PPSMC_MSG_SetFanTemperatureTarget,
 578                                 (uint32_t)table->FanTargetTemperature);
 579
 580         table->FanPwmMin = hwmgr->thermal_controller.
 581                         advanceFanControlParameters.usPWMMin * 255 / 100;
 582         table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
 583                         advanceFanControlParameters.ulTargetGfxClk);
 584         table->FanGainEdge = hwmgr->thermal_controller.
 585                         advanceFanControlParameters.usFanGainEdge;
 586         table->FanGainHotspot = hwmgr->thermal_controller.
 587                         advanceFanControlParameters.usFanGainHotspot;
 588         table->FanGainLiquid = hwmgr->thermal_controller.
 589                         advanceFanControlParameters.usFanGainLiquid;
 590         table->FanGainVrVddc = hwmgr->thermal_controller.
 591                         advanceFanControlParameters.usFanGainVrVddc;
 592         table->FanGainVrMvdd = hwmgr->thermal_controller.
 593                         advanceFanControlParameters.usFanGainVrMvdd;
 594         table->FanGainPlx = hwmgr->thermal_controller.
 595                         advanceFanControlParameters.usFanGainPlx;
 596         table->FanGainHbm = hwmgr->thermal_controller.
 597                         advanceFanControlParameters.usFanGainHbm;
 598         table->FanZeroRpmEnable = hwmgr->thermal_controller.
 599                         advanceFanControlParameters.ucEnableZeroRPM;
 600         table->FanStopTemp = hwmgr->thermal_controller.
 601                         advanceFanControlParameters.usZeroRPMStopTemperature;
 602         table->FanStartTemp = hwmgr->thermal_controller.
 603                         advanceFanControlParameters.usZeroRPMStartTemperature;
 604
 605         ret = vega10_copy_table_to_smc(hwmgr->smumgr,
 606                         (uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
 607         if (ret)
 608                 pr_info("Failed to update Fan Control Table in PPTable!");
 609
 610         return ret;
 611 }
 612
 613 /**
 614 * Start the fan control on the SMC.
 615 * @param    hwmgr  the address of the powerplay hardware manager.
 616 * @param    pInput the pointer to input data
 617 * @param    pOutput the pointer to output data
 618 * @param    pStorage the pointer to temporary storage
 619 * @param    Result the last failure code
 620 * @return   result from set temperature range routine
 621 */
 622 int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
 623                 void *input, void *output, void *storage, int result)
 624 {
 625 /* If the fantable setup has failed we could have disabled
 626  * PHM_PlatformCaps_MicrocodeFanControl even after
 627  * this function was included in the table.
 628  * Make sure that we still think controlling the fan is OK.
 629 */
 630         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 631                         PHM_PlatformCaps_MicrocodeFanControl)) {
 632                 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 633         }
 634
 635         return 0;
 636 }
 637
 638 /**
 639 * Set temperature range for high and low alerts
 640 * @param    hwmgr  the address of the powerplay hardware manager.
 641 * @param    pInput the pointer to input data
 642 * @param    pOutput the pointer to output data
 643 * @param    pStorage the pointer to temporary storage
 644 * @param    Result the last failure code
 645 * @return   result from set temperature range routine
 646 */
 647 int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 648                 void *input, void *output, void *storage, int result)
 649 {
 650         struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
 651
 652         if (range == NULL)
 653                 return -EINVAL;
 654
 655         return vega10_thermal_set_temperature_range(hwmgr, range);
 656 }
 657
 658 /**
 659 * Programs one-time setting registers
 660 * @param    hwmgr  the address of the powerplay hardware manager.
 661 * @param    pInput the pointer to input data
 662 * @param    pOutput the pointer to output data
 663 * @param    pStorage the pointer to temporary storage
 664 * @param    Result the last failure code
 665 * @return   result from initialize thermal controller routine
 666 */
 667 int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
 668                 void *input, void *output, void *storage, int result)
 669 {
 670         return vega10_thermal_initialize(hwmgr);
 671 }
 672
 673 /**
 674 * Enable high and low alerts
 675 * @param    hwmgr  the address of the powerplay hardware manager.
 676 * @param    pInput the pointer to input data
 677 * @param    pOutput the pointer to output data
 678 * @param    pStorage the pointer to temporary storage
 679 * @param    Result the last failure code
 680 * @return   result from enable alert routine
 681 */
 682 int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
 683                 void *input, void *output, void *storage, int result)
 684 {
 685         return vega10_thermal_enable_alert(hwmgr);
 686 }
 687
 688 /**
 689 * Disable high and low alerts
 690 * @param    hwmgr  the address of the powerplay hardware manager.
 691 * @param    pInput the pointer to input data
 692 * @param    pOutput the pointer to output data
 693 * @param    pStorage the pointer to temporary storage
 694 * @param    Result the last failure code
 695 * @return   result from disable alert routine
 696 */
 697 static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
 698                 void *input, void *output, void *storage, int result)
 699 {
 700         return vega10_thermal_disable_alert(hwmgr);
 701 }
 702
 703 static struct phm_master_table_item
 704 vega10_thermal_start_thermal_controller_master_list[] = {
 705         { .tableFunction = tf_vega10_thermal_initialize },
 706         { .tableFunction = tf_vega10_thermal_set_temperature_range },
 707         { .tableFunction = tf_vega10_thermal_enable_alert },
 708 /* We should restrict performance levels to low before we halt the SMC.
 709  * On the other hand we are still in boot state when we do this
 710  * so it would be pointless.
 711  * If this assumption changes we have to revisit this table.
 712  */
 713         { .tableFunction = tf_vega10_thermal_setup_fan_table },
 714         { .tableFunction = tf_vega10_thermal_start_smc_fan_control },
 715         { }
 716 };
 717
 718 static struct phm_master_table_header
 719 vega10_thermal_start_thermal_controller_master = {
 720         0,
 721         PHM_MasterTableFlag_None,
 722         vega10_thermal_start_thermal_controller_master_list
 723 };
 724
 725 static struct phm_master_table_item
 726 vega10_thermal_set_temperature_range_master_list[] = {
 727         { .tableFunction = tf_vega10_thermal_disable_alert },
 728         { .tableFunction = tf_vega10_thermal_set_temperature_range },
 729         { .tableFunction = tf_vega10_thermal_enable_alert },
 730         { }
 731 };
 732
 733 struct phm_master_table_header
 734 vega10_thermal_set_temperature_range_master = {
 735         0,
 736         PHM_MasterTableFlag_None,
 737         vega10_thermal_set_temperature_range_master_list
 738 };
 739
 740 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 741 {
 742         if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
 743                 vega10_fan_ctrl_set_default_mode(hwmgr);
 744                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 745         }
 746         return 0;
 747 }
 748
 749 /**
 750 * Initializes the thermal controller related functions
 751 * in the Hardware Manager structure.
 752 * @param    hwmgr The address of the hardware manager.
 753 * @exception Any error code from the low-level communication.
 754 */
 755 int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 756 {
 757         int result;
 758
 759         result = phm_construct_table(hwmgr,
 760                         &vega10_thermal_set_temperature_range_master,
 761                         &(hwmgr->set_temperature_range));
 762
 763         if (!result) {
 764                 result = phm_construct_table(hwmgr,
 765                                 &vega10_thermal_start_thermal_controller_master,
 766                                 &(hwmgr->start_thermal_controller));
 767                 if (result)
 768                         phm_destroy_table(hwmgr,
 769                                         &(hwmgr->set_temperature_range));
 770         }
 771
 772         if (!result)
 773                 hwmgr->fan_ctrl_is_in_default_mode = true;
 774         return result;
 775 }
 776