drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include "smumgr.h"
  26 #include "smu73.h"
  27 #include "smu_ucode_xfer_vi.h"
  28 #include "fiji_smumgr.h"
  29 #include "fiji_ppsmc.h"
  30 #include "smu73_discrete.h"
  31 #include "ppatomctrl.h"
  32 #include "smu/smu_7_1_3_d.h"
  33 #include "smu/smu_7_1_3_sh_mask.h"
  34 #include "gmc/gmc_8_1_d.h"
  35 #include "gmc/gmc_8_1_sh_mask.h"
  36 #include "oss/oss_3_0_d.h"
  37 #include "gca/gfx_8_0_d.h"
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40 #include "fiji_pwrvirus.h"
  41 #include "fiji_smc.h"
  42
  43 #define AVFS_EN_MSB                                        1568
  44 #define AVFS_EN_LSB                                        1568
  45
  46 #define FIJI_SMC_SIZE 0x20000
  47
  48 static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
  49                 /*  Min        Sclk       pcie     DeepSleep Activity  CgSpll      CgSpll    spllSpread  SpllSpread   CcPwr  CcPwr  Sclk   Display     Enabled     Enabled                       Voltage    Power */
  50                 /* Voltage,  Frequency,  DpmLevel,  DivId,    Level,  FuncCntl3,  FuncCntl4,  Spectrum,   Spectrum2,  DynRm, DynRm1  Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
  51                 { 0x3c0fd047, 0x30750000,   0x00,     0x03,   0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  52                 { 0xa00fd047, 0x409c0000,   0x01,     0x04,   0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  53                 { 0x0410d047, 0x50c30000,   0x01,     0x00,   0x1e00, 0x00600410, 0x87020000, 0x21680000, 0x0d000000,   0,      0,   0x0e,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  54                 { 0x6810d047, 0x60ea0000,   0x01,     0x00,   0x1e00, 0x00800410, 0x87020000, 0x21680000, 0x0e000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  55                 { 0xcc10d047, 0xe8fd0000,   0x01,     0x00,   0x1e00, 0x00e00410, 0x87020000, 0x21680000, 0x0f000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  56                 { 0x3011d047, 0x70110100,   0x01,     0x00,   0x1e00, 0x00400510, 0x87020000, 0x21680000, 0x10000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  57                 { 0x9411d047, 0xf8240100,   0x01,     0x00,   0x1e00, 0x00a00510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  58                 { 0xf811d047, 0x80380100,   0x01,     0x00,   0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000,   0,      0,   0x0c,   0x01,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 }
  59 };
  60
  61 static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
  62 {
  63         int result = 0;
  64
  65         /* Wait for smc boot up */
  66         /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
  67                 RCU_UC_EVENTS, boot_seq_done, 0); */
  68
  69         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  70                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
  71
  72         result = smu7_upload_smu_firmware_image(smumgr);
  73         if (result)
  74                 return result;
  75
  76         /* Clear status */
  77         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
  78                         ixSMU_STATUS, 0);
  79
  80         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  81                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
  82
  83         /* De-assert reset */
  84         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  85                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
  86
  87         /* Wait for ROM firmware to initialize interrupt hendler */
  88         /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
  89                         SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
  90
  91         /* Set SMU Auto Start */
  92         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  93                         SMU_INPUT_DATA, AUTO_START, 1);
  94
  95         /* Clear firmware interrupt enable flag */
  96         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
  97                         ixFIRMWARE_FLAGS, 0);
  98
  99         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS,
 100                         INTERRUPTS_ENABLED, 1);
 101
 102         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
 103         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
 104         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 105
 106         /* Wait for done bit to be set */
 107         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
 108                         SMU_STATUS, SMU_DONE, 0);
 109
 110         /* Check pass/failed indicator */
 111         if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 112                         SMU_STATUS, SMU_PASS) != 1) {
 113                 PP_ASSERT_WITH_CODE(false,
 114                                 "SMU Firmware start failed!", return -1);
 115         }
 116
 117         /* Wait for firmware to initialize */
 118         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 119                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 120
 121         return result;
 122 }
 123
 124 static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
 125 {
 126         int result = 0;
 127
 128         /* wait for smc boot up */
 129         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
 130                         RCU_UC_EVENTS, boot_seq_done, 0);
 131
 132         /* Clear firmware interrupt enable flag */
 133         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
 134                         ixFIRMWARE_FLAGS, 0);
 135
 136         /* Assert reset */
 137         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 138                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 139
 140         result = smu7_upload_smu_firmware_image(smumgr);
 141         if (result)
 142                 return result;
 143
 144         /* Set smc instruct start point at 0x0 */
 145         smu7_program_jump_on_start(smumgr);
 146
 147         /* Enable clock */
 148         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 149                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 150
 151         /* De-assert reset */
 152         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 153                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 154
 155         /* Wait for firmware to initialize */
 156         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 157                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 158
 159         return result;
 160 }
 161
 162 static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
 163 {
 164         int i;
 165         int result = -EINVAL;
 166         uint32_t reg, data;
 167
 168         const PWR_Command_Table *pvirus = PwrVirusTable;
 169         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 170
 171         for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
 172                 switch (pvirus->command) {
 173                 case PwrCmdWrite:
 174                         reg  = pvirus->reg;
 175                         data = pvirus->data;
 176                         cgs_write_register(smumgr->device, reg, data);
 177                         break;
 178
 179                 case PwrCmdEnd:
 180                         result = 0;
 181                         break;
 182
 183                 default:
 184                         pr_info("Table Exit with Invalid Command!");
 185                         smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
 186                         result = -EINVAL;
 187                         break;
 188                 }
 189                 pvirus++;
 190         }
 191
 192         return result;
 193 }
 194
 195 static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
 196 {
 197         int result = 0;
 198         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 199
 200         if (0 != smu_data->avfs.avfs_btc_param) {
 201                 if (0 != smu7_send_msg_to_smc_with_parameter(smumgr,
 202                                 PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
 203                         pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
 204                         result = -EINVAL;
 205                 }
 206         }
 207         /* Soft-Reset to reset the engine before loading uCode */
 208          /* halt */
 209         cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
 210         /* reset everything */
 211         cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
 212         /* clear reset */
 213         cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
 214
 215         return result;
 216 }
 217
 218 static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 219 {
 220         int32_t vr_config;
 221         uint32_t table_start;
 222         uint32_t level_addr, vr_config_addr;
 223         uint32_t level_size = sizeof(avfs_graphics_level);
 224
 225         PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
 226                         SMU7_FIRMWARE_HEADER_LOCATION +
 227                         offsetof(SMU73_Firmware_Header, DpmTable),
 228                         &table_start, 0x40000),
 229                         "[AVFS][Fiji_SetupGfxLvlStruct] SMU could not "
 230                         "communicate starting address of DPM table",
 231                         return -1;);
 232
 233         /* Default value for vr_config =
 234          * VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
 235         vr_config = 0x01000500;   /* Real value:0x50001 */
 236
 237         vr_config_addr = table_start +
 238                         offsetof(SMU73_Discrete_DpmTable, VRConfig);
 239
 240         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr,
 241                         (uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
 242                         "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
 243                         "vr_config value over to SMC",
 244                         return -1;);
 245
 246         level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
 247
 248         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr,
 249                         (uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
 250                         "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
 251                         return -1;);
 252
 253         return 0;
 254 }
 255
 256 static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
 257 {
 258         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 259
 260         switch (smu_data->avfs.avfs_btc_status) {
 261         case AVFS_BTC_COMPLETED_PREVIOUSLY:
 262                 break;
 263
 264         case AVFS_BTC_BOOT: /*Cold Boot State - Post SMU Start*/
 265                 if (!smu_started)
 266                         break;
 267                 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
 268                 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr),
 269                                 "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
 270                                 " table over to SMU",
 271                                 return -EINVAL;);
 272                 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
 273                 PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr),
 274                                 "[AVFS][fiji_avfs_event_mgr] Could not setup "
 275                                 "Pwr Virus for AVFS ",
 276                                 return -EINVAL;);
 277                 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
 278                 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr),
 279                                 "[AVFS][fiji_avfs_event_mgr] Failure at "
 280                                 "fiji_start_avfs_btc. AVFS Disabled",
 281                                 return -EINVAL;);
 282
 283                 smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
 284                 break;
 285         case AVFS_BTC_DISABLED: /* Do nothing */
 286         case AVFS_BTC_NOTSUPPORTED: /* Do nothing */
 287         case AVFS_BTC_ENABLEAVFS:
 288                 break;
 289         default:
 290                 pr_err("AVFS failed status is %x !\n", smu_data->avfs.avfs_btc_status);
 291                 break;
 292         }
 293         return 0;
 294 }
 295
 296 static int fiji_start_smu(struct pp_smumgr *smumgr)
 297 {
 298         int result = 0;
 299         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 300
 301         /* Only start SMC if SMC RAM is not running */
 302         if (!(smu7_is_smc_ram_running(smumgr)
 303                 || cgs_is_virtualization_enabled(smumgr->device))) {
 304                 fiji_avfs_event_mgr(smumgr, false);
 305
 306                 /* Check if SMU is running in protected mode */
 307                 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
 308                                 CGS_IND_REG__SMC,
 309                                 SMU_FIRMWARE, SMU_MODE)) {
 310                         result = fiji_start_smu_in_non_protection_mode(smumgr);
 311                         if (result)
 312                                 return result;
 313                 } else {
 314                         result = fiji_start_smu_in_protection_mode(smumgr);
 315                         if (result)
 316                                 return result;
 317                 }
 318                 fiji_avfs_event_mgr(smumgr, true);
 319         }
 320
 321         /* To initialize all clock gating before RLC loaded and running.*/
 322         cgs_set_clockgating_state(smumgr->device,
 323                         AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
 324         cgs_set_clockgating_state(smumgr->device,
 325                         AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
 326         cgs_set_clockgating_state(smumgr->device,
 327                         AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
 328         cgs_set_clockgating_state(smumgr->device,
 329                         AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
 330
 331         /* Setup SoftRegsStart here for register lookup in case
 332          * DummyBackEnd is used and ProcessFirmwareHeader is not executed
 333          */
 334         smu7_read_smc_sram_dword(smumgr,
 335                         SMU7_FIRMWARE_HEADER_LOCATION +
 336                         offsetof(SMU73_Firmware_Header, SoftRegisters),
 337                         &(priv->smu7_data.soft_regs_start), 0x40000);
 338
 339         result = smu7_request_smu_load_fw(smumgr);
 340
 341         return result;
 342 }
 343
 344 static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
 345 {
 346
 347         uint32_t efuse = 0;
 348         uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
 349
 350         if (cgs_is_virtualization_enabled(smumgr->device))
 351                 return 0;
 352
 353         if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
 354                         mask, &efuse)) {
 355                 if (efuse)
 356                         return true;
 357         }
 358         return false;
 359 }
 360
 361 /**
 362 * Write a 32bit value to the SMC SRAM space.
 363 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
 364 * @param    smumgr  the address of the powerplay hardware manager.
 365 * @param    smc_addr the address in the SMC RAM to access.
 366 * @param    value to write to the SMC SRAM.
 367 */
 368 static int fiji_smu_init(struct pp_smumgr *smumgr)
 369 {
 370         int i;
 371         struct fiji_smumgr *fiji_priv = NULL;
 372
 373         fiji_priv = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
 374
 375         if (fiji_priv == NULL)
 376                 return -ENOMEM;
 377
 378         smumgr->backend = fiji_priv;
 379
 380         if (smu7_init(smumgr))
 381                 return -EINVAL;
 382
 383         for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
 384                 fiji_priv->activity_target[i] = 30;
 385
 386         return 0;
 387 }
 388
 389
 390 const struct pp_smumgr_func fiji_smu_funcs = {
 391         .smu_init = &fiji_smu_init,
 392         .smu_fini = &smu7_smu_fini,
 393         .start_smu = &fiji_start_smu,
 394         .check_fw_load_finish = &smu7_check_fw_load_finish,
 395         .request_smu_load_fw = &smu7_reload_firmware,
 396         .request_smu_load_specific_fw = NULL,
 397         .send_msg_to_smc = &smu7_send_msg_to_smc,
 398         .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
 399         .download_pptable_settings = NULL,
 400         .upload_pptable_settings = NULL,
 401         .update_smc_table = fiji_update_smc_table,
 402         .get_offsetof = fiji_get_offsetof,
 403         .process_firmware_header = fiji_process_firmware_header,
 404         .init_smc_table = fiji_init_smc_table,
 405         .update_sclk_threshold = fiji_update_sclk_threshold,
 406         .thermal_setup_fan_table = fiji_thermal_setup_fan_table,
 407         .thermal_avfs_enable = fiji_thermal_avfs_enable,
 408         .populate_all_graphic_levels = fiji_populate_all_graphic_levels,
 409         .populate_all_memory_levels = fiji_populate_all_memory_levels,
 410         .get_mac_definition = fiji_get_mac_definition,
 411         .initialize_mc_reg_table = fiji_initialize_mc_reg_table,
 412         .is_dpm_running = fiji_is_dpm_running,
 413         .populate_requested_graphic_levels = fiji_populate_requested_graphic_levels,
 414         .is_hw_avfs_present = fiji_is_hw_avfs_present,
 415 };