drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include "smumgr.h"
  26 #include "smu74.h"
  27 #include "smu_ucode_xfer_vi.h"
  28 #include "polaris10_smumgr.h"
  29 #include "smu74_discrete.h"
  30 #include "smu/smu_7_1_3_d.h"
  31 #include "smu/smu_7_1_3_sh_mask.h"
  32 #include "gmc/gmc_8_1_d.h"
  33 #include "gmc/gmc_8_1_sh_mask.h"
  34 #include "oss/oss_3_0_d.h"
  35 #include "gca/gfx_8_0_d.h"
  36 #include "bif/bif_5_0_d.h"
  37 #include "bif/bif_5_0_sh_mask.h"
  38 #include "polaris10_pwrvirus.h"
  39 #include "ppatomctrl.h"
  40 #include "cgs_common.h"
  41 #include "polaris10_smc.h"
  42 #include "smu7_ppsmc.h"
  43 #include "smu7_smumgr.h"
  44
  45 #define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
  46
  47 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
  48         /*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
  49         /* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
  50         { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  51         { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  52         { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
  53         { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  54         { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
  55         { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  56         { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
  57         { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
  58 };
  59
  60 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
  61         0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
  62
  63 static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
  64 {
  65         int i;
  66         int result = -EINVAL;
  67         uint32_t reg, data;
  68
  69         const PWR_Command_Table *pvirus = pwr_virus_table;
  70         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
  71
  72         for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
  73                 switch (pvirus->command) {
  74                 case PwrCmdWrite:
  75                         reg  = pvirus->reg;
  76                         data = pvirus->data;
  77                         cgs_write_register(smumgr->device, reg, data);
  78                         break;
  79
  80                 case PwrCmdEnd:
  81                         result = 0;
  82                         break;
  83
  84                 default:
  85                         pr_info("Table Exit with Invalid Command!");
  86                         smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
  87                         result = -EINVAL;
  88                         break;
  89                 }
  90                 pvirus++;
  91         }
  92
  93         return result;
  94 }
  95
  96 static int polaris10_perform_btc(struct pp_smumgr *smumgr)
  97 {
  98         int result = 0;
  99         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 100
 101         if (0 != smu_data->avfs.avfs_btc_param) {
 102                 if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
 103                         pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
 104                         result = -1;
 105                 }
 106         }
 107         if (smu_data->avfs.avfs_btc_param > 1) {
 108                 /* Soft-Reset to reset the engine before loading uCode */
 109                 /* halt */
 110                 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
 111                 /* reset everything */
 112                 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
 113                 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
 114         }
 115         return result;
 116 }
 117
 118
 119 static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 120 {
 121         uint32_t vr_config;
 122         uint32_t dpm_table_start;
 123
 124         uint16_t u16_boot_mvdd;
 125         uint32_t graphics_level_address, vr_config_address, graphics_level_size;
 126
 127         graphics_level_size = sizeof(avfs_graphics_level_polaris10);
 128         u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
 129
 130         PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
 131                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
 132                                 &dpm_table_start, 0x40000),
 133                         "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
 134                         return -1);
 135
 136         /*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
 137         vr_config = 0x01000500; /* Real value:0x50001 */
 138
 139         vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
 140
 141         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address,
 142                                 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
 143                         "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
 144                         return -1);
 145
 146         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
 147
 148         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
 149                                 (uint8_t *)(&avfs_graphics_level_polaris10),
 150                                 graphics_level_size, 0x40000),
 151                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
 152                         return -1);
 153
 154         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
 155
 156         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
 157                                 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
 158                                 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
 159                         return -1);
 160
 161         /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
 162
 163         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
 164
 165         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
 166                         (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
 167                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
 168                         return -1);
 169
 170         return 0;
 171 }
 172
 173
 174 static int
 175 polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
 176 {
 177         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 178
 179         switch (smu_data->avfs.avfs_btc_status) {
 180         case AVFS_BTC_COMPLETED_PREVIOUSLY:
 181                 break;
 182
 183         case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
 184
 185                 smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
 186                 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
 187                         "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
 188                         return -EINVAL);
 189
 190                 if (smu_data->avfs.avfs_btc_param > 1) {
 191                         pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
 192                         smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
 193                         PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(smumgr),
 194                         "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
 195                         return -EINVAL);
 196                 }
 197
 198                 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
 199                 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
 200                                         "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
 201                                  return -EINVAL);
 202                 smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
 203                 break;
 204
 205         case AVFS_BTC_DISABLED:
 206         case AVFS_BTC_ENABLEAVFS:
 207         case AVFS_BTC_NOTSUPPORTED:
 208                 break;
 209
 210         default:
 211                 pr_err("AVFS failed status is %x!\n", smu_data->avfs.avfs_btc_status);
 212                 break;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
 219 {
 220         int result = 0;
 221
 222         /* Wait for smc boot up */
 223         /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
 224
 225         /* Assert reset */
 226         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 227                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 228
 229         result = smu7_upload_smu_firmware_image(smumgr);
 230         if (result != 0)
 231                 return result;
 232
 233         /* Clear status */
 234         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
 235
 236         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 237                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 238
 239         /* De-assert reset */
 240         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 241                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 242
 243
 244         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
 245
 246
 247         /* Call Test SMU message with 0x20000 offset to trigger SMU start */
 248         smu7_send_msg_to_smc_offset(smumgr);
 249
 250         /* Wait done bit to be set */
 251         /* Check pass/failed indicator */
 252
 253         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
 254
 255         if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 256                                                 SMU_STATUS, SMU_PASS))
 257                 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
 258
 259         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
 260
 261         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 262                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 263
 264         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 265                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 266
 267         /* Wait for firmware to initialize */
 268         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 269
 270         return result;
 271 }
 272
 273 static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
 274 {
 275         int result = 0;
 276
 277         /* wait for smc boot up */
 278         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
 279
 280         /* Clear firmware interrupt enable flag */
 281         /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
 282         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
 283                                 ixFIRMWARE_FLAGS, 0);
 284
 285         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 286                                         SMC_SYSCON_RESET_CNTL,
 287                                         rst_reg, 1);
 288
 289         result = smu7_upload_smu_firmware_image(smumgr);
 290         if (result != 0)
 291                 return result;
 292
 293         /* Set smc instruct start point at 0x0 */
 294         smu7_program_jump_on_start(smumgr);
 295
 296         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 297                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 298
 299         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 300                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 301
 302         /* Wait for firmware to initialize */
 303
 304         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 305                                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 306
 307         return result;
 308 }
 309
 310 static int polaris10_start_smu(struct pp_smumgr *smumgr)
 311 {
 312         int result = 0;
 313         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
 314         bool SMU_VFT_INTACT;
 315
 316         /* Only start SMC if SMC RAM is not running */
 317         if (!smu7_is_smc_ram_running(smumgr)) {
 318                 SMU_VFT_INTACT = false;
 319                 smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
 320                 smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
 321
 322                 /* Check if SMU is running in protected mode */
 323                 if (smu_data->protected_mode == 0) {
 324                         result = polaris10_start_smu_in_non_protection_mode(smumgr);
 325                 } else {
 326                         result = polaris10_start_smu_in_protection_mode(smumgr);
 327
 328                         /* If failed, try with different security Key. */
 329                         if (result != 0) {
 330                                 smu_data->smu7_data.security_hard_key ^= 1;
 331                                 cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
 332                                 result = polaris10_start_smu_in_protection_mode(smumgr);
 333                         }
 334                 }
 335
 336                 if (result != 0)
 337                         PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
 338
 339                 polaris10_avfs_event_mgr(smumgr, true);
 340         } else
 341                 SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
 342
 343         polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
 344         /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
 345         smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
 346                                         &(smu_data->smu7_data.soft_regs_start), 0x40000);
 347
 348         result = smu7_request_smu_load_fw(smumgr);
 349
 350         return result;
 351 }
 352
 353 static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
 354 {
 355         uint32_t efuse;
 356
 357         efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
 358         efuse &= 0x00000001;
 359         if (efuse)
 360                 return true;
 361
 362         return false;
 363 }
 364
 365 static int polaris10_smu_init(struct pp_smumgr *smumgr)
 366 {
 367         struct polaris10_smumgr *smu_data;
 368         int i;
 369
 370         smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
 371         if (smu_data == NULL)
 372                 return -ENOMEM;
 373
 374         smumgr->backend = smu_data;
 375
 376         if (smu7_init(smumgr))
 377                 return -EINVAL;
 378
 379         for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
 380                 smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;
 381
 382         return 0;
 383 }
 384
 385 const struct pp_smumgr_func polaris10_smu_funcs = {
 386         .smu_init = polaris10_smu_init,
 387         .smu_fini = smu7_smu_fini,
 388         .start_smu = polaris10_start_smu,
 389         .check_fw_load_finish = smu7_check_fw_load_finish,
 390         .request_smu_load_fw = smu7_reload_firmware,
 391         .request_smu_load_specific_fw = NULL,
 392         .send_msg_to_smc = smu7_send_msg_to_smc,
 393         .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
 394         .download_pptable_settings = NULL,
 395         .upload_pptable_settings = NULL,
 396         .update_smc_table = polaris10_update_smc_table,
 397         .get_offsetof = polaris10_get_offsetof,
 398         .process_firmware_header = polaris10_process_firmware_header,
 399         .init_smc_table = polaris10_init_smc_table,
 400         .update_sclk_threshold = polaris10_update_sclk_threshold,
 401         .thermal_avfs_enable = polaris10_thermal_avfs_enable,
 402         .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
 403         .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
 404         .populate_all_memory_levels = polaris10_populate_all_memory_levels,
 405         .get_mac_definition = polaris10_get_mac_definition,
 406         .is_dpm_running = polaris10_is_dpm_running,
 407         .populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
 408         .is_hw_avfs_present = polaris10_is_hw_avfs_present,
 409 };